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Searched refs:DMA1_Channel4_5_IRQn (Results 1 – 25 of 35) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/soc/
Dstm32f030x6.h85 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt … enumerator
5338 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
5339 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Dstm32f030x8.h85 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt … enumerator
5403 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
5404 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
Dstm32f070x6.h85 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt … enumerator
5590 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
5591 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
Dstm32f031x6.h86 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt … enumerator
5660 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
5661 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Dstm32f030xc.h85 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt … enumerator
5778 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
5779 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Dstm32f038xx.h85 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt … enumerator
5629 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
5630 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Dstm32f070xb.h85 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt … enumerator
5770 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
5771 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
Dstm32f058xx.h86 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt … enumerator
6712 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
6713 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
Dstm32f051x8.h87 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt … enumerator
6743 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
6744 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
Dstm32f042x6.h87 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt … enumerator
10646 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
10647 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Dstm32f048xx.h87 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt … enumerator
10610 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
10611 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l011xx.h89 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts … enumerator
5920 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Dstm32l021xx.h89 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts … enumerator
6060 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Dstm32l010x4.h88 …DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts … enumerator
5778 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Dstm32l041xx.h6206 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn macro
Dstm32l010x8.h5830 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn macro
Dstm32l010xb.h5906 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn macro
Dstm32l031xx.h6066 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn macro
Dstm32l051xx.h6240 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn macro
Dstm32l010x6.h5834 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn macro
Dstm32l081xx.h6613 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn macro
Dstm32l071xx.h6473 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn macro
Dstm32l052xx.h7322 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn macro
Dstm32l062xx.h7462 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn macro
Dstm32l053xx.h7484 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn macro

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