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Searched refs:DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (Results 1 – 25 of 71) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wlxx/soc/
Dstm32wle4xx.h8599 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
8600 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
Dstm32wle5xx.h8599 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
8600 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
Dstm32wl5mxx.h10228 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
10229 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
Dstm32wl54xx.h10228 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
10229 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
Dstm32wl55xx.h10228 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
10229 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
/hal_stm32-latest/stm32cube/stm32wbxx/soc/
Dstm32wb50xx.h10618 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
10619 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
Dstm32wb1mxx.h10640 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
10641 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
Dstm32wb30xx.h10614 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
10615 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
Dstm32wb35xx.h12086 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
12087 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
Dstm32wb55xx.h12991 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
12992 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
Dstm32wb5mxx.h12991 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
12992 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
/hal_stm32-latest/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h10468 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
10469 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
Dstm32wb15xx.h10640 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
10641 …DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*…
/hal_stm32-latest/stm32cube/stm32g4xx/soc/
Dstm32g411xb.h2721 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
2722 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x0…
Dstm32g411xc.h2758 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
2759 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x0…
Dstm32g441xx.h3066 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
3067 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x0…
Dstm32gbk1cb.h2831 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
2832 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x0…
Dstm32g431xx.h2845 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
2846 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x0…
Dstm32g4a1xx.h3146 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
3147 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x0…
Dstm32g491xx.h2925 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
2926 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x0…
Dstm32g473xx.h3014 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
3015 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x0…
Dstm32g471xx.h2936 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
2937 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x0…
/hal_stm32-latest/stm32cube/stm32l4xx/soc/
Dstm32l422xx.h10032 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
10033 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x…
Dstm32l412xx.h9807 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
9808 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x…
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h3464 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) macro
3465 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)

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