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Searched refs:CSR2 (Results 1 – 25 of 31) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_pwr_ex.c289 …if ((PWR->CSR2 & (PWR_CSR2_SDEN | PWR_CSR2_LDOEN | PWR_CSR2_BYPASS)) != (PWR_CSR2_SDEN | PWR_CSR2_… in HAL_PWREx_ConfigSupply()
292 if ((PWR->CSR2 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) in HAL_PWREx_ConfigSupply()
307 MODIFY_REG(PWR->CSR2, PWR_SUPPLY_CONFIG_MASK, SupplySource); in HAL_PWREx_ConfigSupply()
329 while ((PWR->CSR2 & PWR_CSR2_SDEXTRDY) == 0U) in HAL_PWREx_ConfigSupply()
346 return (PWR->CSR2 & PWR_SUPPLY_CONFIG_MASK); in HAL_PWREx_GetSupplyConfig()
833 SET_BIT(PWR->CSR2, PWR_CSR2_USBREGEN); in HAL_PWREx_EnableUSBReg()
843 CLEAR_BIT(PWR->CSR2, PWR_CSR2_USBREGEN); in HAL_PWREx_DisableUSBReg()
855 SET_BIT(PWR->CSR2, PWR_CSR2_USB33DEN); in HAL_PWREx_EnableUSBVoltageDetector()
861 while ((PWR->CSR2 & PWR_CSR2_USB33RDY) == 0U) in HAL_PWREx_EnableUSBVoltageDetector()
880 CLEAR_BIT(PWR->CSR2, PWR_CSR2_USB33DEN); in HAL_PWREx_DisableUSBVoltageDetector()
[all …]
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_pwr.h612 …MODIFY_REG(PWR->CSR2, (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_LDOEN | … in LL_PWR_ConfigSupply()
634 return READ_BIT(PWR->CSR2, in LL_PWR_GetSupply()
645 SET_BIT(PWR->CSR2, PWR_CSR2_VBE); in LL_PWR_EnableBatteryCharging()
655 CLEAR_BIT(PWR->CSR2, PWR_CSR2_VBE); in LL_PWR_DisableBatteryCharging()
665 return ((READ_BIT(PWR->CSR2, PWR_CSR2_VBE) == (PWR_CSR2_VBE)) ? 1UL : 0UL); in LL_PWR_IsEnabledBatteryCharging()
678 MODIFY_REG(PWR->CSR2, PWR_CSR2_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
690 return (READ_BIT(PWR->CSR2, PWR_CSR2_VBRS)); in LL_PWR_GetBattChargResistor()
705 MODIFY_REG(PWR->CSR2, PWR_CSR2_XSPICAP1, Capacitor); in LL_PWR_SetXSPI1Capacitor()
719 return (READ_BIT(PWR->CSR2, PWR_CSR2_XSPICAP1)); in LL_PWR_GetXSPI1Capacitor()
734 MODIFY_REG(PWR->CSR2, PWR_CSR2_XSPICAP2, Capacitor); in LL_PWR_SetXSPI2Capacitor()
[all …]
Dstm32h7rsxx_hal_pwr.h289 … ((__FLAG__) == PWR_FLAG_SDEXTRDY) ? ((PWR->CSR2 & PWR_CSR2_SDEXTRDY) == PWR_CSR2_SDEXTRDY) : \
290 … ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CSR2 & PWR_CSR2_USB33RDY) == PWR_CSR2_USB33RDY) : \
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_pwr.h620 SET_BIT(PWR->CSR2, WakeUpPin); in LL_PWR_EnableWakeUpPin()
642 CLEAR_BIT(PWR->CSR2, WakeUpPin); in LL_PWR_DisableWakeUpPin()
664 return (READ_BIT(PWR->CSR2, WakeUpPin) == (WakeUpPin)); in LL_PWR_IsEnabledWakeUpPin()
780 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF6) == (PWR_CSR2_WUPF6)); in LL_PWR_IsActiveFlag_WU6()
790 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF5) == (PWR_CSR2_WUPF5)); in LL_PWR_IsActiveFlag_WU5()
800 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF4) == (PWR_CSR2_WUPF4)); in LL_PWR_IsActiveFlag_WU4()
810 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF3) == (PWR_CSR2_WUPF3)); in LL_PWR_IsActiveFlag_WU3()
820 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF2) == (PWR_CSR2_WUPF2)); in LL_PWR_IsActiveFlag_WU2()
830 return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF1) == (PWR_CSR2_WUPF1)); in LL_PWR_IsActiveFlag_WU1()
Dstm32f7xx_hal_pwr_ex.h159 #define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_rcc.h1021 SET_BIT(RCC->CSR2, RCC_CSR2_LSION); in LL_RCC_LSI_Enable()
1031 CLEAR_BIT(RCC->CSR2, RCC_CSR2_LSION); in LL_RCC_LSI_Disable()
1041 return ((READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == (RCC_CSR2_LSIRDY)) ? 1UL : 0UL); in LL_RCC_LSI_IsReady()
1795 return ((READ_BIT(RCC->CSR2, RCC_CSR2_IWDGRSTF) == (RCC_CSR2_IWDGRSTF)) ? 1UL : 0UL); in LL_RCC_IsActiveFlag_IWDGRST()
1805 return ((READ_BIT(RCC->CSR2, RCC_CSR2_LPWRRSTF) == (RCC_CSR2_LPWRRSTF)) ? 1UL : 0UL); in LL_RCC_IsActiveFlag_LPWRRST()
1815 return ((READ_BIT(RCC->CSR2, RCC_CSR2_OBLRSTF) == (RCC_CSR2_OBLRSTF)) ? 1UL : 0UL); in LL_RCC_IsActiveFlag_OBLRST()
1825 return ((READ_BIT(RCC->CSR2, RCC_CSR2_PINRSTF) == (RCC_CSR2_PINRSTF)) ? 1UL : 0UL); in LL_RCC_IsActiveFlag_PINRST()
1835 return ((READ_BIT(RCC->CSR2, RCC_CSR2_SFTRSTF) == (RCC_CSR2_SFTRSTF)) ? 1UL : 0UL); in LL_RCC_IsActiveFlag_SFTRST()
1845 return ((READ_BIT(RCC->CSR2, RCC_CSR2_WWDGRSTF) == (RCC_CSR2_WWDGRSTF)) ? 1UL : 0UL); in LL_RCC_IsActiveFlag_WWDGRST()
1855 return ((READ_BIT(RCC->CSR2, RCC_CSR2_PWRRSTF) == (RCC_CSR2_PWRRSTF)) ? 1UL : 0UL); in LL_RCC_IsActiveFlag_PWRRST()
[all …]
Dstm32c0xx_hal_rcc.h1648 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR2, RCC_CSR2_LSION)
1650 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR2, RCC_CSR2_LSION)
1956 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR2 |= RCC_CSR2_RMVF)
1979 … ((((__FLAG__) >> 5U) == RCC_CSR2_REG_INDEX) ? RCC->CSR2 : RCC->CIFR))) & \
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_hal_rcc.c465 while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) in HAL_RCC_OscConfig()
482 while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U) in HAL_RCC_OscConfig()
731 if (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) in HAL_RCC_ClockConfig()
1049 regval = RCC->CSR2; in HAL_RCC_GetOscConfig()
Dstm32c0xx_hal_rcc_ex.c306 else if ((HAL_IS_BIT_SET(RCC->CSR2, RCC_CSR2_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI)) in HAL_RCCEx_GetPeriphCLKFreq()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_pwr.c340 SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity)); in HAL_PWR_EnableWakeUpPin()
363 CLEAR_BIT(PWR->CSR2, WakeUpPinx); in HAL_PWR_DisableWakeUpPin()
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h364 …__IO uint32_t CSR2; /*!< RCC Control and status Register 2, … member
Dstm32c031xx.h366 …__IO uint32_t CSR2; /*!< RCC Control and status Register 2, … member
Dstm32c071xx.h389 …__IO uint32_t CSR2; /*!< RCC Control and status Register 2, … member
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h499 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member
Dstm32f722xx.h499 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member
Dstm32f730xx.h500 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member
Dstm32f733xx.h500 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member
Dstm32f732xx.h500 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member
Dstm32f750xx.h696 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member
Dstm32f745xx.h646 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member
Dstm32f756xx.h696 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member
Dstm32f746xx.h695 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member
Dstm32f765xx.h691 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member
Dstm32f777xx.h742 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member
Dstm32f767xx.h741 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ member

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