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Searched refs:CSR1 (Results 1 – 25 of 88) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_rcc.h901 SET_BIT(RCC->CSR1, RCC_CSR1_LSEON); in LL_RCC_LSE_Enable()
911 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEON); in LL_RCC_LSE_Disable()
921 SET_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); in LL_RCC_LSE_EnableBypass()
931 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); in LL_RCC_LSE_DisableBypass()
947 MODIFY_REG(RCC->CSR1, RCC_CSR1_LSEDRV, LSEDrive); in LL_RCC_LSE_SetDriveCapability()
961 return (uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_LSEDRV)); in LL_RCC_LSE_GetDriveCapability()
971 SET_BIT(RCC->CSR1, RCC_CSR1_LSECSSON); in LL_RCC_LSE_EnableCSS()
983 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSECSSON); in LL_RCC_LSE_DisableCSS()
993 return ((READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == (RCC_CSR1_LSERDY)) ? 1UL : 0UL); in LL_RCC_LSE_IsReady()
1003 return ((READ_BIT(RCC->CSR1, RCC_CSR1_LSECSSD) == (RCC_CSR1_LSECSSD)) ? 1UL : 0UL); in LL_RCC_LSE_IsCSSDetected()
[all …]
Dstm32c0xx_hal_rcc.h1537 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR1, RCC_CSR1_RTCRST)
1539 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCRST)
1552 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR1, RCC_CSR1_RTCEN)
1554 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCEN)
1713 SET_BIT(RCC->CSR1, RCC_CSR1_LSEON); \
1717 SET_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); \
1718 SET_BIT(RCC->CSR1, RCC_CSR1_LSEON); \
1722 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEON); \
1723 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); \
1771 MODIFY_REG( RCC->CSR1, RCC_CSR1_RTCSEL, (__RTC_CLKSOURCE__))
[all …]
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_hal_pwr.h379 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
380 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
381 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
404 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
405 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
406 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
421 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
422 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\
423 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
440 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\
[all …]
Dstm32h7xx_ll_pwr.h1880 return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
1890 return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_ACTVOS()
1900 return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_AVDO()
1911 return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_MMCVDO()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/include/
Dstm32f7xx_ll_pwr.h447 SET_BIT(PWR->CSR1, PWR_CSR1_BRE); in LL_PWR_EnableBkUpRegulator()
457 CLEAR_BIT(PWR->CSR1, PWR_CSR1_BRE); in LL_PWR_DisableBkUpRegulator()
467 return (READ_BIT(PWR->CSR1, PWR_CSR1_BRE) == (PWR_CSR1_BRE)); in LL_PWR_IsEnabledBkUpRegulator()
742 SET_BIT(PWR->CSR1, PWR_CSR1_EIWUP); in LL_PWR_EnableInternalWakeUp()
752 CLEAR_BIT(PWR->CSR1, PWR_CSR1_EIWUP); in LL_PWR_DisableInternalWakeUp()
762 return (READ_BIT(PWR->CSR1, PWR_CSR1_EIWUP) == (PWR_CSR1_EIWUP)); in LL_PWR_IsEnabledInternalWakeUp()
840 return (READ_BIT(PWR->CSR1, PWR_CSR1_SBF) == (PWR_CSR1_SBF)); in LL_PWR_IsActiveFlag_SB()
850 return (READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)); in LL_PWR_IsActiveFlag_PVDO()
860 return (READ_BIT(PWR->CSR1, PWR_CSR1_BRR) == (PWR_CSR1_BRR)); in LL_PWR_IsActiveFlag_BRR()
870 return (READ_BIT(PWR->CSR1, PWR_CSR1_VOSRDY) == (PWR_CSR1_VOSRDY)); in LL_PWR_IsActiveFlag_VOS()
[all …]
Dstm32f7xx_hal_pwr_ex.h143 #define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
147 #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= (PWR_FLAG_UDRDY | PWR_CSR1_EIWUP))
Dstm32f7xx_hal_pwr.h191 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dsystem_stm32h7xx_dualcore_bootcm4_cm7gated.c440 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
450 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
456 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
462 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
468 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
474 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
480 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
486 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
492 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
Dsystem_stm32h7xx_dualcore_bootcm7_cm4gated.c446 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
456 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
462 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
468 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
474 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
480 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
486 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
492 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
498 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
Dsystem_stm32h7xx_dualcore_boot_cm4_cm7.c448 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
458 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
464 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
470 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
476 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
482 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
488 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
494 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
500 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
Dsystem_stm32h7xx_singlecore.c443 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
453 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
459 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
465 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
471 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
477 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
483 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
489 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
495 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
Dsystem_stm32h7xx.c478 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
488 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
494 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
500 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
506 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
512 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
518 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
524 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
530 while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) in ExitRun0Mode()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_pwr.h540 SET_BIT(PWR->CSR1, PWR_CSR1_BREN); in LL_PWR_EnableBkUpRegulator()
550 CLEAR_BIT(PWR->CSR1, PWR_CSR1_BREN); in LL_PWR_DisableBkUpRegulator()
560 return ((READ_BIT(PWR->CSR1, PWR_CSR1_BREN) == (PWR_CSR1_BREN)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpRegulator()
570 SET_BIT(PWR->CSR1, PWR_CSR1_MONEN); in LL_PWR_EnableMonitoring()
580 CLEAR_BIT(PWR->CSR1, PWR_CSR1_MONEN); in LL_PWR_DisableMonitoring()
590 return ((READ_BIT(PWR->CSR1, PWR_CSR1_MONEN) == (PWR_CSR1_MONEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledMonitoring()
1654 return ((READ_BIT(PWR->CSR1, PWR_CSR1_BRRDY) == (PWR_CSR1_BRRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_BRRDY()
1664 return ((READ_BIT(PWR->CSR1, PWR_CSR1_VBATL) == (PWR_CSR1_VBATL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATL()
1674 return ((READ_BIT(PWR->CSR1, PWR_CSR1_VBATH) == (PWR_CSR1_VBATH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATH()
1684 return ((READ_BIT(PWR->CSR1, PWR_CSR1_TEMPL) == (PWR_CSR1_TEMPL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPL()
[all …]
Dstm32h7rsxx_hal_pwr.h284 … ((__FLAG__) == PWR_FLAG_BRRDY) ? ((PWR->CSR1 & PWR_CSR1_BRRDY) == PWR_CSR1_BRRDY) : \
285 … ((__FLAG__) == PWR_FLAG_VBATL) ? ((PWR->CSR1 & PWR_CSR1_VBATL) == PWR_CSR1_VBATL) : \
286 … ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CSR1 & PWR_CSR1_VBATH) == PWR_CSR1_VBATH) : \
287 … ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CSR1 & PWR_CSR1_TEMPL) == PWR_CSR1_TEMPL) : \
288 … ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CSR1 & PWR_CSR1_TEMPH) == PWR_CSR1_TEMPH) : \
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_hal_rcc_ex.c121 tmpregister = READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL); in HAL_RCCEx_PeriphCLKConfig()
127 tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL)); in HAL_RCCEx_PeriphCLKConfig()
132 RCC->CSR1 = tmpregister; in HAL_RCCEx_PeriphCLKConfig()
142 while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) in HAL_RCCEx_PeriphCLKConfig()
301 if ((HAL_IS_BIT_SET(RCC->CSR1, RCC_CSR1_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE)) in HAL_RCCEx_GetPeriphCLKFreq()
344 … else if ((HAL_IS_BIT_SET(RCC->CSR1, RCC_CSR1_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) in HAL_RCCEx_GetPeriphCLKFreq()
490 MODIFY_REG(RCC->CSR1, RCC_CSR1_LSCOSEL | RCC_CSR1_LSCOEN, LSCOSource | RCC_CSR1_LSCOEN); in HAL_RCCEx_EnableLSCO()
501 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSCOEN); in HAL_RCCEx_DisableLSCO()
Dstm32c0xx_hal_rcc.c521 while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) in HAL_RCC_OscConfig()
535 while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U) in HAL_RCC_OscConfig()
740 if (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) in HAL_RCC_ClockConfig()
1043 regval = RCC->CSR1; in HAL_RCC_GetOscConfig()
1132 SET_BIT(RCC->CSR1, RCC_CSR1_LSECSSON) ; in HAL_RCC_EnableLSECSS()
1143 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSECSSON) ; in HAL_RCC_DisableLSECSS()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_pwr_ex.c783 SET_BIT(PWR->CSR1, PWR_CSR1_BREN); in HAL_PWREx_EnableBkUpReg()
789 while ((PWR->CSR1 & PWR_CSR1_BRRDY) == 0U) in HAL_PWREx_EnableBkUpReg()
809 CLEAR_BIT(PWR->CSR1, PWR_CSR1_BREN); in HAL_PWREx_DisableBkUpReg()
815 while ((PWR->CSR1 & PWR_CSR1_BRRDY) != 0U) in HAL_PWREx_DisableBkUpReg()
1181 SET_BIT(PWR->CSR1, PWR_CSR1_MONEN); in HAL_PWREx_EnableMonitoring()
1191 CLEAR_BIT(PWR->CSR1, PWR_CSR1_MONEN); in HAL_PWREx_DisableMonitoring()
1205 regValue = READ_BIT(PWR->CSR1, (PWR_CSR1_TEMPH | PWR_CSR1_TEMPL)); in HAL_PWREx_GetTemperatureLevel()
1237 regValue = READ_BIT(PWR->CSR1, (PWR_CSR1_VBATH | PWR_CSR1_VBATL)); in HAL_PWREx_GetVBATLevel()
/hal_stm32-latest/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_hal_pwr_ex.c139 PWR->CSR1 |= PWR_CSR1_BRE; in HAL_PWREx_EnableBkUpReg()
143 PWR->CSR1 |= PWR_CSR1_EIWUP; in HAL_PWREx_EnableBkUpReg()
168 PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE); in HAL_PWREx_DisableBkUpReg()
172 PWR->CSR1 |= PWR_CSR1_EIWUP; in HAL_PWREx_DisableBkUpReg()
/hal_stm32-latest/stm32cube/stm32mp1xx/drivers/include/
Dstm32mp1xx_hal_pwr.h197 ((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
198 ((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
213 ((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
214 ((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
Dstm32mp1xx_ll_pwr.h900 return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
910 return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_AVDO()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_pwr_ex.c425 if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling) in HAL_PWREx_ControlVoltageScaling()
466 if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1) in HAL_PWREx_ControlVoltageScaling()
519 return (PWR->CSR1 & PWR_CSR1_ACTVOS); in HAL_PWREx_GetVoltageRange()
1953 if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U) in HAL_PWREx_GetMMCVoltage()
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h363 …__IO uint32_t CSR1; /*!< RCC Control and status Register 1, … member
Dstm32c031xx.h365 …__IO uint32_t CSR1; /*!< RCC Control and status Register 1, … member
Dstm32c071xx.h388 …__IO uint32_t CSR1; /*!< RCC Control and status Register 1, … member
/hal_stm32-latest/stm32cube/stm32f7xx/soc/
Dstm32f723xx.h497 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ member

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