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Searched refs:CRS_CFGR_FELIM_Pos (Results 1 – 25 of 152) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32f0xx/drivers/include/
Dstm32f0xx_ll_crs.h330 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); in LL_CRS_SetFreqErrorLimit()
340 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); in LL_CRS_GetFreqErrorLimit()
455 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); in LL_CRS_ConfigSynchronization()
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_ll_crs.h357 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); in LL_CRS_SetFreqErrorLimit()
367 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); in LL_CRS_GetFreqErrorLimit()
483 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); in LL_CRS_ConfigSynchronization()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_ll_crs.h330 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); in LL_CRS_SetFreqErrorLimit()
340 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); in LL_CRS_GetFreqErrorLimit()
455 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); in LL_CRS_ConfigSynchronization()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/include/
Dstm32h7rsxx_ll_crs.h331 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); in LL_CRS_SetFreqErrorLimit()
341 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); in LL_CRS_GetFreqErrorLimit()
461 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); in LL_CRS_ConfigSynchronization()
Dstm32h7rsxx_hal_rcc_ex.h1971 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) ((__VALUE__) <= (CRS_CFGR_FELIM >> CRS_CFGR_FELIM_Pos))
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/include/
Dstm32l4xx_ll_crs.h335 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); in LL_CRS_SetFreqErrorLimit()
345 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); in LL_CRS_GetFreqErrorLimit()
460 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); in LL_CRS_ConfigSynchronization()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/include/
Dstm32l5xx_ll_crs.h330 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); in LL_CRS_SetFreqErrorLimit()
340 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); in LL_CRS_GetFreqErrorLimit()
455 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); in LL_CRS_ConfigSynchronization()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/include/
Dstm32h7xx_ll_crs.h330 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); in LL_CRS_SetFreqErrorLimit()
340 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); in LL_CRS_GetFreqErrorLimit()
455 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); in LL_CRS_ConfigSynchronization()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/include/
Dstm32g4xx_ll_crs.h329 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); in LL_CRS_SetFreqErrorLimit()
339 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); in LL_CRS_GetFreqErrorLimit()
455 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); in LL_CRS_ConfigSynchronization()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/include/
Dstm32wbxx_ll_crs.h51 #define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_ll_crs.h51 #define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
/hal_stm32-latest/stm32cube/stm32h5xx/drivers/include/
Dstm32h5xx_ll_crs.h50 #define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_crs.h50 #define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_ll_crs.h52 #define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_hal_rcc_ex.c605 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); in HAL_RCCEx_CRSConfig()
/hal_stm32-latest/stm32cube/stm32l0xx/drivers/src/
Dstm32l0xx_hal_rcc_ex.c944 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); in HAL_RCCEx_CRSConfig()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/src/
Dstm32u0xx_hal_rcc_ex.c1545 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); in HAL_RCCEx_CRSConfig()
/hal_stm32-latest/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_hal_rcc_ex.c1625 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); in HAL_RCCEx_CRSConfig()
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_hal_rcc_ex.c1395 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); in HAL_RCCEx_CRSConfig()
/hal_stm32-latest/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_hal_rcc_ex.c1586 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); in HAL_RCCEx_CRSConfig()
/hal_stm32-latest/stm32cube/stm32h7rsxx/drivers/src/
Dstm32h7rsxx_hal_rcc_ex.c2915 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); in HAL_RCCEx_CRSConfig()
/hal_stm32-latest/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_rcc_ex.c2139 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); in HAL_RCCEx_CRSConfig()
/hal_stm32-latest/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_rcc_ex.c3415 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); in HAL_RCCEx_CRSConfig()
/hal_stm32-latest/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_hal_rcc_ex.c2624 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); in HAL_RCCEx_CRSConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_rcc_ex.c3798 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); in HAL_RCCEx_CRSConfig()

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