1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_crs.h
4 * @author MCD Application Team
5 * @brief Header file of CRS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef STM32C0xx_LL_CRS_H
38 #define STM32C0xx_LL_CRS_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32c0xx.h"
46
47 /** @addtogroup STM32C0xx_LL_Driver
48 * @{
49 */
50
51 #if defined(CRS)
52
53 /** @defgroup CRS_LL CRS
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61 /** @defgroup CRS_LL_Private_Constants CRS Private Constants
62 * @{
63 */
64
65
66 /**
67 * @}
68 */
69
70 /* Private macros ------------------------------------------------------------*/
71
72 /* Exported types ------------------------------------------------------------*/
73 /* Exported constants --------------------------------------------------------*/
74 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
75 * @{
76 */
77
78 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
79 * @brief Flags defines which can be used with LL_CRS_ReadReg function
80 * @{
81 */
82 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
83 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
84 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
85 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
86 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
87 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
88 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
89 /**
90 * @}
91 */
92
93 /** @defgroup CRS_LL_EC_IT IT Defines
94 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
95 * @{
96 */
97 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
98 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
99 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
100 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
101 /**
102 * @}
103 */
104
105 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
106 * @{
107 */
108 #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
109 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
110 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
111 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
112 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
113 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
114 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
115 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
116 /**
117 * @}
118 */
119
120 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
121 * @{
122 */
123 #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
124 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
125 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
126 /**
127 * @}
128 */
129
130 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
131 * @{
132 */
133 #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
134 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
135 /**
136 * @}
137 */
138
139 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
140 * @{
141 */
142 #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
143 #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
144 /**
145 * @}
146 */
147
148 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
149 * @{
150 */
151 /**
152 * @brief Reset value of the RELOAD field
153 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
154 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
155 */
156 #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
157
158 /**
159 * @brief Reset value of Frequency error limit.
160 */
161 #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
162
163 /**
164 * @brief Reset value of the HSI48 Calibration field
165 * @note The default value is 64, which corresponds to the middle of the trimming interval.
166 * The trimming step is around 67 kHz between two consecutive TRIM steps.
167 * A higher TRIM value corresponds to a higher output frequency
168 */
169 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x40U)
170 /**
171 * @}
172 */
173
174 /**
175 * @}
176 */
177
178 /* Exported macro ------------------------------------------------------------*/
179 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
180 * @{
181 */
182
183 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
184 * @{
185 */
186
187 /**
188 * @brief Write a value in CRS register
189 * @param __INSTANCE__ CRS Instance
190 * @param __REG__ Register to be written
191 * @param __VALUE__ Value to be written in the register
192 * @retval None
193 */
194 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
195
196 /**
197 * @brief Read a value in CRS register
198 * @param __INSTANCE__ CRS Instance
199 * @param __REG__ Register to be read
200 * @retval Register value
201 */
202 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
203 /**
204 * @}
205 */
206
207 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
208 * @{
209 */
210
211 /**
212 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
213 * @note The RELOAD value should be selected according to the ratio between
214 * the target frequency and the frequency of the synchronization source after
215 * prescaling. It is then decreased by one in order to reach the expected
216 * synchronization on the zero value. The formula is the following:
217 * RELOAD = (fTARGET / fSYNC) -1
218 * @param __FTARGET__ Target frequency (value in Hz)
219 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
220 * @retval Reload value (in Hz)
221 */
222 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
223
224 /**
225 * @}
226 */
227
228 /**
229 * @}
230 */
231
232 /* Exported functions --------------------------------------------------------*/
233 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
234 * @{
235 */
236
237 /** @defgroup CRS_LL_EF_Configuration Configuration
238 * @{
239 */
240
241 /**
242 * @brief Enable Frequency error counter
243 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
244 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
245 * @retval None
246 */
LL_CRS_EnableFreqErrorCounter(void)247 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
248 {
249 SET_BIT(CRS->CR, CRS_CR_CEN);
250 }
251
252 /**
253 * @brief Disable Frequency error counter
254 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
255 * @retval None
256 */
LL_CRS_DisableFreqErrorCounter(void)257 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
258 {
259 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
260 }
261
262 /**
263 * @brief Check if Frequency error counter is enabled or not
264 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
265 * @retval State of bit (1 or 0).
266 */
LL_CRS_IsEnabledFreqErrorCounter(void)267 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
268 {
269 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
270 }
271
272 /**
273 * @brief Enable Automatic trimming counter
274 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
275 * @retval None
276 */
LL_CRS_EnableAutoTrimming(void)277 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
278 {
279 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
280 }
281
282 /**
283 * @brief Disable Automatic trimming counter
284 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
285 * @retval None
286 */
LL_CRS_DisableAutoTrimming(void)287 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
288 {
289 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
290 }
291
292 /**
293 * @brief Check if Automatic trimming is enabled or not
294 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
295 * @retval State of bit (1 or 0).
296 */
LL_CRS_IsEnabledAutoTrimming(void)297 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
298 {
299 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
300 }
301
302 /**
303 * @brief Set HSI48 oscillator smooth trimming
304 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
305 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
306 * @param Value a number between Min_Data = 0 and Max_Data = 63
307 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
308 * @retval None
309 */
LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)310 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
311 {
312 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
313 }
314
315 /**
316 * @brief Get HSI48 oscillator smooth trimming
317 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
318 * @retval a number between Min_Data = 0 and Max_Data = 63
319 */
LL_CRS_GetHSI48SmoothTrimming(void)320 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
321 {
322 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
323 }
324
325 /**
326 * @brief Set counter reload value
327 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
328 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
329 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
330 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
331 * @retval None
332 */
LL_CRS_SetReloadCounter(uint32_t Value)333 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
334 {
335 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
336 }
337
338 /**
339 * @brief Get counter reload value
340 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
341 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
342 */
LL_CRS_GetReloadCounter(void)343 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
344 {
345 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
346 }
347
348 /**
349 * @brief Set frequency error limit
350 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
351 * @param Value a number between Min_Data = 0 and Max_Data = 255
352 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
353 * @retval None
354 */
LL_CRS_SetFreqErrorLimit(uint32_t Value)355 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
356 {
357 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
358 }
359
360 /**
361 * @brief Get frequency error limit
362 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
363 * @retval A number between Min_Data = 0 and Max_Data = 255
364 */
LL_CRS_GetFreqErrorLimit(void)365 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
366 {
367 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
368 }
369
370 /**
371 * @brief Set division factor for SYNC signal
372 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
373 * @param Divider This parameter can be one of the following values:
374 * @arg @ref LL_CRS_SYNC_DIV_1
375 * @arg @ref LL_CRS_SYNC_DIV_2
376 * @arg @ref LL_CRS_SYNC_DIV_4
377 * @arg @ref LL_CRS_SYNC_DIV_8
378 * @arg @ref LL_CRS_SYNC_DIV_16
379 * @arg @ref LL_CRS_SYNC_DIV_32
380 * @arg @ref LL_CRS_SYNC_DIV_64
381 * @arg @ref LL_CRS_SYNC_DIV_128
382 * @retval None
383 */
LL_CRS_SetSyncDivider(uint32_t Divider)384 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
385 {
386 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
387 }
388
389 /**
390 * @brief Get division factor for SYNC signal
391 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
392 * @retval Returned value can be one of the following values:
393 * @arg @ref LL_CRS_SYNC_DIV_1
394 * @arg @ref LL_CRS_SYNC_DIV_2
395 * @arg @ref LL_CRS_SYNC_DIV_4
396 * @arg @ref LL_CRS_SYNC_DIV_8
397 * @arg @ref LL_CRS_SYNC_DIV_16
398 * @arg @ref LL_CRS_SYNC_DIV_32
399 * @arg @ref LL_CRS_SYNC_DIV_64
400 * @arg @ref LL_CRS_SYNC_DIV_128
401 */
LL_CRS_GetSyncDivider(void)402 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
403 {
404 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
405 }
406
407 /**
408 * @brief Set SYNC signal source
409 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
410 * @param Source This parameter can be one of the following values:
411 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
412 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
413 * @arg @ref LL_CRS_SYNC_SOURCE_USB
414 * @retval None
415 */
LL_CRS_SetSyncSignalSource(uint32_t Source)416 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
417 {
418 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
419 }
420
421 /**
422 * @brief Get SYNC signal source
423 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
424 * @retval Returned value can be one of the following values:
425 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
426 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
427 * @arg @ref LL_CRS_SYNC_SOURCE_USB
428 */
LL_CRS_GetSyncSignalSource(void)429 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
430 {
431 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
432 }
433
434 /**
435 * @brief Set input polarity for the SYNC signal source
436 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
437 * @param Polarity This parameter can be one of the following values:
438 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
439 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
440 * @retval None
441 */
LL_CRS_SetSyncPolarity(uint32_t Polarity)442 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
443 {
444 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
445 }
446
447 /**
448 * @brief Get input polarity for the SYNC signal source
449 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
450 * @retval Returned value can be one of the following values:
451 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
452 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
453 */
LL_CRS_GetSyncPolarity(void)454 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
455 {
456 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
457 }
458
459 /**
460 * @brief Configure CRS for the synchronization
461 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
462 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
463 * CFGR FELIM LL_CRS_ConfigSynchronization\n
464 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
465 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
466 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
467 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
468 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
469 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
470 * @param Settings This parameter can be a combination of the following values:
471 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
472 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
473 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
474 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
475 * @retval None
476 */
LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue,uint32_t ErrorLimitValue,uint32_t ReloadValue,uint32_t Settings)477 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
478 uint32_t ReloadValue, uint32_t Settings)
479 {
480 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
481 MODIFY_REG(CRS->CFGR,
482 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
483 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
484 }
485
486 /**
487 * @}
488 */
489
490 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
491 * @{
492 */
493
494 /**
495 * @brief Generate software SYNC event
496 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
497 * @retval None
498 */
LL_CRS_GenerateEvent_SWSYNC(void)499 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
500 {
501 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
502 }
503
504 /**
505 * @brief Get the frequency error direction latched in the time of the last
506 * SYNC event
507 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
508 * @retval Returned value can be one of the following values:
509 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
510 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
511 */
LL_CRS_GetFreqErrorDirection(void)512 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
513 {
514 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
515 }
516
517 /**
518 * @brief Get the frequency error counter value latched in the time of the last SYNC event
519 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
520 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
521 */
LL_CRS_GetFreqErrorCapture(void)522 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
523 {
524 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
525 }
526
527 /**
528 * @}
529 */
530
531 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
532 * @{
533 */
534
535 /**
536 * @brief Check if SYNC event OK signal occurred or not
537 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
538 * @retval State of bit (1 or 0).
539 */
LL_CRS_IsActiveFlag_SYNCOK(void)540 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
541 {
542 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
543 }
544
545 /**
546 * @brief Check if SYNC warning signal occurred or not
547 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
548 * @retval State of bit (1 or 0).
549 */
LL_CRS_IsActiveFlag_SYNCWARN(void)550 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
551 {
552 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
553 }
554
555 /**
556 * @brief Check if Synchronization or trimming error signal occurred or not
557 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
558 * @retval State of bit (1 or 0).
559 */
LL_CRS_IsActiveFlag_ERR(void)560 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
561 {
562 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
563 }
564
565 /**
566 * @brief Check if Expected SYNC signal occurred or not
567 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
568 * @retval State of bit (1 or 0).
569 */
LL_CRS_IsActiveFlag_ESYNC(void)570 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
571 {
572 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
573 }
574
575 /**
576 * @brief Check if SYNC error signal occurred or not
577 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
578 * @retval State of bit (1 or 0).
579 */
LL_CRS_IsActiveFlag_SYNCERR(void)580 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
581 {
582 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
583 }
584
585 /**
586 * @brief Check if SYNC missed error signal occurred or not
587 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
588 * @retval State of bit (1 or 0).
589 */
LL_CRS_IsActiveFlag_SYNCMISS(void)590 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
591 {
592 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
593 }
594
595 /**
596 * @brief Check if Trimming overflow or underflow occurred or not
597 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
598 * @retval State of bit (1 or 0).
599 */
LL_CRS_IsActiveFlag_TRIMOVF(void)600 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
601 {
602 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
603 }
604
605 /**
606 * @brief Clear the SYNC event OK flag
607 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
608 * @retval None
609 */
LL_CRS_ClearFlag_SYNCOK(void)610 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
611 {
612 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
613 }
614
615 /**
616 * @brief Clear the SYNC warning flag
617 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
618 * @retval None
619 */
LL_CRS_ClearFlag_SYNCWARN(void)620 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
621 {
622 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
623 }
624
625 /**
626 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
627 * the ERR flag
628 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
629 * @retval None
630 */
LL_CRS_ClearFlag_ERR(void)631 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
632 {
633 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
634 }
635
636 /**
637 * @brief Clear Expected SYNC flag
638 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
639 * @retval None
640 */
LL_CRS_ClearFlag_ESYNC(void)641 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
642 {
643 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
644 }
645
646 /**
647 * @}
648 */
649
650 /** @defgroup CRS_LL_EF_IT_Management IT_Management
651 * @{
652 */
653
654 /**
655 * @brief Enable SYNC event OK interrupt
656 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
657 * @retval None
658 */
LL_CRS_EnableIT_SYNCOK(void)659 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
660 {
661 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
662 }
663
664 /**
665 * @brief Disable SYNC event OK interrupt
666 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
667 * @retval None
668 */
LL_CRS_DisableIT_SYNCOK(void)669 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
670 {
671 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
672 }
673
674 /**
675 * @brief Check if SYNC event OK interrupt is enabled or not
676 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
677 * @retval State of bit (1 or 0).
678 */
LL_CRS_IsEnabledIT_SYNCOK(void)679 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
680 {
681 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
682 }
683
684 /**
685 * @brief Enable SYNC warning interrupt
686 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
687 * @retval None
688 */
LL_CRS_EnableIT_SYNCWARN(void)689 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
690 {
691 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
692 }
693
694 /**
695 * @brief Disable SYNC warning interrupt
696 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
697 * @retval None
698 */
LL_CRS_DisableIT_SYNCWARN(void)699 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
700 {
701 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
702 }
703
704 /**
705 * @brief Check if SYNC warning interrupt is enabled or not
706 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
707 * @retval State of bit (1 or 0).
708 */
LL_CRS_IsEnabledIT_SYNCWARN(void)709 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
710 {
711 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
712 }
713
714 /**
715 * @brief Enable Synchronization or trimming error interrupt
716 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
717 * @retval None
718 */
LL_CRS_EnableIT_ERR(void)719 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
720 {
721 SET_BIT(CRS->CR, CRS_CR_ERRIE);
722 }
723
724 /**
725 * @brief Disable Synchronization or trimming error interrupt
726 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
727 * @retval None
728 */
LL_CRS_DisableIT_ERR(void)729 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
730 {
731 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
732 }
733
734 /**
735 * @brief Check if Synchronization or trimming error interrupt is enabled or not
736 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
737 * @retval State of bit (1 or 0).
738 */
LL_CRS_IsEnabledIT_ERR(void)739 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
740 {
741 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
742 }
743
744 /**
745 * @brief Enable Expected SYNC interrupt
746 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
747 * @retval None
748 */
LL_CRS_EnableIT_ESYNC(void)749 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
750 {
751 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
752 }
753
754 /**
755 * @brief Disable Expected SYNC interrupt
756 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
757 * @retval None
758 */
LL_CRS_DisableIT_ESYNC(void)759 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
760 {
761 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
762 }
763
764 /**
765 * @brief Check if Expected SYNC interrupt is enabled or not
766 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
767 * @retval State of bit (1 or 0).
768 */
LL_CRS_IsEnabledIT_ESYNC(void)769 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
770 {
771 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
772 }
773
774 /**
775 * @}
776 */
777
778 #if defined(USE_FULL_LL_DRIVER)
779 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
780 * @{
781 */
782
783 ErrorStatus LL_CRS_DeInit(void);
784
785 /**
786 * @}
787 */
788 #endif /* USE_FULL_LL_DRIVER */
789
790 /**
791 * @}
792 */
793
794 /**
795 * @}
796 */
797
798 #endif /* defined(CRS) */
799
800 /**
801 * @}
802 */
803
804 #ifdef __cplusplus
805 }
806 #endif
807
808 #endif /* STM32C0xx_LL_CRS_H */
809
810 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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