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Searched refs:BDCR2 (Results 1 – 25 of 28) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_rcc_ex.c359 tmpreg2 = RCC->BDCR2; in HAL_RCCEx_PeriphCLKConfig()
366 RCC->BDCR2 = tmpreg2; in HAL_RCCEx_PeriphCLKConfig()
1281 WRITE_REG(RCC->BDCR2, (pConfig->FreqTempSens | pConfig->OpMode)); in HAL_RCCEx_LSI2SetConfig()
1298 regbdcr2 = RCC->BDCR2; in HAL_RCCEx_LSI2GetConfig()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_pwr.h2428 SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE); in LL_PWR_EnableBatteryCharging()
2438 CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE); in LL_PWR_DisableBatteryCharging()
2448 return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_VBE) == (PWR_BDCR2_VBE)) ? 1UL : 0UL); in LL_PWR_IsEnabledBatteryCharging()
2461 MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
2473 return (uint32_t)(READ_BIT(PWR->BDCR2, PWR_BDCR2_VBRS)); in LL_PWR_GetBattChargResistor()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_pwr.h554 SET_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN); in LL_PWR_EnableBkpSRAMSBRetention()
564 CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN); in LL_PWR_DisableBkpSRAMSBRetention()
574 return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN) == (PWR_BDCR2_BKPRBSEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkpSRAMSBRetention()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_rcc.h1329 MODIFY_REG(RCC->BDCR2, RCC_BDCR2_LSI2CFG, Sensitivity); in LL_RCC_LSI2_SetTempSensitivity()
1342 return (uint32_t)(READ_BIT(RCC->BDCR2, RCC_BDCR2_LSI2CFG)); in LL_RCC_LSI2_GetTempSensitivity()
1356 MODIFY_REG(RCC->BDCR2, RCC_BDCR2_LSI2MODE, Mode); in LL_RCC_LSI2_SetOperatingMode()
1369 return (uint32_t)(READ_BIT(RCC->BDCR2, RCC_BDCR2_LSI2MODE)); in LL_RCC_LSI2_GetOperatingMode()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_pwr_ex.c1528 MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, ResistorValue); in HAL_PWREx_EnableBatteryCharging()
1531 SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE); in HAL_PWREx_EnableBatteryCharging()
1540 CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE); in HAL_PWREx_DisableBatteryCharging()
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_pwr_ex.c498 SET_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN); in HAL_PWREx_EnableBkupRAMRetention()
509 CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_BKPRBSEN); in HAL_PWREx_DisableBkupRAMRetention()
Dstm32n6xx_ll_pwr.c63 WRITE_REG(PWR->BDCR2, 0x00000000U); in LL_PWR_DeInit()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h603 …__IO uint32_t BDCR2; /*!< Backup Domain Control Register 2 Address … member
Dstm32wba52xx.h696 …__IO uint32_t BDCR2; /*!< Backup Domain Control Register 2 Address … member
Dstm32wba54xx.h723 …__IO uint32_t BDCR2; /*!< Backup Domain Control Register 2 Address … member
Dstm32wba5mxx.h723 …__IO uint32_t BDCR2; /*!< Backup Domain Control Register 2 Address … member
Dstm32wba55xx.h723 …__IO uint32_t BDCR2; /*!< Backup Domain Control Register 2 Address … member
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h895 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
Dstm32u535xx.h829 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
Dstm32u575xx.h892 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
Dstm32u585xx.h959 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
Dstm32u595xx.h929 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
Dstm32u5a5xx.h996 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
Dstm32u5f7xx.h1090 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
Dstm32u599xx.h1110 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
Dstm32u5g7xx.h1157 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
Dstm32u5f9xx.h1194 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
Dstm32u5a9xx.h1177 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
Dstm32u5g9xx.h1261 …__IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x… member
/hal_stm32-latest/stm32cube/stm32n6xx/soc/
Dstm32n645xx.h1864 …__IO uint32_t BDCR2; /*!< PWR Backup domain control register 2 Address offse… member

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