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Searched refs:BDCR1 (Results 1 – 25 of 33) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_rcc_ex.c352 tmpreg1 = (RCC->BDCR1 & ~RCC_BDCR1_RTCSEL); in HAL_RCCEx_PeriphCLKConfig()
371 RCC->BDCR1 = (tmpreg1 | PeriphClkInit->RTCClockSelection); in HAL_RCCEx_PeriphCLKConfig()
388 while (READ_BIT(RCC->BDCR1, (tmpreg2 << 1)) == 0x00u) in HAL_RCCEx_PeriphCLKConfig()
513 tmpreg = RCC->BDCR1; in HAL_RCCEx_GetPeriphCLKConfig()
579 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) in HAL_RCCEx_GetPeriphCLKFreq()
608 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) in HAL_RCCEx_GetPeriphCLKFreq()
659 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY)) in HAL_RCCEx_GetPeriphCLKFreq()
665 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV)) in HAL_RCCEx_GetPeriphCLKFreq()
671 else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY)) in HAL_RCCEx_GetPeriphCLKFreq()
690 if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) in HAL_RCCEx_GetPeriphCLKFreq()
[all …]
Dstm32wbaxx_hal_rcc.c524 tmpreg1 = RCC->BDCR1; in HAL_RCC_OscConfig()
545 RCC->BDCR1 = tmpreg1; in HAL_RCC_OscConfig()
551 while (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI1RDY) != 0x00u) in HAL_RCC_OscConfig()
572 RCC->BDCR1 = tmpreg1; in HAL_RCC_OscConfig()
578 while (READ_BIT(RCC->BDCR1, (RCC_OscInitStruct->LSIState << 1)) == 0x00u) in HAL_RCC_OscConfig()
590 RCC->BDCR1 = tmpreg1; in HAL_RCC_OscConfig()
596 while (READ_BIT(RCC->BDCR1, (mask << 1)) != 0x00u) in HAL_RCC_OscConfig()
609 RCC->BDCR1 = tmpreg1; in HAL_RCC_OscConfig()
615 while (READ_BIT(RCC->BDCR1, (mask << 1)) != 0x00u) in HAL_RCC_OscConfig()
668 tmpreg1 = (RCC->BDCR1 & ~RCC_BDCR1_LSESYSEN); in HAL_RCC_OscConfig()
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Dstm32wbaxx_ll_rcc.c560 if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) in LL_RCC_GetLPTIMClockFreq()
600 if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) in LL_RCC_GetLPTIMClockFreq()
736 if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) in LL_RCC_GetRNGClockFreq()
/hal_stm32-latest/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_rcc.h1033 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEON); in LL_RCC_LSE_Enable()
1043 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEON); in LL_RCC_LSE_Disable()
1053 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); in LL_RCC_LSE_EnableBypass()
1063 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); in LL_RCC_LSE_DisableBypass()
1073 SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON); in LL_RCC_LSE_EnableGlitchFilter()
1083 CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON); in LL_RCC_LSE_DisableGlitchFilter()
1098 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSETRIM, LSETrim); in LL_RCC_LSE_SetClockTrimming()
1113 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSETRIM)); in LL_RCC_LSE_GetClockTrimming()
1128 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSEDRV, LSEDrive); in LL_RCC_LSE_SetDriveCapability()
1141 return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSEDRV)); in LL_RCC_LSE_GetDriveCapability()
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Dstm32wbaxx_hal_rcc.h1743 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR1, RCC_BDCR1_BDRST)
1744 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_BDRST)
1805 #define __HAL_RCC_LSI1_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON)
1806 #define __HAL_RCC_LSI1_DISABLE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON)
1818 #define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV, __DI…
1832 #define __HAL_RCC_LSI2_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON)
1833 #define __HAL_RCC_LSI2_DISABLE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON)
1866 #define __HAL_RCC_LSESYS_ENABLE() SET_BIT(RCC->BDCR1,RCC_BDCR1_LSESYSEN)
1867 #define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR1,RCC_BDCR1_LSESYSEN)
1875 #define __HAL_RCC_LSE_GlitchFilter_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON )
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Dstm32wbaxx_hal_rcc_ex.h763 MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL, (__RADIOST_CLKSOURCE__))
772 #define __HAL_RCC_GET_RADIOSLPTIM_SOURCE() READ_BIT(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL)
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/include/
Dstm32n6xx_ll_pwr.h520 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in LL_PWR_EnableMonitoring()
530 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in LL_PWR_DisableMonitoring()
540 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledMonitoring()
1475 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_VBATL) == (PWR_BDCR1_VBATL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATL()
1485 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_VBATH) == (PWR_BDCR1_VBATH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATH()
1495 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_TEMPL) == (PWR_BDCR1_TEMPL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPL()
1505 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_TEMPH) == (PWR_BDCR1_TEMPH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPH()
Dstm32n6xx_hal_pwr.h341 …((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->BDCR1 & PWR_BDCR1_TEMPH) == PWR_BDCR1_TEMPH) …
342 …((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->BDCR1 & PWR_BDCR1_TEMPL) == PWR_BDCR1_TEMPL) …
343 …((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->BDCR1 & PWR_BDCR1_VBATH) == PWR_BDCR1_VBATH) …
344 …((__FLAG__) == PWR_FLAG_VBATL) ? ((PWR->BDCR1 & PWR_BDCR1_VBATL) == PWR_BDCR1_VBATL) …
/hal_stm32-latest/stm32cube/stm32n6xx/drivers/src/
Dstm32n6xx_hal_pwr_ex.c676 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in HAL_PWREx_EnableMonitoring()
688 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in HAL_PWREx_DisableMonitoring()
702 regValue = READ_BIT(PWR->BDCR1, (PWR_BDCR1_TEMPH | PWR_BDCR1_TEMPL)); in HAL_PWREx_GetTemperatureLevel()
734 regValue = READ_BIT(PWR->BDCR1, (PWR_BDCR1_VBATH | PWR_BDCR1_VBATL)); in HAL_PWREx_GetVBATLevel()
Dstm32n6xx_ll_pwr.c62 WRITE_REG(PWR->BDCR1, 0x00000000U); in LL_PWR_DeInit()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/include/
Dstm32u5xx_ll_pwr.h2367 SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN); in LL_PWR_EnableBkUpRegulator()
2377 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN); in LL_PWR_DisableBkUpRegulator()
2387 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_BREN) == (PWR_BDCR1_BREN)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpRegulator()
2397 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in LL_PWR_EnableMonitoring()
2407 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in LL_PWR_DisableMonitoring()
2418 return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledMonitoring()
/hal_stm32-latest/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_pwr_ex.c1371 SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in HAL_PWREx_EnableMonitoring()
1380 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); in HAL_PWREx_DisableMonitoring()
2317 SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN); in HAL_PWREx_EnableBkupRAMRetention()
2337 CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN); in HAL_PWREx_DisableBkupRAMRetention()
/hal_stm32-latest/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h601 …__IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address … member
Dstm32wba52xx.h694 …__IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address … member
Dstm32wba54xx.h721 …__IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address … member
Dstm32wba5mxx.h721 …__IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address … member
Dstm32wba55xx.h721 …__IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address … member
/hal_stm32-latest/stm32cube/stm32u5xx/soc/
Dstm32u545xx.h894 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u535xx.h828 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u575xx.h891 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u585xx.h958 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u595xx.h928 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u5a5xx.h995 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u5f7xx.h1089 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member
Dstm32u599xx.h1109 …__IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x… member

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