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Searched refs:AHBSMENR (Results 1 – 25 of 46) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32l0xx/drivers/include/
Dstm32l0xx_hal_rcc.h939 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
940 #define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
941 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
942 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
944 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
945 #define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
946 #define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
947 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
1018 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != 0…
1019 #define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != 0…
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Dstm32l0xx_ll_bus.h353 SET_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep()
355 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_EnableClockSleep()
382 CLEAR_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_DisableClockSleep()
Dstm32l0xx_hal_rcc_ex.h1107 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
1108 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
1109 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
1110 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
1112 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) !=…
1113 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) !=…
1114 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN) ==…
1115 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) ==…
/hal_stm32-latest/stm32cube/stm32g0xx/drivers/include/
Dstm32g0xx_hal_rcc.h1940 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1942 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
1944 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
1945 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)
1946 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
1948 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)
1951 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)
1953 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1955 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
1957 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
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Dstm32g0xx_ll_bus.h366 SET_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_EnableClockStopSleep()
368 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_EnableClockStopSleep()
392 CLEAR_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_DisableClockStopSleep()
/hal_stm32-latest/stm32cube/stm32c0xx/drivers/include/
Dstm32c0xx_hal_rcc.h1266 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1267 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
1268 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)
1269 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
1271 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1272 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
1273 #define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN)
1274 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
1401 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) !=…
1402 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!=…
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Dstm32c0xx_ll_bus.h274 SET_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_EnableClockStopSleep()
276 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_EnableClockStopSleep()
295 CLEAR_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_DisableClockStopSleep()
/hal_stm32-latest/stm32cube/stm32u0xx/drivers/include/
Dstm32u0xx_hal_rcc.h1744 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1747 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
1750 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)
1752 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAM1SMEN)
1754 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN)
1757 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN)
1760 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN)
1762 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_TSCSMEN)
1764 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN)
1767 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN)
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Dstm32u0xx_ll_bus.h358 SET_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_EnableClockStopSleep()
360 tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_EnableClockStopSleep()
390 CLEAR_BIT(RCC->AHBSMENR, Periphs); in LL_AHB1_GRP1_DisableClockStopSleep()
/hal_stm32-latest/stm32cube/stm32l0xx/soc/
Dstm32l041xx.h379 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l010x8.h344 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l010xb.h345 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l011xx.h359 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l021xx.h378 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l031xx.h360 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l051xx.h381 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l010x4.h344 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l010x6.h344 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l081xx.h408 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l071xx.h389 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l052xx.h412 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l062xx.h431 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
Dstm32l053xx.h426 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Ad… member
/hal_stm32-latest/stm32cube/stm32c0xx/soc/
Dstm32c011xx.h358 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, … member
Dstm32c031xx.h360 …__IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, … member

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