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Searched refs:TSC_IOASCR_G5_IO1_Pos (Results 1 – 25 of 77) sorted by relevance

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/hal_stm32-3.7.0/stm32cube/stm32f0xx/soc/
Dstm32f058xx.h5621 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
5622 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f051x8.h5652 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
5653 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f071xb.h6205 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
6206 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f048xx.h9391 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
9392 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f042x6.h9427 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
9428 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f072xb.h10002 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
10003 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f078xx.h9972 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
9973 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f091xc.h10659 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
10660 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f098xx.h10626 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
10627 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-3.7.0/stm32cube/stm32l0xx/soc/
Dstm32l062xx.h6315 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
6316 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l053xx.h6337 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
6338 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l052xx.h6178 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
6179 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l073xx.h6633 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
6634 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l082xx.h6611 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
6612 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l083xx.h6770 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
6771 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l063xx.h6472 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
6473 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32l072xx.h6474 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
6475 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-3.7.0/stm32cube/stm32f3xx/soc/
Dstm32f301x8.h7439 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
7440 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f318xx.h7426 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
7427 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f373xc.h10617 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
10618 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32f378xx.h10515 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
10516 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h9319 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
9320 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-3.7.0/stm32cube/stm32wbxx/soc/Include/
Dstm32wb10xx.h7920 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
7921 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
Dstm32wb15xx.h8092 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
8093 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
/hal_stm32-3.7.0/stm32cube/stm32wbxx/soc/
Dstm32wb1mxx.h8092 #define TSC_IOASCR_G5_IO1_Pos (16U) macro
8093 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */

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