/hal_stm32-3.7.0/stm32cube/stm32f0xx/soc/ |
D | stm32f058xx.h | 5621 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 5622 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32f051x8.h | 5652 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 5653 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32f071xb.h | 6205 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 6206 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32f048xx.h | 9391 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 9392 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32f042x6.h | 9427 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 9428 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32f072xb.h | 10002 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 10003 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32f078xx.h | 9972 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 9973 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32f091xc.h | 10659 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 10660 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32f098xx.h | 10626 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 10627 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
/hal_stm32-3.7.0/stm32cube/stm32l0xx/soc/ |
D | stm32l062xx.h | 6315 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 6316 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32l053xx.h | 6337 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 6338 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32l052xx.h | 6178 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 6179 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32l073xx.h | 6633 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 6634 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32l082xx.h | 6611 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 6612 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32l083xx.h | 6770 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 6771 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32l063xx.h | 6472 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 6473 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32l072xx.h | 6474 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 6475 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
/hal_stm32-3.7.0/stm32cube/stm32f3xx/soc/ |
D | stm32f301x8.h | 7439 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 7440 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32f318xx.h | 7426 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 7427 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32f373xc.h | 10617 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 10618 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32f378xx.h | 10515 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 10516 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
/hal_stm32-3.7.0/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9319 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 9320 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
/hal_stm32-3.7.0/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb10xx.h | 7920 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 7921 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
D | stm32wb15xx.h | 8092 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 8093 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|
/hal_stm32-3.7.0/stm32cube/stm32wbxx/soc/ |
D | stm32wb1mxx.h | 8092 #define TSC_IOASCR_G5_IO1_Pos (16U) macro 8093 #define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
|