1 /**
2   ******************************************************************************
3   * @file    stm32l062xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for stm32l062xx devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral's registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * Copyright (c) 2016 STMicroelectronics.
18   * All rights reserved.
19   *
20   * This software is licensed under terms that can be found in the LICENSE file
21   * in the root directory of this software component.
22   * If no LICENSE file comes with this software, it is provided AS-IS.
23   *
24   ******************************************************************************
25   */
26 
27 /** @addtogroup CMSIS
28   * @{
29   */
30 
31 /** @addtogroup stm32l062xx
32   * @{
33   */
34 
35 #ifndef __STM32L062xx_H
36 #define __STM32L062xx_H
37 
38 #ifdef __cplusplus
39  extern "C" {
40 #endif
41 
42 
43 /** @addtogroup Configuration_section_for_CMSIS
44   * @{
45   */
46 /**
47   * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
48   */
49 #define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
50 #define __MPU_PRESENT             1U /*!< STM32L0xx  provides an MPU                    */
51 #define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
52 #define __NVIC_PRIO_BITS          2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
53 #define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
54 
55 /**
56   * @}
57   */
58 
59 /** @addtogroup Peripheral_interrupt_number_definition
60   * @{
61   */
62 
63 /**
64  * @brief stm32l062xx Interrupt Number Definition, according to the selected device
65  *        in @ref Library_configuration_section
66  */
67 
68 /*!< Interrupt Number Definition */
69 typedef enum
70 {
71 /******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
72   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
73   HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
74   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
77 
78 /******  STM32L-0 specific Interrupt Numbers *********************************************************/
79   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
80   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
81   RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
82   FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
83   RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
84   EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
85   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
86   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
87   TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
88   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
89   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
90   DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
91   ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
92   LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
93   TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
94   TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
95   TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
96   TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
97   I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
98   I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
99   SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
100   SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
101   USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
102   USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
103   AES_RNG_LPUART1_IRQn        = 29,     /*!< AES and RNG and LPUART1 Interrupts                      */
104   USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
105 } IRQn_Type;
106 
107 /**
108   * @}
109   */
110 
111 #include "core_cm0plus.h"
112 #include "system_stm32l0xx.h"
113 #include <stdint.h>
114 
115 /** @addtogroup Peripheral_registers_structures
116   * @{
117   */
118 
119 /**
120   * @brief Analog to Digital Converter
121   */
122 
123 typedef struct
124 {
125   __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
126   __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
127   __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
128   __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
129   __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
130   __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
131   uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
132   uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
133   __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
134   uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
135   __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
136   uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
137   __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
138   uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
139   __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
140 } ADC_TypeDef;
141 
142 typedef struct
143 {
144   __IO uint32_t CCR;
145 } ADC_Common_TypeDef;
146 
147 /**
148   * @brief AES hardware accelerator
149   */
150 
151 typedef struct
152 {
153   __IO uint32_t CR;      /*!< AES control register,                        Address offset: 0x00 */
154   __IO uint32_t SR;      /*!< AES status register,                         Address offset: 0x04 */
155   __IO uint32_t DINR;    /*!< AES data input register,                     Address offset: 0x08 */
156   __IO uint32_t DOUTR;   /*!< AES data output register,                    Address offset: 0x0C */
157   __IO uint32_t KEYR0;   /*!< AES key register 0,                          Address offset: 0x10 */
158   __IO uint32_t KEYR1;   /*!< AES key register 1,                          Address offset: 0x14 */
159   __IO uint32_t KEYR2;   /*!< AES key register 2,                          Address offset: 0x18 */
160   __IO uint32_t KEYR3;   /*!< AES key register 3,                          Address offset: 0x1C */
161   __IO uint32_t IVR0;    /*!< AES initialization vector register 0,        Address offset: 0x20 */
162   __IO uint32_t IVR1;    /*!< AES initialization vector register 1,        Address offset: 0x24 */
163   __IO uint32_t IVR2;    /*!< AES initialization vector register 2,        Address offset: 0x28 */
164   __IO uint32_t IVR3;    /*!< AES initialization vector register 3,        Address offset: 0x2C */
165 } AES_TypeDef;
166 
167 /**
168   * @brief Comparator
169   */
170 
171 typedef struct
172 {
173   __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
174 } COMP_TypeDef;
175 
176 typedef struct
177 {
178   __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
179 } COMP_Common_TypeDef;
180 
181 
182 /**
183 * @brief CRC calculation unit
184 */
185 
186 typedef struct
187 {
188 __IO uint32_t DR;            /*!< CRC Data register,                            Address offset: 0x00 */
189 __IO uint8_t IDR;            /*!< CRC Independent data register,                Address offset: 0x04 */
190 uint8_t RESERVED0;           /*!< Reserved,                                                     0x05 */
191 uint16_t RESERVED1;          /*!< Reserved,                                                     0x06 */
192 __IO uint32_t CR;            /*!< CRC Control register,                         Address offset: 0x08 */
193 uint32_t RESERVED2;          /*!< Reserved,                                                     0x0C */
194 __IO uint32_t INIT;          /*!< Initial CRC value register,                   Address offset: 0x10 */
195 __IO uint32_t POL;           /*!< CRC polynomial register,                      Address offset: 0x14 */
196 } CRC_TypeDef;
197 
198 /**
199   * @brief Clock Recovery System
200   */
201 
202 typedef struct
203 {
204 __IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
205 __IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
206 __IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
207 __IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
208 } CRS_TypeDef;
209 
210 /**
211   * @brief Digital to Analog Converter
212   */
213 
214 typedef struct
215 {
216   __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
217   __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
218   __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
219   __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
220   __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
221   uint32_t      RESERVED0[6];  /*!<                                                                     0x14-0x28 */
222   __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
223   uint32_t      RESERVED1;     /*!<                                                                          0x30 */
224   __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
225 } DAC_TypeDef;
226 
227 /**
228   * @brief Debug MCU
229   */
230 
231 typedef struct
232 {
233   __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
234   __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
235   __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
236   __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
237 }DBGMCU_TypeDef;
238 
239 /**
240   * @brief DMA Controller
241   */
242 
243 typedef struct
244 {
245   __IO uint32_t CCR;          /*!< DMA channel x configuration register */
246   __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
247   __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
248   __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
249 } DMA_Channel_TypeDef;
250 
251 typedef struct
252 {
253   __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
254   __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
255 } DMA_TypeDef;
256 
257 typedef struct
258 {
259   __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
260 } DMA_Request_TypeDef;
261 
262 /**
263   * @brief External Interrupt/Event Controller
264   */
265 
266 typedef struct
267 {
268   __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
269   __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
270   __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
271   __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
272   __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
273   __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
274 }EXTI_TypeDef;
275 
276 /**
277   * @brief FLASH Registers
278   */
279 typedef struct
280 {
281   __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
282   __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
283   __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
284   __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
285   __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
286   __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
287   __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
288   __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
289   __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
290 } FLASH_TypeDef;
291 
292 
293 /**
294   * @brief Option Bytes Registers
295   */
296 typedef struct
297 {
298   __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
299   __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
300   __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
301 } OB_TypeDef;
302 
303 
304 /**
305   * @brief General Purpose IO
306   */
307 
308 typedef struct
309 {
310   __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
311   __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
312   __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
313   __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
314   __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
315   __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
316   __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
317   __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
318   __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
319   __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
320 }GPIO_TypeDef;
321 
322 /**
323   * @brief LPTIMIMER
324   */
325 typedef struct
326 {
327   __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
328   __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
329   __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
330   __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
331   __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
332   __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
333   __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
334   __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
335 } LPTIM_TypeDef;
336 
337 /**
338   * @brief SysTem Configuration
339   */
340 
341 typedef struct
342 {
343   __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
344   __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
345   __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
346        uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
347   __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */
348 } SYSCFG_TypeDef;
349 
350 
351 
352 /**
353   * @brief Inter-integrated Circuit Interface
354   */
355 
356 typedef struct
357 {
358   __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
359   __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
360   __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
361   __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
362   __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
363   __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
364   __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
365   __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
366   __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
367   __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
368   __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
369 }I2C_TypeDef;
370 
371 
372 /**
373   * @brief Independent WATCHDOG
374   */
375 typedef struct
376 {
377   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
378   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
379   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
380   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
381   __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
382 } IWDG_TypeDef;
383 
384 /**
385   * @brief MIFARE Firewall
386   */
387 typedef struct
388 {
389   __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
390   __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
391   __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
392   __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
393   __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
394   __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
395   __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
396   __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
397   __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
398 
399 } FIREWALL_TypeDef;
400 
401 /**
402   * @brief Power Control
403   */
404 typedef struct
405 {
406   __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
407   __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
408 } PWR_TypeDef;
409 
410 /**
411   * @brief Reset and Clock Control
412   */
413 typedef struct
414 {
415   __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
416   __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
417   __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
418   __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
419   __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
420   __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
421   __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
422   __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
423   __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
424   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
425   __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
426   __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
427   __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
428   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
429   __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
430   __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
431   __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
432   __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
433   __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
434   __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
435   __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
436 } RCC_TypeDef;
437 
438 /**
439   * @brief Random numbers generator
440   */
441 typedef struct
442 {
443   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
444   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
445   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
446 } RNG_TypeDef;
447 
448 /**
449   * @brief Real-Time Clock
450   */
451 typedef struct
452 {
453   __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
454   __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
455   __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
456   __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
457   __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
458   __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
459        uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
460   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
461   __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
462   __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
463   __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
464   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
465   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
466   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
467   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
468   __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
469   __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
470   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
471   __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
472   __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
473   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
474   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
475   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
476   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
477   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
478 } RTC_TypeDef;
479 
480 
481 /**
482   * @brief Serial Peripheral Interface
483   */
484 typedef struct
485 {
486   __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
487   __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
488   __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
489   __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
490   __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
491   __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
492   __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
493   __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
494   __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
495 } SPI_TypeDef;
496 
497 /**
498   * @brief TIM
499   */
500 typedef struct
501 {
502   __IO uint32_t CR1;       /*!< TIM control register 1,                       Address offset: 0x00 */
503   __IO uint32_t CR2;       /*!< TIM control register 2,                       Address offset: 0x04 */
504   __IO uint32_t SMCR;      /*!< TIM slave Mode Control register,              Address offset: 0x08 */
505   __IO uint32_t DIER;      /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
506   __IO uint32_t SR;        /*!< TIM status register,                          Address offset: 0x10 */
507   __IO uint32_t EGR;       /*!< TIM event generation register,                Address offset: 0x14 */
508   __IO uint32_t CCMR1;     /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
509   __IO uint32_t CCMR2;     /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
510   __IO uint32_t CCER;      /*!< TIM capture/compare enable register,          Address offset: 0x20 */
511   __IO uint32_t CNT;       /*!< TIM counter register,                         Address offset: 0x24 */
512   __IO uint32_t PSC;       /*!< TIM prescaler register,                       Address offset: 0x28 */
513   __IO uint32_t ARR;       /*!< TIM auto-reload register,                     Address offset: 0x2C */
514   uint32_t      RESERVED12;/*!< Reserved                                      Address offset: 0x30 */
515   __IO uint32_t CCR1;      /*!< TIM capture/compare register 1,               Address offset: 0x34 */
516   __IO uint32_t CCR2;      /*!< TIM capture/compare register 2,               Address offset: 0x38 */
517   __IO uint32_t CCR3;      /*!< TIM capture/compare register 3,               Address offset: 0x3C */
518   __IO uint32_t CCR4;      /*!< TIM capture/compare register 4,               Address offset: 0x40 */
519   uint32_t      RESERVED17;/*!< Reserved,                                     Address offset: 0x44 */
520   __IO uint32_t DCR;       /*!< TIM DMA control register,                     Address offset: 0x48 */
521   __IO uint32_t DMAR;      /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
522   __IO uint32_t OR;        /*!< TIM option register,                          Address offset: 0x50 */
523 } TIM_TypeDef;
524 
525 /**
526   * @brief Touch Sensing Controller (TSC)
527   */
528 typedef struct
529 {
530   __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
531   __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
532   __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
533   __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
534   __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
535   uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
536   __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
537   uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
538   __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
539   uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
540   __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
541   uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
542   __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
543   __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
544 } TSC_TypeDef;
545 
546 /**
547   * @brief Universal Synchronous Asynchronous Receiver Transmitter
548   */
549 typedef struct
550 {
551   __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
552   __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
553   __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
554   __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
555   __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
556   __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
557   __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
558   __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
559   __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
560   __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
561   __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
562 } USART_TypeDef;
563 
564 /**
565   * @brief Window WATCHDOG
566   */
567 typedef struct
568 {
569   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
570   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
571   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
572 } WWDG_TypeDef;
573 
574 /**
575   * @brief Universal Serial Bus Full Speed Device
576   */
577 typedef struct
578 {
579   __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */
580   __IO uint16_t RESERVED0;       /*!< Reserved */
581   __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
582   __IO uint16_t RESERVED1;       /*!< Reserved */
583   __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
584   __IO uint16_t RESERVED2;       /*!< Reserved */
585   __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */
586   __IO uint16_t RESERVED3;       /*!< Reserved */
587   __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
588   __IO uint16_t RESERVED4;       /*!< Reserved */
589   __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
590   __IO uint16_t RESERVED5;       /*!< Reserved */
591   __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
592   __IO uint16_t RESERVED6;       /*!< Reserved */
593   __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
594   __IO uint16_t RESERVED7[17];   /*!< Reserved */
595   __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
596   __IO uint16_t RESERVED8;       /*!< Reserved */
597   __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
598   __IO uint16_t RESERVED9;       /*!< Reserved */
599   __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
600   __IO uint16_t RESERVEDA;       /*!< Reserved */
601   __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
602   __IO uint16_t RESERVEDB;       /*!< Reserved */
603   __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
604   __IO uint16_t RESERVEDC;       /*!< Reserved */
605   __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
606   __IO uint16_t RESERVEDD;       /*!< Reserved */
607   __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
608   __IO uint16_t RESERVEDE;       /*!< Reserved */
609 } USB_TypeDef;
610 
611 /**
612   * @}
613   */
614 
615 /** @addtogroup Peripheral_memory_map
616   * @{
617   */
618 #define FLASH_BASE             (0x08000000UL) /*!< FLASH base address in the alias region */
619 
620 #define DATA_EEPROM_BASE       (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
621 #define DATA_EEPROM_END        (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
622 #define SRAM_BASE              (0x20000000UL) /*!< SRAM base address in the alias region */
623 #define SRAM_SIZE_MAX          (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
624 
625 #define PERIPH_BASE            (0x40000000UL) /*!< Peripheral base address in the alias region */
626 
627 /*!< Peripheral memory map */
628 #define APBPERIPH_BASE        PERIPH_BASE
629 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
630 #define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000UL)
631 
632 #define TIM2_BASE             (APBPERIPH_BASE + 0x00000000UL)
633 #define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
634 #define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
635 #define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
636 #define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
637 #define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
638 #define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
639 #define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800UL)
640 #define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
641 #define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
642 #define CRS_BASE              (APBPERIPH_BASE + 0x00006C00UL)
643 #define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
644 #define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL)
645 #define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
646 
647 #define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
648 #define COMP1_BASE            (APBPERIPH_BASE + 0x00010018UL)
649 #define COMP2_BASE            (APBPERIPH_BASE + 0x0001001CUL)
650 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
651 #define EXTI_BASE             (APBPERIPH_BASE + 0x00010400UL)
652 #define TIM21_BASE            (APBPERIPH_BASE + 0x00010800UL)
653 #define TIM22_BASE            (APBPERIPH_BASE + 0x00011400UL)
654 #define FIREWALL_BASE         (APBPERIPH_BASE + 0x00011C00UL)
655 #define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
656 #define ADC_BASE              (APBPERIPH_BASE + 0x00012708UL)
657 #define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
658 #define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
659 #define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800UL)
660 
661 #define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
662 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
663 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
664 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
665 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
666 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
667 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
668 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
669 #define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8UL)
670 
671 
672 #define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
673 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
674 #define OB_BASE               (0x1FF80000UL)        /*!< FLASH Option Bytes base address */
675 #define FLASHSIZE_BASE        (0x1FF8007CUL)        /*!< FLASH Size register base address */
676 #define UID_BASE              (0x1FF80050UL)        /*!< Unique device ID register base address  */
677 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
678 #define TSC_BASE              (AHBPERIPH_BASE + 0x00004000UL)
679 #define RNG_BASE              (AHBPERIPH_BASE + 0x00005000UL)
680 #define AES_BASE              (AHBPERIPH_BASE + 0x00006000UL)
681 
682 #define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000UL)
683 #define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400UL)
684 #define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800UL)
685 #define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00UL)
686 #define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00UL)
687 
688 /**
689   * @}
690   */
691 
692 /** @addtogroup Peripheral_declaration
693   * @{
694   */
695 
696 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
697 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
698 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
699 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
700 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
701 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
702 #define USART2              ((USART_TypeDef *) USART2_BASE)
703 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
704 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
705 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
706 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
707 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
708 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
709 #define DAC1                ((DAC_TypeDef *) DAC_BASE)
710 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
711 
712 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
713 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
714 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
715 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
716 #define TIM21               ((TIM_TypeDef *) TIM21_BASE)
717 #define TIM22               ((TIM_TypeDef *) TIM22_BASE)
718 #define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
719 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
720 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
721 /* Legacy defines */
722 #define ADC                 ADC1_COMMON
723 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
724 #define USART1              ((USART_TypeDef *) USART1_BASE)
725 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
726 
727 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
728 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
729 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
730 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
731 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
732 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
733 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
734 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
735 #define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
736 
737 
738 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
739 #define OB                  ((OB_TypeDef *) OB_BASE)
740 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
741 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
742 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
743 #define AES                 ((AES_TypeDef *) AES_BASE)
744 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
745 
746 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
747 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
748 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
749 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
750 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
751 
752 #define USB                 ((USB_TypeDef *) USB_BASE)
753 
754 /**
755   * @}
756   */
757 
758 /** @addtogroup Exported_constants
759   * @{
760   */
761 
762   /** @addtogroup Hardware_Constant_Definition
763     * @{
764     */
765 #define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
766 
767   /**
768     * @}
769     */
770 
771   /** @addtogroup Peripheral_Registers_Bits_Definition
772   * @{
773   */
774 
775 /******************************************************************************/
776 /*                         Peripheral Registers Bits Definition               */
777 /******************************************************************************/
778 /******************************************************************************/
779 /*                                                                            */
780 /*                      Analog to Digital Converter (ADC)                     */
781 /*                                                                            */
782 /******************************************************************************/
783 /********************  Bits definition for ADC_ISR register  ******************/
784 #define ADC_ISR_EOCAL_Pos          (11U)
785 #define ADC_ISR_EOCAL_Msk          (0x1UL << ADC_ISR_EOCAL_Pos)                 /*!< 0x00000800 */
786 #define ADC_ISR_EOCAL              ADC_ISR_EOCAL_Msk                           /*!< End of calibration flag */
787 #define ADC_ISR_AWD_Pos            (7U)
788 #define ADC_ISR_AWD_Msk            (0x1UL << ADC_ISR_AWD_Pos)                   /*!< 0x00000080 */
789 #define ADC_ISR_AWD                ADC_ISR_AWD_Msk                             /*!< Analog watchdog flag */
790 #define ADC_ISR_OVR_Pos            (4U)
791 #define ADC_ISR_OVR_Msk            (0x1UL << ADC_ISR_OVR_Pos)                   /*!< 0x00000010 */
792 #define ADC_ISR_OVR                ADC_ISR_OVR_Msk                             /*!< Overrun flag */
793 #define ADC_ISR_EOSEQ_Pos          (3U)
794 #define ADC_ISR_EOSEQ_Msk          (0x1UL << ADC_ISR_EOSEQ_Pos)                 /*!< 0x00000008 */
795 #define ADC_ISR_EOSEQ              ADC_ISR_EOSEQ_Msk                           /*!< End of Sequence flag */
796 #define ADC_ISR_EOC_Pos            (2U)
797 #define ADC_ISR_EOC_Msk            (0x1UL << ADC_ISR_EOC_Pos)                   /*!< 0x00000004 */
798 #define ADC_ISR_EOC                ADC_ISR_EOC_Msk                             /*!< End of Conversion */
799 #define ADC_ISR_EOSMP_Pos          (1U)
800 #define ADC_ISR_EOSMP_Msk          (0x1UL << ADC_ISR_EOSMP_Pos)                 /*!< 0x00000002 */
801 #define ADC_ISR_EOSMP              ADC_ISR_EOSMP_Msk                           /*!< End of sampling flag */
802 #define ADC_ISR_ADRDY_Pos          (0U)
803 #define ADC_ISR_ADRDY_Msk          (0x1UL << ADC_ISR_ADRDY_Pos)                 /*!< 0x00000001 */
804 #define ADC_ISR_ADRDY              ADC_ISR_ADRDY_Msk                           /*!< ADC Ready */
805 
806 /* Old EOSEQ bit definition, maintained for legacy purpose */
807 #define ADC_ISR_EOS                          ADC_ISR_EOSEQ
808 
809 /********************  Bits definition for ADC_IER register  ******************/
810 #define ADC_IER_EOCALIE_Pos        (11U)
811 #define ADC_IER_EOCALIE_Msk        (0x1UL << ADC_IER_EOCALIE_Pos)               /*!< 0x00000800 */
812 #define ADC_IER_EOCALIE            ADC_IER_EOCALIE_Msk                         /*!< Enf Of Calibration interrupt enable */
813 #define ADC_IER_AWDIE_Pos          (7U)
814 #define ADC_IER_AWDIE_Msk          (0x1UL << ADC_IER_AWDIE_Pos)                 /*!< 0x00000080 */
815 #define ADC_IER_AWDIE              ADC_IER_AWDIE_Msk                           /*!< Analog Watchdog interrupt enable */
816 #define ADC_IER_OVRIE_Pos          (4U)
817 #define ADC_IER_OVRIE_Msk          (0x1UL << ADC_IER_OVRIE_Pos)                 /*!< 0x00000010 */
818 #define ADC_IER_OVRIE              ADC_IER_OVRIE_Msk                           /*!< Overrun interrupt enable */
819 #define ADC_IER_EOSEQIE_Pos        (3U)
820 #define ADC_IER_EOSEQIE_Msk        (0x1UL << ADC_IER_EOSEQIE_Pos)               /*!< 0x00000008 */
821 #define ADC_IER_EOSEQIE            ADC_IER_EOSEQIE_Msk                         /*!< End of Sequence of conversion interrupt enable */
822 #define ADC_IER_EOCIE_Pos          (2U)
823 #define ADC_IER_EOCIE_Msk          (0x1UL << ADC_IER_EOCIE_Pos)                 /*!< 0x00000004 */
824 #define ADC_IER_EOCIE              ADC_IER_EOCIE_Msk                           /*!< End of Conversion interrupt enable */
825 #define ADC_IER_EOSMPIE_Pos        (1U)
826 #define ADC_IER_EOSMPIE_Msk        (0x1UL << ADC_IER_EOSMPIE_Pos)               /*!< 0x00000002 */
827 #define ADC_IER_EOSMPIE            ADC_IER_EOSMPIE_Msk                         /*!< End of sampling interrupt enable */
828 #define ADC_IER_ADRDYIE_Pos        (0U)
829 #define ADC_IER_ADRDYIE_Msk        (0x1UL << ADC_IER_ADRDYIE_Pos)               /*!< 0x00000001 */
830 #define ADC_IER_ADRDYIE            ADC_IER_ADRDYIE_Msk                         /*!< ADC Ready interrupt enable */
831 
832 /* Old EOSEQIE bit definition, maintained for legacy purpose */
833 #define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
834 
835 /********************  Bits definition for ADC_CR register  *******************/
836 #define ADC_CR_ADCAL_Pos           (31U)
837 #define ADC_CR_ADCAL_Msk           (0x1UL << ADC_CR_ADCAL_Pos)                  /*!< 0x80000000 */
838 #define ADC_CR_ADCAL               ADC_CR_ADCAL_Msk                            /*!< ADC calibration */
839 #define ADC_CR_ADVREGEN_Pos        (28U)
840 #define ADC_CR_ADVREGEN_Msk        (0x1UL << ADC_CR_ADVREGEN_Pos)               /*!< 0x10000000 */
841 #define ADC_CR_ADVREGEN            ADC_CR_ADVREGEN_Msk                         /*!< ADC Voltage Regulator Enable */
842 #define ADC_CR_ADSTP_Pos           (4U)
843 #define ADC_CR_ADSTP_Msk           (0x1UL << ADC_CR_ADSTP_Pos)                  /*!< 0x00000010 */
844 #define ADC_CR_ADSTP               ADC_CR_ADSTP_Msk                            /*!< ADC stop of conversion command */
845 #define ADC_CR_ADSTART_Pos         (2U)
846 #define ADC_CR_ADSTART_Msk         (0x1UL << ADC_CR_ADSTART_Pos)                /*!< 0x00000004 */
847 #define ADC_CR_ADSTART             ADC_CR_ADSTART_Msk                          /*!< ADC start of conversion */
848 #define ADC_CR_ADDIS_Pos           (1U)
849 #define ADC_CR_ADDIS_Msk           (0x1UL << ADC_CR_ADDIS_Pos)                  /*!< 0x00000002 */
850 #define ADC_CR_ADDIS               ADC_CR_ADDIS_Msk                            /*!< ADC disable command */
851 #define ADC_CR_ADEN_Pos            (0U)
852 #define ADC_CR_ADEN_Msk            (0x1UL << ADC_CR_ADEN_Pos)                   /*!< 0x00000001 */
853 #define ADC_CR_ADEN                ADC_CR_ADEN_Msk                             /*!< ADC enable control */ /*####   TBV  */
854 
855 /*******************  Bits definition for ADC_CFGR1 register  *****************/
856 #define ADC_CFGR1_AWDCH_Pos        (26U)
857 #define ADC_CFGR1_AWDCH_Msk        (0x1FUL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x7C000000 */
858 #define ADC_CFGR1_AWDCH            ADC_CFGR1_AWDCH_Msk                         /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
859 #define ADC_CFGR1_AWDCH_0          (0x01UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x04000000 */
860 #define ADC_CFGR1_AWDCH_1          (0x02UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x08000000 */
861 #define ADC_CFGR1_AWDCH_2          (0x04UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x10000000 */
862 #define ADC_CFGR1_AWDCH_3          (0x08UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x20000000 */
863 #define ADC_CFGR1_AWDCH_4          (0x10UL << ADC_CFGR1_AWDCH_Pos)              /*!< 0x40000000 */
864 #define ADC_CFGR1_AWDEN_Pos        (23U)
865 #define ADC_CFGR1_AWDEN_Msk        (0x1UL << ADC_CFGR1_AWDEN_Pos)               /*!< 0x00800000 */
866 #define ADC_CFGR1_AWDEN            ADC_CFGR1_AWDEN_Msk                         /*!< Analog watchdog enable on regular channels */
867 #define ADC_CFGR1_AWDSGL_Pos       (22U)
868 #define ADC_CFGR1_AWDSGL_Msk       (0x1UL << ADC_CFGR1_AWDSGL_Pos)              /*!< 0x00400000 */
869 #define ADC_CFGR1_AWDSGL           ADC_CFGR1_AWDSGL_Msk                        /*!< Enable the watchdog on a single channel or on all channels  */
870 #define ADC_CFGR1_DISCEN_Pos       (16U)
871 #define ADC_CFGR1_DISCEN_Msk       (0x1UL << ADC_CFGR1_DISCEN_Pos)              /*!< 0x00010000 */
872 #define ADC_CFGR1_DISCEN           ADC_CFGR1_DISCEN_Msk                        /*!< Discontinuous mode on regular channels */
873 #define ADC_CFGR1_AUTOFF_Pos       (15U)
874 #define ADC_CFGR1_AUTOFF_Msk       (0x1UL << ADC_CFGR1_AUTOFF_Pos)              /*!< 0x00008000 */
875 #define ADC_CFGR1_AUTOFF           ADC_CFGR1_AUTOFF_Msk                        /*!< ADC auto power off */
876 #define ADC_CFGR1_WAIT_Pos         (14U)
877 #define ADC_CFGR1_WAIT_Msk         (0x1UL << ADC_CFGR1_WAIT_Pos)                /*!< 0x00004000 */
878 #define ADC_CFGR1_WAIT             ADC_CFGR1_WAIT_Msk                          /*!< ADC wait conversion mode */
879 #define ADC_CFGR1_CONT_Pos         (13U)
880 #define ADC_CFGR1_CONT_Msk         (0x1UL << ADC_CFGR1_CONT_Pos)                /*!< 0x00002000 */
881 #define ADC_CFGR1_CONT             ADC_CFGR1_CONT_Msk                          /*!< Continuous Conversion */
882 #define ADC_CFGR1_OVRMOD_Pos       (12U)
883 #define ADC_CFGR1_OVRMOD_Msk       (0x1UL << ADC_CFGR1_OVRMOD_Pos)              /*!< 0x00001000 */
884 #define ADC_CFGR1_OVRMOD           ADC_CFGR1_OVRMOD_Msk                        /*!< Overrun mode */
885 #define ADC_CFGR1_EXTEN_Pos        (10U)
886 #define ADC_CFGR1_EXTEN_Msk        (0x3UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000C00 */
887 #define ADC_CFGR1_EXTEN            ADC_CFGR1_EXTEN_Msk                         /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
888 #define ADC_CFGR1_EXTEN_0          (0x1UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000400 */
889 #define ADC_CFGR1_EXTEN_1          (0x2UL << ADC_CFGR1_EXTEN_Pos)               /*!< 0x00000800 */
890 #define ADC_CFGR1_EXTSEL_Pos       (6U)
891 #define ADC_CFGR1_EXTSEL_Msk       (0x7UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x000001C0 */
892 #define ADC_CFGR1_EXTSEL           ADC_CFGR1_EXTSEL_Msk                        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
893 #define ADC_CFGR1_EXTSEL_0         (0x1UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000040 */
894 #define ADC_CFGR1_EXTSEL_1         (0x2UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000080 */
895 #define ADC_CFGR1_EXTSEL_2         (0x4UL << ADC_CFGR1_EXTSEL_Pos)              /*!< 0x00000100 */
896 #define ADC_CFGR1_ALIGN_Pos        (5U)
897 #define ADC_CFGR1_ALIGN_Msk        (0x1UL << ADC_CFGR1_ALIGN_Pos)               /*!< 0x00000020 */
898 #define ADC_CFGR1_ALIGN            ADC_CFGR1_ALIGN_Msk                         /*!< Data Alignment */
899 #define ADC_CFGR1_RES_Pos          (3U)
900 #define ADC_CFGR1_RES_Msk          (0x3UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000018 */
901 #define ADC_CFGR1_RES              ADC_CFGR1_RES_Msk                           /*!< RES[1:0] bits (Resolution) */
902 #define ADC_CFGR1_RES_0            (0x1UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000008 */
903 #define ADC_CFGR1_RES_1            (0x2UL << ADC_CFGR1_RES_Pos)                 /*!< 0x00000010 */
904 #define ADC_CFGR1_SCANDIR_Pos      (2U)
905 #define ADC_CFGR1_SCANDIR_Msk      (0x1UL << ADC_CFGR1_SCANDIR_Pos)             /*!< 0x00000004 */
906 #define ADC_CFGR1_SCANDIR          ADC_CFGR1_SCANDIR_Msk                       /*!< Sequence scan direction */
907 #define ADC_CFGR1_DMACFG_Pos       (1U)
908 #define ADC_CFGR1_DMACFG_Msk       (0x1UL << ADC_CFGR1_DMACFG_Pos)              /*!< 0x00000002 */
909 #define ADC_CFGR1_DMACFG           ADC_CFGR1_DMACFG_Msk                        /*!< Direct memory access configuration */
910 #define ADC_CFGR1_DMAEN_Pos        (0U)
911 #define ADC_CFGR1_DMAEN_Msk        (0x1UL << ADC_CFGR1_DMAEN_Pos)               /*!< 0x00000001 */
912 #define ADC_CFGR1_DMAEN            ADC_CFGR1_DMAEN_Msk                         /*!< Direct memory access enable */
913 
914 /* Old WAIT bit definition, maintained for legacy purpose */
915 #define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
916 
917 /*******************  Bits definition for ADC_CFGR2 register  *****************/
918 #define ADC_CFGR2_TOVS_Pos         (9U)
919 #define ADC_CFGR2_TOVS_Msk         (0x1UL << ADC_CFGR2_TOVS_Pos)                /*!< 0x80000200 */
920 #define ADC_CFGR2_TOVS             ADC_CFGR2_TOVS_Msk                          /*!< Triggered Oversampling */
921 #define ADC_CFGR2_OVSS_Pos         (5U)
922 #define ADC_CFGR2_OVSS_Msk         (0xFUL << ADC_CFGR2_OVSS_Pos)                /*!< 0x000001E0 */
923 #define ADC_CFGR2_OVSS             ADC_CFGR2_OVSS_Msk                          /*!< OVSS [3:0] bits (Oversampling shift) */
924 #define ADC_CFGR2_OVSS_0           (0x1UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000020 */
925 #define ADC_CFGR2_OVSS_1           (0x2UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000040 */
926 #define ADC_CFGR2_OVSS_2           (0x4UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000080 */
927 #define ADC_CFGR2_OVSS_3           (0x8UL << ADC_CFGR2_OVSS_Pos)                /*!< 0x00000100 */
928 #define ADC_CFGR2_OVSR_Pos         (2U)
929 #define ADC_CFGR2_OVSR_Msk         (0x7UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x0000001C */
930 #define ADC_CFGR2_OVSR             ADC_CFGR2_OVSR_Msk                          /*!< OVSR  [2:0] bits (Oversampling ratio) */
931 #define ADC_CFGR2_OVSR_0           (0x1UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000004 */
932 #define ADC_CFGR2_OVSR_1           (0x2UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000008 */
933 #define ADC_CFGR2_OVSR_2           (0x4UL << ADC_CFGR2_OVSR_Pos)                /*!< 0x00000010 */
934 #define ADC_CFGR2_OVSE_Pos         (0U)
935 #define ADC_CFGR2_OVSE_Msk         (0x1UL << ADC_CFGR2_OVSE_Pos)                /*!< 0x00000001 */
936 #define ADC_CFGR2_OVSE             ADC_CFGR2_OVSE_Msk                          /*!< Oversampler Enable */
937 #define ADC_CFGR2_CKMODE_Pos       (30U)
938 #define ADC_CFGR2_CKMODE_Msk       (0x3UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0xC0000000 */
939 #define ADC_CFGR2_CKMODE           ADC_CFGR2_CKMODE_Msk                        /*!< CKMODE [1:0] bits (ADC clock mode) */
940 #define ADC_CFGR2_CKMODE_0         (0x1UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x40000000 */
941 #define ADC_CFGR2_CKMODE_1         (0x2UL << ADC_CFGR2_CKMODE_Pos)              /*!< 0x80000000 */
942 
943 
944 /******************  Bit definition for ADC_SMPR register  ********************/
945 #define ADC_SMPR_SMP_Pos           (0U)
946 #define ADC_SMPR_SMP_Msk           (0x7UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000007 */
947 #define ADC_SMPR_SMP               ADC_SMPR_SMP_Msk                            /*!< SMPR[2:0] bits (Sampling time selection) */
948 #define ADC_SMPR_SMP_0             (0x1UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000001 */
949 #define ADC_SMPR_SMP_1             (0x2UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000002 */
950 #define ADC_SMPR_SMP_2             (0x4UL << ADC_SMPR_SMP_Pos)                  /*!< 0x00000004 */
951 
952 /* Legacy defines */
953 #define ADC_SMPR_SMPR                       ADC_SMPR_SMP
954 #define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
955 #define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
956 #define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
957 
958 /*******************  Bit definition for ADC_TR register  ********************/
959 #define ADC_TR_HT_Pos              (16U)
960 #define ADC_TR_HT_Msk              (0xFFFUL << ADC_TR_HT_Pos)                   /*!< 0x0FFF0000 */
961 #define ADC_TR_HT                  ADC_TR_HT_Msk                               /*!< Analog watchdog high threshold */
962 #define ADC_TR_LT_Pos              (0U)
963 #define ADC_TR_LT_Msk              (0xFFFUL << ADC_TR_LT_Pos)                   /*!< 0x00000FFF */
964 #define ADC_TR_LT                  ADC_TR_LT_Msk                               /*!< Analog watchdog low threshold */
965 
966 /******************  Bit definition for ADC_CHSELR register  ******************/
967 #define ADC_CHSELR_CHSEL_Pos       (0U)
968 #define ADC_CHSELR_CHSEL_Msk       (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)          /*!< 0x0007FFFF */
969 #define ADC_CHSELR_CHSEL           ADC_CHSELR_CHSEL_Msk                        /*!< ADC group regular sequencer channels */
970 #define ADC_CHSELR_CHSEL18_Pos     (18U)
971 #define ADC_CHSELR_CHSEL18_Msk     (0x1UL << ADC_CHSELR_CHSEL18_Pos)            /*!< 0x00040000 */
972 #define ADC_CHSELR_CHSEL18         ADC_CHSELR_CHSEL18_Msk                      /*!< Channel 18 selection */
973 #define ADC_CHSELR_CHSEL17_Pos     (17U)
974 #define ADC_CHSELR_CHSEL17_Msk     (0x1UL << ADC_CHSELR_CHSEL17_Pos)            /*!< 0x00020000 */
975 #define ADC_CHSELR_CHSEL17         ADC_CHSELR_CHSEL17_Msk                      /*!< Channel 17 selection */
976 #define ADC_CHSELR_CHSEL15_Pos     (15U)
977 #define ADC_CHSELR_CHSEL15_Msk     (0x1UL << ADC_CHSELR_CHSEL15_Pos)            /*!< 0x00008000 */
978 #define ADC_CHSELR_CHSEL15         ADC_CHSELR_CHSEL15_Msk                      /*!< Channel 15 selection */
979 #define ADC_CHSELR_CHSEL14_Pos     (14U)
980 #define ADC_CHSELR_CHSEL14_Msk     (0x1UL << ADC_CHSELR_CHSEL14_Pos)            /*!< 0x00004000 */
981 #define ADC_CHSELR_CHSEL14         ADC_CHSELR_CHSEL14_Msk                      /*!< Channel 14 selection */
982 #define ADC_CHSELR_CHSEL13_Pos     (13U)
983 #define ADC_CHSELR_CHSEL13_Msk     (0x1UL << ADC_CHSELR_CHSEL13_Pos)            /*!< 0x00002000 */
984 #define ADC_CHSELR_CHSEL13         ADC_CHSELR_CHSEL13_Msk                      /*!< Channel 13 selection */
985 #define ADC_CHSELR_CHSEL12_Pos     (12U)
986 #define ADC_CHSELR_CHSEL12_Msk     (0x1UL << ADC_CHSELR_CHSEL12_Pos)            /*!< 0x00001000 */
987 #define ADC_CHSELR_CHSEL12         ADC_CHSELR_CHSEL12_Msk                      /*!< Channel 12 selection */
988 #define ADC_CHSELR_CHSEL11_Pos     (11U)
989 #define ADC_CHSELR_CHSEL11_Msk     (0x1UL << ADC_CHSELR_CHSEL11_Pos)            /*!< 0x00000800 */
990 #define ADC_CHSELR_CHSEL11         ADC_CHSELR_CHSEL11_Msk                      /*!< Channel 11 selection */
991 #define ADC_CHSELR_CHSEL10_Pos     (10U)
992 #define ADC_CHSELR_CHSEL10_Msk     (0x1UL << ADC_CHSELR_CHSEL10_Pos)            /*!< 0x00000400 */
993 #define ADC_CHSELR_CHSEL10         ADC_CHSELR_CHSEL10_Msk                      /*!< Channel 10 selection */
994 #define ADC_CHSELR_CHSEL9_Pos      (9U)
995 #define ADC_CHSELR_CHSEL9_Msk      (0x1UL << ADC_CHSELR_CHSEL9_Pos)             /*!< 0x00000200 */
996 #define ADC_CHSELR_CHSEL9          ADC_CHSELR_CHSEL9_Msk                       /*!< Channel 9 selection */
997 #define ADC_CHSELR_CHSEL8_Pos      (8U)
998 #define ADC_CHSELR_CHSEL8_Msk      (0x1UL << ADC_CHSELR_CHSEL8_Pos)             /*!< 0x00000100 */
999 #define ADC_CHSELR_CHSEL8          ADC_CHSELR_CHSEL8_Msk                       /*!< Channel 8 selection */
1000 #define ADC_CHSELR_CHSEL7_Pos      (7U)
1001 #define ADC_CHSELR_CHSEL7_Msk      (0x1UL << ADC_CHSELR_CHSEL7_Pos)             /*!< 0x00000080 */
1002 #define ADC_CHSELR_CHSEL7          ADC_CHSELR_CHSEL7_Msk                       /*!< Channel 7 selection */
1003 #define ADC_CHSELR_CHSEL6_Pos      (6U)
1004 #define ADC_CHSELR_CHSEL6_Msk      (0x1UL << ADC_CHSELR_CHSEL6_Pos)             /*!< 0x00000040 */
1005 #define ADC_CHSELR_CHSEL6          ADC_CHSELR_CHSEL6_Msk                       /*!< Channel 6 selection */
1006 #define ADC_CHSELR_CHSEL5_Pos      (5U)
1007 #define ADC_CHSELR_CHSEL5_Msk      (0x1UL << ADC_CHSELR_CHSEL5_Pos)             /*!< 0x00000020 */
1008 #define ADC_CHSELR_CHSEL5          ADC_CHSELR_CHSEL5_Msk                       /*!< Channel 5 selection */
1009 #define ADC_CHSELR_CHSEL4_Pos      (4U)
1010 #define ADC_CHSELR_CHSEL4_Msk      (0x1UL << ADC_CHSELR_CHSEL4_Pos)             /*!< 0x00000010 */
1011 #define ADC_CHSELR_CHSEL4          ADC_CHSELR_CHSEL4_Msk                       /*!< Channel 4 selection */
1012 #define ADC_CHSELR_CHSEL3_Pos      (3U)
1013 #define ADC_CHSELR_CHSEL3_Msk      (0x1UL << ADC_CHSELR_CHSEL3_Pos)             /*!< 0x00000008 */
1014 #define ADC_CHSELR_CHSEL3          ADC_CHSELR_CHSEL3_Msk                       /*!< Channel 3 selection */
1015 #define ADC_CHSELR_CHSEL2_Pos      (2U)
1016 #define ADC_CHSELR_CHSEL2_Msk      (0x1UL << ADC_CHSELR_CHSEL2_Pos)             /*!< 0x00000004 */
1017 #define ADC_CHSELR_CHSEL2          ADC_CHSELR_CHSEL2_Msk                       /*!< Channel 2 selection */
1018 #define ADC_CHSELR_CHSEL1_Pos      (1U)
1019 #define ADC_CHSELR_CHSEL1_Msk      (0x1UL << ADC_CHSELR_CHSEL1_Pos)             /*!< 0x00000002 */
1020 #define ADC_CHSELR_CHSEL1          ADC_CHSELR_CHSEL1_Msk                       /*!< Channel 1 selection */
1021 #define ADC_CHSELR_CHSEL0_Pos      (0U)
1022 #define ADC_CHSELR_CHSEL0_Msk      (0x1UL << ADC_CHSELR_CHSEL0_Pos)             /*!< 0x00000001 */
1023 #define ADC_CHSELR_CHSEL0          ADC_CHSELR_CHSEL0_Msk                       /*!< Channel 0 selection */
1024 
1025 /********************  Bit definition for ADC_DR register  ********************/
1026 #define ADC_DR_DATA_Pos            (0U)
1027 #define ADC_DR_DATA_Msk            (0xFFFFUL << ADC_DR_DATA_Pos)                /*!< 0x0000FFFF */
1028 #define ADC_DR_DATA                ADC_DR_DATA_Msk                             /*!< Regular data */
1029 
1030 /********************  Bit definition for ADC_CALFACT register  ********************/
1031 #define ADC_CALFACT_CALFACT_Pos    (0U)
1032 #define ADC_CALFACT_CALFACT_Msk    (0x7FUL << ADC_CALFACT_CALFACT_Pos)          /*!< 0x0000007F */
1033 #define ADC_CALFACT_CALFACT        ADC_CALFACT_CALFACT_Msk                     /*!< Calibration factor */
1034 
1035 /*******************  Bit definition for ADC_CCR register  ********************/
1036 #define ADC_CCR_LFMEN_Pos          (25U)
1037 #define ADC_CCR_LFMEN_Msk          (0x1UL << ADC_CCR_LFMEN_Pos)                 /*!< 0x02000000 */
1038 #define ADC_CCR_LFMEN              ADC_CCR_LFMEN_Msk                           /*!< Low Frequency Mode enable */
1039 #define ADC_CCR_TSEN_Pos           (23U)
1040 #define ADC_CCR_TSEN_Msk           (0x1UL << ADC_CCR_TSEN_Pos)                  /*!< 0x00800000 */
1041 #define ADC_CCR_TSEN               ADC_CCR_TSEN_Msk                            /*!< Temperature sensore enable */
1042 #define ADC_CCR_VREFEN_Pos         (22U)
1043 #define ADC_CCR_VREFEN_Msk         (0x1UL << ADC_CCR_VREFEN_Pos)                /*!< 0x00400000 */
1044 #define ADC_CCR_VREFEN             ADC_CCR_VREFEN_Msk                          /*!< Vrefint enable */
1045 #define ADC_CCR_PRESC_Pos          (18U)
1046 #define ADC_CCR_PRESC_Msk          (0xFUL << ADC_CCR_PRESC_Pos)                 /*!< 0x003C0000 */
1047 #define ADC_CCR_PRESC              ADC_CCR_PRESC_Msk                           /*!< PRESC  [3:0] bits (ADC prescaler) */
1048 #define ADC_CCR_PRESC_0            (0x1UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00040000 */
1049 #define ADC_CCR_PRESC_1            (0x2UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00080000 */
1050 #define ADC_CCR_PRESC_2            (0x4UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00100000 */
1051 #define ADC_CCR_PRESC_3            (0x8UL << ADC_CCR_PRESC_Pos)                 /*!< 0x00200000 */
1052 
1053 /******************************************************************************/
1054 /*                                                                            */
1055 /*                       Advanced Encryption Standard (AES)                   */
1056 /*                                                                            */
1057 /******************************************************************************/
1058 /*******************  Bit definition for AES_CR register  *********************/
1059 #define AES_CR_EN_Pos            (0U)
1060 #define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                       /*!< 0x00000001 */
1061 #define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
1062 #define AES_CR_DATATYPE_Pos      (1U)
1063 #define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000006 */
1064 #define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
1065 #define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
1066 #define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
1067 
1068 #define AES_CR_MODE_Pos          (3U)
1069 #define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                     /*!< 0x00000018 */
1070 #define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
1071 #define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
1072 #define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
1073 
1074 #define AES_CR_CHMOD_Pos         (5U)
1075 #define AES_CR_CHMOD_Msk         (0x3UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000060 */
1076 #define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
1077 #define AES_CR_CHMOD_0           (0x1UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000020 */
1078 #define AES_CR_CHMOD_1           (0x2UL << AES_CR_CHMOD_Pos)                    /*!< 0x00000040 */
1079 
1080 #define AES_CR_CCFC_Pos          (7U)
1081 #define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                     /*!< 0x00000080 */
1082 #define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
1083 #define AES_CR_ERRC_Pos          (8U)
1084 #define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                     /*!< 0x00000100 */
1085 #define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
1086 #define AES_CR_CCIE_Pos          (9U)
1087 #define AES_CR_CCIE_Msk          (0x1UL << AES_CR_CCIE_Pos)                     /*!< 0x00000200 */
1088 #define AES_CR_CCIE              AES_CR_CCIE_Msk                               /*!< Computation Complete Interrupt Enable */
1089 #define AES_CR_ERRIE_Pos         (10U)
1090 #define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                    /*!< 0x00000400 */
1091 #define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
1092 #define AES_CR_DMAINEN_Pos       (11U)
1093 #define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                  /*!< 0x00000800 */
1094 #define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< DMA ENable managing the data input phase */
1095 #define AES_CR_DMAOUTEN_Pos      (12U)
1096 #define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                 /*!< 0x00001000 */
1097 #define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< DMA Enable managing the data output phase */
1098 
1099 /*******************  Bit definition for AES_SR register  *********************/
1100 #define AES_SR_CCF_Pos           (0U)
1101 #define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                      /*!< 0x00000001 */
1102 #define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
1103 #define AES_SR_RDERR_Pos         (1U)
1104 #define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                    /*!< 0x00000002 */
1105 #define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
1106 #define AES_SR_WRERR_Pos         (2U)
1107 #define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                    /*!< 0x00000004 */
1108 #define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
1109 
1110 /*******************  Bit definition for AES_DINR register  *******************/
1111 #define AES_DINR_Pos             (0U)
1112 #define AES_DINR_Msk             (0xFFFFUL << AES_DINR_Pos)                     /*!< 0x0000FFFF */
1113 #define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
1114 
1115 /*******************  Bit definition for AES_DOUTR register  ******************/
1116 #define AES_DOUTR_Pos            (0U)
1117 #define AES_DOUTR_Msk            (0xFFFFUL << AES_DOUTR_Pos)                    /*!< 0x0000FFFF */
1118 #define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
1119 
1120 /*******************  Bit definition for AES_KEYR0 register  ******************/
1121 #define AES_KEYR0_Pos            (0U)
1122 #define AES_KEYR0_Msk            (0xFFFFUL << AES_KEYR0_Pos)                    /*!< 0x0000FFFF */
1123 #define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
1124 
1125 /*******************  Bit definition for AES_KEYR1 register  ******************/
1126 #define AES_KEYR1_Pos            (0U)
1127 #define AES_KEYR1_Msk            (0xFFFFUL << AES_KEYR1_Pos)                    /*!< 0x0000FFFF */
1128 #define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
1129 
1130 /*******************  Bit definition for AES_KEYR2 register  ******************/
1131 #define AES_KEYR2_Pos            (0U)
1132 #define AES_KEYR2_Msk            (0xFFFFUL << AES_KEYR2_Pos)                    /*!< 0x0000FFFF */
1133 #define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
1134 
1135 /*******************  Bit definition for AES_KEYR3 register  ******************/
1136 #define AES_KEYR3_Pos            (0U)
1137 #define AES_KEYR3_Msk            (0xFFFFUL << AES_KEYR3_Pos)                    /*!< 0x0000FFFF */
1138 #define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
1139 
1140 /*******************  Bit definition for AES_IVR0 register  *******************/
1141 #define AES_IVR0_Pos             (0U)
1142 #define AES_IVR0_Msk             (0xFFFFUL << AES_IVR0_Pos)                     /*!< 0x0000FFFF */
1143 #define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
1144 
1145 /*******************  Bit definition for AES_IVR1 register  *******************/
1146 #define AES_IVR1_Pos             (0U)
1147 #define AES_IVR1_Msk             (0xFFFFUL << AES_IVR1_Pos)                     /*!< 0x0000FFFF */
1148 #define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
1149 
1150 /*******************  Bit definition for AES_IVR2 register  *******************/
1151 #define AES_IVR2_Pos             (0U)
1152 #define AES_IVR2_Msk             (0xFFFFUL << AES_IVR2_Pos)                     /*!< 0x0000FFFF */
1153 #define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
1154 
1155 /*******************  Bit definition for AES_IVR3 register  *******************/
1156 #define AES_IVR3_Pos             (0U)
1157 #define AES_IVR3_Msk             (0xFFFFUL << AES_IVR3_Pos)                     /*!< 0x0000FFFF */
1158 #define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
1159 
1160 /******************************************************************************/
1161 /*                                                                            */
1162 /*                      Analog Comparators (COMP)                             */
1163 /*                                                                            */
1164 /******************************************************************************/
1165 /*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
1166 /* COMP1 bits definition */
1167 #define COMP_CSR_COMP1EN_Pos           (0U)
1168 #define COMP_CSR_COMP1EN_Msk           (0x1UL << COMP_CSR_COMP1EN_Pos)          /*!< 0x00000001 */
1169 #define COMP_CSR_COMP1EN               COMP_CSR_COMP1EN_Msk                    /*!< COMP1 enable */
1170 #define COMP_CSR_COMP1INNSEL_Pos       (4U)
1171 #define COMP_CSR_COMP1INNSEL_Msk       (0x3UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000030 */
1172 #define COMP_CSR_COMP1INNSEL           COMP_CSR_COMP1INNSEL_Msk                /*!< COMP1 inverting input select */
1173 #define COMP_CSR_COMP1INNSEL_0         (0x1UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000010 */
1174 #define COMP_CSR_COMP1INNSEL_1         (0x2UL << COMP_CSR_COMP1INNSEL_Pos)      /*!< 0x00000020 */
1175 #define COMP_CSR_COMP1WM_Pos           (8U)
1176 #define COMP_CSR_COMP1WM_Msk           (0x1UL << COMP_CSR_COMP1WM_Pos)          /*!< 0x00000100 */
1177 #define COMP_CSR_COMP1WM               COMP_CSR_COMP1WM_Msk                    /*!< Comparators window mode enable */
1178 #define COMP_CSR_COMP1LPTIM1IN1_Pos    (12U)
1179 #define COMP_CSR_COMP1LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos)   /*!< 0x00001000 */
1180 #define COMP_CSR_COMP1LPTIM1IN1        COMP_CSR_COMP1LPTIM1IN1_Msk             /*!< COMP1 LPTIM1 IN1 connection */
1181 #define COMP_CSR_COMP1POLARITY_Pos     (15U)
1182 #define COMP_CSR_COMP1POLARITY_Msk     (0x1UL << COMP_CSR_COMP1POLARITY_Pos)    /*!< 0x00008000 */
1183 #define COMP_CSR_COMP1POLARITY         COMP_CSR_COMP1POLARITY_Msk              /*!< COMP1 output polarity */
1184 #define COMP_CSR_COMP1VALUE_Pos        (30U)
1185 #define COMP_CSR_COMP1VALUE_Msk        (0x1UL << COMP_CSR_COMP1VALUE_Pos)       /*!< 0x40000000 */
1186 #define COMP_CSR_COMP1VALUE            COMP_CSR_COMP1VALUE_Msk                 /*!< COMP1 output level */
1187 #define COMP_CSR_COMP1LOCK_Pos         (31U)
1188 #define COMP_CSR_COMP1LOCK_Msk         (0x1UL << COMP_CSR_COMP1LOCK_Pos)        /*!< 0x80000000 */
1189 #define COMP_CSR_COMP1LOCK             COMP_CSR_COMP1LOCK_Msk                  /*!< COMP1 lock */
1190 /* COMP2 bits definition */
1191 #define COMP_CSR_COMP2EN_Pos           (0U)
1192 #define COMP_CSR_COMP2EN_Msk           (0x1UL << COMP_CSR_COMP2EN_Pos)          /*!< 0x00000001 */
1193 #define COMP_CSR_COMP2EN               COMP_CSR_COMP2EN_Msk                    /*!< COMP2 enable */
1194 #define COMP_CSR_COMP2SPEED_Pos        (3U)
1195 #define COMP_CSR_COMP2SPEED_Msk        (0x1UL << COMP_CSR_COMP2SPEED_Pos)       /*!< 0x00000008 */
1196 #define COMP_CSR_COMP2SPEED            COMP_CSR_COMP2SPEED_Msk                 /*!< COMP2 power mode */
1197 #define COMP_CSR_COMP2INNSEL_Pos       (4U)
1198 #define COMP_CSR_COMP2INNSEL_Msk       (0x7UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000070 */
1199 #define COMP_CSR_COMP2INNSEL           COMP_CSR_COMP2INNSEL_Msk                /*!< COMP2 inverting input select */
1200 #define COMP_CSR_COMP2INNSEL_0         (0x1UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000010 */
1201 #define COMP_CSR_COMP2INNSEL_1         (0x2UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000020 */
1202 #define COMP_CSR_COMP2INNSEL_2         (0x4UL << COMP_CSR_COMP2INNSEL_Pos)      /*!< 0x00000040 */
1203 #define COMP_CSR_COMP2INPSEL_Pos       (8U)
1204 #define COMP_CSR_COMP2INPSEL_Msk       (0x7UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000700 */
1205 #define COMP_CSR_COMP2INPSEL           COMP_CSR_COMP2INPSEL_Msk                /*!< COMPx non inverting input select */
1206 #define COMP_CSR_COMP2INPSEL_0         (0x1UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000100 */
1207 #define COMP_CSR_COMP2INPSEL_1         (0x2UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000200 */
1208 #define COMP_CSR_COMP2INPSEL_2         (0x4UL << COMP_CSR_COMP2INPSEL_Pos)      /*!< 0x00000400 */
1209 #define COMP_CSR_COMP2LPTIM1IN2_Pos    (12U)
1210 #define COMP_CSR_COMP2LPTIM1IN2_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos)   /*!< 0x00001000 */
1211 #define COMP_CSR_COMP2LPTIM1IN2        COMP_CSR_COMP2LPTIM1IN2_Msk             /*!< COMP2 LPTIM1 IN2 connection */
1212 #define COMP_CSR_COMP2LPTIM1IN1_Pos    (13U)
1213 #define COMP_CSR_COMP2LPTIM1IN1_Msk    (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos)   /*!< 0x00002000 */
1214 #define COMP_CSR_COMP2LPTIM1IN1        COMP_CSR_COMP2LPTIM1IN1_Msk             /*!< COMP2 LPTIM1 IN1 connection */
1215 #define COMP_CSR_COMP2POLARITY_Pos     (15U)
1216 #define COMP_CSR_COMP2POLARITY_Msk     (0x1UL << COMP_CSR_COMP2POLARITY_Pos)    /*!< 0x00008000 */
1217 #define COMP_CSR_COMP2POLARITY         COMP_CSR_COMP2POLARITY_Msk              /*!< COMP2 output polarity */
1218 #define COMP_CSR_COMP2VALUE_Pos        (30U)
1219 #define COMP_CSR_COMP2VALUE_Msk        (0x1UL << COMP_CSR_COMP2VALUE_Pos)       /*!< 0x40000000 */
1220 #define COMP_CSR_COMP2VALUE            COMP_CSR_COMP2VALUE_Msk                 /*!< COMP2 output level */
1221 #define COMP_CSR_COMP2LOCK_Pos         (31U)
1222 #define COMP_CSR_COMP2LOCK_Msk         (0x1UL << COMP_CSR_COMP2LOCK_Pos)        /*!< 0x80000000 */
1223 #define COMP_CSR_COMP2LOCK             COMP_CSR_COMP2LOCK_Msk                  /*!< COMP2 lock */
1224 
1225 /**********************  Bit definition for COMP_CSR register common  ****************/
1226 #define COMP_CSR_COMPxEN_Pos           (0U)
1227 #define COMP_CSR_COMPxEN_Msk           (0x1UL << COMP_CSR_COMPxEN_Pos)          /*!< 0x00000001 */
1228 #define COMP_CSR_COMPxEN               COMP_CSR_COMPxEN_Msk                    /*!< COMPx enable */
1229 #define COMP_CSR_COMPxPOLARITY_Pos     (15U)
1230 #define COMP_CSR_COMPxPOLARITY_Msk     (0x1UL << COMP_CSR_COMPxPOLARITY_Pos)    /*!< 0x00008000 */
1231 #define COMP_CSR_COMPxPOLARITY         COMP_CSR_COMPxPOLARITY_Msk              /*!< COMPx output polarity */
1232 #define COMP_CSR_COMPxOUTVALUE_Pos     (30U)
1233 #define COMP_CSR_COMPxOUTVALUE_Msk     (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos)    /*!< 0x40000000 */
1234 #define COMP_CSR_COMPxOUTVALUE         COMP_CSR_COMPxOUTVALUE_Msk              /*!< COMPx output level */
1235 #define COMP_CSR_COMPxLOCK_Pos         (31U)
1236 #define COMP_CSR_COMPxLOCK_Msk         (0x1UL << COMP_CSR_COMPxLOCK_Pos)        /*!< 0x80000000 */
1237 #define COMP_CSR_COMPxLOCK             COMP_CSR_COMPxLOCK_Msk                  /*!< COMPx lock */
1238 
1239 /* Reference defines */
1240 #define COMP_CSR_WINMODE   COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
1241 
1242 /******************************************************************************/
1243 /*                                                                            */
1244 /*                       CRC calculation unit (CRC)                           */
1245 /*                                                                            */
1246 /******************************************************************************/
1247 /*******************  Bit definition for CRC_DR register  *********************/
1248 #define CRC_DR_DR_Pos            (0U)
1249 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
1250 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
1251 
1252 /*******************  Bit definition for CRC_IDR register  ********************/
1253 #define CRC_IDR_IDR              (0xFFU)                                       /*!< General-purpose 8-bit data register bits */
1254 
1255 /********************  Bit definition for CRC_CR register  ********************/
1256 #define CRC_CR_RESET_Pos         (0U)
1257 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
1258 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
1259 #define CRC_CR_POLYSIZE_Pos      (3U)
1260 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
1261 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
1262 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
1263 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
1264 #define CRC_CR_REV_IN_Pos        (5U)
1265 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
1266 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
1267 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
1268 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
1269 #define CRC_CR_REV_OUT_Pos       (7U)
1270 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
1271 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
1272 
1273 /*******************  Bit definition for CRC_INIT register  *******************/
1274 #define CRC_INIT_INIT_Pos        (0U)
1275 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
1276 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
1277 
1278 /*******************  Bit definition for CRC_POL register  ********************/
1279 #define CRC_POL_POL_Pos          (0U)
1280 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
1281 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
1282 
1283 /******************************************************************************/
1284 /*                                                                            */
1285 /*                          CRS Clock Recovery System                         */
1286 /*                                                                            */
1287 /******************************************************************************/
1288 
1289 /*******************  Bit definition for CRS_CR register  *********************/
1290 #define CRS_CR_SYNCOKIE_Pos       (0U)
1291 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
1292 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /* SYNC event OK interrupt enable        */
1293 #define CRS_CR_SYNCWARNIE_Pos     (1U)
1294 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
1295 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /* SYNC warning interrupt enable         */
1296 #define CRS_CR_ERRIE_Pos          (2U)
1297 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
1298 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /* SYNC error interrupt enable           */
1299 #define CRS_CR_ESYNCIE_Pos        (3U)
1300 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
1301 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /* Expected SYNC(ESYNCF) interrupt Enable*/
1302 #define CRS_CR_CEN_Pos            (5U)
1303 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
1304 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /* Frequency error counter enable        */
1305 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
1306 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
1307 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /* Automatic trimming enable             */
1308 #define CRS_CR_SWSYNC_Pos         (7U)
1309 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
1310 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /* A Software SYNC event is generated    */
1311 #define CRS_CR_TRIM_Pos           (8U)
1312 #define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
1313 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /* HSI48 oscillator smooth trimming      */
1314 
1315 /*******************  Bit definition for CRS_CFGR register  *********************/
1316 #define CRS_CFGR_RELOAD_Pos       (0U)
1317 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
1318 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /* Counter reload value               */
1319 #define CRS_CFGR_FELIM_Pos        (16U)
1320 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
1321 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /* Frequency error limit              */
1322 
1323 #define CRS_CFGR_SYNCDIV_Pos      (24U)
1324 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
1325 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /* SYNC divider                       */
1326 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
1327 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
1328 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
1329 
1330 #define CRS_CFGR_SYNCSRC_Pos      (28U)
1331 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
1332 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /* SYNC signal source selection       */
1333 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
1334 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
1335 
1336 #define CRS_CFGR_SYNCPOL_Pos      (31U)
1337 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
1338 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /* SYNC polarity selection            */
1339 
1340 /*******************  Bit definition for CRS_ISR register  *********************/
1341 #define CRS_ISR_SYNCOKF_Pos       (0U)
1342 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
1343 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /* SYNC event OK flag             */
1344 #define CRS_ISR_SYNCWARNF_Pos     (1U)
1345 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
1346 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /* SYNC warning                   */
1347 #define CRS_ISR_ERRF_Pos          (2U)
1348 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
1349 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /* SYNC error flag                */
1350 #define CRS_ISR_ESYNCF_Pos        (3U)
1351 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
1352 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /* Expected SYNC flag             */
1353 #define CRS_ISR_SYNCERR_Pos       (8U)
1354 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
1355 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /* SYNC error                     */
1356 #define CRS_ISR_SYNCMISS_Pos      (9U)
1357 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
1358 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /* SYNC missed                    */
1359 #define CRS_ISR_TRIMOVF_Pos       (10U)
1360 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
1361 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /* Trimming overflow or underflow */
1362 #define CRS_ISR_FEDIR_Pos         (15U)
1363 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
1364 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /* Frequency error direction      */
1365 #define CRS_ISR_FECAP_Pos         (16U)
1366 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
1367 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /* Frequency error capture        */
1368 
1369 /*******************  Bit definition for CRS_ICR register  *********************/
1370 #define CRS_ICR_SYNCOKC_Pos       (0U)
1371 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
1372 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /* SYNC event OK clear flag     */
1373 #define CRS_ICR_SYNCWARNC_Pos     (1U)
1374 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
1375 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /* SYNC warning clear flag      */
1376 #define CRS_ICR_ERRC_Pos          (2U)
1377 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
1378 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /* Error clear flag             */
1379 #define CRS_ICR_ESYNCC_Pos        (3U)
1380 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
1381 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /* Expected SYNC clear flag     */
1382 
1383 /******************************************************************************/
1384 /*                                                                            */
1385 /*                 Digital to Analog Converter (DAC)                          */
1386 /*                                                                            */
1387 /******************************************************************************/
1388 
1389 /*
1390  * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
1391  */
1392 /* Note: No specific macro feature on this device */
1393 
1394 /********************  Bit definition for DAC_CR register  ********************/
1395 #define DAC_CR_EN1_Pos              (0U)
1396 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
1397 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!< DAC channel1 enable */
1398 #define DAC_CR_BOFF1_Pos            (1U)
1399 #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
1400 #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!< DAC channel1 output buffer disable */
1401 #define DAC_CR_TEN1_Pos             (2U)
1402 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
1403 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!< DAC channel1 Trigger enable */
1404 
1405 #define DAC_CR_TSEL1_Pos            (3U)
1406 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
1407 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
1408 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
1409 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
1410 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
1411 
1412 #define DAC_CR_WAVE1_Pos            (6U)
1413 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
1414 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1415 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
1416 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
1417 
1418 #define DAC_CR_MAMP1_Pos            (8U)
1419 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
1420 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1421 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
1422 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
1423 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
1424 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
1425 
1426 #define DAC_CR_DMAEN1_Pos           (12U)
1427 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
1428 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!< DAC channel1 DMA enable */
1429 #define DAC_CR_DMAUDRIE1_Pos        (13U)
1430 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
1431 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!< DAC channel1 DMA Underrun interrupt enable */
1432 
1433 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
1434 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
1435 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
1436 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!< DAC channel1 software trigger */
1437 
1438 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
1439 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
1440 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
1441 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Right aligned data */
1442 
1443 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
1444 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
1445 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
1446 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!< DAC channel1 12-bit Left aligned data */
1447 
1448 /******************  Bit definition for DAC_DHR8R1 register  ******************/
1449 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
1450 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
1451 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!< DAC channel1 8-bit Right aligned data */
1452 
1453 /*******************  Bit definition for DAC_DOR1 register  *******************/
1454 #define DAC_DOR1_DACC1DOR_Pos       (0U)
1455 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
1456 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!< DAC channel1 data output */
1457 
1458 /********************  Bit definition for DAC_SR register  ********************/
1459 #define DAC_SR_DMAUDR1_Pos          (13U)
1460 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
1461 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!< DAC channel1 DMA underrun flag */
1462 
1463 /******************************************************************************/
1464 /*                                                                            */
1465 /*                           Debug MCU (DBGMCU)                               */
1466 /*                                                                            */
1467 /******************************************************************************/
1468 
1469 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
1470 #define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
1471 #define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
1472 #define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk        /*!< Device Identifier */
1473 
1474 #define DBGMCU_IDCODE_REV_ID_Pos               (16U)
1475 #define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
1476 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk        /*!< REV_ID[15:0] bits (Revision Identifier) */
1477 #define DBGMCU_IDCODE_REV_ID_0                 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
1478 #define DBGMCU_IDCODE_REV_ID_1                 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
1479 #define DBGMCU_IDCODE_REV_ID_2                 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
1480 #define DBGMCU_IDCODE_REV_ID_3                 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
1481 #define DBGMCU_IDCODE_REV_ID_4                 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
1482 #define DBGMCU_IDCODE_REV_ID_5                 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
1483 #define DBGMCU_IDCODE_REV_ID_6                 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
1484 #define DBGMCU_IDCODE_REV_ID_7                 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
1485 #define DBGMCU_IDCODE_REV_ID_8                 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
1486 #define DBGMCU_IDCODE_REV_ID_9                 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
1487 #define DBGMCU_IDCODE_REV_ID_10                (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
1488 #define DBGMCU_IDCODE_REV_ID_11                (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
1489 #define DBGMCU_IDCODE_REV_ID_12                (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
1490 #define DBGMCU_IDCODE_REV_ID_13                (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
1491 #define DBGMCU_IDCODE_REV_ID_14                (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
1492 #define DBGMCU_IDCODE_REV_ID_15                (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
1493 
1494 /******************  Bit definition for DBGMCU_CR register  *******************/
1495 #define DBGMCU_CR_DBG_Pos                      (0U)
1496 #define DBGMCU_CR_DBG_Msk                      (0x7UL << DBGMCU_CR_DBG_Pos)     /*!< 0x00000007 */
1497 #define DBGMCU_CR_DBG                          DBGMCU_CR_DBG_Msk               /*!< Debug mode mask */
1498 #define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
1499 #define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
1500 #define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk         /*!< Debug Sleep Mode */
1501 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
1502 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
1503 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk          /*!< Debug Stop Mode */
1504 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
1505 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
1506 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk       /*!< Debug Standby mode */
1507 
1508 /******************  Bit definition for DBGMCU_APB1_FZ register  **************/
1509 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos       (0U)
1510 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
1511 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP           DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
1512 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos       (4U)
1513 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
1514 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP           DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
1515 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos        (10U)
1516 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk        (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
1517 #define DBGMCU_APB1_FZ_DBG_RTC_STOP            DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
1518 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos       (11U)
1519 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
1520 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP           DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
1521 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos       (12U)
1522 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
1523 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
1524 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos       (21U)
1525 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
1526 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP           DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
1527 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos       (22U)
1528 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk       (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
1529 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP           DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
1530 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos    (31U)
1531 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
1532 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP        DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
1533 /******************  Bit definition for DBGMCU_APB2_FZ register  **************/
1534 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos      (5U)
1535 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
1536 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP          DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
1537 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos      (2U)
1538 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk      (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
1539 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP          DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
1540 
1541 /******************************************************************************/
1542 /*                                                                            */
1543 /*                           DMA Controller (DMA)                             */
1544 /*                                                                            */
1545 /******************************************************************************/
1546 
1547 /*******************  Bit definition for DMA_ISR register  ********************/
1548 #define DMA_ISR_GIF1_Pos       (0U)
1549 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
1550 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag    */
1551 #define DMA_ISR_TCIF1_Pos      (1U)
1552 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
1553 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag   */
1554 #define DMA_ISR_HTIF1_Pos      (2U)
1555 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
1556 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag       */
1557 #define DMA_ISR_TEIF1_Pos      (3U)
1558 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
1559 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag      */
1560 #define DMA_ISR_GIF2_Pos       (4U)
1561 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
1562 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag    */
1563 #define DMA_ISR_TCIF2_Pos      (5U)
1564 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
1565 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag   */
1566 #define DMA_ISR_HTIF2_Pos      (6U)
1567 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
1568 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag       */
1569 #define DMA_ISR_TEIF2_Pos      (7U)
1570 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
1571 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag      */
1572 #define DMA_ISR_GIF3_Pos       (8U)
1573 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
1574 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag    */
1575 #define DMA_ISR_TCIF3_Pos      (9U)
1576 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
1577 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag   */
1578 #define DMA_ISR_HTIF3_Pos      (10U)
1579 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
1580 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag       */
1581 #define DMA_ISR_TEIF3_Pos      (11U)
1582 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
1583 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag      */
1584 #define DMA_ISR_GIF4_Pos       (12U)
1585 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
1586 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag    */
1587 #define DMA_ISR_TCIF4_Pos      (13U)
1588 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
1589 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag   */
1590 #define DMA_ISR_HTIF4_Pos      (14U)
1591 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
1592 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag       */
1593 #define DMA_ISR_TEIF4_Pos      (15U)
1594 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
1595 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag      */
1596 #define DMA_ISR_GIF5_Pos       (16U)
1597 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
1598 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag    */
1599 #define DMA_ISR_TCIF5_Pos      (17U)
1600 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
1601 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag   */
1602 #define DMA_ISR_HTIF5_Pos      (18U)
1603 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
1604 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag       */
1605 #define DMA_ISR_TEIF5_Pos      (19U)
1606 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
1607 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag      */
1608 #define DMA_ISR_GIF6_Pos       (20U)
1609 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
1610 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
1611 #define DMA_ISR_TCIF6_Pos      (21U)
1612 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
1613 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
1614 #define DMA_ISR_HTIF6_Pos      (22U)
1615 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
1616 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
1617 #define DMA_ISR_TEIF6_Pos      (23U)
1618 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
1619 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
1620 #define DMA_ISR_GIF7_Pos       (24U)
1621 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
1622 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
1623 #define DMA_ISR_TCIF7_Pos      (25U)
1624 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
1625 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
1626 #define DMA_ISR_HTIF7_Pos      (26U)
1627 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
1628 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
1629 #define DMA_ISR_TEIF7_Pos      (27U)
1630 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
1631 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
1632 
1633 /*******************  Bit definition for DMA_IFCR register  *******************/
1634 #define DMA_IFCR_CGIF1_Pos     (0U)
1635 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
1636 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear    */
1637 #define DMA_IFCR_CTCIF1_Pos    (1U)
1638 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
1639 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear   */
1640 #define DMA_IFCR_CHTIF1_Pos    (2U)
1641 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
1642 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear       */
1643 #define DMA_IFCR_CTEIF1_Pos    (3U)
1644 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
1645 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear      */
1646 #define DMA_IFCR_CGIF2_Pos     (4U)
1647 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
1648 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear    */
1649 #define DMA_IFCR_CTCIF2_Pos    (5U)
1650 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
1651 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear   */
1652 #define DMA_IFCR_CHTIF2_Pos    (6U)
1653 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
1654 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear       */
1655 #define DMA_IFCR_CTEIF2_Pos    (7U)
1656 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
1657 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear      */
1658 #define DMA_IFCR_CGIF3_Pos     (8U)
1659 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
1660 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear    */
1661 #define DMA_IFCR_CTCIF3_Pos    (9U)
1662 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
1663 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear   */
1664 #define DMA_IFCR_CHTIF3_Pos    (10U)
1665 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
1666 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear       */
1667 #define DMA_IFCR_CTEIF3_Pos    (11U)
1668 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
1669 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear      */
1670 #define DMA_IFCR_CGIF4_Pos     (12U)
1671 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
1672 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear    */
1673 #define DMA_IFCR_CTCIF4_Pos    (13U)
1674 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
1675 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear   */
1676 #define DMA_IFCR_CHTIF4_Pos    (14U)
1677 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
1678 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear       */
1679 #define DMA_IFCR_CTEIF4_Pos    (15U)
1680 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
1681 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear      */
1682 #define DMA_IFCR_CGIF5_Pos     (16U)
1683 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
1684 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear    */
1685 #define DMA_IFCR_CTCIF5_Pos    (17U)
1686 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
1687 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear   */
1688 #define DMA_IFCR_CHTIF5_Pos    (18U)
1689 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
1690 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear       */
1691 #define DMA_IFCR_CTEIF5_Pos    (19U)
1692 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
1693 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear      */
1694 #define DMA_IFCR_CGIF6_Pos     (20U)
1695 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
1696 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
1697 #define DMA_IFCR_CTCIF6_Pos    (21U)
1698 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
1699 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
1700 #define DMA_IFCR_CHTIF6_Pos    (22U)
1701 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
1702 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
1703 #define DMA_IFCR_CTEIF6_Pos    (23U)
1704 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
1705 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
1706 #define DMA_IFCR_CGIF7_Pos     (24U)
1707 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
1708 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
1709 #define DMA_IFCR_CTCIF7_Pos    (25U)
1710 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
1711 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
1712 #define DMA_IFCR_CHTIF7_Pos    (26U)
1713 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
1714 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
1715 #define DMA_IFCR_CTEIF7_Pos    (27U)
1716 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
1717 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
1718 
1719 /*******************  Bit definition for DMA_CCR register  ********************/
1720 #define DMA_CCR_EN_Pos         (0U)
1721 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
1722 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
1723 #define DMA_CCR_TCIE_Pos       (1U)
1724 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
1725 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
1726 #define DMA_CCR_HTIE_Pos       (2U)
1727 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
1728 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
1729 #define DMA_CCR_TEIE_Pos       (3U)
1730 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
1731 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
1732 #define DMA_CCR_DIR_Pos        (4U)
1733 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
1734 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
1735 #define DMA_CCR_CIRC_Pos       (5U)
1736 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
1737 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
1738 #define DMA_CCR_PINC_Pos       (6U)
1739 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
1740 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
1741 #define DMA_CCR_MINC_Pos       (7U)
1742 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
1743 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
1744 
1745 #define DMA_CCR_PSIZE_Pos      (8U)
1746 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
1747 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
1748 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
1749 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
1750 
1751 #define DMA_CCR_MSIZE_Pos      (10U)
1752 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
1753 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
1754 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
1755 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
1756 
1757 #define DMA_CCR_PL_Pos         (12U)
1758 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
1759 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
1760 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
1761 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
1762 
1763 #define DMA_CCR_MEM2MEM_Pos    (14U)
1764 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
1765 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
1766 
1767 /******************  Bit definition for DMA_CNDTR register  *******************/
1768 #define DMA_CNDTR_NDT_Pos      (0U)
1769 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
1770 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
1771 
1772 /******************  Bit definition for DMA_CPAR register  ********************/
1773 #define DMA_CPAR_PA_Pos        (0U)
1774 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
1775 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
1776 
1777 /******************  Bit definition for DMA_CMAR register  ********************/
1778 #define DMA_CMAR_MA_Pos        (0U)
1779 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
1780 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
1781 
1782 
1783 /*******************  Bit definition for DMA_CSELR register  *******************/
1784 #define DMA_CSELR_C1S_Pos      (0U)
1785 #define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
1786 #define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
1787 #define DMA_CSELR_C2S_Pos      (4U)
1788 #define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
1789 #define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
1790 #define DMA_CSELR_C3S_Pos      (8U)
1791 #define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
1792 #define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
1793 #define DMA_CSELR_C4S_Pos      (12U)
1794 #define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
1795 #define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
1796 #define DMA_CSELR_C5S_Pos      (16U)
1797 #define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
1798 #define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
1799 #define DMA_CSELR_C6S_Pos      (20U)
1800 #define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
1801 #define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
1802 #define DMA_CSELR_C7S_Pos      (24U)
1803 #define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
1804 #define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
1805 
1806 /******************************************************************************/
1807 /*                                                                            */
1808 /*                 External Interrupt/Event Controller (EXTI)                 */
1809 /*                                                                            */
1810 /******************************************************************************/
1811 
1812 /*******************  Bit definition for EXTI_IMR register  *******************/
1813 #define EXTI_IMR_IM0_Pos        (0U)
1814 #define EXTI_IMR_IM0_Msk        (0x1UL << EXTI_IMR_IM0_Pos)                     /*!< 0x00000001 */
1815 #define EXTI_IMR_IM0            EXTI_IMR_IM0_Msk                               /*!< Interrupt Mask on line 0  */
1816 #define EXTI_IMR_IM1_Pos        (1U)
1817 #define EXTI_IMR_IM1_Msk        (0x1UL << EXTI_IMR_IM1_Pos)                     /*!< 0x00000002 */
1818 #define EXTI_IMR_IM1            EXTI_IMR_IM1_Msk                               /*!< Interrupt Mask on line 1  */
1819 #define EXTI_IMR_IM2_Pos        (2U)
1820 #define EXTI_IMR_IM2_Msk        (0x1UL << EXTI_IMR_IM2_Pos)                     /*!< 0x00000004 */
1821 #define EXTI_IMR_IM2            EXTI_IMR_IM2_Msk                               /*!< Interrupt Mask on line 2  */
1822 #define EXTI_IMR_IM3_Pos        (3U)
1823 #define EXTI_IMR_IM3_Msk        (0x1UL << EXTI_IMR_IM3_Pos)                     /*!< 0x00000008 */
1824 #define EXTI_IMR_IM3            EXTI_IMR_IM3_Msk                               /*!< Interrupt Mask on line 3  */
1825 #define EXTI_IMR_IM4_Pos        (4U)
1826 #define EXTI_IMR_IM4_Msk        (0x1UL << EXTI_IMR_IM4_Pos)                     /*!< 0x00000010 */
1827 #define EXTI_IMR_IM4            EXTI_IMR_IM4_Msk                               /*!< Interrupt Mask on line 4  */
1828 #define EXTI_IMR_IM5_Pos        (5U)
1829 #define EXTI_IMR_IM5_Msk        (0x1UL << EXTI_IMR_IM5_Pos)                     /*!< 0x00000020 */
1830 #define EXTI_IMR_IM5            EXTI_IMR_IM5_Msk                               /*!< Interrupt Mask on line 5  */
1831 #define EXTI_IMR_IM6_Pos        (6U)
1832 #define EXTI_IMR_IM6_Msk        (0x1UL << EXTI_IMR_IM6_Pos)                     /*!< 0x00000040 */
1833 #define EXTI_IMR_IM6            EXTI_IMR_IM6_Msk                               /*!< Interrupt Mask on line 6  */
1834 #define EXTI_IMR_IM7_Pos        (7U)
1835 #define EXTI_IMR_IM7_Msk        (0x1UL << EXTI_IMR_IM7_Pos)                     /*!< 0x00000080 */
1836 #define EXTI_IMR_IM7            EXTI_IMR_IM7_Msk                               /*!< Interrupt Mask on line 7  */
1837 #define EXTI_IMR_IM8_Pos        (8U)
1838 #define EXTI_IMR_IM8_Msk        (0x1UL << EXTI_IMR_IM8_Pos)                     /*!< 0x00000100 */
1839 #define EXTI_IMR_IM8            EXTI_IMR_IM8_Msk                               /*!< Interrupt Mask on line 8  */
1840 #define EXTI_IMR_IM9_Pos        (9U)
1841 #define EXTI_IMR_IM9_Msk        (0x1UL << EXTI_IMR_IM9_Pos)                     /*!< 0x00000200 */
1842 #define EXTI_IMR_IM9            EXTI_IMR_IM9_Msk                               /*!< Interrupt Mask on line 9  */
1843 #define EXTI_IMR_IM10_Pos       (10U)
1844 #define EXTI_IMR_IM10_Msk       (0x1UL << EXTI_IMR_IM10_Pos)                    /*!< 0x00000400 */
1845 #define EXTI_IMR_IM10           EXTI_IMR_IM10_Msk                              /*!< Interrupt Mask on line 10 */
1846 #define EXTI_IMR_IM11_Pos       (11U)
1847 #define EXTI_IMR_IM11_Msk       (0x1UL << EXTI_IMR_IM11_Pos)                    /*!< 0x00000800 */
1848 #define EXTI_IMR_IM11           EXTI_IMR_IM11_Msk                              /*!< Interrupt Mask on line 11 */
1849 #define EXTI_IMR_IM12_Pos       (12U)
1850 #define EXTI_IMR_IM12_Msk       (0x1UL << EXTI_IMR_IM12_Pos)                    /*!< 0x00001000 */
1851 #define EXTI_IMR_IM12           EXTI_IMR_IM12_Msk                              /*!< Interrupt Mask on line 12 */
1852 #define EXTI_IMR_IM13_Pos       (13U)
1853 #define EXTI_IMR_IM13_Msk       (0x1UL << EXTI_IMR_IM13_Pos)                    /*!< 0x00002000 */
1854 #define EXTI_IMR_IM13           EXTI_IMR_IM13_Msk                              /*!< Interrupt Mask on line 13 */
1855 #define EXTI_IMR_IM14_Pos       (14U)
1856 #define EXTI_IMR_IM14_Msk       (0x1UL << EXTI_IMR_IM14_Pos)                    /*!< 0x00004000 */
1857 #define EXTI_IMR_IM14           EXTI_IMR_IM14_Msk                              /*!< Interrupt Mask on line 14 */
1858 #define EXTI_IMR_IM15_Pos       (15U)
1859 #define EXTI_IMR_IM15_Msk       (0x1UL << EXTI_IMR_IM15_Pos)                    /*!< 0x00008000 */
1860 #define EXTI_IMR_IM15           EXTI_IMR_IM15_Msk                              /*!< Interrupt Mask on line 15 */
1861 #define EXTI_IMR_IM16_Pos       (16U)
1862 #define EXTI_IMR_IM16_Msk       (0x1UL << EXTI_IMR_IM16_Pos)                    /*!< 0x00010000 */
1863 #define EXTI_IMR_IM16           EXTI_IMR_IM16_Msk                              /*!< Interrupt Mask on line 16 */
1864 #define EXTI_IMR_IM17_Pos       (17U)
1865 #define EXTI_IMR_IM17_Msk       (0x1UL << EXTI_IMR_IM17_Pos)                    /*!< 0x00020000 */
1866 #define EXTI_IMR_IM17           EXTI_IMR_IM17_Msk                              /*!< Interrupt Mask on line 17 */
1867 #define EXTI_IMR_IM18_Pos       (18U)
1868 #define EXTI_IMR_IM18_Msk       (0x1UL << EXTI_IMR_IM18_Pos)                    /*!< 0x00040000 */
1869 #define EXTI_IMR_IM18           EXTI_IMR_IM18_Msk                              /*!< Interrupt Mask on line 18 */
1870 #define EXTI_IMR_IM19_Pos       (19U)
1871 #define EXTI_IMR_IM19_Msk       (0x1UL << EXTI_IMR_IM19_Pos)                    /*!< 0x00080000 */
1872 #define EXTI_IMR_IM19           EXTI_IMR_IM19_Msk                              /*!< Interrupt Mask on line 19 */
1873 #define EXTI_IMR_IM20_Pos       (20U)
1874 #define EXTI_IMR_IM20_Msk       (0x1UL << EXTI_IMR_IM20_Pos)                    /*!< 0x00100000 */
1875 #define EXTI_IMR_IM20           EXTI_IMR_IM20_Msk                              /*!< Interrupt Mask on line 20 */
1876 #define EXTI_IMR_IM21_Pos       (21U)
1877 #define EXTI_IMR_IM21_Msk       (0x1UL << EXTI_IMR_IM21_Pos)                    /*!< 0x00200000 */
1878 #define EXTI_IMR_IM21           EXTI_IMR_IM21_Msk                              /*!< Interrupt Mask on line 21 */
1879 #define EXTI_IMR_IM22_Pos       (22U)
1880 #define EXTI_IMR_IM22_Msk       (0x1UL << EXTI_IMR_IM22_Pos)                    /*!< 0x00400000 */
1881 #define EXTI_IMR_IM22           EXTI_IMR_IM22_Msk                              /*!< Interrupt Mask on line 22 */
1882 #define EXTI_IMR_IM23_Pos       (23U)
1883 #define EXTI_IMR_IM23_Msk       (0x1UL << EXTI_IMR_IM23_Pos)                    /*!< 0x00800000 */
1884 #define EXTI_IMR_IM23           EXTI_IMR_IM23_Msk                              /*!< Interrupt Mask on line 23 */
1885 #define EXTI_IMR_IM25_Pos       (25U)
1886 #define EXTI_IMR_IM25_Msk       (0x1UL << EXTI_IMR_IM25_Pos)                    /*!< 0x02000000 */
1887 #define EXTI_IMR_IM25           EXTI_IMR_IM25_Msk                              /*!< Interrupt Mask on line 25 */
1888 #define EXTI_IMR_IM26_Pos       (26U)
1889 #define EXTI_IMR_IM26_Msk       (0x1UL << EXTI_IMR_IM26_Pos)                    /*!< 0x04000000 */
1890 #define EXTI_IMR_IM26           EXTI_IMR_IM26_Msk                              /*!< Interrupt Mask on line 26 */
1891 #define EXTI_IMR_IM28_Pos       (28U)
1892 #define EXTI_IMR_IM28_Msk       (0x1UL << EXTI_IMR_IM28_Pos)                    /*!< 0x10000000 */
1893 #define EXTI_IMR_IM28           EXTI_IMR_IM28_Msk                              /*!< Interrupt Mask on line 28 */
1894 #define EXTI_IMR_IM29_Pos       (29U)
1895 #define EXTI_IMR_IM29_Msk       (0x1UL << EXTI_IMR_IM29_Pos)                    /*!< 0x20000000 */
1896 #define EXTI_IMR_IM29           EXTI_IMR_IM29_Msk                              /*!< Interrupt Mask on line 29 */
1897 
1898 #define EXTI_IMR_IM_Pos         (0U)
1899 #define EXTI_IMR_IM_Msk         (0x36FFFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x36FFFFFF */
1900 #define EXTI_IMR_IM             EXTI_IMR_IM_Msk                                /*!< Interrupt Mask All */
1901 
1902 /******************  Bit definition for EXTI_EMR register  ********************/
1903 #define EXTI_EMR_EM0_Pos        (0U)
1904 #define EXTI_EMR_EM0_Msk        (0x1UL << EXTI_EMR_EM0_Pos)                     /*!< 0x00000001 */
1905 #define EXTI_EMR_EM0            EXTI_EMR_EM0_Msk                               /*!< Event Mask on line 0  */
1906 #define EXTI_EMR_EM1_Pos        (1U)
1907 #define EXTI_EMR_EM1_Msk        (0x1UL << EXTI_EMR_EM1_Pos)                     /*!< 0x00000002 */
1908 #define EXTI_EMR_EM1            EXTI_EMR_EM1_Msk                               /*!< Event Mask on line 1  */
1909 #define EXTI_EMR_EM2_Pos        (2U)
1910 #define EXTI_EMR_EM2_Msk        (0x1UL << EXTI_EMR_EM2_Pos)                     /*!< 0x00000004 */
1911 #define EXTI_EMR_EM2            EXTI_EMR_EM2_Msk                               /*!< Event Mask on line 2  */
1912 #define EXTI_EMR_EM3_Pos        (3U)
1913 #define EXTI_EMR_EM3_Msk        (0x1UL << EXTI_EMR_EM3_Pos)                     /*!< 0x00000008 */
1914 #define EXTI_EMR_EM3            EXTI_EMR_EM3_Msk                               /*!< Event Mask on line 3  */
1915 #define EXTI_EMR_EM4_Pos        (4U)
1916 #define EXTI_EMR_EM4_Msk        (0x1UL << EXTI_EMR_EM4_Pos)                     /*!< 0x00000010 */
1917 #define EXTI_EMR_EM4            EXTI_EMR_EM4_Msk                               /*!< Event Mask on line 4  */
1918 #define EXTI_EMR_EM5_Pos        (5U)
1919 #define EXTI_EMR_EM5_Msk        (0x1UL << EXTI_EMR_EM5_Pos)                     /*!< 0x00000020 */
1920 #define EXTI_EMR_EM5            EXTI_EMR_EM5_Msk                               /*!< Event Mask on line 5  */
1921 #define EXTI_EMR_EM6_Pos        (6U)
1922 #define EXTI_EMR_EM6_Msk        (0x1UL << EXTI_EMR_EM6_Pos)                     /*!< 0x00000040 */
1923 #define EXTI_EMR_EM6            EXTI_EMR_EM6_Msk                               /*!< Event Mask on line 6  */
1924 #define EXTI_EMR_EM7_Pos        (7U)
1925 #define EXTI_EMR_EM7_Msk        (0x1UL << EXTI_EMR_EM7_Pos)                     /*!< 0x00000080 */
1926 #define EXTI_EMR_EM7            EXTI_EMR_EM7_Msk                               /*!< Event Mask on line 7  */
1927 #define EXTI_EMR_EM8_Pos        (8U)
1928 #define EXTI_EMR_EM8_Msk        (0x1UL << EXTI_EMR_EM8_Pos)                     /*!< 0x00000100 */
1929 #define EXTI_EMR_EM8            EXTI_EMR_EM8_Msk                               /*!< Event Mask on line 8  */
1930 #define EXTI_EMR_EM9_Pos        (9U)
1931 #define EXTI_EMR_EM9_Msk        (0x1UL << EXTI_EMR_EM9_Pos)                     /*!< 0x00000200 */
1932 #define EXTI_EMR_EM9            EXTI_EMR_EM9_Msk                               /*!< Event Mask on line 9  */
1933 #define EXTI_EMR_EM10_Pos       (10U)
1934 #define EXTI_EMR_EM10_Msk       (0x1UL << EXTI_EMR_EM10_Pos)                    /*!< 0x00000400 */
1935 #define EXTI_EMR_EM10           EXTI_EMR_EM10_Msk                              /*!< Event Mask on line 10 */
1936 #define EXTI_EMR_EM11_Pos       (11U)
1937 #define EXTI_EMR_EM11_Msk       (0x1UL << EXTI_EMR_EM11_Pos)                    /*!< 0x00000800 */
1938 #define EXTI_EMR_EM11           EXTI_EMR_EM11_Msk                              /*!< Event Mask on line 11 */
1939 #define EXTI_EMR_EM12_Pos       (12U)
1940 #define EXTI_EMR_EM12_Msk       (0x1UL << EXTI_EMR_EM12_Pos)                    /*!< 0x00001000 */
1941 #define EXTI_EMR_EM12           EXTI_EMR_EM12_Msk                              /*!< Event Mask on line 12 */
1942 #define EXTI_EMR_EM13_Pos       (13U)
1943 #define EXTI_EMR_EM13_Msk       (0x1UL << EXTI_EMR_EM13_Pos)                    /*!< 0x00002000 */
1944 #define EXTI_EMR_EM13           EXTI_EMR_EM13_Msk                              /*!< Event Mask on line 13 */
1945 #define EXTI_EMR_EM14_Pos       (14U)
1946 #define EXTI_EMR_EM14_Msk       (0x1UL << EXTI_EMR_EM14_Pos)                    /*!< 0x00004000 */
1947 #define EXTI_EMR_EM14           EXTI_EMR_EM14_Msk                              /*!< Event Mask on line 14 */
1948 #define EXTI_EMR_EM15_Pos       (15U)
1949 #define EXTI_EMR_EM15_Msk       (0x1UL << EXTI_EMR_EM15_Pos)                    /*!< 0x00008000 */
1950 #define EXTI_EMR_EM15           EXTI_EMR_EM15_Msk                              /*!< Event Mask on line 15 */
1951 #define EXTI_EMR_EM16_Pos       (16U)
1952 #define EXTI_EMR_EM16_Msk       (0x1UL << EXTI_EMR_EM16_Pos)                    /*!< 0x00010000 */
1953 #define EXTI_EMR_EM16           EXTI_EMR_EM16_Msk                              /*!< Event Mask on line 16 */
1954 #define EXTI_EMR_EM17_Pos       (17U)
1955 #define EXTI_EMR_EM17_Msk       (0x1UL << EXTI_EMR_EM17_Pos)                    /*!< 0x00020000 */
1956 #define EXTI_EMR_EM17           EXTI_EMR_EM17_Msk                              /*!< Event Mask on line 17 */
1957 #define EXTI_EMR_EM18_Pos       (18U)
1958 #define EXTI_EMR_EM18_Msk       (0x1UL << EXTI_EMR_EM18_Pos)                    /*!< 0x00040000 */
1959 #define EXTI_EMR_EM18           EXTI_EMR_EM18_Msk                              /*!< Event Mask on line 18 */
1960 #define EXTI_EMR_EM19_Pos       (19U)
1961 #define EXTI_EMR_EM19_Msk       (0x1UL << EXTI_EMR_EM19_Pos)                    /*!< 0x00080000 */
1962 #define EXTI_EMR_EM19           EXTI_EMR_EM19_Msk                              /*!< Event Mask on line 19 */
1963 #define EXTI_EMR_EM20_Pos       (20U)
1964 #define EXTI_EMR_EM20_Msk       (0x1UL << EXTI_EMR_EM20_Pos)                    /*!< 0x00100000 */
1965 #define EXTI_EMR_EM20           EXTI_EMR_EM20_Msk                              /*!< Event Mask on line 20 */
1966 #define EXTI_EMR_EM21_Pos       (21U)
1967 #define EXTI_EMR_EM21_Msk       (0x1UL << EXTI_EMR_EM21_Pos)                    /*!< 0x00200000 */
1968 #define EXTI_EMR_EM21           EXTI_EMR_EM21_Msk                              /*!< Event Mask on line 21 */
1969 #define EXTI_EMR_EM22_Pos       (22U)
1970 #define EXTI_EMR_EM22_Msk       (0x1UL << EXTI_EMR_EM22_Pos)                    /*!< 0x00400000 */
1971 #define EXTI_EMR_EM22           EXTI_EMR_EM22_Msk                              /*!< Event Mask on line 22 */
1972 #define EXTI_EMR_EM23_Pos       (23U)
1973 #define EXTI_EMR_EM23_Msk       (0x1UL << EXTI_EMR_EM23_Pos)                    /*!< 0x00800000 */
1974 #define EXTI_EMR_EM23           EXTI_EMR_EM23_Msk                              /*!< Event Mask on line 23 */
1975 #define EXTI_EMR_EM25_Pos       (25U)
1976 #define EXTI_EMR_EM25_Msk       (0x1UL << EXTI_EMR_EM25_Pos)                    /*!< 0x02000000 */
1977 #define EXTI_EMR_EM25           EXTI_EMR_EM25_Msk                              /*!< Event Mask on line 25 */
1978 #define EXTI_EMR_EM26_Pos       (26U)
1979 #define EXTI_EMR_EM26_Msk       (0x1UL << EXTI_EMR_EM26_Pos)                    /*!< 0x04000000 */
1980 #define EXTI_EMR_EM26           EXTI_EMR_EM26_Msk                              /*!< Event Mask on line 26 */
1981 #define EXTI_EMR_EM28_Pos       (28U)
1982 #define EXTI_EMR_EM28_Msk       (0x1UL << EXTI_EMR_EM28_Pos)                    /*!< 0x10000000 */
1983 #define EXTI_EMR_EM28           EXTI_EMR_EM28_Msk                              /*!< Event Mask on line 28 */
1984 #define EXTI_EMR_EM29_Pos       (29U)
1985 #define EXTI_EMR_EM29_Msk       (0x1UL << EXTI_EMR_EM29_Pos)                    /*!< 0x20000000 */
1986 #define EXTI_EMR_EM29           EXTI_EMR_EM29_Msk                              /*!< Event Mask on line 29 */
1987 
1988 /*******************  Bit definition for EXTI_RTSR register  ******************/
1989 #define EXTI_RTSR_RT0_Pos       (0U)
1990 #define EXTI_RTSR_RT0_Msk       (0x1UL << EXTI_RTSR_RT0_Pos)                    /*!< 0x00000001 */
1991 #define EXTI_RTSR_RT0           EXTI_RTSR_RT0_Msk                              /*!< Rising trigger event configuration bit of line 0 */
1992 #define EXTI_RTSR_RT1_Pos       (1U)
1993 #define EXTI_RTSR_RT1_Msk       (0x1UL << EXTI_RTSR_RT1_Pos)                    /*!< 0x00000002 */
1994 #define EXTI_RTSR_RT1           EXTI_RTSR_RT1_Msk                              /*!< Rising trigger event configuration bit of line 1 */
1995 #define EXTI_RTSR_RT2_Pos       (2U)
1996 #define EXTI_RTSR_RT2_Msk       (0x1UL << EXTI_RTSR_RT2_Pos)                    /*!< 0x00000004 */
1997 #define EXTI_RTSR_RT2           EXTI_RTSR_RT2_Msk                              /*!< Rising trigger event configuration bit of line 2 */
1998 #define EXTI_RTSR_RT3_Pos       (3U)
1999 #define EXTI_RTSR_RT3_Msk       (0x1UL << EXTI_RTSR_RT3_Pos)                    /*!< 0x00000008 */
2000 #define EXTI_RTSR_RT3           EXTI_RTSR_RT3_Msk                              /*!< Rising trigger event configuration bit of line 3 */
2001 #define EXTI_RTSR_RT4_Pos       (4U)
2002 #define EXTI_RTSR_RT4_Msk       (0x1UL << EXTI_RTSR_RT4_Pos)                    /*!< 0x00000010 */
2003 #define EXTI_RTSR_RT4           EXTI_RTSR_RT4_Msk                              /*!< Rising trigger event configuration bit of line 4 */
2004 #define EXTI_RTSR_RT5_Pos       (5U)
2005 #define EXTI_RTSR_RT5_Msk       (0x1UL << EXTI_RTSR_RT5_Pos)                    /*!< 0x00000020 */
2006 #define EXTI_RTSR_RT5           EXTI_RTSR_RT5_Msk                              /*!< Rising trigger event configuration bit of line 5 */
2007 #define EXTI_RTSR_RT6_Pos       (6U)
2008 #define EXTI_RTSR_RT6_Msk       (0x1UL << EXTI_RTSR_RT6_Pos)                    /*!< 0x00000040 */
2009 #define EXTI_RTSR_RT6           EXTI_RTSR_RT6_Msk                              /*!< Rising trigger event configuration bit of line 6 */
2010 #define EXTI_RTSR_RT7_Pos       (7U)
2011 #define EXTI_RTSR_RT7_Msk       (0x1UL << EXTI_RTSR_RT7_Pos)                    /*!< 0x00000080 */
2012 #define EXTI_RTSR_RT7           EXTI_RTSR_RT7_Msk                              /*!< Rising trigger event configuration bit of line 7 */
2013 #define EXTI_RTSR_RT8_Pos       (8U)
2014 #define EXTI_RTSR_RT8_Msk       (0x1UL << EXTI_RTSR_RT8_Pos)                    /*!< 0x00000100 */
2015 #define EXTI_RTSR_RT8           EXTI_RTSR_RT8_Msk                              /*!< Rising trigger event configuration bit of line 8 */
2016 #define EXTI_RTSR_RT9_Pos       (9U)
2017 #define EXTI_RTSR_RT9_Msk       (0x1UL << EXTI_RTSR_RT9_Pos)                    /*!< 0x00000200 */
2018 #define EXTI_RTSR_RT9           EXTI_RTSR_RT9_Msk                              /*!< Rising trigger event configuration bit of line 9 */
2019 #define EXTI_RTSR_RT10_Pos      (10U)
2020 #define EXTI_RTSR_RT10_Msk      (0x1UL << EXTI_RTSR_RT10_Pos)                   /*!< 0x00000400 */
2021 #define EXTI_RTSR_RT10          EXTI_RTSR_RT10_Msk                             /*!< Rising trigger event configuration bit of line 10 */
2022 #define EXTI_RTSR_RT11_Pos      (11U)
2023 #define EXTI_RTSR_RT11_Msk      (0x1UL << EXTI_RTSR_RT11_Pos)                   /*!< 0x00000800 */
2024 #define EXTI_RTSR_RT11          EXTI_RTSR_RT11_Msk                             /*!< Rising trigger event configuration bit of line 11 */
2025 #define EXTI_RTSR_RT12_Pos      (12U)
2026 #define EXTI_RTSR_RT12_Msk      (0x1UL << EXTI_RTSR_RT12_Pos)                   /*!< 0x00001000 */
2027 #define EXTI_RTSR_RT12          EXTI_RTSR_RT12_Msk                             /*!< Rising trigger event configuration bit of line 12 */
2028 #define EXTI_RTSR_RT13_Pos      (13U)
2029 #define EXTI_RTSR_RT13_Msk      (0x1UL << EXTI_RTSR_RT13_Pos)                   /*!< 0x00002000 */
2030 #define EXTI_RTSR_RT13          EXTI_RTSR_RT13_Msk                             /*!< Rising trigger event configuration bit of line 13 */
2031 #define EXTI_RTSR_RT14_Pos      (14U)
2032 #define EXTI_RTSR_RT14_Msk      (0x1UL << EXTI_RTSR_RT14_Pos)                   /*!< 0x00004000 */
2033 #define EXTI_RTSR_RT14          EXTI_RTSR_RT14_Msk                             /*!< Rising trigger event configuration bit of line 14 */
2034 #define EXTI_RTSR_RT15_Pos      (15U)
2035 #define EXTI_RTSR_RT15_Msk      (0x1UL << EXTI_RTSR_RT15_Pos)                   /*!< 0x00008000 */
2036 #define EXTI_RTSR_RT15          EXTI_RTSR_RT15_Msk                             /*!< Rising trigger event configuration bit of line 15 */
2037 #define EXTI_RTSR_RT16_Pos      (16U)
2038 #define EXTI_RTSR_RT16_Msk      (0x1UL << EXTI_RTSR_RT16_Pos)                   /*!< 0x00010000 */
2039 #define EXTI_RTSR_RT16          EXTI_RTSR_RT16_Msk                             /*!< Rising trigger event configuration bit of line 16 */
2040 #define EXTI_RTSR_RT17_Pos      (17U)
2041 #define EXTI_RTSR_RT17_Msk      (0x1UL << EXTI_RTSR_RT17_Pos)                   /*!< 0x00020000 */
2042 #define EXTI_RTSR_RT17          EXTI_RTSR_RT17_Msk                             /*!< Rising trigger event configuration bit of line 17 */
2043 #define EXTI_RTSR_RT19_Pos      (19U)
2044 #define EXTI_RTSR_RT19_Msk      (0x1UL << EXTI_RTSR_RT19_Pos)                   /*!< 0x00080000 */
2045 #define EXTI_RTSR_RT19          EXTI_RTSR_RT19_Msk                             /*!< Rising trigger event configuration bit of line 19 */
2046 #define EXTI_RTSR_RT20_Pos      (20U)
2047 #define EXTI_RTSR_RT20_Msk      (0x1UL << EXTI_RTSR_RT20_Pos)                   /*!< 0x00100000 */
2048 #define EXTI_RTSR_RT20          EXTI_RTSR_RT20_Msk                             /*!< Rising trigger event configuration bit of line 20 */
2049 #define EXTI_RTSR_RT21_Pos      (21U)
2050 #define EXTI_RTSR_RT21_Msk      (0x1UL << EXTI_RTSR_RT21_Pos)                   /*!< 0x00200000 */
2051 #define EXTI_RTSR_RT21          EXTI_RTSR_RT21_Msk                             /*!< Rising trigger event configuration bit of line 21 */
2052 #define EXTI_RTSR_RT22_Pos      (22U)
2053 #define EXTI_RTSR_RT22_Msk      (0x1UL << EXTI_RTSR_RT22_Pos)                   /*!< 0x00400000 */
2054 #define EXTI_RTSR_RT22          EXTI_RTSR_RT22_Msk                             /*!< Rising trigger event configuration bit of line 22 */
2055 
2056 /* Legacy defines */
2057 #define EXTI_RTSR_TR0                       EXTI_RTSR_RT0
2058 #define EXTI_RTSR_TR1                       EXTI_RTSR_RT1
2059 #define EXTI_RTSR_TR2                       EXTI_RTSR_RT2
2060 #define EXTI_RTSR_TR3                       EXTI_RTSR_RT3
2061 #define EXTI_RTSR_TR4                       EXTI_RTSR_RT4
2062 #define EXTI_RTSR_TR5                       EXTI_RTSR_RT5
2063 #define EXTI_RTSR_TR6                       EXTI_RTSR_RT6
2064 #define EXTI_RTSR_TR7                       EXTI_RTSR_RT7
2065 #define EXTI_RTSR_TR8                       EXTI_RTSR_RT8
2066 #define EXTI_RTSR_TR9                       EXTI_RTSR_RT9
2067 #define EXTI_RTSR_TR10                      EXTI_RTSR_RT10
2068 #define EXTI_RTSR_TR11                      EXTI_RTSR_RT11
2069 #define EXTI_RTSR_TR12                      EXTI_RTSR_RT12
2070 #define EXTI_RTSR_TR13                      EXTI_RTSR_RT13
2071 #define EXTI_RTSR_TR14                      EXTI_RTSR_RT14
2072 #define EXTI_RTSR_TR15                      EXTI_RTSR_RT15
2073 #define EXTI_RTSR_TR16                      EXTI_RTSR_RT16
2074 #define EXTI_RTSR_TR17                      EXTI_RTSR_RT17
2075 #define EXTI_RTSR_TR19                      EXTI_RTSR_RT19
2076 #define EXTI_RTSR_TR20                      EXTI_RTSR_RT20
2077 #define EXTI_RTSR_TR21                      EXTI_RTSR_RT21
2078 #define EXTI_RTSR_TR22                      EXTI_RTSR_RT22
2079 
2080 /*******************  Bit definition for EXTI_FTSR register *******************/
2081 #define EXTI_FTSR_FT0_Pos       (0U)
2082 #define EXTI_FTSR_FT0_Msk       (0x1UL << EXTI_FTSR_FT0_Pos)                    /*!< 0x00000001 */
2083 #define EXTI_FTSR_FT0           EXTI_FTSR_FT0_Msk                              /*!< Falling trigger event configuration bit of line 0 */
2084 #define EXTI_FTSR_FT1_Pos       (1U)
2085 #define EXTI_FTSR_FT1_Msk       (0x1UL << EXTI_FTSR_FT1_Pos)                    /*!< 0x00000002 */
2086 #define EXTI_FTSR_FT1           EXTI_FTSR_FT1_Msk                              /*!< Falling trigger event configuration bit of line 1 */
2087 #define EXTI_FTSR_FT2_Pos       (2U)
2088 #define EXTI_FTSR_FT2_Msk       (0x1UL << EXTI_FTSR_FT2_Pos)                    /*!< 0x00000004 */
2089 #define EXTI_FTSR_FT2           EXTI_FTSR_FT2_Msk                              /*!< Falling trigger event configuration bit of line 2 */
2090 #define EXTI_FTSR_FT3_Pos       (3U)
2091 #define EXTI_FTSR_FT3_Msk       (0x1UL << EXTI_FTSR_FT3_Pos)                    /*!< 0x00000008 */
2092 #define EXTI_FTSR_FT3           EXTI_FTSR_FT3_Msk                              /*!< Falling trigger event configuration bit of line 3 */
2093 #define EXTI_FTSR_FT4_Pos       (4U)
2094 #define EXTI_FTSR_FT4_Msk       (0x1UL << EXTI_FTSR_FT4_Pos)                    /*!< 0x00000010 */
2095 #define EXTI_FTSR_FT4           EXTI_FTSR_FT4_Msk                              /*!< Falling trigger event configuration bit of line 4 */
2096 #define EXTI_FTSR_FT5_Pos       (5U)
2097 #define EXTI_FTSR_FT5_Msk       (0x1UL << EXTI_FTSR_FT5_Pos)                    /*!< 0x00000020 */
2098 #define EXTI_FTSR_FT5           EXTI_FTSR_FT5_Msk                              /*!< Falling trigger event configuration bit of line 5 */
2099 #define EXTI_FTSR_FT6_Pos       (6U)
2100 #define EXTI_FTSR_FT6_Msk       (0x1UL << EXTI_FTSR_FT6_Pos)                    /*!< 0x00000040 */
2101 #define EXTI_FTSR_FT6           EXTI_FTSR_FT6_Msk                              /*!< Falling trigger event configuration bit of line 6 */
2102 #define EXTI_FTSR_FT7_Pos       (7U)
2103 #define EXTI_FTSR_FT7_Msk       (0x1UL << EXTI_FTSR_FT7_Pos)                    /*!< 0x00000080 */
2104 #define EXTI_FTSR_FT7           EXTI_FTSR_FT7_Msk                              /*!< Falling trigger event configuration bit of line 7 */
2105 #define EXTI_FTSR_FT8_Pos       (8U)
2106 #define EXTI_FTSR_FT8_Msk       (0x1UL << EXTI_FTSR_FT8_Pos)                    /*!< 0x00000100 */
2107 #define EXTI_FTSR_FT8           EXTI_FTSR_FT8_Msk                              /*!< Falling trigger event configuration bit of line 8 */
2108 #define EXTI_FTSR_FT9_Pos       (9U)
2109 #define EXTI_FTSR_FT9_Msk       (0x1UL << EXTI_FTSR_FT9_Pos)                    /*!< 0x00000200 */
2110 #define EXTI_FTSR_FT9           EXTI_FTSR_FT9_Msk                              /*!< Falling trigger event configuration bit of line 9 */
2111 #define EXTI_FTSR_FT10_Pos      (10U)
2112 #define EXTI_FTSR_FT10_Msk      (0x1UL << EXTI_FTSR_FT10_Pos)                   /*!< 0x00000400 */
2113 #define EXTI_FTSR_FT10          EXTI_FTSR_FT10_Msk                             /*!< Falling trigger event configuration bit of line 10 */
2114 #define EXTI_FTSR_FT11_Pos      (11U)
2115 #define EXTI_FTSR_FT11_Msk      (0x1UL << EXTI_FTSR_FT11_Pos)                   /*!< 0x00000800 */
2116 #define EXTI_FTSR_FT11          EXTI_FTSR_FT11_Msk                             /*!< Falling trigger event configuration bit of line 11 */
2117 #define EXTI_FTSR_FT12_Pos      (12U)
2118 #define EXTI_FTSR_FT12_Msk      (0x1UL << EXTI_FTSR_FT12_Pos)                   /*!< 0x00001000 */
2119 #define EXTI_FTSR_FT12          EXTI_FTSR_FT12_Msk                             /*!< Falling trigger event configuration bit of line 12 */
2120 #define EXTI_FTSR_FT13_Pos      (13U)
2121 #define EXTI_FTSR_FT13_Msk      (0x1UL << EXTI_FTSR_FT13_Pos)                   /*!< 0x00002000 */
2122 #define EXTI_FTSR_FT13          EXTI_FTSR_FT13_Msk                             /*!< Falling trigger event configuration bit of line 13 */
2123 #define EXTI_FTSR_FT14_Pos      (14U)
2124 #define EXTI_FTSR_FT14_Msk      (0x1UL << EXTI_FTSR_FT14_Pos)                   /*!< 0x00004000 */
2125 #define EXTI_FTSR_FT14          EXTI_FTSR_FT14_Msk                             /*!< Falling trigger event configuration bit of line 14 */
2126 #define EXTI_FTSR_FT15_Pos      (15U)
2127 #define EXTI_FTSR_FT15_Msk      (0x1UL << EXTI_FTSR_FT15_Pos)                   /*!< 0x00008000 */
2128 #define EXTI_FTSR_FT15          EXTI_FTSR_FT15_Msk                             /*!< Falling trigger event configuration bit of line 15 */
2129 #define EXTI_FTSR_FT16_Pos      (16U)
2130 #define EXTI_FTSR_FT16_Msk      (0x1UL << EXTI_FTSR_FT16_Pos)                   /*!< 0x00010000 */
2131 #define EXTI_FTSR_FT16          EXTI_FTSR_FT16_Msk                             /*!< Falling trigger event configuration bit of line 16 */
2132 #define EXTI_FTSR_FT17_Pos      (17U)
2133 #define EXTI_FTSR_FT17_Msk      (0x1UL << EXTI_FTSR_FT17_Pos)                   /*!< 0x00020000 */
2134 #define EXTI_FTSR_FT17          EXTI_FTSR_FT17_Msk                             /*!< Falling trigger event configuration bit of line 17 */
2135 #define EXTI_FTSR_FT19_Pos      (19U)
2136 #define EXTI_FTSR_FT19_Msk      (0x1UL << EXTI_FTSR_FT19_Pos)                   /*!< 0x00080000 */
2137 #define EXTI_FTSR_FT19          EXTI_FTSR_FT19_Msk                             /*!< Falling trigger event configuration bit of line 19 */
2138 #define EXTI_FTSR_FT20_Pos      (20U)
2139 #define EXTI_FTSR_FT20_Msk      (0x1UL << EXTI_FTSR_FT20_Pos)                   /*!< 0x00100000 */
2140 #define EXTI_FTSR_FT20          EXTI_FTSR_FT20_Msk                             /*!< Falling trigger event configuration bit of line 20 */
2141 #define EXTI_FTSR_FT21_Pos      (21U)
2142 #define EXTI_FTSR_FT21_Msk      (0x1UL << EXTI_FTSR_FT21_Pos)                   /*!< 0x00200000 */
2143 #define EXTI_FTSR_FT21          EXTI_FTSR_FT21_Msk                             /*!< Falling trigger event configuration bit of line 21 */
2144 #define EXTI_FTSR_FT22_Pos      (22U)
2145 #define EXTI_FTSR_FT22_Msk      (0x1UL << EXTI_FTSR_FT22_Pos)                   /*!< 0x00400000 */
2146 #define EXTI_FTSR_FT22          EXTI_FTSR_FT22_Msk                             /*!< Falling trigger event configuration bit of line 22 */
2147 
2148 /* Legacy defines */
2149 #define EXTI_FTSR_TR0                       EXTI_FTSR_FT0
2150 #define EXTI_FTSR_TR1                       EXTI_FTSR_FT1
2151 #define EXTI_FTSR_TR2                       EXTI_FTSR_FT2
2152 #define EXTI_FTSR_TR3                       EXTI_FTSR_FT3
2153 #define EXTI_FTSR_TR4                       EXTI_FTSR_FT4
2154 #define EXTI_FTSR_TR5                       EXTI_FTSR_FT5
2155 #define EXTI_FTSR_TR6                       EXTI_FTSR_FT6
2156 #define EXTI_FTSR_TR7                       EXTI_FTSR_FT7
2157 #define EXTI_FTSR_TR8                       EXTI_FTSR_FT8
2158 #define EXTI_FTSR_TR9                       EXTI_FTSR_FT9
2159 #define EXTI_FTSR_TR10                      EXTI_FTSR_FT10
2160 #define EXTI_FTSR_TR11                      EXTI_FTSR_FT11
2161 #define EXTI_FTSR_TR12                      EXTI_FTSR_FT12
2162 #define EXTI_FTSR_TR13                      EXTI_FTSR_FT13
2163 #define EXTI_FTSR_TR14                      EXTI_FTSR_FT14
2164 #define EXTI_FTSR_TR15                      EXTI_FTSR_FT15
2165 #define EXTI_FTSR_TR16                      EXTI_FTSR_FT16
2166 #define EXTI_FTSR_TR17                      EXTI_FTSR_FT17
2167 #define EXTI_FTSR_TR19                      EXTI_FTSR_FT19
2168 #define EXTI_FTSR_TR20                      EXTI_FTSR_FT20
2169 #define EXTI_FTSR_TR21                      EXTI_FTSR_FT21
2170 #define EXTI_FTSR_TR22                      EXTI_FTSR_FT22
2171 
2172 /******************* Bit definition for EXTI_SWIER register *******************/
2173 #define EXTI_SWIER_SWI0_Pos     (0U)
2174 #define EXTI_SWIER_SWI0_Msk     (0x1UL << EXTI_SWIER_SWI0_Pos)                  /*!< 0x00000001 */
2175 #define EXTI_SWIER_SWI0         EXTI_SWIER_SWI0_Msk                            /*!< Software Interrupt on line 0  */
2176 #define EXTI_SWIER_SWI1_Pos     (1U)
2177 #define EXTI_SWIER_SWI1_Msk     (0x1UL << EXTI_SWIER_SWI1_Pos)                  /*!< 0x00000002 */
2178 #define EXTI_SWIER_SWI1         EXTI_SWIER_SWI1_Msk                            /*!< Software Interrupt on line 1  */
2179 #define EXTI_SWIER_SWI2_Pos     (2U)
2180 #define EXTI_SWIER_SWI2_Msk     (0x1UL << EXTI_SWIER_SWI2_Pos)                  /*!< 0x00000004 */
2181 #define EXTI_SWIER_SWI2         EXTI_SWIER_SWI2_Msk                            /*!< Software Interrupt on line 2  */
2182 #define EXTI_SWIER_SWI3_Pos     (3U)
2183 #define EXTI_SWIER_SWI3_Msk     (0x1UL << EXTI_SWIER_SWI3_Pos)                  /*!< 0x00000008 */
2184 #define EXTI_SWIER_SWI3         EXTI_SWIER_SWI3_Msk                            /*!< Software Interrupt on line 3  */
2185 #define EXTI_SWIER_SWI4_Pos     (4U)
2186 #define EXTI_SWIER_SWI4_Msk     (0x1UL << EXTI_SWIER_SWI4_Pos)                  /*!< 0x00000010 */
2187 #define EXTI_SWIER_SWI4         EXTI_SWIER_SWI4_Msk                            /*!< Software Interrupt on line 4  */
2188 #define EXTI_SWIER_SWI5_Pos     (5U)
2189 #define EXTI_SWIER_SWI5_Msk     (0x1UL << EXTI_SWIER_SWI5_Pos)                  /*!< 0x00000020 */
2190 #define EXTI_SWIER_SWI5         EXTI_SWIER_SWI5_Msk                            /*!< Software Interrupt on line 5  */
2191 #define EXTI_SWIER_SWI6_Pos     (6U)
2192 #define EXTI_SWIER_SWI6_Msk     (0x1UL << EXTI_SWIER_SWI6_Pos)                  /*!< 0x00000040 */
2193 #define EXTI_SWIER_SWI6         EXTI_SWIER_SWI6_Msk                            /*!< Software Interrupt on line 6  */
2194 #define EXTI_SWIER_SWI7_Pos     (7U)
2195 #define EXTI_SWIER_SWI7_Msk     (0x1UL << EXTI_SWIER_SWI7_Pos)                  /*!< 0x00000080 */
2196 #define EXTI_SWIER_SWI7         EXTI_SWIER_SWI7_Msk                            /*!< Software Interrupt on line 7  */
2197 #define EXTI_SWIER_SWI8_Pos     (8U)
2198 #define EXTI_SWIER_SWI8_Msk     (0x1UL << EXTI_SWIER_SWI8_Pos)                  /*!< 0x00000100 */
2199 #define EXTI_SWIER_SWI8         EXTI_SWIER_SWI8_Msk                            /*!< Software Interrupt on line 8  */
2200 #define EXTI_SWIER_SWI9_Pos     (9U)
2201 #define EXTI_SWIER_SWI9_Msk     (0x1UL << EXTI_SWIER_SWI9_Pos)                  /*!< 0x00000200 */
2202 #define EXTI_SWIER_SWI9         EXTI_SWIER_SWI9_Msk                            /*!< Software Interrupt on line 9  */
2203 #define EXTI_SWIER_SWI10_Pos    (10U)
2204 #define EXTI_SWIER_SWI10_Msk    (0x1UL << EXTI_SWIER_SWI10_Pos)                 /*!< 0x00000400 */
2205 #define EXTI_SWIER_SWI10        EXTI_SWIER_SWI10_Msk                           /*!< Software Interrupt on line 10 */
2206 #define EXTI_SWIER_SWI11_Pos    (11U)
2207 #define EXTI_SWIER_SWI11_Msk    (0x1UL << EXTI_SWIER_SWI11_Pos)                 /*!< 0x00000800 */
2208 #define EXTI_SWIER_SWI11        EXTI_SWIER_SWI11_Msk                           /*!< Software Interrupt on line 11 */
2209 #define EXTI_SWIER_SWI12_Pos    (12U)
2210 #define EXTI_SWIER_SWI12_Msk    (0x1UL << EXTI_SWIER_SWI12_Pos)                 /*!< 0x00001000 */
2211 #define EXTI_SWIER_SWI12        EXTI_SWIER_SWI12_Msk                           /*!< Software Interrupt on line 12 */
2212 #define EXTI_SWIER_SWI13_Pos    (13U)
2213 #define EXTI_SWIER_SWI13_Msk    (0x1UL << EXTI_SWIER_SWI13_Pos)                 /*!< 0x00002000 */
2214 #define EXTI_SWIER_SWI13        EXTI_SWIER_SWI13_Msk                           /*!< Software Interrupt on line 13 */
2215 #define EXTI_SWIER_SWI14_Pos    (14U)
2216 #define EXTI_SWIER_SWI14_Msk    (0x1UL << EXTI_SWIER_SWI14_Pos)                 /*!< 0x00004000 */
2217 #define EXTI_SWIER_SWI14        EXTI_SWIER_SWI14_Msk                           /*!< Software Interrupt on line 14 */
2218 #define EXTI_SWIER_SWI15_Pos    (15U)
2219 #define EXTI_SWIER_SWI15_Msk    (0x1UL << EXTI_SWIER_SWI15_Pos)                 /*!< 0x00008000 */
2220 #define EXTI_SWIER_SWI15        EXTI_SWIER_SWI15_Msk                           /*!< Software Interrupt on line 15 */
2221 #define EXTI_SWIER_SWI16_Pos    (16U)
2222 #define EXTI_SWIER_SWI16_Msk    (0x1UL << EXTI_SWIER_SWI16_Pos)                 /*!< 0x00010000 */
2223 #define EXTI_SWIER_SWI16        EXTI_SWIER_SWI16_Msk                           /*!< Software Interrupt on line 16 */
2224 #define EXTI_SWIER_SWI17_Pos    (17U)
2225 #define EXTI_SWIER_SWI17_Msk    (0x1UL << EXTI_SWIER_SWI17_Pos)                 /*!< 0x00020000 */
2226 #define EXTI_SWIER_SWI17        EXTI_SWIER_SWI17_Msk                           /*!< Software Interrupt on line 17 */
2227 #define EXTI_SWIER_SWI19_Pos    (19U)
2228 #define EXTI_SWIER_SWI19_Msk    (0x1UL << EXTI_SWIER_SWI19_Pos)                 /*!< 0x00080000 */
2229 #define EXTI_SWIER_SWI19        EXTI_SWIER_SWI19_Msk                           /*!< Software Interrupt on line 19 */
2230 #define EXTI_SWIER_SWI20_Pos    (20U)
2231 #define EXTI_SWIER_SWI20_Msk    (0x1UL << EXTI_SWIER_SWI20_Pos)                 /*!< 0x00100000 */
2232 #define EXTI_SWIER_SWI20        EXTI_SWIER_SWI20_Msk                           /*!< Software Interrupt on line 20 */
2233 #define EXTI_SWIER_SWI21_Pos    (21U)
2234 #define EXTI_SWIER_SWI21_Msk    (0x1UL << EXTI_SWIER_SWI21_Pos)                 /*!< 0x00200000 */
2235 #define EXTI_SWIER_SWI21        EXTI_SWIER_SWI21_Msk                           /*!< Software Interrupt on line 21 */
2236 #define EXTI_SWIER_SWI22_Pos    (22U)
2237 #define EXTI_SWIER_SWI22_Msk    (0x1UL << EXTI_SWIER_SWI22_Pos)                 /*!< 0x00400000 */
2238 #define EXTI_SWIER_SWI22        EXTI_SWIER_SWI22_Msk                           /*!< Software Interrupt on line 22 */
2239 
2240 /* Legacy defines */
2241 #define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWI0
2242 #define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWI1
2243 #define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWI2
2244 #define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWI3
2245 #define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWI4
2246 #define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWI5
2247 #define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWI6
2248 #define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWI7
2249 #define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWI8
2250 #define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWI9
2251 #define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWI10
2252 #define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWI11
2253 #define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWI12
2254 #define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWI13
2255 #define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWI14
2256 #define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWI15
2257 #define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWI16
2258 #define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWI17
2259 #define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWI19
2260 #define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWI20
2261 #define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWI21
2262 #define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWI22
2263 
2264 /******************  Bit definition for EXTI_PR register  *********************/
2265 #define EXTI_PR_PIF0_Pos        (0U)
2266 #define EXTI_PR_PIF0_Msk        (0x1UL << EXTI_PR_PIF0_Pos)                     /*!< 0x00000001 */
2267 #define EXTI_PR_PIF0            EXTI_PR_PIF0_Msk                               /*!< Pending bit 0  */
2268 #define EXTI_PR_PIF1_Pos        (1U)
2269 #define EXTI_PR_PIF1_Msk        (0x1UL << EXTI_PR_PIF1_Pos)                     /*!< 0x00000002 */
2270 #define EXTI_PR_PIF1            EXTI_PR_PIF1_Msk                               /*!< Pending bit 1  */
2271 #define EXTI_PR_PIF2_Pos        (2U)
2272 #define EXTI_PR_PIF2_Msk        (0x1UL << EXTI_PR_PIF2_Pos)                     /*!< 0x00000004 */
2273 #define EXTI_PR_PIF2            EXTI_PR_PIF2_Msk                               /*!< Pending bit 2  */
2274 #define EXTI_PR_PIF3_Pos        (3U)
2275 #define EXTI_PR_PIF3_Msk        (0x1UL << EXTI_PR_PIF3_Pos)                     /*!< 0x00000008 */
2276 #define EXTI_PR_PIF3            EXTI_PR_PIF3_Msk                               /*!< Pending bit 3  */
2277 #define EXTI_PR_PIF4_Pos        (4U)
2278 #define EXTI_PR_PIF4_Msk        (0x1UL << EXTI_PR_PIF4_Pos)                     /*!< 0x00000010 */
2279 #define EXTI_PR_PIF4            EXTI_PR_PIF4_Msk                               /*!< Pending bit 4  */
2280 #define EXTI_PR_PIF5_Pos        (5U)
2281 #define EXTI_PR_PIF5_Msk        (0x1UL << EXTI_PR_PIF5_Pos)                     /*!< 0x00000020 */
2282 #define EXTI_PR_PIF5            EXTI_PR_PIF5_Msk                               /*!< Pending bit 5  */
2283 #define EXTI_PR_PIF6_Pos        (6U)
2284 #define EXTI_PR_PIF6_Msk        (0x1UL << EXTI_PR_PIF6_Pos)                     /*!< 0x00000040 */
2285 #define EXTI_PR_PIF6            EXTI_PR_PIF6_Msk                               /*!< Pending bit 6  */
2286 #define EXTI_PR_PIF7_Pos        (7U)
2287 #define EXTI_PR_PIF7_Msk        (0x1UL << EXTI_PR_PIF7_Pos)                     /*!< 0x00000080 */
2288 #define EXTI_PR_PIF7            EXTI_PR_PIF7_Msk                               /*!< Pending bit 7  */
2289 #define EXTI_PR_PIF8_Pos        (8U)
2290 #define EXTI_PR_PIF8_Msk        (0x1UL << EXTI_PR_PIF8_Pos)                     /*!< 0x00000100 */
2291 #define EXTI_PR_PIF8            EXTI_PR_PIF8_Msk                               /*!< Pending bit 8  */
2292 #define EXTI_PR_PIF9_Pos        (9U)
2293 #define EXTI_PR_PIF9_Msk        (0x1UL << EXTI_PR_PIF9_Pos)                     /*!< 0x00000200 */
2294 #define EXTI_PR_PIF9            EXTI_PR_PIF9_Msk                               /*!< Pending bit 9  */
2295 #define EXTI_PR_PIF10_Pos       (10U)
2296 #define EXTI_PR_PIF10_Msk       (0x1UL << EXTI_PR_PIF10_Pos)                    /*!< 0x00000400 */
2297 #define EXTI_PR_PIF10           EXTI_PR_PIF10_Msk                              /*!< Pending bit 10 */
2298 #define EXTI_PR_PIF11_Pos       (11U)
2299 #define EXTI_PR_PIF11_Msk       (0x1UL << EXTI_PR_PIF11_Pos)                    /*!< 0x00000800 */
2300 #define EXTI_PR_PIF11           EXTI_PR_PIF11_Msk                              /*!< Pending bit 11 */
2301 #define EXTI_PR_PIF12_Pos       (12U)
2302 #define EXTI_PR_PIF12_Msk       (0x1UL << EXTI_PR_PIF12_Pos)                    /*!< 0x00001000 */
2303 #define EXTI_PR_PIF12           EXTI_PR_PIF12_Msk                              /*!< Pending bit 12 */
2304 #define EXTI_PR_PIF13_Pos       (13U)
2305 #define EXTI_PR_PIF13_Msk       (0x1UL << EXTI_PR_PIF13_Pos)                    /*!< 0x00002000 */
2306 #define EXTI_PR_PIF13           EXTI_PR_PIF13_Msk                              /*!< Pending bit 13 */
2307 #define EXTI_PR_PIF14_Pos       (14U)
2308 #define EXTI_PR_PIF14_Msk       (0x1UL << EXTI_PR_PIF14_Pos)                    /*!< 0x00004000 */
2309 #define EXTI_PR_PIF14           EXTI_PR_PIF14_Msk                              /*!< Pending bit 14 */
2310 #define EXTI_PR_PIF15_Pos       (15U)
2311 #define EXTI_PR_PIF15_Msk       (0x1UL << EXTI_PR_PIF15_Pos)                    /*!< 0x00008000 */
2312 #define EXTI_PR_PIF15           EXTI_PR_PIF15_Msk                              /*!< Pending bit 15 */
2313 #define EXTI_PR_PIF16_Pos       (16U)
2314 #define EXTI_PR_PIF16_Msk       (0x1UL << EXTI_PR_PIF16_Pos)                    /*!< 0x00010000 */
2315 #define EXTI_PR_PIF16           EXTI_PR_PIF16_Msk                              /*!< Pending bit 16 */
2316 #define EXTI_PR_PIF17_Pos       (17U)
2317 #define EXTI_PR_PIF17_Msk       (0x1UL << EXTI_PR_PIF17_Pos)                    /*!< 0x00020000 */
2318 #define EXTI_PR_PIF17           EXTI_PR_PIF17_Msk                              /*!< Pending bit 17 */
2319 #define EXTI_PR_PIF19_Pos       (19U)
2320 #define EXTI_PR_PIF19_Msk       (0x1UL << EXTI_PR_PIF19_Pos)                    /*!< 0x00080000 */
2321 #define EXTI_PR_PIF19           EXTI_PR_PIF19_Msk                              /*!< Pending bit 19 */
2322 #define EXTI_PR_PIF20_Pos       (20U)
2323 #define EXTI_PR_PIF20_Msk       (0x1UL << EXTI_PR_PIF20_Pos)                    /*!< 0x00100000 */
2324 #define EXTI_PR_PIF20           EXTI_PR_PIF20_Msk                              /*!< Pending bit 20 */
2325 #define EXTI_PR_PIF21_Pos       (21U)
2326 #define EXTI_PR_PIF21_Msk       (0x1UL << EXTI_PR_PIF21_Pos)                    /*!< 0x00200000 */
2327 #define EXTI_PR_PIF21           EXTI_PR_PIF21_Msk                              /*!< Pending bit 21 */
2328 #define EXTI_PR_PIF22_Pos       (22U)
2329 #define EXTI_PR_PIF22_Msk       (0x1UL << EXTI_PR_PIF22_Pos)                    /*!< 0x00400000 */
2330 #define EXTI_PR_PIF22           EXTI_PR_PIF22_Msk                              /*!< Pending bit 22 */
2331 
2332 /* Legacy defines */
2333 #define EXTI_PR_PR0                         EXTI_PR_PIF0
2334 #define EXTI_PR_PR1                         EXTI_PR_PIF1
2335 #define EXTI_PR_PR2                         EXTI_PR_PIF2
2336 #define EXTI_PR_PR3                         EXTI_PR_PIF3
2337 #define EXTI_PR_PR4                         EXTI_PR_PIF4
2338 #define EXTI_PR_PR5                         EXTI_PR_PIF5
2339 #define EXTI_PR_PR6                         EXTI_PR_PIF6
2340 #define EXTI_PR_PR7                         EXTI_PR_PIF7
2341 #define EXTI_PR_PR8                         EXTI_PR_PIF8
2342 #define EXTI_PR_PR9                         EXTI_PR_PIF9
2343 #define EXTI_PR_PR10                        EXTI_PR_PIF10
2344 #define EXTI_PR_PR11                        EXTI_PR_PIF11
2345 #define EXTI_PR_PR12                        EXTI_PR_PIF12
2346 #define EXTI_PR_PR13                        EXTI_PR_PIF13
2347 #define EXTI_PR_PR14                        EXTI_PR_PIF14
2348 #define EXTI_PR_PR15                        EXTI_PR_PIF15
2349 #define EXTI_PR_PR16                        EXTI_PR_PIF16
2350 #define EXTI_PR_PR17                        EXTI_PR_PIF17
2351 #define EXTI_PR_PR19                        EXTI_PR_PIF19
2352 #define EXTI_PR_PR20                        EXTI_PR_PIF20
2353 #define EXTI_PR_PR21                        EXTI_PR_PIF21
2354 #define EXTI_PR_PR22                        EXTI_PR_PIF22
2355 
2356 /******************************************************************************/
2357 /*                                                                            */
2358 /*                      FLASH and Option Bytes Registers                      */
2359 /*                                                                            */
2360 /******************************************************************************/
2361 
2362 /*******************  Bit definition for FLASH_ACR register  ******************/
2363 #define FLASH_ACR_LATENCY_Pos        (0U)
2364 #define FLASH_ACR_LATENCY_Msk        (0x1UL << FLASH_ACR_LATENCY_Pos)           /*!< 0x00000001 */
2365 #define FLASH_ACR_LATENCY            FLASH_ACR_LATENCY_Msk                     /*!< LATENCY bit (Latency) */
2366 #define FLASH_ACR_PRFTEN_Pos         (1U)
2367 #define FLASH_ACR_PRFTEN_Msk         (0x1UL << FLASH_ACR_PRFTEN_Pos)            /*!< 0x00000002 */
2368 #define FLASH_ACR_PRFTEN             FLASH_ACR_PRFTEN_Msk                      /*!< Prefetch Buffer Enable */
2369 #define FLASH_ACR_SLEEP_PD_Pos       (3U)
2370 #define FLASH_ACR_SLEEP_PD_Msk       (0x1UL << FLASH_ACR_SLEEP_PD_Pos)          /*!< 0x00000008 */
2371 #define FLASH_ACR_SLEEP_PD           FLASH_ACR_SLEEP_PD_Msk                    /*!< Flash mode during sleep mode */
2372 #define FLASH_ACR_RUN_PD_Pos         (4U)
2373 #define FLASH_ACR_RUN_PD_Msk         (0x1UL << FLASH_ACR_RUN_PD_Pos)            /*!< 0x00000010 */
2374 #define FLASH_ACR_RUN_PD             FLASH_ACR_RUN_PD_Msk                      /*!< Flash mode during RUN mode */
2375 #define FLASH_ACR_DISAB_BUF_Pos      (5U)
2376 #define FLASH_ACR_DISAB_BUF_Msk      (0x1UL << FLASH_ACR_DISAB_BUF_Pos)         /*!< 0x00000020 */
2377 #define FLASH_ACR_DISAB_BUF          FLASH_ACR_DISAB_BUF_Msk                   /*!< Disable Buffer */
2378 #define FLASH_ACR_PRE_READ_Pos       (6U)
2379 #define FLASH_ACR_PRE_READ_Msk       (0x1UL << FLASH_ACR_PRE_READ_Pos)          /*!< 0x00000040 */
2380 #define FLASH_ACR_PRE_READ           FLASH_ACR_PRE_READ_Msk                    /*!< Pre-read data address */
2381 
2382 /*******************  Bit definition for FLASH_PECR register  ******************/
2383 #define FLASH_PECR_PELOCK_Pos        (0U)
2384 #define FLASH_PECR_PELOCK_Msk        (0x1UL << FLASH_PECR_PELOCK_Pos)           /*!< 0x00000001 */
2385 #define FLASH_PECR_PELOCK            FLASH_PECR_PELOCK_Msk                     /*!< FLASH_PECR and Flash data Lock */
2386 #define FLASH_PECR_PRGLOCK_Pos       (1U)
2387 #define FLASH_PECR_PRGLOCK_Msk       (0x1UL << FLASH_PECR_PRGLOCK_Pos)          /*!< 0x00000002 */
2388 #define FLASH_PECR_PRGLOCK           FLASH_PECR_PRGLOCK_Msk                    /*!< Program matrix Lock */
2389 #define FLASH_PECR_OPTLOCK_Pos       (2U)
2390 #define FLASH_PECR_OPTLOCK_Msk       (0x1UL << FLASH_PECR_OPTLOCK_Pos)          /*!< 0x00000004 */
2391 #define FLASH_PECR_OPTLOCK           FLASH_PECR_OPTLOCK_Msk                    /*!< Option byte matrix Lock */
2392 #define FLASH_PECR_PROG_Pos          (3U)
2393 #define FLASH_PECR_PROG_Msk          (0x1UL << FLASH_PECR_PROG_Pos)             /*!< 0x00000008 */
2394 #define FLASH_PECR_PROG              FLASH_PECR_PROG_Msk                       /*!< Program matrix selection */
2395 #define FLASH_PECR_DATA_Pos          (4U)
2396 #define FLASH_PECR_DATA_Msk          (0x1UL << FLASH_PECR_DATA_Pos)             /*!< 0x00000010 */
2397 #define FLASH_PECR_DATA              FLASH_PECR_DATA_Msk                       /*!< Data matrix selection */
2398 #define FLASH_PECR_FIX_Pos           (8U)
2399 #define FLASH_PECR_FIX_Msk           (0x1UL << FLASH_PECR_FIX_Pos)              /*!< 0x00000100 */
2400 #define FLASH_PECR_FIX               FLASH_PECR_FIX_Msk                        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
2401 #define FLASH_PECR_ERASE_Pos         (9U)
2402 #define FLASH_PECR_ERASE_Msk         (0x1UL << FLASH_PECR_ERASE_Pos)            /*!< 0x00000200 */
2403 #define FLASH_PECR_ERASE             FLASH_PECR_ERASE_Msk                      /*!< Page erasing mode */
2404 #define FLASH_PECR_FPRG_Pos          (10U)
2405 #define FLASH_PECR_FPRG_Msk          (0x1UL << FLASH_PECR_FPRG_Pos)             /*!< 0x00000400 */
2406 #define FLASH_PECR_FPRG              FLASH_PECR_FPRG_Msk                       /*!< Fast Page/Half Page programming mode */
2407 #define FLASH_PECR_EOPIE_Pos         (16U)
2408 #define FLASH_PECR_EOPIE_Msk         (0x1UL << FLASH_PECR_EOPIE_Pos)            /*!< 0x00010000 */
2409 #define FLASH_PECR_EOPIE             FLASH_PECR_EOPIE_Msk                      /*!< End of programming interrupt */
2410 #define FLASH_PECR_ERRIE_Pos         (17U)
2411 #define FLASH_PECR_ERRIE_Msk         (0x1UL << FLASH_PECR_ERRIE_Pos)            /*!< 0x00020000 */
2412 #define FLASH_PECR_ERRIE             FLASH_PECR_ERRIE_Msk                      /*!< Error interrupt */
2413 #define FLASH_PECR_OBL_LAUNCH_Pos    (18U)
2414 #define FLASH_PECR_OBL_LAUNCH_Msk    (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos)       /*!< 0x00040000 */
2415 #define FLASH_PECR_OBL_LAUNCH        FLASH_PECR_OBL_LAUNCH_Msk                 /*!< Launch the option byte loading */
2416 #define FLASH_PECR_HALF_ARRAY_Pos    (19U)
2417 #define FLASH_PECR_HALF_ARRAY_Msk    (0x1UL << FLASH_PECR_HALF_ARRAY_Pos)       /*!< 0x00080000 */
2418 #define FLASH_PECR_HALF_ARRAY        FLASH_PECR_HALF_ARRAY_Msk                 /*!< Half array mode */
2419 
2420 /******************  Bit definition for FLASH_PDKEYR register  ******************/
2421 #define FLASH_PDKEYR_PDKEYR_Pos      (0U)
2422 #define FLASH_PDKEYR_PDKEYR_Msk      (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos)  /*!< 0xFFFFFFFF */
2423 #define FLASH_PDKEYR_PDKEYR          FLASH_PDKEYR_PDKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
2424 
2425 /******************  Bit definition for FLASH_PEKEYR register  ******************/
2426 #define FLASH_PEKEYR_PEKEYR_Pos      (0U)
2427 #define FLASH_PEKEYR_PEKEYR_Msk      (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos)  /*!< 0xFFFFFFFF */
2428 #define FLASH_PEKEYR_PEKEYR          FLASH_PEKEYR_PEKEYR_Msk                   /*!< FLASH_PEC and data matrix Key */
2429 
2430 /******************  Bit definition for FLASH_PRGKEYR register  ******************/
2431 #define FLASH_PRGKEYR_PRGKEYR_Pos    (0U)
2432 #define FLASH_PRGKEYR_PRGKEYR_Msk    (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
2433 #define FLASH_PRGKEYR_PRGKEYR        FLASH_PRGKEYR_PRGKEYR_Msk                 /*!< Program matrix Key */
2434 
2435 /******************  Bit definition for FLASH_OPTKEYR register  ******************/
2436 #define FLASH_OPTKEYR_OPTKEYR_Pos    (0U)
2437 #define FLASH_OPTKEYR_OPTKEYR_Msk    (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
2438 #define FLASH_OPTKEYR_OPTKEYR        FLASH_OPTKEYR_OPTKEYR_Msk                 /*!< Option bytes matrix Key */
2439 
2440 /******************  Bit definition for FLASH_SR register  *******************/
2441 #define FLASH_SR_BSY_Pos             (0U)
2442 #define FLASH_SR_BSY_Msk             (0x1UL << FLASH_SR_BSY_Pos)                /*!< 0x00000001 */
2443 #define FLASH_SR_BSY                 FLASH_SR_BSY_Msk                          /*!< Busy */
2444 #define FLASH_SR_EOP_Pos             (1U)
2445 #define FLASH_SR_EOP_Msk             (0x1UL << FLASH_SR_EOP_Pos)                /*!< 0x00000002 */
2446 #define FLASH_SR_EOP                 FLASH_SR_EOP_Msk                          /*!< End Of Programming*/
2447 #define FLASH_SR_HVOFF_Pos           (2U)
2448 #define FLASH_SR_HVOFF_Msk           (0x1UL << FLASH_SR_HVOFF_Pos)              /*!< 0x00000004 */
2449 #define FLASH_SR_HVOFF               FLASH_SR_HVOFF_Msk                        /*!< End of high voltage */
2450 #define FLASH_SR_READY_Pos           (3U)
2451 #define FLASH_SR_READY_Msk           (0x1UL << FLASH_SR_READY_Pos)              /*!< 0x00000008 */
2452 #define FLASH_SR_READY               FLASH_SR_READY_Msk                        /*!< Flash ready after low power mode */
2453 
2454 #define FLASH_SR_WRPERR_Pos          (8U)
2455 #define FLASH_SR_WRPERR_Msk          (0x1UL << FLASH_SR_WRPERR_Pos)             /*!< 0x00000100 */
2456 #define FLASH_SR_WRPERR              FLASH_SR_WRPERR_Msk                       /*!< Write protection error */
2457 #define FLASH_SR_PGAERR_Pos          (9U)
2458 #define FLASH_SR_PGAERR_Msk          (0x1UL << FLASH_SR_PGAERR_Pos)             /*!< 0x00000200 */
2459 #define FLASH_SR_PGAERR              FLASH_SR_PGAERR_Msk                       /*!< Programming Alignment Error */
2460 #define FLASH_SR_SIZERR_Pos          (10U)
2461 #define FLASH_SR_SIZERR_Msk          (0x1UL << FLASH_SR_SIZERR_Pos)             /*!< 0x00000400 */
2462 #define FLASH_SR_SIZERR              FLASH_SR_SIZERR_Msk                       /*!< Size error */
2463 #define FLASH_SR_OPTVERR_Pos         (11U)
2464 #define FLASH_SR_OPTVERR_Msk         (0x1UL << FLASH_SR_OPTVERR_Pos)            /*!< 0x00000800 */
2465 #define FLASH_SR_OPTVERR             FLASH_SR_OPTVERR_Msk                      /*!< Option Valid error */
2466 #define FLASH_SR_RDERR_Pos           (13U)
2467 #define FLASH_SR_RDERR_Msk           (0x1UL << FLASH_SR_RDERR_Pos)              /*!< 0x00002000 */
2468 #define FLASH_SR_RDERR               FLASH_SR_RDERR_Msk                        /*!< Read protected error */
2469 #define FLASH_SR_NOTZEROERR_Pos      (16U)
2470 #define FLASH_SR_NOTZEROERR_Msk      (0x1UL << FLASH_SR_NOTZEROERR_Pos)         /*!< 0x00010000 */
2471 #define FLASH_SR_NOTZEROERR          FLASH_SR_NOTZEROERR_Msk                   /*!< Not Zero error */
2472 #define FLASH_SR_FWWERR_Pos          (17U)
2473 #define FLASH_SR_FWWERR_Msk          (0x1UL << FLASH_SR_FWWERR_Pos)             /*!< 0x00020000 */
2474 #define FLASH_SR_FWWERR              FLASH_SR_FWWERR_Msk                       /*!< Write/Errase operation aborted */
2475 
2476 /* Legacy defines */
2477 #define FLASH_SR_FWWER                      FLASH_SR_FWWERR
2478 #define FLASH_SR_ENHV                       FLASH_SR_HVOFF
2479 #define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
2480 
2481 /******************  Bit definition for FLASH_OPTR register  *******************/
2482 #define FLASH_OPTR_RDPROT_Pos        (0U)
2483 #define FLASH_OPTR_RDPROT_Msk        (0xFFUL << FLASH_OPTR_RDPROT_Pos)          /*!< 0x000000FF */
2484 #define FLASH_OPTR_RDPROT            FLASH_OPTR_RDPROT_Msk                     /*!< Read Protection */
2485 #define FLASH_OPTR_WPRMOD_Pos        (8U)
2486 #define FLASH_OPTR_WPRMOD_Msk        (0x1UL << FLASH_OPTR_WPRMOD_Pos)           /*!< 0x00000100 */
2487 #define FLASH_OPTR_WPRMOD            FLASH_OPTR_WPRMOD_Msk                     /*!< Selection of protection mode of WPR bits */
2488 #define FLASH_OPTR_BOR_LEV_Pos       (16U)
2489 #define FLASH_OPTR_BOR_LEV_Msk       (0xFUL << FLASH_OPTR_BOR_LEV_Pos)          /*!< 0x000F0000 */
2490 #define FLASH_OPTR_BOR_LEV           FLASH_OPTR_BOR_LEV_Msk                    /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
2491 #define FLASH_OPTR_IWDG_SW_Pos       (20U)
2492 #define FLASH_OPTR_IWDG_SW_Msk       (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00100000 */
2493 #define FLASH_OPTR_IWDG_SW           FLASH_OPTR_IWDG_SW_Msk                    /*!< IWDG_SW */
2494 #define FLASH_OPTR_nRST_STOP_Pos     (21U)
2495 #define FLASH_OPTR_nRST_STOP_Msk     (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00200000 */
2496 #define FLASH_OPTR_nRST_STOP         FLASH_OPTR_nRST_STOP_Msk                  /*!< nRST_STOP */
2497 #define FLASH_OPTR_nRST_STDBY_Pos    (22U)
2498 #define FLASH_OPTR_nRST_STDBY_Msk    (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00400000 */
2499 #define FLASH_OPTR_nRST_STDBY        FLASH_OPTR_nRST_STDBY_Msk                 /*!< nRST_STDBY */
2500 #define FLASH_OPTR_USER_Pos          (20U)
2501 #define FLASH_OPTR_USER_Msk          (0x7UL << FLASH_OPTR_USER_Pos)             /*!< 0x00700000 */
2502 #define FLASH_OPTR_USER              FLASH_OPTR_USER_Msk                       /*!< User Option Bytes */
2503 #define FLASH_OPTR_BOOT1_Pos         (31U)
2504 #define FLASH_OPTR_BOOT1_Msk         (0x1UL << FLASH_OPTR_BOOT1_Pos)            /*!< 0x80000000 */
2505 #define FLASH_OPTR_BOOT1             FLASH_OPTR_BOOT1_Msk                      /*!< BOOT1 */
2506 
2507 /******************  Bit definition for FLASH_WRPR register  ******************/
2508 #define FLASH_WRPR_WRP_Pos           (0U)
2509 #define FLASH_WRPR_WRP_Msk           (0xFFFFUL << FLASH_WRPR_WRP_Pos)           /*!< 0x0000FFFF */
2510 #define FLASH_WRPR_WRP               FLASH_WRPR_WRP_Msk                        /*!< Write Protection bits */
2511 
2512 /******************************************************************************/
2513 /*                                                                            */
2514 /*                       General Purpose IOs (GPIO)                           */
2515 /*                                                                            */
2516 /******************************************************************************/
2517 /*******************  Bit definition for GPIO_MODER register  *****************/
2518 #define GPIO_MODER_MODE0_Pos            (0U)
2519 #define GPIO_MODER_MODE0_Msk            (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
2520 #define GPIO_MODER_MODE0                GPIO_MODER_MODE0_Msk
2521 #define GPIO_MODER_MODE0_0              (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
2522 #define GPIO_MODER_MODE0_1              (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
2523 #define GPIO_MODER_MODE1_Pos            (2U)
2524 #define GPIO_MODER_MODE1_Msk            (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
2525 #define GPIO_MODER_MODE1                GPIO_MODER_MODE1_Msk
2526 #define GPIO_MODER_MODE1_0              (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
2527 #define GPIO_MODER_MODE1_1              (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
2528 #define GPIO_MODER_MODE2_Pos            (4U)
2529 #define GPIO_MODER_MODE2_Msk            (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
2530 #define GPIO_MODER_MODE2                GPIO_MODER_MODE2_Msk
2531 #define GPIO_MODER_MODE2_0              (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
2532 #define GPIO_MODER_MODE2_1              (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
2533 #define GPIO_MODER_MODE3_Pos            (6U)
2534 #define GPIO_MODER_MODE3_Msk            (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
2535 #define GPIO_MODER_MODE3                GPIO_MODER_MODE3_Msk
2536 #define GPIO_MODER_MODE3_0              (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
2537 #define GPIO_MODER_MODE3_1              (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
2538 #define GPIO_MODER_MODE4_Pos            (8U)
2539 #define GPIO_MODER_MODE4_Msk            (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
2540 #define GPIO_MODER_MODE4                GPIO_MODER_MODE4_Msk
2541 #define GPIO_MODER_MODE4_0              (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
2542 #define GPIO_MODER_MODE4_1              (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
2543 #define GPIO_MODER_MODE5_Pos            (10U)
2544 #define GPIO_MODER_MODE5_Msk            (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
2545 #define GPIO_MODER_MODE5                GPIO_MODER_MODE5_Msk
2546 #define GPIO_MODER_MODE5_0              (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
2547 #define GPIO_MODER_MODE5_1              (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
2548 #define GPIO_MODER_MODE6_Pos            (12U)
2549 #define GPIO_MODER_MODE6_Msk            (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
2550 #define GPIO_MODER_MODE6                GPIO_MODER_MODE6_Msk
2551 #define GPIO_MODER_MODE6_0              (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
2552 #define GPIO_MODER_MODE6_1              (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
2553 #define GPIO_MODER_MODE7_Pos            (14U)
2554 #define GPIO_MODER_MODE7_Msk            (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
2555 #define GPIO_MODER_MODE7                GPIO_MODER_MODE7_Msk
2556 #define GPIO_MODER_MODE7_0              (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
2557 #define GPIO_MODER_MODE7_1              (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
2558 #define GPIO_MODER_MODE8_Pos            (16U)
2559 #define GPIO_MODER_MODE8_Msk            (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
2560 #define GPIO_MODER_MODE8                GPIO_MODER_MODE8_Msk
2561 #define GPIO_MODER_MODE8_0              (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
2562 #define GPIO_MODER_MODE8_1              (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
2563 #define GPIO_MODER_MODE9_Pos            (18U)
2564 #define GPIO_MODER_MODE9_Msk            (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
2565 #define GPIO_MODER_MODE9                GPIO_MODER_MODE9_Msk
2566 #define GPIO_MODER_MODE9_0              (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
2567 #define GPIO_MODER_MODE9_1              (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
2568 #define GPIO_MODER_MODE10_Pos           (20U)
2569 #define GPIO_MODER_MODE10_Msk           (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
2570 #define GPIO_MODER_MODE10               GPIO_MODER_MODE10_Msk
2571 #define GPIO_MODER_MODE10_0             (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
2572 #define GPIO_MODER_MODE10_1             (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
2573 #define GPIO_MODER_MODE11_Pos           (22U)
2574 #define GPIO_MODER_MODE11_Msk           (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
2575 #define GPIO_MODER_MODE11               GPIO_MODER_MODE11_Msk
2576 #define GPIO_MODER_MODE11_0             (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
2577 #define GPIO_MODER_MODE11_1             (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
2578 #define GPIO_MODER_MODE12_Pos           (24U)
2579 #define GPIO_MODER_MODE12_Msk           (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
2580 #define GPIO_MODER_MODE12               GPIO_MODER_MODE12_Msk
2581 #define GPIO_MODER_MODE12_0             (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
2582 #define GPIO_MODER_MODE12_1             (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
2583 #define GPIO_MODER_MODE13_Pos           (26U)
2584 #define GPIO_MODER_MODE13_Msk           (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
2585 #define GPIO_MODER_MODE13               GPIO_MODER_MODE13_Msk
2586 #define GPIO_MODER_MODE13_0             (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
2587 #define GPIO_MODER_MODE13_1             (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
2588 #define GPIO_MODER_MODE14_Pos           (28U)
2589 #define GPIO_MODER_MODE14_Msk           (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
2590 #define GPIO_MODER_MODE14               GPIO_MODER_MODE14_Msk
2591 #define GPIO_MODER_MODE14_0             (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
2592 #define GPIO_MODER_MODE14_1             (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
2593 #define GPIO_MODER_MODE15_Pos           (30U)
2594 #define GPIO_MODER_MODE15_Msk           (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
2595 #define GPIO_MODER_MODE15               GPIO_MODER_MODE15_Msk
2596 #define GPIO_MODER_MODE15_0             (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
2597 #define GPIO_MODER_MODE15_1             (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
2598 
2599 /******************  Bit definition for GPIO_OTYPER register  *****************/
2600 #define GPIO_OTYPER_OT_0                (0x00000001U)
2601 #define GPIO_OTYPER_OT_1                (0x00000002U)
2602 #define GPIO_OTYPER_OT_2                (0x00000004U)
2603 #define GPIO_OTYPER_OT_3                (0x00000008U)
2604 #define GPIO_OTYPER_OT_4                (0x00000010U)
2605 #define GPIO_OTYPER_OT_5                (0x00000020U)
2606 #define GPIO_OTYPER_OT_6                (0x00000040U)
2607 #define GPIO_OTYPER_OT_7                (0x00000080U)
2608 #define GPIO_OTYPER_OT_8                (0x00000100U)
2609 #define GPIO_OTYPER_OT_9                (0x00000200U)
2610 #define GPIO_OTYPER_OT_10               (0x00000400U)
2611 #define GPIO_OTYPER_OT_11               (0x00000800U)
2612 #define GPIO_OTYPER_OT_12               (0x00001000U)
2613 #define GPIO_OTYPER_OT_13               (0x00002000U)
2614 #define GPIO_OTYPER_OT_14               (0x00004000U)
2615 #define GPIO_OTYPER_OT_15               (0x00008000U)
2616 
2617 /****************  Bit definition for GPIO_OSPEEDR register  ******************/
2618 #define GPIO_OSPEEDER_OSPEED0_Pos       (0U)
2619 #define GPIO_OSPEEDER_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000003 */
2620 #define GPIO_OSPEEDER_OSPEED0           GPIO_OSPEEDER_OSPEED0_Msk
2621 #define GPIO_OSPEEDER_OSPEED0_0         (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000001 */
2622 #define GPIO_OSPEEDER_OSPEED0_1         (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos)    /*!< 0x00000002 */
2623 #define GPIO_OSPEEDER_OSPEED1_Pos       (2U)
2624 #define GPIO_OSPEEDER_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x0000000C */
2625 #define GPIO_OSPEEDER_OSPEED1           GPIO_OSPEEDER_OSPEED1_Msk
2626 #define GPIO_OSPEEDER_OSPEED1_0         (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000004 */
2627 #define GPIO_OSPEEDER_OSPEED1_1         (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos)    /*!< 0x00000008 */
2628 #define GPIO_OSPEEDER_OSPEED2_Pos       (4U)
2629 #define GPIO_OSPEEDER_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000030 */
2630 #define GPIO_OSPEEDER_OSPEED2           GPIO_OSPEEDER_OSPEED2_Msk
2631 #define GPIO_OSPEEDER_OSPEED2_0         (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000010 */
2632 #define GPIO_OSPEEDER_OSPEED2_1         (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos)    /*!< 0x00000020 */
2633 #define GPIO_OSPEEDER_OSPEED3_Pos       (6U)
2634 #define GPIO_OSPEEDER_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x000000C0 */
2635 #define GPIO_OSPEEDER_OSPEED3           GPIO_OSPEEDER_OSPEED3_Msk
2636 #define GPIO_OSPEEDER_OSPEED3_0         (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000040 */
2637 #define GPIO_OSPEEDER_OSPEED3_1         (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos)    /*!< 0x00000080 */
2638 #define GPIO_OSPEEDER_OSPEED4_Pos       (8U)
2639 #define GPIO_OSPEEDER_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000300 */
2640 #define GPIO_OSPEEDER_OSPEED4           GPIO_OSPEEDER_OSPEED4_Msk
2641 #define GPIO_OSPEEDER_OSPEED4_0         (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000100 */
2642 #define GPIO_OSPEEDER_OSPEED4_1         (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos)    /*!< 0x00000200 */
2643 #define GPIO_OSPEEDER_OSPEED5_Pos       (10U)
2644 #define GPIO_OSPEEDER_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000C00 */
2645 #define GPIO_OSPEEDER_OSPEED5           GPIO_OSPEEDER_OSPEED5_Msk
2646 #define GPIO_OSPEEDER_OSPEED5_0         (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000400 */
2647 #define GPIO_OSPEEDER_OSPEED5_1         (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos)    /*!< 0x00000800 */
2648 #define GPIO_OSPEEDER_OSPEED6_Pos       (12U)
2649 #define GPIO_OSPEEDER_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00003000 */
2650 #define GPIO_OSPEEDER_OSPEED6           GPIO_OSPEEDER_OSPEED6_Msk
2651 #define GPIO_OSPEEDER_OSPEED6_0         (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00001000 */
2652 #define GPIO_OSPEEDER_OSPEED6_1         (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos)    /*!< 0x00002000 */
2653 #define GPIO_OSPEEDER_OSPEED7_Pos       (14U)
2654 #define GPIO_OSPEEDER_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x0000C000 */
2655 #define GPIO_OSPEEDER_OSPEED7           GPIO_OSPEEDER_OSPEED7_Msk
2656 #define GPIO_OSPEEDER_OSPEED7_0         (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00004000 */
2657 #define GPIO_OSPEEDER_OSPEED7_1         (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos)    /*!< 0x00008000 */
2658 #define GPIO_OSPEEDER_OSPEED8_Pos       (16U)
2659 #define GPIO_OSPEEDER_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00030000 */
2660 #define GPIO_OSPEEDER_OSPEED8           GPIO_OSPEEDER_OSPEED8_Msk
2661 #define GPIO_OSPEEDER_OSPEED8_0         (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00010000 */
2662 #define GPIO_OSPEEDER_OSPEED8_1         (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos)    /*!< 0x00020000 */
2663 #define GPIO_OSPEEDER_OSPEED9_Pos       (18U)
2664 #define GPIO_OSPEEDER_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x000C0000 */
2665 #define GPIO_OSPEEDER_OSPEED9           GPIO_OSPEEDER_OSPEED9_Msk
2666 #define GPIO_OSPEEDER_OSPEED9_0         (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00040000 */
2667 #define GPIO_OSPEEDER_OSPEED9_1         (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos)    /*!< 0x00080000 */
2668 #define GPIO_OSPEEDER_OSPEED10_Pos      (20U)
2669 #define GPIO_OSPEEDER_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00300000 */
2670 #define GPIO_OSPEEDER_OSPEED10          GPIO_OSPEEDER_OSPEED10_Msk
2671 #define GPIO_OSPEEDER_OSPEED10_0        (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00100000 */
2672 #define GPIO_OSPEEDER_OSPEED10_1        (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos)   /*!< 0x00200000 */
2673 #define GPIO_OSPEEDER_OSPEED11_Pos      (22U)
2674 #define GPIO_OSPEEDER_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00C00000 */
2675 #define GPIO_OSPEEDER_OSPEED11          GPIO_OSPEEDER_OSPEED11_Msk
2676 #define GPIO_OSPEEDER_OSPEED11_0        (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00400000 */
2677 #define GPIO_OSPEEDER_OSPEED11_1        (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos)   /*!< 0x00800000 */
2678 #define GPIO_OSPEEDER_OSPEED12_Pos      (24U)
2679 #define GPIO_OSPEEDER_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x03000000 */
2680 #define GPIO_OSPEEDER_OSPEED12          GPIO_OSPEEDER_OSPEED12_Msk
2681 #define GPIO_OSPEEDER_OSPEED12_0        (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x01000000 */
2682 #define GPIO_OSPEEDER_OSPEED12_1        (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos)   /*!< 0x02000000 */
2683 #define GPIO_OSPEEDER_OSPEED13_Pos      (26U)
2684 #define GPIO_OSPEEDER_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x0C000000 */
2685 #define GPIO_OSPEEDER_OSPEED13          GPIO_OSPEEDER_OSPEED13_Msk
2686 #define GPIO_OSPEEDER_OSPEED13_0        (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x04000000 */
2687 #define GPIO_OSPEEDER_OSPEED13_1        (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos)   /*!< 0x08000000 */
2688 #define GPIO_OSPEEDER_OSPEED14_Pos      (28U)
2689 #define GPIO_OSPEEDER_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x30000000 */
2690 #define GPIO_OSPEEDER_OSPEED14          GPIO_OSPEEDER_OSPEED14_Msk
2691 #define GPIO_OSPEEDER_OSPEED14_0        (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x10000000 */
2692 #define GPIO_OSPEEDER_OSPEED14_1        (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos)   /*!< 0x20000000 */
2693 #define GPIO_OSPEEDER_OSPEED15_Pos      (30U)
2694 #define GPIO_OSPEEDER_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0xC0000000 */
2695 #define GPIO_OSPEEDER_OSPEED15          GPIO_OSPEEDER_OSPEED15_Msk
2696 #define GPIO_OSPEEDER_OSPEED15_0        (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x40000000 */
2697 #define GPIO_OSPEEDER_OSPEED15_1        (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos)   /*!< 0x80000000 */
2698 
2699 /*******************  Bit definition for GPIO_PUPDR register ******************/
2700 #define GPIO_PUPDR_PUPD0_Pos            (0U)
2701 #define GPIO_PUPDR_PUPD0_Msk            (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
2702 #define GPIO_PUPDR_PUPD0                GPIO_PUPDR_PUPD0_Msk
2703 #define GPIO_PUPDR_PUPD0_0              (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
2704 #define GPIO_PUPDR_PUPD0_1              (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
2705 #define GPIO_PUPDR_PUPD1_Pos            (2U)
2706 #define GPIO_PUPDR_PUPD1_Msk            (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
2707 #define GPIO_PUPDR_PUPD1                GPIO_PUPDR_PUPD1_Msk
2708 #define GPIO_PUPDR_PUPD1_0              (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
2709 #define GPIO_PUPDR_PUPD1_1              (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
2710 #define GPIO_PUPDR_PUPD2_Pos            (4U)
2711 #define GPIO_PUPDR_PUPD2_Msk            (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
2712 #define GPIO_PUPDR_PUPD2                GPIO_PUPDR_PUPD2_Msk
2713 #define GPIO_PUPDR_PUPD2_0              (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
2714 #define GPIO_PUPDR_PUPD2_1              (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
2715 #define GPIO_PUPDR_PUPD3_Pos            (6U)
2716 #define GPIO_PUPDR_PUPD3_Msk            (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
2717 #define GPIO_PUPDR_PUPD3                GPIO_PUPDR_PUPD3_Msk
2718 #define GPIO_PUPDR_PUPD3_0              (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
2719 #define GPIO_PUPDR_PUPD3_1              (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
2720 #define GPIO_PUPDR_PUPD4_Pos            (8U)
2721 #define GPIO_PUPDR_PUPD4_Msk            (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
2722 #define GPIO_PUPDR_PUPD4                GPIO_PUPDR_PUPD4_Msk
2723 #define GPIO_PUPDR_PUPD4_0              (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
2724 #define GPIO_PUPDR_PUPD4_1              (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
2725 #define GPIO_PUPDR_PUPD5_Pos            (10U)
2726 #define GPIO_PUPDR_PUPD5_Msk            (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
2727 #define GPIO_PUPDR_PUPD5                GPIO_PUPDR_PUPD5_Msk
2728 #define GPIO_PUPDR_PUPD5_0              (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
2729 #define GPIO_PUPDR_PUPD5_1              (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
2730 #define GPIO_PUPDR_PUPD6_Pos            (12U)
2731 #define GPIO_PUPDR_PUPD6_Msk            (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
2732 #define GPIO_PUPDR_PUPD6                GPIO_PUPDR_PUPD6_Msk
2733 #define GPIO_PUPDR_PUPD6_0              (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
2734 #define GPIO_PUPDR_PUPD6_1              (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
2735 #define GPIO_PUPDR_PUPD7_Pos            (14U)
2736 #define GPIO_PUPDR_PUPD7_Msk            (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
2737 #define GPIO_PUPDR_PUPD7                GPIO_PUPDR_PUPD7_Msk
2738 #define GPIO_PUPDR_PUPD7_0              (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
2739 #define GPIO_PUPDR_PUPD7_1              (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
2740 #define GPIO_PUPDR_PUPD8_Pos            (16U)
2741 #define GPIO_PUPDR_PUPD8_Msk            (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
2742 #define GPIO_PUPDR_PUPD8                GPIO_PUPDR_PUPD8_Msk
2743 #define GPIO_PUPDR_PUPD8_0              (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
2744 #define GPIO_PUPDR_PUPD8_1              (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
2745 #define GPIO_PUPDR_PUPD9_Pos            (18U)
2746 #define GPIO_PUPDR_PUPD9_Msk            (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
2747 #define GPIO_PUPDR_PUPD9                GPIO_PUPDR_PUPD9_Msk
2748 #define GPIO_PUPDR_PUPD9_0              (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
2749 #define GPIO_PUPDR_PUPD9_1              (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
2750 #define GPIO_PUPDR_PUPD10_Pos           (20U)
2751 #define GPIO_PUPDR_PUPD10_Msk           (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
2752 #define GPIO_PUPDR_PUPD10               GPIO_PUPDR_PUPD10_Msk
2753 #define GPIO_PUPDR_PUPD10_0             (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
2754 #define GPIO_PUPDR_PUPD10_1             (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
2755 #define GPIO_PUPDR_PUPD11_Pos           (22U)
2756 #define GPIO_PUPDR_PUPD11_Msk           (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
2757 #define GPIO_PUPDR_PUPD11               GPIO_PUPDR_PUPD11_Msk
2758 #define GPIO_PUPDR_PUPD11_0             (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
2759 #define GPIO_PUPDR_PUPD11_1             (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
2760 #define GPIO_PUPDR_PUPD12_Pos           (24U)
2761 #define GPIO_PUPDR_PUPD12_Msk           (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
2762 #define GPIO_PUPDR_PUPD12               GPIO_PUPDR_PUPD12_Msk
2763 #define GPIO_PUPDR_PUPD12_0             (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
2764 #define GPIO_PUPDR_PUPD12_1             (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
2765 #define GPIO_PUPDR_PUPD13_Pos           (26U)
2766 #define GPIO_PUPDR_PUPD13_Msk           (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
2767 #define GPIO_PUPDR_PUPD13               GPIO_PUPDR_PUPD13_Msk
2768 #define GPIO_PUPDR_PUPD13_0             (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
2769 #define GPIO_PUPDR_PUPD13_1             (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
2770 #define GPIO_PUPDR_PUPD14_Pos           (28U)
2771 #define GPIO_PUPDR_PUPD14_Msk           (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
2772 #define GPIO_PUPDR_PUPD14               GPIO_PUPDR_PUPD14_Msk
2773 #define GPIO_PUPDR_PUPD14_0             (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
2774 #define GPIO_PUPDR_PUPD14_1             (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
2775 #define GPIO_PUPDR_PUPD15_Pos           (30U)
2776 #define GPIO_PUPDR_PUPD15_Msk           (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
2777 #define GPIO_PUPDR_PUPD15               GPIO_PUPDR_PUPD15_Msk
2778 #define GPIO_PUPDR_PUPD15_0             (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
2779 #define GPIO_PUPDR_PUPD15_1             (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
2780 
2781 /*******************  Bit definition for GPIO_IDR register  *******************/
2782 #define GPIO_IDR_ID0_Pos                (0U)
2783 #define GPIO_IDR_ID0_Msk                (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
2784 #define GPIO_IDR_ID0                    GPIO_IDR_ID0_Msk
2785 #define GPIO_IDR_ID1_Pos                (1U)
2786 #define GPIO_IDR_ID1_Msk                (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
2787 #define GPIO_IDR_ID1                    GPIO_IDR_ID1_Msk
2788 #define GPIO_IDR_ID2_Pos                (2U)
2789 #define GPIO_IDR_ID2_Msk                (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
2790 #define GPIO_IDR_ID2                    GPIO_IDR_ID2_Msk
2791 #define GPIO_IDR_ID3_Pos                (3U)
2792 #define GPIO_IDR_ID3_Msk                (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
2793 #define GPIO_IDR_ID3                    GPIO_IDR_ID3_Msk
2794 #define GPIO_IDR_ID4_Pos                (4U)
2795 #define GPIO_IDR_ID4_Msk                (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
2796 #define GPIO_IDR_ID4                    GPIO_IDR_ID4_Msk
2797 #define GPIO_IDR_ID5_Pos                (5U)
2798 #define GPIO_IDR_ID5_Msk                (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
2799 #define GPIO_IDR_ID5                    GPIO_IDR_ID5_Msk
2800 #define GPIO_IDR_ID6_Pos                (6U)
2801 #define GPIO_IDR_ID6_Msk                (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
2802 #define GPIO_IDR_ID6                    GPIO_IDR_ID6_Msk
2803 #define GPIO_IDR_ID7_Pos                (7U)
2804 #define GPIO_IDR_ID7_Msk                (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
2805 #define GPIO_IDR_ID7                    GPIO_IDR_ID7_Msk
2806 #define GPIO_IDR_ID8_Pos                (8U)
2807 #define GPIO_IDR_ID8_Msk                (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
2808 #define GPIO_IDR_ID8                    GPIO_IDR_ID8_Msk
2809 #define GPIO_IDR_ID9_Pos                (9U)
2810 #define GPIO_IDR_ID9_Msk                (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
2811 #define GPIO_IDR_ID9                    GPIO_IDR_ID9_Msk
2812 #define GPIO_IDR_ID10_Pos               (10U)
2813 #define GPIO_IDR_ID10_Msk               (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
2814 #define GPIO_IDR_ID10                   GPIO_IDR_ID10_Msk
2815 #define GPIO_IDR_ID11_Pos               (11U)
2816 #define GPIO_IDR_ID11_Msk               (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
2817 #define GPIO_IDR_ID11                   GPIO_IDR_ID11_Msk
2818 #define GPIO_IDR_ID12_Pos               (12U)
2819 #define GPIO_IDR_ID12_Msk               (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
2820 #define GPIO_IDR_ID12                   GPIO_IDR_ID12_Msk
2821 #define GPIO_IDR_ID13_Pos               (13U)
2822 #define GPIO_IDR_ID13_Msk               (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
2823 #define GPIO_IDR_ID13                   GPIO_IDR_ID13_Msk
2824 #define GPIO_IDR_ID14_Pos               (14U)
2825 #define GPIO_IDR_ID14_Msk               (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
2826 #define GPIO_IDR_ID14                   GPIO_IDR_ID14_Msk
2827 #define GPIO_IDR_ID15_Pos               (15U)
2828 #define GPIO_IDR_ID15_Msk               (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
2829 #define GPIO_IDR_ID15                   GPIO_IDR_ID15_Msk
2830 
2831 /******************  Bit definition for GPIO_ODR register  ********************/
2832 #define GPIO_ODR_OD0_Pos                (0U)
2833 #define GPIO_ODR_OD0_Msk                (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
2834 #define GPIO_ODR_OD0                    GPIO_ODR_OD0_Msk
2835 #define GPIO_ODR_OD1_Pos                (1U)
2836 #define GPIO_ODR_OD1_Msk                (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
2837 #define GPIO_ODR_OD1                    GPIO_ODR_OD1_Msk
2838 #define GPIO_ODR_OD2_Pos                (2U)
2839 #define GPIO_ODR_OD2_Msk                (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
2840 #define GPIO_ODR_OD2                    GPIO_ODR_OD2_Msk
2841 #define GPIO_ODR_OD3_Pos                (3U)
2842 #define GPIO_ODR_OD3_Msk                (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
2843 #define GPIO_ODR_OD3                    GPIO_ODR_OD3_Msk
2844 #define GPIO_ODR_OD4_Pos                (4U)
2845 #define GPIO_ODR_OD4_Msk                (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
2846 #define GPIO_ODR_OD4                    GPIO_ODR_OD4_Msk
2847 #define GPIO_ODR_OD5_Pos                (5U)
2848 #define GPIO_ODR_OD5_Msk                (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
2849 #define GPIO_ODR_OD5                    GPIO_ODR_OD5_Msk
2850 #define GPIO_ODR_OD6_Pos                (6U)
2851 #define GPIO_ODR_OD6_Msk                (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
2852 #define GPIO_ODR_OD6                    GPIO_ODR_OD6_Msk
2853 #define GPIO_ODR_OD7_Pos                (7U)
2854 #define GPIO_ODR_OD7_Msk                (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
2855 #define GPIO_ODR_OD7                    GPIO_ODR_OD7_Msk
2856 #define GPIO_ODR_OD8_Pos                (8U)
2857 #define GPIO_ODR_OD8_Msk                (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
2858 #define GPIO_ODR_OD8                    GPIO_ODR_OD8_Msk
2859 #define GPIO_ODR_OD9_Pos                (9U)
2860 #define GPIO_ODR_OD9_Msk                (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
2861 #define GPIO_ODR_OD9                    GPIO_ODR_OD9_Msk
2862 #define GPIO_ODR_OD10_Pos               (10U)
2863 #define GPIO_ODR_OD10_Msk               (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
2864 #define GPIO_ODR_OD10                   GPIO_ODR_OD10_Msk
2865 #define GPIO_ODR_OD11_Pos               (11U)
2866 #define GPIO_ODR_OD11_Msk               (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
2867 #define GPIO_ODR_OD11                   GPIO_ODR_OD11_Msk
2868 #define GPIO_ODR_OD12_Pos               (12U)
2869 #define GPIO_ODR_OD12_Msk               (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
2870 #define GPIO_ODR_OD12                   GPIO_ODR_OD12_Msk
2871 #define GPIO_ODR_OD13_Pos               (13U)
2872 #define GPIO_ODR_OD13_Msk               (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
2873 #define GPIO_ODR_OD13                   GPIO_ODR_OD13_Msk
2874 #define GPIO_ODR_OD14_Pos               (14U)
2875 #define GPIO_ODR_OD14_Msk               (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
2876 #define GPIO_ODR_OD14                   GPIO_ODR_OD14_Msk
2877 #define GPIO_ODR_OD15_Pos               (15U)
2878 #define GPIO_ODR_OD15_Msk               (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
2879 #define GPIO_ODR_OD15                   GPIO_ODR_OD15_Msk
2880 
2881 /****************** Bit definition for GPIO_BSRR register  ********************/
2882 #define GPIO_BSRR_BS_0                  (0x00000001U)
2883 #define GPIO_BSRR_BS_1                  (0x00000002U)
2884 #define GPIO_BSRR_BS_2                  (0x00000004U)
2885 #define GPIO_BSRR_BS_3                  (0x00000008U)
2886 #define GPIO_BSRR_BS_4                  (0x00000010U)
2887 #define GPIO_BSRR_BS_5                  (0x00000020U)
2888 #define GPIO_BSRR_BS_6                  (0x00000040U)
2889 #define GPIO_BSRR_BS_7                  (0x00000080U)
2890 #define GPIO_BSRR_BS_8                  (0x00000100U)
2891 #define GPIO_BSRR_BS_9                  (0x00000200U)
2892 #define GPIO_BSRR_BS_10                 (0x00000400U)
2893 #define GPIO_BSRR_BS_11                 (0x00000800U)
2894 #define GPIO_BSRR_BS_12                 (0x00001000U)
2895 #define GPIO_BSRR_BS_13                 (0x00002000U)
2896 #define GPIO_BSRR_BS_14                 (0x00004000U)
2897 #define GPIO_BSRR_BS_15                 (0x00008000U)
2898 #define GPIO_BSRR_BR_0                  (0x00010000U)
2899 #define GPIO_BSRR_BR_1                  (0x00020000U)
2900 #define GPIO_BSRR_BR_2                  (0x00040000U)
2901 #define GPIO_BSRR_BR_3                  (0x00080000U)
2902 #define GPIO_BSRR_BR_4                  (0x00100000U)
2903 #define GPIO_BSRR_BR_5                  (0x00200000U)
2904 #define GPIO_BSRR_BR_6                  (0x00400000U)
2905 #define GPIO_BSRR_BR_7                  (0x00800000U)
2906 #define GPIO_BSRR_BR_8                  (0x01000000U)
2907 #define GPIO_BSRR_BR_9                  (0x02000000U)
2908 #define GPIO_BSRR_BR_10                 (0x04000000U)
2909 #define GPIO_BSRR_BR_11                 (0x08000000U)
2910 #define GPIO_BSRR_BR_12                 (0x10000000U)
2911 #define GPIO_BSRR_BR_13                 (0x20000000U)
2912 #define GPIO_BSRR_BR_14                 (0x40000000U)
2913 #define GPIO_BSRR_BR_15                 (0x80000000U)
2914 
2915 /****************** Bit definition for GPIO_LCKR register  ********************/
2916 #define GPIO_LCKR_LCK0_Pos              (0U)
2917 #define GPIO_LCKR_LCK0_Msk              (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
2918 #define GPIO_LCKR_LCK0                  GPIO_LCKR_LCK0_Msk
2919 #define GPIO_LCKR_LCK1_Pos              (1U)
2920 #define GPIO_LCKR_LCK1_Msk              (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
2921 #define GPIO_LCKR_LCK1                  GPIO_LCKR_LCK1_Msk
2922 #define GPIO_LCKR_LCK2_Pos              (2U)
2923 #define GPIO_LCKR_LCK2_Msk              (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
2924 #define GPIO_LCKR_LCK2                  GPIO_LCKR_LCK2_Msk
2925 #define GPIO_LCKR_LCK3_Pos              (3U)
2926 #define GPIO_LCKR_LCK3_Msk              (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
2927 #define GPIO_LCKR_LCK3                  GPIO_LCKR_LCK3_Msk
2928 #define GPIO_LCKR_LCK4_Pos              (4U)
2929 #define GPIO_LCKR_LCK4_Msk              (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
2930 #define GPIO_LCKR_LCK4                  GPIO_LCKR_LCK4_Msk
2931 #define GPIO_LCKR_LCK5_Pos              (5U)
2932 #define GPIO_LCKR_LCK5_Msk              (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
2933 #define GPIO_LCKR_LCK5                  GPIO_LCKR_LCK5_Msk
2934 #define GPIO_LCKR_LCK6_Pos              (6U)
2935 #define GPIO_LCKR_LCK6_Msk              (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
2936 #define GPIO_LCKR_LCK6                  GPIO_LCKR_LCK6_Msk
2937 #define GPIO_LCKR_LCK7_Pos              (7U)
2938 #define GPIO_LCKR_LCK7_Msk              (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
2939 #define GPIO_LCKR_LCK7                  GPIO_LCKR_LCK7_Msk
2940 #define GPIO_LCKR_LCK8_Pos              (8U)
2941 #define GPIO_LCKR_LCK8_Msk              (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
2942 #define GPIO_LCKR_LCK8                  GPIO_LCKR_LCK8_Msk
2943 #define GPIO_LCKR_LCK9_Pos              (9U)
2944 #define GPIO_LCKR_LCK9_Msk              (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
2945 #define GPIO_LCKR_LCK9                  GPIO_LCKR_LCK9_Msk
2946 #define GPIO_LCKR_LCK10_Pos             (10U)
2947 #define GPIO_LCKR_LCK10_Msk             (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
2948 #define GPIO_LCKR_LCK10                 GPIO_LCKR_LCK10_Msk
2949 #define GPIO_LCKR_LCK11_Pos             (11U)
2950 #define GPIO_LCKR_LCK11_Msk             (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
2951 #define GPIO_LCKR_LCK11                 GPIO_LCKR_LCK11_Msk
2952 #define GPIO_LCKR_LCK12_Pos             (12U)
2953 #define GPIO_LCKR_LCK12_Msk             (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
2954 #define GPIO_LCKR_LCK12                 GPIO_LCKR_LCK12_Msk
2955 #define GPIO_LCKR_LCK13_Pos             (13U)
2956 #define GPIO_LCKR_LCK13_Msk             (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
2957 #define GPIO_LCKR_LCK13                 GPIO_LCKR_LCK13_Msk
2958 #define GPIO_LCKR_LCK14_Pos             (14U)
2959 #define GPIO_LCKR_LCK14_Msk             (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
2960 #define GPIO_LCKR_LCK14                 GPIO_LCKR_LCK14_Msk
2961 #define GPIO_LCKR_LCK15_Pos             (15U)
2962 #define GPIO_LCKR_LCK15_Msk             (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
2963 #define GPIO_LCKR_LCK15                 GPIO_LCKR_LCK15_Msk
2964 #define GPIO_LCKR_LCKK_Pos              (16U)
2965 #define GPIO_LCKR_LCKK_Msk              (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
2966 #define GPIO_LCKR_LCKK                  GPIO_LCKR_LCKK_Msk
2967 
2968 /****************** Bit definition for GPIO_AFRL register ********************/
2969 #define GPIO_AFRL_AFSEL0_Pos             (0U)
2970 #define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
2971 #define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk
2972 #define GPIO_AFRL_AFSEL1_Pos             (4U)
2973 #define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
2974 #define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk
2975 #define GPIO_AFRL_AFSEL2_Pos             (8U)
2976 #define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
2977 #define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk
2978 #define GPIO_AFRL_AFSEL3_Pos             (12U)
2979 #define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
2980 #define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk
2981 #define GPIO_AFRL_AFSEL4_Pos             (16U)
2982 #define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
2983 #define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk
2984 #define GPIO_AFRL_AFSEL5_Pos             (20U)
2985 #define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
2986 #define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk
2987 #define GPIO_AFRL_AFSEL6_Pos             (24U)
2988 #define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
2989 #define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk
2990 #define GPIO_AFRL_AFSEL7_Pos             (28U)
2991 #define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
2992 #define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk
2993 
2994 /****************** Bit definition for GPIO_AFRH register ********************/
2995 #define GPIO_AFRH_AFSEL8_Pos             (0U)
2996 #define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
2997 #define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk
2998 #define GPIO_AFRH_AFSEL9_Pos             (4U)
2999 #define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
3000 #define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk
3001 #define GPIO_AFRH_AFSEL10_Pos             (8U)
3002 #define GPIO_AFRH_AFSEL10_Msk             (0xFUL << GPIO_AFRH_AFSEL10_Pos)          /*!< 0x00000F00 */
3003 #define GPIO_AFRH_AFSEL10                 GPIO_AFRH_AFSEL10_Msk
3004 #define GPIO_AFRH_AFSEL11_Pos             (12U)
3005 #define GPIO_AFRH_AFSEL11_Msk             (0xFUL << GPIO_AFRH_AFSEL11_Pos)          /*!< 0x0000F000 */
3006 #define GPIO_AFRH_AFSEL11                 GPIO_AFRH_AFSEL11_Msk
3007 #define GPIO_AFRH_AFSEL12_Pos             (16U)
3008 #define GPIO_AFRH_AFSEL12_Msk             (0xFUL << GPIO_AFRH_AFSEL12_Pos)          /*!< 0x000F0000 */
3009 #define GPIO_AFRH_AFSEL12                 GPIO_AFRH_AFSEL12_Msk
3010 #define GPIO_AFRH_AFSEL13_Pos             (20U)
3011 #define GPIO_AFRH_AFSEL13_Msk             (0xFUL << GPIO_AFRH_AFSEL13_Pos)          /*!< 0x00F00000 */
3012 #define GPIO_AFRH_AFSEL13                 GPIO_AFRH_AFSEL13_Msk
3013 #define GPIO_AFRH_AFSEL14_Pos             (24U)
3014 #define GPIO_AFRH_AFSEL14_Msk             (0xFUL << GPIO_AFRH_AFSEL14_Pos)          /*!< 0x0F000000 */
3015 #define GPIO_AFRH_AFSEL14                 GPIO_AFRH_AFSEL14_Msk
3016 #define GPIO_AFRH_AFSEL15_Pos             (28U)
3017 #define GPIO_AFRH_AFSEL15_Msk             (0xFUL << GPIO_AFRH_AFSEL15_Pos)          /*!< 0xF0000000 */
3018 #define GPIO_AFRH_AFSEL15                 GPIO_AFRH_AFSEL15_Msk
3019 
3020 /****************** Bit definition for GPIO_BRR register  *********************/
3021 #define GPIO_BRR_BR_0                   (0x00000001U)
3022 #define GPIO_BRR_BR_1                   (0x00000002U)
3023 #define GPIO_BRR_BR_2                   (0x00000004U)
3024 #define GPIO_BRR_BR_3                   (0x00000008U)
3025 #define GPIO_BRR_BR_4                   (0x00000010U)
3026 #define GPIO_BRR_BR_5                   (0x00000020U)
3027 #define GPIO_BRR_BR_6                   (0x00000040U)
3028 #define GPIO_BRR_BR_7                   (0x00000080U)
3029 #define GPIO_BRR_BR_8                   (0x00000100U)
3030 #define GPIO_BRR_BR_9                   (0x00000200U)
3031 #define GPIO_BRR_BR_10                  (0x00000400U)
3032 #define GPIO_BRR_BR_11                  (0x00000800U)
3033 #define GPIO_BRR_BR_12                  (0x00001000U)
3034 #define GPIO_BRR_BR_13                  (0x00002000U)
3035 #define GPIO_BRR_BR_14                  (0x00004000U)
3036 #define GPIO_BRR_BR_15                  (0x00008000U)
3037 
3038 /******************************************************************************/
3039 /*                                                                            */
3040 /*                   Inter-integrated Circuit Interface (I2C)                 */
3041 /*                                                                            */
3042 /******************************************************************************/
3043 
3044 /*******************  Bit definition for I2C_CR1 register  *******************/
3045 #define I2C_CR1_PE_Pos               (0U)
3046 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
3047 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
3048 #define I2C_CR1_TXIE_Pos             (1U)
3049 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
3050 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
3051 #define I2C_CR1_RXIE_Pos             (2U)
3052 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
3053 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
3054 #define I2C_CR1_ADDRIE_Pos           (3U)
3055 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
3056 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
3057 #define I2C_CR1_NACKIE_Pos           (4U)
3058 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
3059 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
3060 #define I2C_CR1_STOPIE_Pos           (5U)
3061 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
3062 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
3063 #define I2C_CR1_TCIE_Pos             (6U)
3064 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
3065 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
3066 #define I2C_CR1_ERRIE_Pos            (7U)
3067 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
3068 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
3069 #define I2C_CR1_DNF_Pos              (8U)
3070 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
3071 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
3072 #define I2C_CR1_ANFOFF_Pos           (12U)
3073 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
3074 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
3075 #define I2C_CR1_TXDMAEN_Pos          (14U)
3076 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
3077 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
3078 #define I2C_CR1_RXDMAEN_Pos          (15U)
3079 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
3080 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
3081 #define I2C_CR1_SBC_Pos              (16U)
3082 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
3083 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
3084 #define I2C_CR1_NOSTRETCH_Pos        (17U)
3085 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
3086 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
3087 #define I2C_CR1_WUPEN_Pos            (18U)
3088 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
3089 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
3090 #define I2C_CR1_GCEN_Pos             (19U)
3091 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
3092 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
3093 #define I2C_CR1_SMBHEN_Pos           (20U)
3094 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
3095 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
3096 #define I2C_CR1_SMBDEN_Pos           (21U)
3097 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
3098 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
3099 #define I2C_CR1_ALERTEN_Pos          (22U)
3100 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
3101 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
3102 #define I2C_CR1_PECEN_Pos            (23U)
3103 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
3104 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
3105 
3106 /******************  Bit definition for I2C_CR2 register  ********************/
3107 #define I2C_CR2_SADD_Pos             (0U)
3108 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
3109 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
3110 #define I2C_CR2_RD_WRN_Pos           (10U)
3111 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
3112 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
3113 #define I2C_CR2_ADD10_Pos            (11U)
3114 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
3115 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
3116 #define I2C_CR2_HEAD10R_Pos          (12U)
3117 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
3118 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
3119 #define I2C_CR2_START_Pos            (13U)
3120 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)               /*!< 0x00002000 */
3121 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
3122 #define I2C_CR2_STOP_Pos             (14U)
3123 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
3124 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
3125 #define I2C_CR2_NACK_Pos             (15U)
3126 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
3127 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
3128 #define I2C_CR2_NBYTES_Pos           (16U)
3129 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
3130 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
3131 #define I2C_CR2_RELOAD_Pos           (24U)
3132 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
3133 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
3134 #define I2C_CR2_AUTOEND_Pos          (25U)
3135 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
3136 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
3137 #define I2C_CR2_PECBYTE_Pos          (26U)
3138 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
3139 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
3140 
3141 /*******************  Bit definition for I2C_OAR1 register  ******************/
3142 #define I2C_OAR1_OA1_Pos             (0U)
3143 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
3144 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
3145 #define I2C_OAR1_OA1MODE_Pos         (10U)
3146 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
3147 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
3148 #define I2C_OAR1_OA1EN_Pos           (15U)
3149 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
3150 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
3151 
3152 /*******************  Bit definition for I2C_OAR2 register  ******************/
3153 #define I2C_OAR2_OA2_Pos             (1U)
3154 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
3155 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
3156 #define I2C_OAR2_OA2MSK_Pos          (8U)
3157 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
3158 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
3159 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
3160 #define I2C_OAR2_OA2MASK01_Pos       (8U)
3161 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
3162 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
3163 #define I2C_OAR2_OA2MASK02_Pos       (9U)
3164 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
3165 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
3166 #define I2C_OAR2_OA2MASK03_Pos       (8U)
3167 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
3168 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
3169 #define I2C_OAR2_OA2MASK04_Pos       (10U)
3170 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
3171 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
3172 #define I2C_OAR2_OA2MASK05_Pos       (8U)
3173 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
3174 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
3175 #define I2C_OAR2_OA2MASK06_Pos       (9U)
3176 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
3177 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
3178 #define I2C_OAR2_OA2MASK07_Pos       (8U)
3179 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
3180 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
3181 #define I2C_OAR2_OA2EN_Pos           (15U)
3182 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
3183 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
3184 
3185 /*******************  Bit definition for I2C_TIMINGR register *******************/
3186 #define I2C_TIMINGR_SCLL_Pos         (0U)
3187 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
3188 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
3189 #define I2C_TIMINGR_SCLH_Pos         (8U)
3190 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
3191 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
3192 #define I2C_TIMINGR_SDADEL_Pos       (16U)
3193 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
3194 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
3195 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
3196 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
3197 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
3198 #define I2C_TIMINGR_PRESC_Pos        (28U)
3199 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
3200 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
3201 
3202 /******************* Bit definition for I2C_TIMEOUTR register *******************/
3203 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
3204 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
3205 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
3206 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
3207 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
3208 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
3209 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
3210 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
3211 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
3212 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
3213 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
3214 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
3215 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
3216 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
3217 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
3218 
3219 /******************  Bit definition for I2C_ISR register  *********************/
3220 #define I2C_ISR_TXE_Pos              (0U)
3221 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
3222 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
3223 #define I2C_ISR_TXIS_Pos             (1U)
3224 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
3225 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
3226 #define I2C_ISR_RXNE_Pos             (2U)
3227 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
3228 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
3229 #define I2C_ISR_ADDR_Pos             (3U)
3230 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
3231 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
3232 #define I2C_ISR_NACKF_Pos            (4U)
3233 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
3234 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
3235 #define I2C_ISR_STOPF_Pos            (5U)
3236 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
3237 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
3238 #define I2C_ISR_TC_Pos               (6U)
3239 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
3240 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
3241 #define I2C_ISR_TCR_Pos              (7U)
3242 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
3243 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
3244 #define I2C_ISR_BERR_Pos             (8U)
3245 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
3246 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
3247 #define I2C_ISR_ARLO_Pos             (9U)
3248 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
3249 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
3250 #define I2C_ISR_OVR_Pos              (10U)
3251 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
3252 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
3253 #define I2C_ISR_PECERR_Pos           (11U)
3254 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
3255 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
3256 #define I2C_ISR_TIMEOUT_Pos          (12U)
3257 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
3258 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
3259 #define I2C_ISR_ALERT_Pos            (13U)
3260 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
3261 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
3262 #define I2C_ISR_BUSY_Pos             (15U)
3263 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
3264 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
3265 #define I2C_ISR_DIR_Pos              (16U)
3266 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
3267 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
3268 #define I2C_ISR_ADDCODE_Pos          (17U)
3269 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
3270 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
3271 
3272 /******************  Bit definition for I2C_ICR register  *********************/
3273 #define I2C_ICR_ADDRCF_Pos           (3U)
3274 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
3275 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
3276 #define I2C_ICR_NACKCF_Pos           (4U)
3277 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
3278 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
3279 #define I2C_ICR_STOPCF_Pos           (5U)
3280 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
3281 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
3282 #define I2C_ICR_BERRCF_Pos           (8U)
3283 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
3284 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
3285 #define I2C_ICR_ARLOCF_Pos           (9U)
3286 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
3287 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
3288 #define I2C_ICR_OVRCF_Pos            (10U)
3289 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
3290 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
3291 #define I2C_ICR_PECCF_Pos            (11U)
3292 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
3293 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
3294 #define I2C_ICR_TIMOUTCF_Pos         (12U)
3295 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
3296 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
3297 #define I2C_ICR_ALERTCF_Pos          (13U)
3298 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
3299 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
3300 
3301 /******************  Bit definition for I2C_PECR register  *********************/
3302 #define I2C_PECR_PEC_Pos             (0U)
3303 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
3304 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
3305 
3306 /******************  Bit definition for I2C_RXDR register  *********************/
3307 #define I2C_RXDR_RXDATA_Pos          (0U)
3308 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
3309 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
3310 
3311 /******************  Bit definition for I2C_TXDR register  *********************/
3312 #define I2C_TXDR_TXDATA_Pos          (0U)
3313 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
3314 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
3315 
3316 /******************************************************************************/
3317 /*                                                                            */
3318 /*                        Independent WATCHDOG (IWDG)                         */
3319 /*                                                                            */
3320 /******************************************************************************/
3321 /*******************  Bit definition for IWDG_KR register  ********************/
3322 #define IWDG_KR_KEY_Pos      (0U)
3323 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
3324 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!< Key value (write only, read 0000h) */
3325 
3326 /*******************  Bit definition for IWDG_PR register  ********************/
3327 #define IWDG_PR_PR_Pos       (0U)
3328 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
3329 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!< PR[2:0] (Prescaler divider) */
3330 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
3331 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
3332 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
3333 
3334 /*******************  Bit definition for IWDG_RLR register  *******************/
3335 #define IWDG_RLR_RL_Pos      (0U)
3336 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
3337 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!< Watchdog counter reload value */
3338 
3339 /*******************  Bit definition for IWDG_SR register  ********************/
3340 #define IWDG_SR_PVU_Pos      (0U)
3341 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
3342 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
3343 #define IWDG_SR_RVU_Pos      (1U)
3344 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
3345 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
3346 #define IWDG_SR_WVU_Pos      (2U)
3347 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
3348 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
3349 
3350 /*******************  Bit definition for IWDG_KR register  ********************/
3351 #define IWDG_WINR_WIN_Pos    (0U)
3352 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
3353 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
3354 
3355 /******************************************************************************/
3356 /*                                                                            */
3357 /*                         Low Power Timer (LPTTIM)                           */
3358 /*                                                                            */
3359 /******************************************************************************/
3360 /******************  Bit definition for LPTIM_ISR register  *******************/
3361 #define LPTIM_ISR_CMPM_Pos          (0U)
3362 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
3363 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
3364 #define LPTIM_ISR_ARRM_Pos          (1U)
3365 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
3366 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
3367 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
3368 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
3369 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
3370 #define LPTIM_ISR_CMPOK_Pos         (3U)
3371 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
3372 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
3373 #define LPTIM_ISR_ARROK_Pos         (4U)
3374 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
3375 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
3376 #define LPTIM_ISR_UP_Pos            (5U)
3377 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
3378 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
3379 #define LPTIM_ISR_DOWN_Pos          (6U)
3380 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
3381 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
3382 
3383 /******************  Bit definition for LPTIM_ICR register  *******************/
3384 #define LPTIM_ICR_CMPMCF_Pos        (0U)
3385 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
3386 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
3387 #define LPTIM_ICR_ARRMCF_Pos        (1U)
3388 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
3389 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
3390 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
3391 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
3392 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
3393 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
3394 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
3395 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
3396 #define LPTIM_ICR_ARROKCF_Pos       (4U)
3397 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
3398 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
3399 #define LPTIM_ICR_UPCF_Pos          (5U)
3400 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
3401 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
3402 #define LPTIM_ICR_DOWNCF_Pos        (6U)
3403 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
3404 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
3405 
3406 /******************  Bit definition for LPTIM_IER register ********************/
3407 #define LPTIM_IER_CMPMIE_Pos        (0U)
3408 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
3409 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
3410 #define LPTIM_IER_ARRMIE_Pos        (1U)
3411 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
3412 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
3413 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
3414 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
3415 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
3416 #define LPTIM_IER_CMPOKIE_Pos       (3U)
3417 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
3418 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
3419 #define LPTIM_IER_ARROKIE_Pos       (4U)
3420 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
3421 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
3422 #define LPTIM_IER_UPIE_Pos          (5U)
3423 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
3424 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
3425 #define LPTIM_IER_DOWNIE_Pos        (6U)
3426 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
3427 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
3428 
3429 /******************  Bit definition for LPTIM_CFGR register *******************/
3430 #define LPTIM_CFGR_CKSEL_Pos        (0U)
3431 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
3432 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
3433 
3434 #define LPTIM_CFGR_CKPOL_Pos        (1U)
3435 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
3436 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
3437 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
3438 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
3439 
3440 #define LPTIM_CFGR_CKFLT_Pos        (3U)
3441 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
3442 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
3443 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
3444 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
3445 
3446 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
3447 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
3448 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
3449 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
3450 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
3451 
3452 #define LPTIM_CFGR_PRESC_Pos        (9U)
3453 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
3454 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
3455 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
3456 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
3457 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
3458 
3459 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
3460 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
3461 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
3462 #define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
3463 #define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
3464 #define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
3465 
3466 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
3467 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
3468 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
3469 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
3470 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
3471 
3472 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
3473 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
3474 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
3475 #define LPTIM_CFGR_WAVE_Pos         (20U)
3476 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
3477 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
3478 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
3479 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
3480 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
3481 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
3482 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
3483 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
3484 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
3485 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
3486 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
3487 #define LPTIM_CFGR_ENC_Pos          (24U)
3488 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
3489 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
3490 
3491 /******************  Bit definition for LPTIM_CR register  ********************/
3492 #define LPTIM_CR_ENABLE_Pos         (0U)
3493 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
3494 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
3495 #define LPTIM_CR_SNGSTRT_Pos        (1U)
3496 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
3497 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
3498 #define LPTIM_CR_CNTSTRT_Pos        (2U)
3499 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
3500 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
3501 
3502 /******************  Bit definition for LPTIM_CMP register  *******************/
3503 #define LPTIM_CMP_CMP_Pos           (0U)
3504 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
3505 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
3506 
3507 /******************  Bit definition for LPTIM_ARR register  *******************/
3508 #define LPTIM_ARR_ARR_Pos           (0U)
3509 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
3510 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
3511 
3512 /******************  Bit definition for LPTIM_CNT register  *******************/
3513 #define LPTIM_CNT_CNT_Pos           (0U)
3514 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
3515 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
3516 
3517 /******************************************************************************/
3518 /*                                                                            */
3519 /*                            MIFARE   Firewall                               */
3520 /*                                                                            */
3521 /******************************************************************************/
3522 
3523 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
3524 #define FW_CSSA_ADD_Pos      (8U)
3525 #define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
3526 #define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */
3527 #define FW_CSL_LENG_Pos      (8U)
3528 #define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
3529 #define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */
3530 #define FW_NVDSSA_ADD_Pos    (8U)
3531 #define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
3532 #define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */
3533 #define FW_NVDSL_LENG_Pos    (8U)
3534 #define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
3535 #define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */
3536 #define FW_VDSSA_ADD_Pos     (6U)
3537 #define FW_VDSSA_ADD_Msk     (0x3FFUL << FW_VDSSA_ADD_Pos)                      /*!< 0x0000FFC0 */
3538 #define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */
3539 #define FW_VDSL_LENG_Pos     (6U)
3540 #define FW_VDSL_LENG_Msk     (0x3FFUL << FW_VDSL_LENG_Pos)                      /*!< 0x0000FFC0 */
3541 #define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */
3542 
3543 /**************************Bit definition for CR register *********************/
3544 #define FW_CR_FPA_Pos        (0U)
3545 #define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
3546 #define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/
3547 #define FW_CR_VDS_Pos        (1U)
3548 #define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
3549 #define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/
3550 #define FW_CR_VDE_Pos        (2U)
3551 #define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
3552 #define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/
3553 
3554 /******************************************************************************/
3555 /*                                                                            */
3556 /*                          Power Control (PWR)                               */
3557 /*                                                                            */
3558 /******************************************************************************/
3559 
3560 #define PWR_PVD_SUPPORT                     /*!< PVD feature available on all devices: Power Voltage Detection feature */
3561 
3562 /********************  Bit definition for PWR_CR register  ********************/
3563 #define PWR_CR_LPSDSR_Pos          (0U)
3564 #define PWR_CR_LPSDSR_Msk          (0x1UL << PWR_CR_LPSDSR_Pos)                 /*!< 0x00000001 */
3565 #define PWR_CR_LPSDSR              PWR_CR_LPSDSR_Msk                           /*!< Low-power deepsleep/sleep/low power run */
3566 #define PWR_CR_PDDS_Pos            (1U)
3567 #define PWR_CR_PDDS_Msk            (0x1UL << PWR_CR_PDDS_Pos)                   /*!< 0x00000002 */
3568 #define PWR_CR_PDDS                PWR_CR_PDDS_Msk                             /*!< Power Down Deepsleep */
3569 #define PWR_CR_CWUF_Pos            (2U)
3570 #define PWR_CR_CWUF_Msk            (0x1UL << PWR_CR_CWUF_Pos)                   /*!< 0x00000004 */
3571 #define PWR_CR_CWUF                PWR_CR_CWUF_Msk                             /*!< Clear Wakeup Flag */
3572 #define PWR_CR_CSBF_Pos            (3U)
3573 #define PWR_CR_CSBF_Msk            (0x1UL << PWR_CR_CSBF_Pos)                   /*!< 0x00000008 */
3574 #define PWR_CR_CSBF                PWR_CR_CSBF_Msk                             /*!< Clear Standby Flag */
3575 #define PWR_CR_PVDE_Pos            (4U)
3576 #define PWR_CR_PVDE_Msk            (0x1UL << PWR_CR_PVDE_Pos)                   /*!< 0x00000010 */
3577 #define PWR_CR_PVDE                PWR_CR_PVDE_Msk                             /*!< Power Voltage Detector Enable */
3578 
3579 #define PWR_CR_PLS_Pos             (5U)
3580 #define PWR_CR_PLS_Msk             (0x7UL << PWR_CR_PLS_Pos)                    /*!< 0x000000E0 */
3581 #define PWR_CR_PLS                 PWR_CR_PLS_Msk                              /*!< PLS[2:0] bits (PVD Level Selection) */
3582 #define PWR_CR_PLS_0               (0x1UL << PWR_CR_PLS_Pos)                    /*!< 0x00000020 */
3583 #define PWR_CR_PLS_1               (0x2UL << PWR_CR_PLS_Pos)                    /*!< 0x00000040 */
3584 #define PWR_CR_PLS_2               (0x4UL << PWR_CR_PLS_Pos)                    /*!< 0x00000080 */
3585 
3586 /*!< PVD level configuration */
3587 #define PWR_CR_PLS_LEV0            (0x00000000U)                               /*!< PVD level 0 */
3588 #define PWR_CR_PLS_LEV1            (0x00000020U)                               /*!< PVD level 1 */
3589 #define PWR_CR_PLS_LEV2            (0x00000040U)                               /*!< PVD level 2 */
3590 #define PWR_CR_PLS_LEV3            (0x00000060U)                               /*!< PVD level 3 */
3591 #define PWR_CR_PLS_LEV4            (0x00000080U)                               /*!< PVD level 4 */
3592 #define PWR_CR_PLS_LEV5            (0x000000A0U)                               /*!< PVD level 5 */
3593 #define PWR_CR_PLS_LEV6            (0x000000C0U)                               /*!< PVD level 6 */
3594 #define PWR_CR_PLS_LEV7            (0x000000E0U)                               /*!< PVD level 7 */
3595 
3596 #define PWR_CR_DBP_Pos             (8U)
3597 #define PWR_CR_DBP_Msk             (0x1UL << PWR_CR_DBP_Pos)                    /*!< 0x00000100 */
3598 #define PWR_CR_DBP                 PWR_CR_DBP_Msk                              /*!< Disable Backup Domain write protection */
3599 #define PWR_CR_ULP_Pos             (9U)
3600 #define PWR_CR_ULP_Msk             (0x1UL << PWR_CR_ULP_Pos)                    /*!< 0x00000200 */
3601 #define PWR_CR_ULP                 PWR_CR_ULP_Msk                              /*!< Ultra Low Power mode */
3602 #define PWR_CR_FWU_Pos             (10U)
3603 #define PWR_CR_FWU_Msk             (0x1UL << PWR_CR_FWU_Pos)                    /*!< 0x00000400 */
3604 #define PWR_CR_FWU                 PWR_CR_FWU_Msk                              /*!< Fast wakeup */
3605 
3606 #define PWR_CR_VOS_Pos             (11U)
3607 #define PWR_CR_VOS_Msk             (0x3UL << PWR_CR_VOS_Pos)                    /*!< 0x00001800 */
3608 #define PWR_CR_VOS                 PWR_CR_VOS_Msk                              /*!< VOS[1:0] bits (Voltage scaling range selection) */
3609 #define PWR_CR_VOS_0               (0x1UL << PWR_CR_VOS_Pos)                    /*!< 0x00000800 */
3610 #define PWR_CR_VOS_1               (0x2UL << PWR_CR_VOS_Pos)                    /*!< 0x00001000 */
3611 #define PWR_CR_DSEEKOFF_Pos        (13U)
3612 #define PWR_CR_DSEEKOFF_Msk        (0x1UL << PWR_CR_DSEEKOFF_Pos)               /*!< 0x00002000 */
3613 #define PWR_CR_DSEEKOFF            PWR_CR_DSEEKOFF_Msk                         /*!< Deep Sleep mode with EEPROM kept Off */
3614 #define PWR_CR_LPRUN_Pos           (14U)
3615 #define PWR_CR_LPRUN_Msk           (0x1UL << PWR_CR_LPRUN_Pos)                  /*!< 0x00004000 */
3616 #define PWR_CR_LPRUN               PWR_CR_LPRUN_Msk                            /*!< Low power run mode */
3617 
3618 /*******************  Bit definition for PWR_CSR register  ********************/
3619 #define PWR_CSR_WUF_Pos            (0U)
3620 #define PWR_CSR_WUF_Msk            (0x1UL << PWR_CSR_WUF_Pos)                   /*!< 0x00000001 */
3621 #define PWR_CSR_WUF                PWR_CSR_WUF_Msk                             /*!< Wakeup Flag */
3622 #define PWR_CSR_SBF_Pos            (1U)
3623 #define PWR_CSR_SBF_Msk            (0x1UL << PWR_CSR_SBF_Pos)                   /*!< 0x00000002 */
3624 #define PWR_CSR_SBF                PWR_CSR_SBF_Msk                             /*!< Standby Flag */
3625 #define PWR_CSR_PVDO_Pos           (2U)
3626 #define PWR_CSR_PVDO_Msk           (0x1UL << PWR_CSR_PVDO_Pos)                  /*!< 0x00000004 */
3627 #define PWR_CSR_PVDO               PWR_CSR_PVDO_Msk                            /*!< PVD Output */
3628 #define PWR_CSR_VREFINTRDYF_Pos    (3U)
3629 #define PWR_CSR_VREFINTRDYF_Msk    (0x1UL << PWR_CSR_VREFINTRDYF_Pos)           /*!< 0x00000008 */
3630 #define PWR_CSR_VREFINTRDYF        PWR_CSR_VREFINTRDYF_Msk                     /*!< Internal voltage reference (VREFINT) ready flag */
3631 #define PWR_CSR_VOSF_Pos           (4U)
3632 #define PWR_CSR_VOSF_Msk           (0x1UL << PWR_CSR_VOSF_Pos)                  /*!< 0x00000010 */
3633 #define PWR_CSR_VOSF               PWR_CSR_VOSF_Msk                            /*!< Voltage Scaling select flag */
3634 #define PWR_CSR_REGLPF_Pos         (5U)
3635 #define PWR_CSR_REGLPF_Msk         (0x1UL << PWR_CSR_REGLPF_Pos)                /*!< 0x00000020 */
3636 #define PWR_CSR_REGLPF             PWR_CSR_REGLPF_Msk                          /*!< Regulator LP flag */
3637 
3638 #define PWR_CSR_EWUP1_Pos          (8U)
3639 #define PWR_CSR_EWUP1_Msk          (0x1UL << PWR_CSR_EWUP1_Pos)                 /*!< 0x00000100 */
3640 #define PWR_CSR_EWUP1              PWR_CSR_EWUP1_Msk                           /*!< Enable WKUP pin 1 */
3641 #define PWR_CSR_EWUP2_Pos          (9U)
3642 #define PWR_CSR_EWUP2_Msk          (0x1UL << PWR_CSR_EWUP2_Pos)                 /*!< 0x00000200 */
3643 #define PWR_CSR_EWUP2              PWR_CSR_EWUP2_Msk                           /*!< Enable WKUP pin 2 */
3644 
3645 /******************************************************************************/
3646 /*                                                                            */
3647 /*                         Reset and Clock Control                            */
3648 /*                                                                            */
3649 /******************************************************************************/
3650 /*
3651 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
3652 */
3653 #define RCC_HSI48_SUPPORT           /*!< HSI48 feature support */
3654 #define RCC_HSECSS_SUPPORT          /*!< HSE CSS feature activation support */
3655 
3656 /********************  Bit definition for RCC_CR register  ********************/
3657 #define RCC_CR_HSION_Pos                 (0U)
3658 #define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)            /*!< 0x00000001 */
3659 #define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
3660 #define RCC_CR_HSIKERON_Pos              (1U)
3661 #define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)         /*!< 0x00000002 */
3662 #define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
3663 #define RCC_CR_HSIRDY_Pos                (2U)
3664 #define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)           /*!< 0x00000004 */
3665 #define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
3666 #define RCC_CR_HSIDIVEN_Pos              (3U)
3667 #define RCC_CR_HSIDIVEN_Msk              (0x1UL << RCC_CR_HSIDIVEN_Pos)         /*!< 0x00000008 */
3668 #define RCC_CR_HSIDIVEN                  RCC_CR_HSIDIVEN_Msk                   /*!< Internal High Speed clock divider enable */
3669 #define RCC_CR_HSIDIVF_Pos               (4U)
3670 #define RCC_CR_HSIDIVF_Msk               (0x1UL << RCC_CR_HSIDIVF_Pos)          /*!< 0x00000010 */
3671 #define RCC_CR_HSIDIVF                   RCC_CR_HSIDIVF_Msk                    /*!< Internal High Speed clock divider flag */
3672 #define RCC_CR_MSION_Pos                 (8U)
3673 #define RCC_CR_MSION_Msk                 (0x1UL << RCC_CR_MSION_Pos)            /*!< 0x00000100 */
3674 #define RCC_CR_MSION                     RCC_CR_MSION_Msk                      /*!< Internal Multi Speed clock enable */
3675 #define RCC_CR_MSIRDY_Pos                (9U)
3676 #define RCC_CR_MSIRDY_Msk                (0x1UL << RCC_CR_MSIRDY_Pos)           /*!< 0x00000200 */
3677 #define RCC_CR_MSIRDY                    RCC_CR_MSIRDY_Msk                     /*!< Internal Multi Speed clock ready flag */
3678 #define RCC_CR_HSEON_Pos                 (16U)
3679 #define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)            /*!< 0x00010000 */
3680 #define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
3681 #define RCC_CR_HSERDY_Pos                (17U)
3682 #define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)           /*!< 0x00020000 */
3683 #define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready flag */
3684 #define RCC_CR_HSEBYP_Pos                (18U)
3685 #define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)           /*!< 0x00040000 */
3686 #define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
3687 #define RCC_CR_CSSHSEON_Pos              (19U)
3688 #define RCC_CR_CSSHSEON_Msk              (0x1UL << RCC_CR_CSSHSEON_Pos)         /*!< 0x00080000 */
3689 #define RCC_CR_CSSHSEON                  RCC_CR_CSSHSEON_Msk                   /*!< HSE Clock Security System enable */
3690 #define RCC_CR_RTCPRE_Pos                (20U)
3691 #define RCC_CR_RTCPRE_Msk                (0x3UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00300000 */
3692 #define RCC_CR_RTCPRE                    RCC_CR_RTCPRE_Msk                     /*!< RTC prescaler [1:0] bits */
3693 #define RCC_CR_RTCPRE_0                  (0x1UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00100000 */
3694 #define RCC_CR_RTCPRE_1                  (0x2UL << RCC_CR_RTCPRE_Pos)           /*!< 0x00200000 */
3695 #define RCC_CR_PLLON_Pos                 (24U)
3696 #define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)            /*!< 0x01000000 */
3697 #define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< PLL enable */
3698 #define RCC_CR_PLLRDY_Pos                (25U)
3699 #define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)           /*!< 0x02000000 */
3700 #define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< PLL clock ready flag */
3701 
3702 /* Reference defines */
3703 #define RCC_CR_CSSON     RCC_CR_CSSHSEON
3704 
3705 /********************  Bit definition for RCC_ICSCR register  *****************/
3706 #define RCC_ICSCR_HSICAL_Pos             (0U)
3707 #define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)       /*!< 0x000000FF */
3708 #define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< Internal High Speed clock Calibration */
3709 #define RCC_ICSCR_HSITRIM_Pos            (8U)
3710 #define RCC_ICSCR_HSITRIM_Msk            (0x1FUL << RCC_ICSCR_HSITRIM_Pos)      /*!< 0x00001F00 */
3711 #define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< Internal High Speed clock trimming */
3712 
3713 #define RCC_ICSCR_MSIRANGE_Pos           (13U)
3714 #define RCC_ICSCR_MSIRANGE_Msk           (0x7UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000E000 */
3715 #define RCC_ICSCR_MSIRANGE               RCC_ICSCR_MSIRANGE_Msk                /*!< Internal Multi Speed clock Range */
3716 #define RCC_ICSCR_MSIRANGE_0             (0x0UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00000000 */
3717 #define RCC_ICSCR_MSIRANGE_1             (0x1UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00002000 */
3718 #define RCC_ICSCR_MSIRANGE_2             (0x2UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00004000 */
3719 #define RCC_ICSCR_MSIRANGE_3             (0x3UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00006000 */
3720 #define RCC_ICSCR_MSIRANGE_4             (0x4UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x00008000 */
3721 #define RCC_ICSCR_MSIRANGE_5             (0x5UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000A000 */
3722 #define RCC_ICSCR_MSIRANGE_6             (0x6UL << RCC_ICSCR_MSIRANGE_Pos)      /*!< 0x0000C000 */
3723 #define RCC_ICSCR_MSICAL_Pos             (16U)
3724 #define RCC_ICSCR_MSICAL_Msk             (0xFFUL << RCC_ICSCR_MSICAL_Pos)       /*!< 0x00FF0000 */
3725 #define RCC_ICSCR_MSICAL                 RCC_ICSCR_MSICAL_Msk                  /*!< Internal Multi Speed clock Calibration */
3726 #define RCC_ICSCR_MSITRIM_Pos            (24U)
3727 #define RCC_ICSCR_MSITRIM_Msk            (0xFFUL << RCC_ICSCR_MSITRIM_Pos)      /*!< 0xFF000000 */
3728 #define RCC_ICSCR_MSITRIM                RCC_ICSCR_MSITRIM_Msk                 /*!< Internal Multi Speed clock trimming */
3729 
3730 /********************  Bit definition for RCC_CRRCR register  *****************/
3731 #define RCC_CRRCR_HSI48ON_Pos            (0U)
3732 #define RCC_CRRCR_HSI48ON_Msk            (0x1UL << RCC_CRRCR_HSI48ON_Pos)       /*!< 0x00000001 */
3733 #define RCC_CRRCR_HSI48ON                RCC_CRRCR_HSI48ON_Msk                 /*!< HSI 48MHz clock enable */
3734 #define RCC_CRRCR_HSI48RDY_Pos           (1U)
3735 #define RCC_CRRCR_HSI48RDY_Msk           (0x1UL << RCC_CRRCR_HSI48RDY_Pos)      /*!< 0x00000002 */
3736 #define RCC_CRRCR_HSI48RDY               RCC_CRRCR_HSI48RDY_Msk                /*!< HSI 48MHz clock ready flag */
3737 #define RCC_CRRCR_HSI48CAL_Pos           (8U)
3738 #define RCC_CRRCR_HSI48CAL_Msk           (0xFFUL << RCC_CRRCR_HSI48CAL_Pos)     /*!< 0x0000FF00 */
3739 #define RCC_CRRCR_HSI48CAL               RCC_CRRCR_HSI48CAL_Msk                /*!< HSI 48MHz clock Calibration */
3740 
3741 /*******************  Bit definition for RCC_CFGR register  *******************/
3742 /*!< SW configuration */
3743 #define RCC_CFGR_SW_Pos                      (0U)
3744 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
3745 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
3746 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
3747 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
3748 
3749 #define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI selected as system clock */
3750 #define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI selected as system clock */
3751 #define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE selected as system clock */
3752 #define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selected as system clock */
3753 
3754 /*!< SWS configuration */
3755 #define RCC_CFGR_SWS_Pos                     (2U)
3756 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
3757 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
3758 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
3759 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
3760 
3761 #define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
3762 #define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI oscillator used as system clock */
3763 #define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
3764 #define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
3765 
3766 /*!< HPRE configuration */
3767 #define RCC_CFGR_HPRE_Pos                    (4U)
3768 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
3769 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
3770 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
3771 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
3772 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
3773 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
3774 
3775 #define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
3776 #define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
3777 #define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
3778 #define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
3779 #define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
3780 #define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
3781 #define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
3782 #define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
3783 #define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
3784 
3785 /*!< PPRE1 configuration */
3786 #define RCC_CFGR_PPRE1_Pos                   (8U)
3787 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
3788 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
3789 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
3790 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
3791 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
3792 
3793 #define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
3794 #define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
3795 #define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
3796 #define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
3797 #define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
3798 
3799 /*!< PPRE2 configuration */
3800 #define RCC_CFGR_PPRE2_Pos                   (11U)
3801 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
3802 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
3803 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
3804 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
3805 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
3806 
3807 #define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
3808 #define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
3809 #define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
3810 #define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
3811 #define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
3812 
3813 #define RCC_CFGR_STOPWUCK_Pos                (15U)
3814 #define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
3815 #define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from Stop Clock selection */
3816 
3817 /*!< PLL entry clock source*/
3818 #define RCC_CFGR_PLLSRC_Pos                  (16U)
3819 #define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
3820 #define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
3821 
3822 #define RCC_CFGR_PLLSRC_HSI                  (0x00000000U)                     /*!< HSI as PLL entry clock source */
3823 #define RCC_CFGR_PLLSRC_HSE                  (0x00010000U)                     /*!< HSE as PLL entry clock source */
3824 
3825 
3826 /*!< PLLMUL configuration */
3827 #define RCC_CFGR_PLLMUL_Pos                  (18U)
3828 #define RCC_CFGR_PLLMUL_Msk                  (0xFUL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x003C0000 */
3829 #define RCC_CFGR_PLLMUL                      RCC_CFGR_PLLMUL_Msk               /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
3830 #define RCC_CFGR_PLLMUL_0                    (0x1UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00040000 */
3831 #define RCC_CFGR_PLLMUL_1                    (0x2UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00080000 */
3832 #define RCC_CFGR_PLLMUL_2                    (0x4UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00100000 */
3833 #define RCC_CFGR_PLLMUL_3                    (0x8UL << RCC_CFGR_PLLMUL_Pos)     /*!< 0x00200000 */
3834 
3835 #define RCC_CFGR_PLLMUL3                     (0x00000000U)                     /*!< PLL input clock * 3 */
3836 #define RCC_CFGR_PLLMUL4                     (0x00040000U)                     /*!< PLL input clock * 4 */
3837 #define RCC_CFGR_PLLMUL6                     (0x00080000U)                     /*!< PLL input clock * 6 */
3838 #define RCC_CFGR_PLLMUL8                     (0x000C0000U)                     /*!< PLL input clock * 8 */
3839 #define RCC_CFGR_PLLMUL12                    (0x00100000U)                     /*!< PLL input clock * 12 */
3840 #define RCC_CFGR_PLLMUL16                    (0x00140000U)                     /*!< PLL input clock * 16 */
3841 #define RCC_CFGR_PLLMUL24                    (0x00180000U)                     /*!< PLL input clock * 24 */
3842 #define RCC_CFGR_PLLMUL32                    (0x001C0000U)                     /*!< PLL input clock * 32 */
3843 #define RCC_CFGR_PLLMUL48                    (0x00200000U)                     /*!< PLL input clock * 48 */
3844 
3845 /*!< PLLDIV configuration */
3846 #define RCC_CFGR_PLLDIV_Pos                  (22U)
3847 #define RCC_CFGR_PLLDIV_Msk                  (0x3UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00C00000 */
3848 #define RCC_CFGR_PLLDIV                      RCC_CFGR_PLLDIV_Msk               /*!< PLLDIV[1:0] bits (PLL Output Division) */
3849 #define RCC_CFGR_PLLDIV_0                    (0x1UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00400000 */
3850 #define RCC_CFGR_PLLDIV_1                    (0x2UL << RCC_CFGR_PLLDIV_Pos)     /*!< 0x00800000 */
3851 
3852 #define RCC_CFGR_PLLDIV2_Pos                 (22U)
3853 #define RCC_CFGR_PLLDIV2_Msk                 (0x1UL << RCC_CFGR_PLLDIV2_Pos)    /*!< 0x00400000 */
3854 #define RCC_CFGR_PLLDIV2                     RCC_CFGR_PLLDIV2_Msk              /*!< PLL clock output = CKVCO / 2 */
3855 #define RCC_CFGR_PLLDIV3_Pos                 (23U)
3856 #define RCC_CFGR_PLLDIV3_Msk                 (0x1UL << RCC_CFGR_PLLDIV3_Pos)    /*!< 0x00800000 */
3857 #define RCC_CFGR_PLLDIV3                     RCC_CFGR_PLLDIV3_Msk              /*!< PLL clock output = CKVCO / 3 */
3858 #define RCC_CFGR_PLLDIV4_Pos                 (22U)
3859 #define RCC_CFGR_PLLDIV4_Msk                 (0x3UL << RCC_CFGR_PLLDIV4_Pos)    /*!< 0x00C00000 */
3860 #define RCC_CFGR_PLLDIV4                     RCC_CFGR_PLLDIV4_Msk              /*!< PLL clock output = CKVCO / 4 */
3861 
3862 /*!< MCO configuration */
3863 #define RCC_CFGR_MCOSEL_Pos                  (24U)
3864 #define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
3865 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCO[3:0] bits (Microcontroller Clock Output) */
3866 #define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
3867 #define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
3868 #define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
3869 #define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
3870 
3871 #define RCC_CFGR_MCOSEL_NOCLOCK              (0x00000000U)                     /*!< No clock */
3872 #define RCC_CFGR_MCOSEL_SYSCLK_Pos           (24U)
3873 #define RCC_CFGR_MCOSEL_SYSCLK_Msk           (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
3874 #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCOSEL_SYSCLK_Msk        /*!< System clock selected as MCO source */
3875 #define RCC_CFGR_MCOSEL_HSI_Pos              (25U)
3876 #define RCC_CFGR_MCOSEL_HSI_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
3877 #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCOSEL_HSI_Msk           /*!< Internal 16 MHz RC oscillator clock selected */
3878 #define RCC_CFGR_MCOSEL_MSI_Pos              (24U)
3879 #define RCC_CFGR_MCOSEL_MSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
3880 #define RCC_CFGR_MCOSEL_MSI                  RCC_CFGR_MCOSEL_MSI_Msk           /*!< Internal Medium Speed RC oscillator clock selected */
3881 #define RCC_CFGR_MCOSEL_HSE_Pos              (26U)
3882 #define RCC_CFGR_MCOSEL_HSE_Msk              (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
3883 #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCOSEL_HSE_Msk           /*!< External 1-25 MHz oscillator clock selected */
3884 #define RCC_CFGR_MCOSEL_PLL_Pos              (24U)
3885 #define RCC_CFGR_MCOSEL_PLL_Msk              (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
3886 #define RCC_CFGR_MCOSEL_PLL                  RCC_CFGR_MCOSEL_PLL_Msk           /*!< PLL clock divided */
3887 #define RCC_CFGR_MCOSEL_LSI_Pos              (25U)
3888 #define RCC_CFGR_MCOSEL_LSI_Msk              (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
3889 #define RCC_CFGR_MCOSEL_LSI                  RCC_CFGR_MCOSEL_LSI_Msk           /*!< LSI selected */
3890 #define RCC_CFGR_MCOSEL_LSE_Pos              (24U)
3891 #define RCC_CFGR_MCOSEL_LSE_Msk              (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
3892 #define RCC_CFGR_MCOSEL_LSE                  RCC_CFGR_MCOSEL_LSE_Msk           /*!< LSE selected */
3893 #define RCC_CFGR_MCOSEL_HSI48_Pos            (27U)
3894 #define RCC_CFGR_MCOSEL_HSI48_Msk            (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
3895 #define RCC_CFGR_MCOSEL_HSI48                RCC_CFGR_MCOSEL_HSI48_Msk         /*!< HSI48 clock selected as MCO source */
3896 
3897 #define RCC_CFGR_MCOPRE_Pos                  (28U)
3898 #define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
3899 #define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
3900 #define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
3901 #define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
3902 #define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
3903 
3904 #define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
3905 #define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
3906 #define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
3907 #define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
3908 #define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
3909 
3910 /* Legacy defines */
3911 #define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK
3912 #define RCC_CFGR_MCO_SYSCLK    RCC_CFGR_MCOSEL_SYSCLK
3913 #define RCC_CFGR_MCO_HSI       RCC_CFGR_MCOSEL_HSI
3914 #define RCC_CFGR_MCO_MSI       RCC_CFGR_MCOSEL_MSI
3915 #define RCC_CFGR_MCO_HSE       RCC_CFGR_MCOSEL_HSE
3916 #define RCC_CFGR_MCO_PLL       RCC_CFGR_MCOSEL_PLL
3917 #define RCC_CFGR_MCO_LSI       RCC_CFGR_MCOSEL_LSI
3918 #define RCC_CFGR_MCO_LSE       RCC_CFGR_MCOSEL_LSE
3919 #ifdef RCC_CFGR_MCOSEL_HSI48
3920 #define RCC_CFGR_MCO_HSI48     RCC_CFGR_MCOSEL_HSI48
3921 #endif
3922 
3923 #define RCC_CFGR_MCO_PRE                    RCC_CFGR_MCOPRE          /*!< MCO prescaler */
3924 #define RCC_CFGR_MCO_PRE_1                  RCC_CFGR_MCOPRE_DIV1        /*!< MCO is divided by 1 */
3925 #define RCC_CFGR_MCO_PRE_2                  RCC_CFGR_MCOPRE_DIV2        /*!< MCO is divided by 1 */
3926 #define RCC_CFGR_MCO_PRE_4                  RCC_CFGR_MCOPRE_DIV4        /*!< MCO is divided by 1 */
3927 #define RCC_CFGR_MCO_PRE_8                  RCC_CFGR_MCOPRE_DIV8        /*!< MCO is divided by 1 */
3928 #define RCC_CFGR_MCO_PRE_16                 RCC_CFGR_MCOPRE_DIV16       /*!< MCO is divided by 1 */
3929 
3930 /*!<******************  Bit definition for RCC_CIER register  ********************/
3931 #define RCC_CIER_LSIRDYIE_Pos            (0U)
3932 #define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)       /*!< 0x00000001 */
3933 #define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk                 /*!< LSI Ready Interrupt Enable */
3934 #define RCC_CIER_LSERDYIE_Pos            (1U)
3935 #define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)       /*!< 0x00000002 */
3936 #define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk                 /*!< LSE Ready Interrupt Enable */
3937 #define RCC_CIER_HSIRDYIE_Pos            (2U)
3938 #define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)       /*!< 0x00000004 */
3939 #define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk                 /*!< HSI Ready Interrupt Enable */
3940 #define RCC_CIER_HSERDYIE_Pos            (3U)
3941 #define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)       /*!< 0x00000008 */
3942 #define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk                 /*!< HSE Ready Interrupt Enable */
3943 #define RCC_CIER_PLLRDYIE_Pos            (4U)
3944 #define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)       /*!< 0x00000010 */
3945 #define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk                 /*!< PLL Ready Interrupt Enable */
3946 #define RCC_CIER_MSIRDYIE_Pos            (5U)
3947 #define RCC_CIER_MSIRDYIE_Msk            (0x1UL << RCC_CIER_MSIRDYIE_Pos)       /*!< 0x00000020 */
3948 #define RCC_CIER_MSIRDYIE                RCC_CIER_MSIRDYIE_Msk                 /*!< MSI Ready Interrupt Enable */
3949 #define RCC_CIER_HSI48RDYIE_Pos          (6U)
3950 #define RCC_CIER_HSI48RDYIE_Msk          (0x1UL << RCC_CIER_HSI48RDYIE_Pos)     /*!< 0x00000040 */
3951 #define RCC_CIER_HSI48RDYIE              RCC_CIER_HSI48RDYIE_Msk               /*!< HSI48 Ready Interrupt Enable */
3952 #define RCC_CIER_CSSLSE_Pos              (7U)
3953 #define RCC_CIER_CSSLSE_Msk              (0x1UL << RCC_CIER_CSSLSE_Pos)         /*!< 0x00000080 */
3954 #define RCC_CIER_CSSLSE                  RCC_CIER_CSSLSE_Msk                   /*!< LSE CSS Interrupt Enable */
3955 
3956 /* Reference defines */
3957 #define RCC_CIER_LSECSSIE                    RCC_CIER_CSSLSE
3958 
3959 /*!<******************  Bit definition for RCC_CIFR register  ********************/
3960 #define RCC_CIFR_LSIRDYF_Pos             (0U)
3961 #define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)        /*!< 0x00000001 */
3962 #define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk                  /*!< LSI Ready Interrupt flag */
3963 #define RCC_CIFR_LSERDYF_Pos             (1U)
3964 #define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)        /*!< 0x00000002 */
3965 #define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk                  /*!< LSE Ready Interrupt flag */
3966 #define RCC_CIFR_HSIRDYF_Pos             (2U)
3967 #define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)        /*!< 0x00000004 */
3968 #define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk                  /*!< HSI Ready Interrupt flag */
3969 #define RCC_CIFR_HSERDYF_Pos             (3U)
3970 #define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)        /*!< 0x00000008 */
3971 #define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk                  /*!< HSE Ready Interrupt flag */
3972 #define RCC_CIFR_PLLRDYF_Pos             (4U)
3973 #define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)        /*!< 0x00000010 */
3974 #define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk                  /*!< PLL Ready Interrupt flag */
3975 #define RCC_CIFR_MSIRDYF_Pos             (5U)
3976 #define RCC_CIFR_MSIRDYF_Msk             (0x1UL << RCC_CIFR_MSIRDYF_Pos)        /*!< 0x00000020 */
3977 #define RCC_CIFR_MSIRDYF                 RCC_CIFR_MSIRDYF_Msk                  /*!< MSI Ready Interrupt flag */
3978 #define RCC_CIFR_HSI48RDYF_Pos           (6U)
3979 #define RCC_CIFR_HSI48RDYF_Msk           (0x1UL << RCC_CIFR_HSI48RDYF_Pos)      /*!< 0x00000040 */
3980 #define RCC_CIFR_HSI48RDYF               RCC_CIFR_HSI48RDYF_Msk                /*!< HSI48 Ready Interrupt flag */
3981 #define RCC_CIFR_CSSLSEF_Pos             (7U)
3982 #define RCC_CIFR_CSSLSEF_Msk             (0x1UL << RCC_CIFR_CSSLSEF_Pos)        /*!< 0x00000080 */
3983 #define RCC_CIFR_CSSLSEF                 RCC_CIFR_CSSLSEF_Msk                  /*!< LSE Clock Security System Interrupt flag */
3984 #define RCC_CIFR_CSSHSEF_Pos             (8U)
3985 #define RCC_CIFR_CSSHSEF_Msk             (0x1UL << RCC_CIFR_CSSHSEF_Pos)        /*!< 0x00000100 */
3986 #define RCC_CIFR_CSSHSEF                 RCC_CIFR_CSSHSEF_Msk                  /*!< HSE Clock Security System Interrupt flag */
3987 
3988 /* Reference defines */
3989 #define RCC_CIFR_LSECSSF                    RCC_CIFR_CSSLSEF
3990 #define RCC_CIFR_CSSF                       RCC_CIFR_CSSHSEF
3991 
3992 /*!<******************  Bit definition for RCC_CICR register  ********************/
3993 #define RCC_CICR_LSIRDYC_Pos             (0U)
3994 #define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)        /*!< 0x00000001 */
3995 #define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk                  /*!< LSI Ready Interrupt Clear */
3996 #define RCC_CICR_LSERDYC_Pos             (1U)
3997 #define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)        /*!< 0x00000002 */
3998 #define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk                  /*!< LSE Ready Interrupt Clear */
3999 #define RCC_CICR_HSIRDYC_Pos             (2U)
4000 #define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)        /*!< 0x00000004 */
4001 #define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk                  /*!< HSI Ready Interrupt Clear */
4002 #define RCC_CICR_HSERDYC_Pos             (3U)
4003 #define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)        /*!< 0x00000008 */
4004 #define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk                  /*!< HSE Ready Interrupt Clear */
4005 #define RCC_CICR_PLLRDYC_Pos             (4U)
4006 #define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)        /*!< 0x00000010 */
4007 #define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk                  /*!< PLL Ready Interrupt Clear */
4008 #define RCC_CICR_MSIRDYC_Pos             (5U)
4009 #define RCC_CICR_MSIRDYC_Msk             (0x1UL << RCC_CICR_MSIRDYC_Pos)        /*!< 0x00000020 */
4010 #define RCC_CICR_MSIRDYC                 RCC_CICR_MSIRDYC_Msk                  /*!< MSI Ready Interrupt Clear */
4011 #define RCC_CICR_HSI48RDYC_Pos           (6U)
4012 #define RCC_CICR_HSI48RDYC_Msk           (0x1UL << RCC_CICR_HSI48RDYC_Pos)      /*!< 0x00000040 */
4013 #define RCC_CICR_HSI48RDYC               RCC_CICR_HSI48RDYC_Msk                /*!< HSI48 Ready Interrupt Clear */
4014 #define RCC_CICR_CSSLSEC_Pos             (7U)
4015 #define RCC_CICR_CSSLSEC_Msk             (0x1UL << RCC_CICR_CSSLSEC_Pos)        /*!< 0x00000080 */
4016 #define RCC_CICR_CSSLSEC                 RCC_CICR_CSSLSEC_Msk                  /*!< LSE Clock Security System Interrupt Clear */
4017 #define RCC_CICR_CSSHSEC_Pos             (8U)
4018 #define RCC_CICR_CSSHSEC_Msk             (0x1UL << RCC_CICR_CSSHSEC_Pos)        /*!< 0x00000100 */
4019 #define RCC_CICR_CSSHSEC                 RCC_CICR_CSSHSEC_Msk                  /*!< HSE Clock Security System Interrupt Clear */
4020 
4021 /* Reference defines */
4022 #define RCC_CICR_LSECSSC                    RCC_CICR_CSSLSEC
4023 #define RCC_CICR_CSSC                       RCC_CICR_CSSHSEC
4024 /*****************  Bit definition for RCC_IOPRSTR register  ******************/
4025 #define RCC_IOPRSTR_IOPARST_Pos          (0U)
4026 #define RCC_IOPRSTR_IOPARST_Msk          (0x1UL << RCC_IOPRSTR_IOPARST_Pos)     /*!< 0x00000001 */
4027 #define RCC_IOPRSTR_IOPARST              RCC_IOPRSTR_IOPARST_Msk               /*!< GPIO port A reset */
4028 #define RCC_IOPRSTR_IOPBRST_Pos          (1U)
4029 #define RCC_IOPRSTR_IOPBRST_Msk          (0x1UL << RCC_IOPRSTR_IOPBRST_Pos)     /*!< 0x00000002 */
4030 #define RCC_IOPRSTR_IOPBRST              RCC_IOPRSTR_IOPBRST_Msk               /*!< GPIO port B reset */
4031 #define RCC_IOPRSTR_IOPCRST_Pos          (2U)
4032 #define RCC_IOPRSTR_IOPCRST_Msk          (0x1UL << RCC_IOPRSTR_IOPCRST_Pos)     /*!< 0x00000004 */
4033 #define RCC_IOPRSTR_IOPCRST              RCC_IOPRSTR_IOPCRST_Msk               /*!< GPIO port C reset */
4034 #define RCC_IOPRSTR_IOPDRST_Pos          (3U)
4035 #define RCC_IOPRSTR_IOPDRST_Msk          (0x1UL << RCC_IOPRSTR_IOPDRST_Pos)     /*!< 0x00000008 */
4036 #define RCC_IOPRSTR_IOPDRST              RCC_IOPRSTR_IOPDRST_Msk               /*!< GPIO port D reset */
4037 #define RCC_IOPRSTR_IOPHRST_Pos          (7U)
4038 #define RCC_IOPRSTR_IOPHRST_Msk          (0x1UL << RCC_IOPRSTR_IOPHRST_Pos)     /*!< 0x00000080 */
4039 #define RCC_IOPRSTR_IOPHRST              RCC_IOPRSTR_IOPHRST_Msk               /*!< GPIO port H reset */
4040 
4041 /* Reference defines */
4042 #define RCC_IOPRSTR_GPIOARST                RCC_IOPRSTR_IOPARST        /*!< GPIO port A reset */
4043 #define RCC_IOPRSTR_GPIOBRST                RCC_IOPRSTR_IOPBRST        /*!< GPIO port B reset */
4044 #define RCC_IOPRSTR_GPIOCRST                RCC_IOPRSTR_IOPCRST        /*!< GPIO port C reset */
4045 #define RCC_IOPRSTR_GPIODRST                RCC_IOPRSTR_IOPDRST        /*!< GPIO port D reset */
4046 #define RCC_IOPRSTR_GPIOHRST                RCC_IOPRSTR_IOPHRST        /*!< GPIO port H reset */
4047 
4048 
4049 /******************  Bit definition for RCC_AHBRST register  ******************/
4050 #define RCC_AHBRSTR_DMARST_Pos           (0U)
4051 #define RCC_AHBRSTR_DMARST_Msk           (0x1UL << RCC_AHBRSTR_DMARST_Pos)      /*!< 0x00000001 */
4052 #define RCC_AHBRSTR_DMARST               RCC_AHBRSTR_DMARST_Msk                /*!< DMA1 reset */
4053 #define RCC_AHBRSTR_MIFRST_Pos           (8U)
4054 #define RCC_AHBRSTR_MIFRST_Msk           (0x1UL << RCC_AHBRSTR_MIFRST_Pos)      /*!< 0x00000100 */
4055 #define RCC_AHBRSTR_MIFRST               RCC_AHBRSTR_MIFRST_Msk                /*!< Memory interface reset */
4056 #define RCC_AHBRSTR_CRCRST_Pos           (12U)
4057 #define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)      /*!< 0x00001000 */
4058 #define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk                /*!< CRC reset */
4059 #define RCC_AHBRSTR_TSCRST_Pos           (16U)
4060 #define RCC_AHBRSTR_TSCRST_Msk           (0x1UL << RCC_AHBRSTR_TSCRST_Pos)      /*!< 0x00010000 */
4061 #define RCC_AHBRSTR_TSCRST               RCC_AHBRSTR_TSCRST_Msk                /*!< TSC reset */
4062 #define RCC_AHBRSTR_RNGRST_Pos           (20U)
4063 #define RCC_AHBRSTR_RNGRST_Msk           (0x1UL << RCC_AHBRSTR_RNGRST_Pos)      /*!< 0x00100000 */
4064 #define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk                /*!< RNG reset */
4065 #define RCC_AHBRSTR_CRYPRST_Pos          (24U)
4066 #define RCC_AHBRSTR_CRYPRST_Msk          (0x1UL << RCC_AHBRSTR_CRYPRST_Pos)     /*!< 0x01000000 */
4067 #define RCC_AHBRSTR_CRYPRST              RCC_AHBRSTR_CRYPRST_Msk               /*!< Crypto reset */
4068 
4069 /* Reference defines */
4070 #define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMARST            /*!< DMA1 reset */
4071 
4072 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
4073 #define RCC_APB2RSTR_SYSCFGRST_Pos       (0U)
4074 #define RCC_APB2RSTR_SYSCFGRST_Msk       (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)  /*!< 0x00000001 */
4075 #define RCC_APB2RSTR_SYSCFGRST           RCC_APB2RSTR_SYSCFGRST_Msk            /*!< SYSCFG reset */
4076 #define RCC_APB2RSTR_TIM21RST_Pos        (2U)
4077 #define RCC_APB2RSTR_TIM21RST_Msk        (0x1UL << RCC_APB2RSTR_TIM21RST_Pos)   /*!< 0x00000004 */
4078 #define RCC_APB2RSTR_TIM21RST            RCC_APB2RSTR_TIM21RST_Msk             /*!< TIM21 reset */
4079 #define RCC_APB2RSTR_TIM22RST_Pos        (5U)
4080 #define RCC_APB2RSTR_TIM22RST_Msk        (0x1UL << RCC_APB2RSTR_TIM22RST_Pos)   /*!< 0x00000020 */
4081 #define RCC_APB2RSTR_TIM22RST            RCC_APB2RSTR_TIM22RST_Msk             /*!< TIM22 reset */
4082 #define RCC_APB2RSTR_ADCRST_Pos          (9U)
4083 #define RCC_APB2RSTR_ADCRST_Msk          (0x1UL << RCC_APB2RSTR_ADCRST_Pos)     /*!< 0x00000200 */
4084 #define RCC_APB2RSTR_ADCRST              RCC_APB2RSTR_ADCRST_Msk               /*!< ADC1 reset */
4085 #define RCC_APB2RSTR_SPI1RST_Pos         (12U)
4086 #define RCC_APB2RSTR_SPI1RST_Msk         (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)    /*!< 0x00001000 */
4087 #define RCC_APB2RSTR_SPI1RST             RCC_APB2RSTR_SPI1RST_Msk              /*!< SPI1 reset */
4088 #define RCC_APB2RSTR_USART1RST_Pos       (14U)
4089 #define RCC_APB2RSTR_USART1RST_Msk       (0x1UL << RCC_APB2RSTR_USART1RST_Pos)  /*!< 0x00004000 */
4090 #define RCC_APB2RSTR_USART1RST           RCC_APB2RSTR_USART1RST_Msk            /*!< USART1 reset */
4091 #define RCC_APB2RSTR_DBGRST_Pos          (22U)
4092 #define RCC_APB2RSTR_DBGRST_Msk          (0x1UL << RCC_APB2RSTR_DBGRST_Pos)     /*!< 0x00400000 */
4093 #define RCC_APB2RSTR_DBGRST              RCC_APB2RSTR_DBGRST_Msk               /*!< DBGMCU reset */
4094 
4095 /* Reference defines */
4096 #define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADCRST           /*!< ADC1 reset */
4097 #define RCC_APB2RSTR_DBGMCURST              RCC_APB2RSTR_DBGRST           /*!< DBGMCU reset */
4098 
4099 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
4100 #define RCC_APB1RSTR_TIM2RST_Pos         (0U)
4101 #define RCC_APB1RSTR_TIM2RST_Msk         (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)    /*!< 0x00000001 */
4102 #define RCC_APB1RSTR_TIM2RST             RCC_APB1RSTR_TIM2RST_Msk              /*!< Timer 2 reset */
4103 #define RCC_APB1RSTR_TIM6RST_Pos         (4U)
4104 #define RCC_APB1RSTR_TIM6RST_Msk         (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)    /*!< 0x00000010 */
4105 #define RCC_APB1RSTR_TIM6RST             RCC_APB1RSTR_TIM6RST_Msk              /*!< Timer 6 reset */
4106 #define RCC_APB1RSTR_WWDGRST_Pos         (11U)
4107 #define RCC_APB1RSTR_WWDGRST_Msk         (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)    /*!< 0x00000800 */
4108 #define RCC_APB1RSTR_WWDGRST             RCC_APB1RSTR_WWDGRST_Msk              /*!< Window Watchdog reset */
4109 #define RCC_APB1RSTR_SPI2RST_Pos         (14U)
4110 #define RCC_APB1RSTR_SPI2RST_Msk         (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)    /*!< 0x00004000 */
4111 #define RCC_APB1RSTR_SPI2RST             RCC_APB1RSTR_SPI2RST_Msk              /*!< SPI2 reset */
4112 #define RCC_APB1RSTR_USART2RST_Pos       (17U)
4113 #define RCC_APB1RSTR_USART2RST_Msk       (0x1UL << RCC_APB1RSTR_USART2RST_Pos)  /*!< 0x00020000 */
4114 #define RCC_APB1RSTR_USART2RST           RCC_APB1RSTR_USART2RST_Msk            /*!< USART 2 reset */
4115 #define RCC_APB1RSTR_LPUART1RST_Pos      (18U)
4116 #define RCC_APB1RSTR_LPUART1RST_Msk      (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
4117 #define RCC_APB1RSTR_LPUART1RST          RCC_APB1RSTR_LPUART1RST_Msk           /*!< LPUART1 reset */
4118 #define RCC_APB1RSTR_I2C1RST_Pos         (21U)
4119 #define RCC_APB1RSTR_I2C1RST_Msk         (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)    /*!< 0x00200000 */
4120 #define RCC_APB1RSTR_I2C1RST             RCC_APB1RSTR_I2C1RST_Msk              /*!< I2C 1 reset */
4121 #define RCC_APB1RSTR_I2C2RST_Pos         (22U)
4122 #define RCC_APB1RSTR_I2C2RST_Msk         (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)    /*!< 0x00400000 */
4123 #define RCC_APB1RSTR_I2C2RST             RCC_APB1RSTR_I2C2RST_Msk              /*!< I2C 2 reset */
4124 #define RCC_APB1RSTR_USBRST_Pos          (23U)
4125 #define RCC_APB1RSTR_USBRST_Msk          (0x1UL << RCC_APB1RSTR_USBRST_Pos)     /*!< 0x00800000 */
4126 #define RCC_APB1RSTR_USBRST              RCC_APB1RSTR_USBRST_Msk               /*!< USB reset */
4127 #define RCC_APB1RSTR_CRSRST_Pos          (27U)
4128 #define RCC_APB1RSTR_CRSRST_Msk          (0x1UL << RCC_APB1RSTR_CRSRST_Pos)     /*!< 0x08000000 */
4129 #define RCC_APB1RSTR_CRSRST              RCC_APB1RSTR_CRSRST_Msk               /*!< CRS reset */
4130 #define RCC_APB1RSTR_PWRRST_Pos          (28U)
4131 #define RCC_APB1RSTR_PWRRST_Msk          (0x1UL << RCC_APB1RSTR_PWRRST_Pos)     /*!< 0x10000000 */
4132 #define RCC_APB1RSTR_PWRRST              RCC_APB1RSTR_PWRRST_Msk               /*!< PWR reset */
4133 #define RCC_APB1RSTR_DACRST_Pos          (29U)
4134 #define RCC_APB1RSTR_DACRST_Msk          (0x1UL << RCC_APB1RSTR_DACRST_Pos)     /*!< 0x20000000 */
4135 #define RCC_APB1RSTR_DACRST              RCC_APB1RSTR_DACRST_Msk               /*!< DAC reset */
4136 #define RCC_APB1RSTR_LPTIM1RST_Pos       (31U)
4137 #define RCC_APB1RSTR_LPTIM1RST_Msk       (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)  /*!< 0x80000000 */
4138 #define RCC_APB1RSTR_LPTIM1RST           RCC_APB1RSTR_LPTIM1RST_Msk            /*!< LPTIM1 reset */
4139 
4140 /*****************  Bit definition for RCC_IOPENR register  ******************/
4141 #define RCC_IOPENR_IOPAEN_Pos            (0U)
4142 #define RCC_IOPENR_IOPAEN_Msk            (0x1UL << RCC_IOPENR_IOPAEN_Pos)       /*!< 0x00000001 */
4143 #define RCC_IOPENR_IOPAEN                RCC_IOPENR_IOPAEN_Msk                 /*!< GPIO port A clock enable */
4144 #define RCC_IOPENR_IOPBEN_Pos            (1U)
4145 #define RCC_IOPENR_IOPBEN_Msk            (0x1UL << RCC_IOPENR_IOPBEN_Pos)       /*!< 0x00000002 */
4146 #define RCC_IOPENR_IOPBEN                RCC_IOPENR_IOPBEN_Msk                 /*!< GPIO port B clock enable */
4147 #define RCC_IOPENR_IOPCEN_Pos            (2U)
4148 #define RCC_IOPENR_IOPCEN_Msk            (0x1UL << RCC_IOPENR_IOPCEN_Pos)       /*!< 0x00000004 */
4149 #define RCC_IOPENR_IOPCEN                RCC_IOPENR_IOPCEN_Msk                 /*!< GPIO port C clock enable */
4150 #define RCC_IOPENR_IOPDEN_Pos            (3U)
4151 #define RCC_IOPENR_IOPDEN_Msk            (0x1UL << RCC_IOPENR_IOPDEN_Pos)       /*!< 0x00000008 */
4152 #define RCC_IOPENR_IOPDEN                RCC_IOPENR_IOPDEN_Msk                 /*!< GPIO port D clock enable */
4153 #define RCC_IOPENR_IOPHEN_Pos            (7U)
4154 #define RCC_IOPENR_IOPHEN_Msk            (0x1UL << RCC_IOPENR_IOPHEN_Pos)       /*!< 0x00000080 */
4155 #define RCC_IOPENR_IOPHEN                RCC_IOPENR_IOPHEN_Msk                 /*!< GPIO port H clock enable */
4156 
4157 /* Reference defines */
4158 #define RCC_IOPENR_GPIOAEN                  RCC_IOPENR_IOPAEN        /*!< GPIO port A clock enable */
4159 #define RCC_IOPENR_GPIOBEN                  RCC_IOPENR_IOPBEN        /*!< GPIO port B clock enable */
4160 #define RCC_IOPENR_GPIOCEN                  RCC_IOPENR_IOPCEN        /*!< GPIO port C clock enable */
4161 #define RCC_IOPENR_GPIODEN                  RCC_IOPENR_IOPDEN        /*!< GPIO port D clock enable */
4162 #define RCC_IOPENR_GPIOHEN                  RCC_IOPENR_IOPHEN        /*!< GPIO port H clock enable */
4163 
4164 /*****************  Bit definition for RCC_AHBENR register  ******************/
4165 #define RCC_AHBENR_DMAEN_Pos             (0U)
4166 #define RCC_AHBENR_DMAEN_Msk             (0x1UL << RCC_AHBENR_DMAEN_Pos)        /*!< 0x00000001 */
4167 #define RCC_AHBENR_DMAEN                 RCC_AHBENR_DMAEN_Msk                  /*!< DMA1 clock enable */
4168 #define RCC_AHBENR_MIFEN_Pos             (8U)
4169 #define RCC_AHBENR_MIFEN_Msk             (0x1UL << RCC_AHBENR_MIFEN_Pos)        /*!< 0x00000100 */
4170 #define RCC_AHBENR_MIFEN                 RCC_AHBENR_MIFEN_Msk                  /*!< NVM interface clock enable bit */
4171 #define RCC_AHBENR_CRCEN_Pos             (12U)
4172 #define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
4173 #define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk                  /*!< CRC clock enable */
4174 #define RCC_AHBENR_TSCEN_Pos             (16U)
4175 #define RCC_AHBENR_TSCEN_Msk             (0x1UL << RCC_AHBENR_TSCEN_Pos)        /*!< 0x00010000 */
4176 #define RCC_AHBENR_TSCEN                 RCC_AHBENR_TSCEN_Msk                  /*!< TSC clock enable */
4177 #define RCC_AHBENR_RNGEN_Pos             (20U)
4178 #define RCC_AHBENR_RNGEN_Msk             (0x1UL << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00100000 */
4179 #define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk                  /*!< RNG clock enable */
4180 #define RCC_AHBENR_CRYPEN_Pos            (24U)
4181 #define RCC_AHBENR_CRYPEN_Msk            (0x1UL << RCC_AHBENR_CRYPEN_Pos)       /*!< 0x01000000 */
4182 #define RCC_AHBENR_CRYPEN                RCC_AHBENR_CRYPEN_Msk                 /*!< Crypto clock enable*/
4183 
4184 /* Reference defines */
4185 #define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMAEN              /*!< DMA1 clock enable */
4186 
4187 /*****************  Bit definition for RCC_APB2ENR register  ******************/
4188 #define RCC_APB2ENR_SYSCFGEN_Pos         (0U)
4189 #define RCC_APB2ENR_SYSCFGEN_Msk         (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)    /*!< 0x00000001 */
4190 #define RCC_APB2ENR_SYSCFGEN             RCC_APB2ENR_SYSCFGEN_Msk              /*!< SYSCFG clock enable */
4191 #define RCC_APB2ENR_TIM21EN_Pos          (2U)
4192 #define RCC_APB2ENR_TIM21EN_Msk          (0x1UL << RCC_APB2ENR_TIM21EN_Pos)     /*!< 0x00000004 */
4193 #define RCC_APB2ENR_TIM21EN              RCC_APB2ENR_TIM21EN_Msk               /*!< TIM21 clock enable */
4194 #define RCC_APB2ENR_TIM22EN_Pos          (5U)
4195 #define RCC_APB2ENR_TIM22EN_Msk          (0x1UL << RCC_APB2ENR_TIM22EN_Pos)     /*!< 0x00000020 */
4196 #define RCC_APB2ENR_TIM22EN              RCC_APB2ENR_TIM22EN_Msk               /*!< TIM22 clock enable */
4197 #define RCC_APB2ENR_FWEN_Pos             (7U)
4198 #define RCC_APB2ENR_FWEN_Msk             (0x1UL << RCC_APB2ENR_FWEN_Pos)        /*!< 0x00000080 */
4199 #define RCC_APB2ENR_FWEN                 RCC_APB2ENR_FWEN_Msk                  /*!< MiFare Firewall clock enable */
4200 #define RCC_APB2ENR_ADCEN_Pos            (9U)
4201 #define RCC_APB2ENR_ADCEN_Msk            (0x1UL << RCC_APB2ENR_ADCEN_Pos)       /*!< 0x00000200 */
4202 #define RCC_APB2ENR_ADCEN                RCC_APB2ENR_ADCEN_Msk                 /*!< ADC1 clock enable */
4203 #define RCC_APB2ENR_SPI1EN_Pos           (12U)
4204 #define RCC_APB2ENR_SPI1EN_Msk           (0x1UL << RCC_APB2ENR_SPI1EN_Pos)      /*!< 0x00001000 */
4205 #define RCC_APB2ENR_SPI1EN               RCC_APB2ENR_SPI1EN_Msk                /*!< SPI1 clock enable */
4206 #define RCC_APB2ENR_USART1EN_Pos         (14U)
4207 #define RCC_APB2ENR_USART1EN_Msk         (0x1UL << RCC_APB2ENR_USART1EN_Pos)    /*!< 0x00004000 */
4208 #define RCC_APB2ENR_USART1EN             RCC_APB2ENR_USART1EN_Msk              /*!< USART1 clock enable */
4209 #define RCC_APB2ENR_DBGEN_Pos            (22U)
4210 #define RCC_APB2ENR_DBGEN_Msk            (0x1UL << RCC_APB2ENR_DBGEN_Pos)       /*!< 0x00400000 */
4211 #define RCC_APB2ENR_DBGEN                RCC_APB2ENR_DBGEN_Msk                 /*!< DBGMCU clock enable */
4212 
4213 /* Reference defines */
4214 
4215 #define RCC_APB2ENR_MIFIEN                  RCC_APB2ENR_FWEN              /*!< MiFare Firewall clock enable */
4216 #define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADCEN             /*!< ADC1 clock enable */
4217 #define RCC_APB2ENR_DBGMCUEN                RCC_APB2ENR_DBGEN             /*!< DBGMCU clock enable */
4218 
4219 /*****************  Bit definition for RCC_APB1ENR register  ******************/
4220 #define RCC_APB1ENR_TIM2EN_Pos           (0U)
4221 #define RCC_APB1ENR_TIM2EN_Msk           (0x1UL << RCC_APB1ENR_TIM2EN_Pos)      /*!< 0x00000001 */
4222 #define RCC_APB1ENR_TIM2EN               RCC_APB1ENR_TIM2EN_Msk                /*!< Timer 2 clock enable */
4223 #define RCC_APB1ENR_TIM6EN_Pos           (4U)
4224 #define RCC_APB1ENR_TIM6EN_Msk           (0x1UL << RCC_APB1ENR_TIM6EN_Pos)      /*!< 0x00000010 */
4225 #define RCC_APB1ENR_TIM6EN               RCC_APB1ENR_TIM6EN_Msk                /*!< Timer 6 clock enable */
4226 #define RCC_APB1ENR_WWDGEN_Pos           (11U)
4227 #define RCC_APB1ENR_WWDGEN_Msk           (0x1UL << RCC_APB1ENR_WWDGEN_Pos)      /*!< 0x00000800 */
4228 #define RCC_APB1ENR_WWDGEN               RCC_APB1ENR_WWDGEN_Msk                /*!< Window Watchdog clock enable */
4229 #define RCC_APB1ENR_SPI2EN_Pos           (14U)
4230 #define RCC_APB1ENR_SPI2EN_Msk           (0x1UL << RCC_APB1ENR_SPI2EN_Pos)      /*!< 0x00004000 */
4231 #define RCC_APB1ENR_SPI2EN               RCC_APB1ENR_SPI2EN_Msk                /*!< SPI2 clock enable */
4232 #define RCC_APB1ENR_USART2EN_Pos         (17U)
4233 #define RCC_APB1ENR_USART2EN_Msk         (0x1UL << RCC_APB1ENR_USART2EN_Pos)    /*!< 0x00020000 */
4234 #define RCC_APB1ENR_USART2EN             RCC_APB1ENR_USART2EN_Msk              /*!< USART2 clock enable */
4235 #define RCC_APB1ENR_LPUART1EN_Pos        (18U)
4236 #define RCC_APB1ENR_LPUART1EN_Msk        (0x1UL << RCC_APB1ENR_LPUART1EN_Pos)   /*!< 0x00040000 */
4237 #define RCC_APB1ENR_LPUART1EN            RCC_APB1ENR_LPUART1EN_Msk             /*!< LPUART1 clock enable */
4238 #define RCC_APB1ENR_I2C1EN_Pos           (21U)
4239 #define RCC_APB1ENR_I2C1EN_Msk           (0x1UL << RCC_APB1ENR_I2C1EN_Pos)      /*!< 0x00200000 */
4240 #define RCC_APB1ENR_I2C1EN               RCC_APB1ENR_I2C1EN_Msk                /*!< I2C1 clock enable */
4241 #define RCC_APB1ENR_I2C2EN_Pos           (22U)
4242 #define RCC_APB1ENR_I2C2EN_Msk           (0x1UL << RCC_APB1ENR_I2C2EN_Pos)      /*!< 0x00400000 */
4243 #define RCC_APB1ENR_I2C2EN               RCC_APB1ENR_I2C2EN_Msk                /*!< I2C2 clock enable */
4244 #define RCC_APB1ENR_USBEN_Pos            (23U)
4245 #define RCC_APB1ENR_USBEN_Msk            (0x1UL << RCC_APB1ENR_USBEN_Pos)       /*!< 0x00800000 */
4246 #define RCC_APB1ENR_USBEN                RCC_APB1ENR_USBEN_Msk                 /*!< USB clock enable */
4247 #define RCC_APB1ENR_CRSEN_Pos            (27U)
4248 #define RCC_APB1ENR_CRSEN_Msk            (0x1UL << RCC_APB1ENR_CRSEN_Pos)       /*!< 0x08000000 */
4249 #define RCC_APB1ENR_CRSEN                RCC_APB1ENR_CRSEN_Msk                 /*!< CRS clock enable */
4250 #define RCC_APB1ENR_PWREN_Pos            (28U)
4251 #define RCC_APB1ENR_PWREN_Msk            (0x1UL << RCC_APB1ENR_PWREN_Pos)       /*!< 0x10000000 */
4252 #define RCC_APB1ENR_PWREN                RCC_APB1ENR_PWREN_Msk                 /*!< PWR clock enable */
4253 #define RCC_APB1ENR_DACEN_Pos            (29U)
4254 #define RCC_APB1ENR_DACEN_Msk            (0x1UL << RCC_APB1ENR_DACEN_Pos)       /*!< 0x20000000 */
4255 #define RCC_APB1ENR_DACEN                RCC_APB1ENR_DACEN_Msk                 /*!< DAC clock enable */
4256 #define RCC_APB1ENR_LPTIM1EN_Pos         (31U)
4257 #define RCC_APB1ENR_LPTIM1EN_Msk         (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)    /*!< 0x80000000 */
4258 #define RCC_APB1ENR_LPTIM1EN             RCC_APB1ENR_LPTIM1EN_Msk              /*!< LPTIM1 clock enable */
4259 
4260 /******************  Bit definition for RCC_IOPSMENR register  ****************/
4261 #define RCC_IOPSMENR_IOPASMEN_Pos        (0U)
4262 #define RCC_IOPSMENR_IOPASMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos)   /*!< 0x00000001 */
4263 #define RCC_IOPSMENR_IOPASMEN            RCC_IOPSMENR_IOPASMEN_Msk             /*!< GPIO port A clock enabled in sleep mode */
4264 #define RCC_IOPSMENR_IOPBSMEN_Pos        (1U)
4265 #define RCC_IOPSMENR_IOPBSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos)   /*!< 0x00000002 */
4266 #define RCC_IOPSMENR_IOPBSMEN            RCC_IOPSMENR_IOPBSMEN_Msk             /*!< GPIO port B clock enabled in sleep mode */
4267 #define RCC_IOPSMENR_IOPCSMEN_Pos        (2U)
4268 #define RCC_IOPSMENR_IOPCSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos)   /*!< 0x00000004 */
4269 #define RCC_IOPSMENR_IOPCSMEN            RCC_IOPSMENR_IOPCSMEN_Msk             /*!< GPIO port C clock enabled in sleep mode */
4270 #define RCC_IOPSMENR_IOPDSMEN_Pos        (3U)
4271 #define RCC_IOPSMENR_IOPDSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos)   /*!< 0x00000008 */
4272 #define RCC_IOPSMENR_IOPDSMEN            RCC_IOPSMENR_IOPDSMEN_Msk             /*!< GPIO port D clock enabled in sleep mode */
4273 #define RCC_IOPSMENR_IOPHSMEN_Pos        (7U)
4274 #define RCC_IOPSMENR_IOPHSMEN_Msk        (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos)   /*!< 0x00000080 */
4275 #define RCC_IOPSMENR_IOPHSMEN            RCC_IOPSMENR_IOPHSMEN_Msk             /*!< GPIO port H clock enabled in sleep mode */
4276 
4277 /* Reference defines */
4278 #define RCC_IOPSMENR_GPIOASMEN              RCC_IOPSMENR_IOPASMEN        /*!< GPIO port A clock enabled in sleep mode */
4279 #define RCC_IOPSMENR_GPIOBSMEN              RCC_IOPSMENR_IOPBSMEN        /*!< GPIO port B clock enabled in sleep mode */
4280 #define RCC_IOPSMENR_GPIOCSMEN              RCC_IOPSMENR_IOPCSMEN        /*!< GPIO port C clock enabled in sleep mode */
4281 #define RCC_IOPSMENR_GPIODSMEN              RCC_IOPSMENR_IOPDSMEN        /*!< GPIO port D clock enabled in sleep mode */
4282 #define RCC_IOPSMENR_GPIOHSMEN              RCC_IOPSMENR_IOPHSMEN        /*!< GPIO port H clock enabled in sleep mode */
4283 
4284 /*****************  Bit definition for RCC_AHBSMENR register  ******************/
4285 #define RCC_AHBSMENR_DMASMEN_Pos         (0U)
4286 #define RCC_AHBSMENR_DMASMEN_Msk         (0x1UL << RCC_AHBSMENR_DMASMEN_Pos)    /*!< 0x00000001 */
4287 #define RCC_AHBSMENR_DMASMEN             RCC_AHBSMENR_DMASMEN_Msk              /*!< DMA1 clock enabled in sleep mode */
4288 #define RCC_AHBSMENR_MIFSMEN_Pos         (8U)
4289 #define RCC_AHBSMENR_MIFSMEN_Msk         (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos)    /*!< 0x00000100 */
4290 #define RCC_AHBSMENR_MIFSMEN             RCC_AHBSMENR_MIFSMEN_Msk              /*!< NVM interface clock enable during sleep mode */
4291 #define RCC_AHBSMENR_SRAMSMEN_Pos        (9U)
4292 #define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
4293 #define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk             /*!< SRAM clock enabled in sleep mode */
4294 #define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
4295 #define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
4296 #define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk              /*!< CRC clock enabled in sleep mode */
4297 #define RCC_AHBSMENR_TSCSMEN_Pos         (16U)
4298 #define RCC_AHBSMENR_TSCSMEN_Msk         (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos)    /*!< 0x00010000 */
4299 #define RCC_AHBSMENR_TSCSMEN             RCC_AHBSMENR_TSCSMEN_Msk              /*!< TSC clock enabled in sleep mode */
4300 #define RCC_AHBSMENR_RNGSMEN_Pos         (20U)
4301 #define RCC_AHBSMENR_RNGSMEN_Msk         (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00100000 */
4302 #define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk              /*!< RNG clock enabled in sleep mode */
4303 #define RCC_AHBSMENR_CRYPSMEN_Pos        (24U)
4304 #define RCC_AHBSMENR_CRYPSMEN_Msk        (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos)   /*!< 0x01000000 */
4305 #define RCC_AHBSMENR_CRYPSMEN            RCC_AHBSMENR_CRYPSMEN_Msk             /*!< Crypto clock enabled in sleep mode */
4306 
4307 /* Reference defines */
4308 #define RCC_AHBSMENR_DMA1SMEN               RCC_AHBSMENR_DMASMEN          /*!< DMA1 clock enabled in sleep mode */
4309 
4310 /*****************  Bit definition for RCC_APB2SMENR register  ******************/
4311 #define RCC_APB2SMENR_SYSCFGSMEN_Pos     (0U)
4312 #define RCC_APB2SMENR_SYSCFGSMEN_Msk     (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
4313 #define RCC_APB2SMENR_SYSCFGSMEN         RCC_APB2SMENR_SYSCFGSMEN_Msk          /*!< SYSCFG clock enabled in sleep mode */
4314 #define RCC_APB2SMENR_TIM21SMEN_Pos      (2U)
4315 #define RCC_APB2SMENR_TIM21SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
4316 #define RCC_APB2SMENR_TIM21SMEN          RCC_APB2SMENR_TIM21SMEN_Msk           /*!< TIM21 clock enabled in sleep mode */
4317 #define RCC_APB2SMENR_TIM22SMEN_Pos      (5U)
4318 #define RCC_APB2SMENR_TIM22SMEN_Msk      (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
4319 #define RCC_APB2SMENR_TIM22SMEN          RCC_APB2SMENR_TIM22SMEN_Msk           /*!< TIM22 clock enabled in sleep mode */
4320 #define RCC_APB2SMENR_ADCSMEN_Pos        (9U)
4321 #define RCC_APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)   /*!< 0x00000200 */
4322 #define RCC_APB2SMENR_ADCSMEN            RCC_APB2SMENR_ADCSMEN_Msk             /*!< ADC1 clock enabled in sleep mode */
4323 #define RCC_APB2SMENR_SPI1SMEN_Pos       (12U)
4324 #define RCC_APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)  /*!< 0x00001000 */
4325 #define RCC_APB2SMENR_SPI1SMEN           RCC_APB2SMENR_SPI1SMEN_Msk            /*!< SPI1 clock enabled in sleep mode */
4326 #define RCC_APB2SMENR_USART1SMEN_Pos     (14U)
4327 #define RCC_APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
4328 #define RCC_APB2SMENR_USART1SMEN         RCC_APB2SMENR_USART1SMEN_Msk          /*!< USART1 clock enabled in sleep mode */
4329 #define RCC_APB2SMENR_DBGSMEN_Pos        (22U)
4330 #define RCC_APB2SMENR_DBGSMEN_Msk        (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos)   /*!< 0x00400000 */
4331 #define RCC_APB2SMENR_DBGSMEN            RCC_APB2SMENR_DBGSMEN_Msk             /*!< DBGMCU clock enabled in sleep mode */
4332 
4333 /* Reference defines */
4334 #define RCC_APB2SMENR_ADC1SMEN              RCC_APB2SMENR_ADCSMEN         /*!< ADC1 clock enabled in sleep mode */
4335 #define RCC_APB2SMENR_DBGMCUSMEN            RCC_APB2SMENR_DBGSMEN         /*!< DBGMCU clock enabled in sleep mode */
4336 
4337 /*****************  Bit definition for RCC_APB1SMENR register  ******************/
4338 #define RCC_APB1SMENR_TIM2SMEN_Pos       (0U)
4339 #define RCC_APB1SMENR_TIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos)  /*!< 0x00000001 */
4340 #define RCC_APB1SMENR_TIM2SMEN           RCC_APB1SMENR_TIM2SMEN_Msk            /*!< Timer 2 clock enabled in sleep mode */
4341 #define RCC_APB1SMENR_TIM6SMEN_Pos       (4U)
4342 #define RCC_APB1SMENR_TIM6SMEN_Msk       (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos)  /*!< 0x00000010 */
4343 #define RCC_APB1SMENR_TIM6SMEN           RCC_APB1SMENR_TIM6SMEN_Msk            /*!< Timer 6 clock enabled in sleep mode */
4344 #define RCC_APB1SMENR_WWDGSMEN_Pos       (11U)
4345 #define RCC_APB1SMENR_WWDGSMEN_Msk       (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos)  /*!< 0x00000800 */
4346 #define RCC_APB1SMENR_WWDGSMEN           RCC_APB1SMENR_WWDGSMEN_Msk            /*!< Window Watchdog clock enabled in sleep mode */
4347 #define RCC_APB1SMENR_SPI2SMEN_Pos       (14U)
4348 #define RCC_APB1SMENR_SPI2SMEN_Msk       (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos)  /*!< 0x00004000 */
4349 #define RCC_APB1SMENR_SPI2SMEN           RCC_APB1SMENR_SPI2SMEN_Msk            /*!< SPI2 clock enabled in sleep mode */
4350 #define RCC_APB1SMENR_USART2SMEN_Pos     (17U)
4351 #define RCC_APB1SMENR_USART2SMEN_Msk     (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
4352 #define RCC_APB1SMENR_USART2SMEN         RCC_APB1SMENR_USART2SMEN_Msk          /*!< USART2 clock enabled in sleep mode */
4353 #define RCC_APB1SMENR_LPUART1SMEN_Pos    (18U)
4354 #define RCC_APB1SMENR_LPUART1SMEN_Msk    (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
4355 #define RCC_APB1SMENR_LPUART1SMEN        RCC_APB1SMENR_LPUART1SMEN_Msk         /*!< LPUART1 clock enabled in sleep mode */
4356 #define RCC_APB1SMENR_I2C1SMEN_Pos       (21U)
4357 #define RCC_APB1SMENR_I2C1SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos)  /*!< 0x00200000 */
4358 #define RCC_APB1SMENR_I2C1SMEN           RCC_APB1SMENR_I2C1SMEN_Msk            /*!< I2C1 clock enabled in sleep mode */
4359 #define RCC_APB1SMENR_I2C2SMEN_Pos       (22U)
4360 #define RCC_APB1SMENR_I2C2SMEN_Msk       (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos)  /*!< 0x00400000 */
4361 #define RCC_APB1SMENR_I2C2SMEN           RCC_APB1SMENR_I2C2SMEN_Msk            /*!< I2C2 clock enabled in sleep mode */
4362 #define RCC_APB1SMENR_USBSMEN_Pos        (23U)
4363 #define RCC_APB1SMENR_USBSMEN_Msk        (0x1UL << RCC_APB1SMENR_USBSMEN_Pos)   /*!< 0x00800000 */
4364 #define RCC_APB1SMENR_USBSMEN            RCC_APB1SMENR_USBSMEN_Msk             /*!< USB clock enabled in sleep mode */
4365 #define RCC_APB1SMENR_CRSSMEN_Pos        (27U)
4366 #define RCC_APB1SMENR_CRSSMEN_Msk        (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos)   /*!< 0x08000000 */
4367 #define RCC_APB1SMENR_CRSSMEN            RCC_APB1SMENR_CRSSMEN_Msk             /*!< CRS clock enabled in sleep mode */
4368 #define RCC_APB1SMENR_PWRSMEN_Pos        (28U)
4369 #define RCC_APB1SMENR_PWRSMEN_Msk        (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos)   /*!< 0x10000000 */
4370 #define RCC_APB1SMENR_PWRSMEN            RCC_APB1SMENR_PWRSMEN_Msk             /*!< PWR clock enabled in sleep mode */
4371 #define RCC_APB1SMENR_DACSMEN_Pos        (29U)
4372 #define RCC_APB1SMENR_DACSMEN_Msk        (0x1UL << RCC_APB1SMENR_DACSMEN_Pos)   /*!< 0x20000000 */
4373 #define RCC_APB1SMENR_DACSMEN            RCC_APB1SMENR_DACSMEN_Msk             /*!< DAC clock enabled in sleep mode */
4374 #define RCC_APB1SMENR_LPTIM1SMEN_Pos     (31U)
4375 #define RCC_APB1SMENR_LPTIM1SMEN_Msk     (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
4376 #define RCC_APB1SMENR_LPTIM1SMEN         RCC_APB1SMENR_LPTIM1SMEN_Msk          /*!< LPTIM1 clock enabled in sleep mode */
4377 
4378 /*******************  Bit definition for RCC_CCIPR register  *******************/
4379 /*!< USART1 Clock source selection */
4380 #define RCC_CCIPR_USART1SEL_Pos          (0U)
4381 #define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
4382 #define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk               /*!< USART1SEL[1:0] bits */
4383 #define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
4384 #define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
4385 
4386 /*!< USART2 Clock source selection */
4387 #define RCC_CCIPR_USART2SEL_Pos          (2U)
4388 #define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
4389 #define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk               /*!< USART2SEL[1:0] bits */
4390 #define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
4391 #define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
4392 
4393 /*!< LPUART1 Clock source selection */
4394 #define RCC_CCIPR_LPUART1SEL_Pos         (10U)
4395 #define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
4396 #define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk              /*!< LPUART1SEL[1:0] bits */
4397 #define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000400 */
4398 #define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x0000800 */
4399 
4400 /*!< I2C1 Clock source selection */
4401 #define RCC_CCIPR_I2C1SEL_Pos            (12U)
4402 #define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
4403 #define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk                 /*!< I2C1SEL [1:0] bits */
4404 #define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
4405 #define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
4406 
4407 
4408 /*!< LPTIM1 Clock source selection */
4409 #define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
4410 #define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
4411 #define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk               /*!< LPTIM1SEL [1:0] bits */
4412 #define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
4413 #define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
4414 
4415 /*!< HSI48 Clock source selection */
4416 #define RCC_CCIPR_HSI48SEL_Pos           (26U)
4417 #define RCC_CCIPR_HSI48SEL_Msk           (0x1UL << RCC_CCIPR_HSI48SEL_Pos)      /*!< 0x04000000 */
4418 #define RCC_CCIPR_HSI48SEL               RCC_CCIPR_HSI48SEL_Msk                /*!< HSI48 RC clock source selection bit for USB and RNG*/
4419 
4420 /* Legacy defines */
4421 #define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
4422 
4423 /*******************  Bit definition for RCC_CSR register  *******************/
4424 #define RCC_CSR_LSION_Pos                (0U)
4425 #define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
4426 #define RCC_CSR_LSION                    RCC_CSR_LSION_Msk                     /*!< Internal Low Speed oscillator enable */
4427 #define RCC_CSR_LSIRDY_Pos               (1U)
4428 #define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
4429 #define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk                    /*!< Internal Low Speed oscillator Ready */
4430 
4431 #define RCC_CSR_LSEON_Pos                (8U)
4432 #define RCC_CSR_LSEON_Msk                (0x1UL << RCC_CSR_LSEON_Pos)           /*!< 0x00000100 */
4433 #define RCC_CSR_LSEON                    RCC_CSR_LSEON_Msk                     /*!< External Low Speed oscillator enable */
4434 #define RCC_CSR_LSERDY_Pos               (9U)
4435 #define RCC_CSR_LSERDY_Msk               (0x1UL << RCC_CSR_LSERDY_Pos)          /*!< 0x00000200 */
4436 #define RCC_CSR_LSERDY                   RCC_CSR_LSERDY_Msk                    /*!< External Low Speed oscillator Ready */
4437 #define RCC_CSR_LSEBYP_Pos               (10U)
4438 #define RCC_CSR_LSEBYP_Msk               (0x1UL << RCC_CSR_LSEBYP_Pos)          /*!< 0x00000400 */
4439 #define RCC_CSR_LSEBYP                   RCC_CSR_LSEBYP_Msk                    /*!< External Low Speed oscillator Bypass */
4440 
4441 #define RCC_CSR_LSEDRV_Pos               (11U)
4442 #define RCC_CSR_LSEDRV_Msk               (0x3UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001800 */
4443 #define RCC_CSR_LSEDRV                   RCC_CSR_LSEDRV_Msk                    /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
4444 #define RCC_CSR_LSEDRV_0                 (0x1UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00000800 */
4445 #define RCC_CSR_LSEDRV_1                 (0x2UL << RCC_CSR_LSEDRV_Pos)          /*!< 0x00001000 */
4446 
4447 #define RCC_CSR_LSECSSON_Pos             (13U)
4448 #define RCC_CSR_LSECSSON_Msk             (0x1UL << RCC_CSR_LSECSSON_Pos)        /*!< 0x00002000 */
4449 #define RCC_CSR_LSECSSON                 RCC_CSR_LSECSSON_Msk                  /*!< External Low Speed oscillator CSS Enable */
4450 #define RCC_CSR_LSECSSD_Pos              (14U)
4451 #define RCC_CSR_LSECSSD_Msk              (0x1UL << RCC_CSR_LSECSSD_Pos)         /*!< 0x00004000 */
4452 #define RCC_CSR_LSECSSD                  RCC_CSR_LSECSSD_Msk                   /*!< External Low Speed oscillator CSS Detected */
4453 
4454 /*!< RTC configuration */
4455 #define RCC_CSR_RTCSEL_Pos               (16U)
4456 #define RCC_CSR_RTCSEL_Msk               (0x3UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00030000 */
4457 #define RCC_CSR_RTCSEL                   RCC_CSR_RTCSEL_Msk                    /*!< RTCSEL[1:0] bits (RTC clock source selection) */
4458 #define RCC_CSR_RTCSEL_0                 (0x1UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00010000 */
4459 #define RCC_CSR_RTCSEL_1                 (0x2UL << RCC_CSR_RTCSEL_Pos)          /*!< 0x00020000 */
4460 
4461 #define RCC_CSR_RTCSEL_NOCLOCK               (0x00000000U)                     /*!< No clock */
4462 #define RCC_CSR_RTCSEL_LSE_Pos           (16U)
4463 #define RCC_CSR_RTCSEL_LSE_Msk           (0x1UL << RCC_CSR_RTCSEL_LSE_Pos)      /*!< 0x00010000 */
4464 #define RCC_CSR_RTCSEL_LSE               RCC_CSR_RTCSEL_LSE_Msk                /*!< LSE oscillator clock used as RTC clock */
4465 #define RCC_CSR_RTCSEL_LSI_Pos           (17U)
4466 #define RCC_CSR_RTCSEL_LSI_Msk           (0x1UL << RCC_CSR_RTCSEL_LSI_Pos)      /*!< 0x00020000 */
4467 #define RCC_CSR_RTCSEL_LSI               RCC_CSR_RTCSEL_LSI_Msk                /*!< LSI oscillator clock used as RTC clock */
4468 #define RCC_CSR_RTCSEL_HSE_Pos           (16U)
4469 #define RCC_CSR_RTCSEL_HSE_Msk           (0x3UL << RCC_CSR_RTCSEL_HSE_Pos)      /*!< 0x00030000 */
4470 #define RCC_CSR_RTCSEL_HSE               RCC_CSR_RTCSEL_HSE_Msk                /*!< HSE oscillator clock used as RTC clock */
4471 
4472 #define RCC_CSR_RTCEN_Pos                (18U)
4473 #define RCC_CSR_RTCEN_Msk                (0x1UL << RCC_CSR_RTCEN_Pos)           /*!< 0x00040000 */
4474 #define RCC_CSR_RTCEN                    RCC_CSR_RTCEN_Msk                     /*!< RTC clock enable */
4475 #define RCC_CSR_RTCRST_Pos               (19U)
4476 #define RCC_CSR_RTCRST_Msk               (0x1UL << RCC_CSR_RTCRST_Pos)          /*!< 0x00080000 */
4477 #define RCC_CSR_RTCRST                   RCC_CSR_RTCRST_Msk                    /*!< RTC software reset  */
4478 
4479 #define RCC_CSR_RMVF_Pos                 (23U)
4480 #define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
4481 #define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk                      /*!< Remove reset flag */
4482 #define RCC_CSR_FWRSTF_Pos               (24U)
4483 #define RCC_CSR_FWRSTF_Msk               (0x1UL << RCC_CSR_FWRSTF_Pos)          /*!< 0x01000000 */
4484 #define RCC_CSR_FWRSTF                   RCC_CSR_FWRSTF_Msk                    /*!< Mifare Firewall reset flag */
4485 #define RCC_CSR_OBLRSTF_Pos              (25U)
4486 #define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
4487 #define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk                   /*!< OBL reset flag */
4488 #define RCC_CSR_PINRSTF_Pos              (26U)
4489 #define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
4490 #define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk                   /*!< PIN reset flag */
4491 #define RCC_CSR_PORRSTF_Pos              (27U)
4492 #define RCC_CSR_PORRSTF_Msk              (0x1UL << RCC_CSR_PORRSTF_Pos)         /*!< 0x08000000 */
4493 #define RCC_CSR_PORRSTF                  RCC_CSR_PORRSTF_Msk                   /*!< POR/PDR reset flag */
4494 #define RCC_CSR_SFTRSTF_Pos              (28U)
4495 #define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
4496 #define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk                   /*!< Software Reset flag */
4497 #define RCC_CSR_IWDGRSTF_Pos             (29U)
4498 #define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
4499 #define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk                  /*!< Independent Watchdog reset flag */
4500 #define RCC_CSR_WWDGRSTF_Pos             (30U)
4501 #define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
4502 #define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk                  /*!< Window watchdog reset flag */
4503 #define RCC_CSR_LPWRRSTF_Pos             (31U)
4504 #define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
4505 #define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk                  /*!< Low-Power reset flag */
4506 
4507 /* Reference defines */
4508 #define RCC_CSR_OBL                         RCC_CSR_OBLRSTF               /*!< OBL reset flag */
4509 
4510 
4511 /******************************************************************************/
4512 /*                                                                            */
4513 /*                                    RNG                                     */
4514 /*                                                                            */
4515 /******************************************************************************/
4516 /********************  Bits definition for RNG_CR register  *******************/
4517 #define RNG_CR_RNGEN_Pos    (2U)
4518 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
4519 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
4520 #define RNG_CR_IE_Pos       (3U)
4521 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
4522 #define RNG_CR_IE           RNG_CR_IE_Msk
4523 
4524 /********************  Bits definition for RNG_SR register  *******************/
4525 #define RNG_SR_DRDY_Pos     (0U)
4526 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
4527 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
4528 #define RNG_SR_CECS_Pos     (1U)
4529 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
4530 #define RNG_SR_CECS         RNG_SR_CECS_Msk
4531 #define RNG_SR_SECS_Pos     (2U)
4532 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
4533 #define RNG_SR_SECS         RNG_SR_SECS_Msk
4534 #define RNG_SR_CEIS_Pos     (5U)
4535 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
4536 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
4537 #define RNG_SR_SEIS_Pos     (6U)
4538 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
4539 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
4540 
4541 /******************************************************************************/
4542 /*                                                                            */
4543 /*                           Real-Time Clock (RTC)                            */
4544 /*                                                                            */
4545 /******************************************************************************/
4546 /*
4547 * @brief Specific device feature definitions
4548 */
4549 #define RTC_TAMPER1_SUPPORT
4550 #define RTC_TAMPER2_SUPPORT
4551 #define RTC_WAKEUP_SUPPORT
4552 #define RTC_BACKUP_SUPPORT
4553 
4554 /********************  Bits definition for RTC_TR register  *******************/
4555 #define RTC_TR_PM_Pos                  (22U)
4556 #define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
4557 #define RTC_TR_PM                      RTC_TR_PM_Msk                           /*!<  */
4558 #define RTC_TR_HT_Pos                  (20U)
4559 #define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
4560 #define RTC_TR_HT                      RTC_TR_HT_Msk                           /*!<  */
4561 #define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
4562 #define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
4563 #define RTC_TR_HU_Pos                  (16U)
4564 #define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
4565 #define RTC_TR_HU                      RTC_TR_HU_Msk                           /*!<  */
4566 #define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
4567 #define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
4568 #define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
4569 #define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
4570 #define RTC_TR_MNT_Pos                 (12U)
4571 #define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
4572 #define RTC_TR_MNT                     RTC_TR_MNT_Msk                          /*!<  */
4573 #define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
4574 #define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
4575 #define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
4576 #define RTC_TR_MNU_Pos                 (8U)
4577 #define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
4578 #define RTC_TR_MNU                     RTC_TR_MNU_Msk                          /*!<  */
4579 #define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
4580 #define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
4581 #define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
4582 #define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
4583 #define RTC_TR_ST_Pos                  (4U)
4584 #define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
4585 #define RTC_TR_ST                      RTC_TR_ST_Msk                           /*!<  */
4586 #define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
4587 #define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
4588 #define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
4589 #define RTC_TR_SU_Pos                  (0U)
4590 #define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
4591 #define RTC_TR_SU                      RTC_TR_SU_Msk                           /*!<  */
4592 #define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
4593 #define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
4594 #define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
4595 #define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
4596 
4597 /********************  Bits definition for RTC_DR register  *******************/
4598 #define RTC_DR_YT_Pos                  (20U)
4599 #define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
4600 #define RTC_DR_YT                      RTC_DR_YT_Msk                           /*!<  */
4601 #define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
4602 #define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
4603 #define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
4604 #define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
4605 #define RTC_DR_YU_Pos                  (16U)
4606 #define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
4607 #define RTC_DR_YU                      RTC_DR_YU_Msk                           /*!<  */
4608 #define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
4609 #define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
4610 #define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
4611 #define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
4612 #define RTC_DR_WDU_Pos                 (13U)
4613 #define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
4614 #define RTC_DR_WDU                     RTC_DR_WDU_Msk                          /*!<  */
4615 #define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
4616 #define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
4617 #define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
4618 #define RTC_DR_MT_Pos                  (12U)
4619 #define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
4620 #define RTC_DR_MT                      RTC_DR_MT_Msk                           /*!<  */
4621 #define RTC_DR_MU_Pos                  (8U)
4622 #define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
4623 #define RTC_DR_MU                      RTC_DR_MU_Msk                           /*!<  */
4624 #define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
4625 #define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
4626 #define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
4627 #define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
4628 #define RTC_DR_DT_Pos                  (4U)
4629 #define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
4630 #define RTC_DR_DT                      RTC_DR_DT_Msk                           /*!<  */
4631 #define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
4632 #define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
4633 #define RTC_DR_DU_Pos                  (0U)
4634 #define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
4635 #define RTC_DR_DU                      RTC_DR_DU_Msk                           /*!<  */
4636 #define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
4637 #define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
4638 #define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
4639 #define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
4640 
4641 /********************  Bits definition for RTC_CR register  *******************/
4642 #define RTC_CR_COE_Pos                 (23U)
4643 #define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)                /*!< 0x00800000 */
4644 #define RTC_CR_COE                     RTC_CR_COE_Msk                          /*!<  */
4645 #define RTC_CR_OSEL_Pos                (21U)
4646 #define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
4647 #define RTC_CR_OSEL                    RTC_CR_OSEL_Msk                         /*!<  */
4648 #define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
4649 #define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
4650 #define RTC_CR_POL_Pos                 (20U)
4651 #define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)                /*!< 0x00100000 */
4652 #define RTC_CR_POL                     RTC_CR_POL_Msk                          /*!<  */
4653 #define RTC_CR_COSEL_Pos               (19U)
4654 #define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
4655 #define RTC_CR_COSEL                   RTC_CR_COSEL_Msk                        /*!<  */
4656 #define RTC_CR_BKP_Pos                 (18U)
4657 #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
4658 #define RTC_CR_BKP                     RTC_CR_BKP_Msk                          /*!<  */
4659 #define RTC_CR_SUB1H_Pos               (17U)
4660 #define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
4661 #define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk                        /*!<  */
4662 #define RTC_CR_ADD1H_Pos               (16U)
4663 #define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
4664 #define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk                        /*!<  */
4665 #define RTC_CR_TSIE_Pos                (15U)
4666 #define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
4667 #define RTC_CR_TSIE                    RTC_CR_TSIE_Msk                         /*!<  */
4668 #define RTC_CR_WUTIE_Pos               (14U)
4669 #define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
4670 #define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk                        /*!<  */
4671 #define RTC_CR_ALRBIE_Pos              (13U)
4672 #define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
4673 #define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk                       /*!<  */
4674 #define RTC_CR_ALRAIE_Pos              (12U)
4675 #define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
4676 #define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk                       /*!<  */
4677 #define RTC_CR_TSE_Pos                 (11U)
4678 #define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
4679 #define RTC_CR_TSE                     RTC_CR_TSE_Msk                          /*!<  */
4680 #define RTC_CR_WUTE_Pos                (10U)
4681 #define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
4682 #define RTC_CR_WUTE                    RTC_CR_WUTE_Msk                         /*!<  */
4683 #define RTC_CR_ALRBE_Pos               (9U)
4684 #define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
4685 #define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk                        /*!<  */
4686 #define RTC_CR_ALRAE_Pos               (8U)
4687 #define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
4688 #define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk                        /*!<  */
4689 #define RTC_CR_FMT_Pos                 (6U)
4690 #define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
4691 #define RTC_CR_FMT                     RTC_CR_FMT_Msk                          /*!<  */
4692 #define RTC_CR_BYPSHAD_Pos             (5U)
4693 #define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
4694 #define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk                      /*!<  */
4695 #define RTC_CR_REFCKON_Pos             (4U)
4696 #define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
4697 #define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk                      /*!<  */
4698 #define RTC_CR_TSEDGE_Pos              (3U)
4699 #define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
4700 #define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk                       /*!<  */
4701 #define RTC_CR_WUCKSEL_Pos             (0U)
4702 #define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
4703 #define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk                      /*!<  */
4704 #define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
4705 #define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
4706 #define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
4707 
4708 /********************  Bits definition for RTC_ISR register  ******************/
4709 #define RTC_ISR_RECALPF_Pos            (16U)
4710 #define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
4711 #define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk                     /*!<  */
4712 #define RTC_ISR_TAMP2F_Pos             (14U)
4713 #define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
4714 #define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk                      /*!<  */
4715 #define RTC_ISR_TAMP1F_Pos             (13U)
4716 #define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
4717 #define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk                      /*!<  */
4718 #define RTC_ISR_TSOVF_Pos              (12U)
4719 #define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
4720 #define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk                       /*!<  */
4721 #define RTC_ISR_TSF_Pos                (11U)
4722 #define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
4723 #define RTC_ISR_TSF                    RTC_ISR_TSF_Msk                         /*!<  */
4724 #define RTC_ISR_WUTF_Pos               (10U)
4725 #define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
4726 #define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk                        /*!<  */
4727 #define RTC_ISR_ALRBF_Pos              (9U)
4728 #define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
4729 #define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk                       /*!<  */
4730 #define RTC_ISR_ALRAF_Pos              (8U)
4731 #define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
4732 #define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk                       /*!<  */
4733 #define RTC_ISR_INIT_Pos               (7U)
4734 #define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
4735 #define RTC_ISR_INIT                   RTC_ISR_INIT_Msk                        /*!<  */
4736 #define RTC_ISR_INITF_Pos              (6U)
4737 #define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
4738 #define RTC_ISR_INITF                  RTC_ISR_INITF_Msk                       /*!<  */
4739 #define RTC_ISR_RSF_Pos                (5U)
4740 #define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
4741 #define RTC_ISR_RSF                    RTC_ISR_RSF_Msk                         /*!<  */
4742 #define RTC_ISR_INITS_Pos              (4U)
4743 #define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
4744 #define RTC_ISR_INITS                  RTC_ISR_INITS_Msk                       /*!<  */
4745 #define RTC_ISR_SHPF_Pos               (3U)
4746 #define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
4747 #define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk                        /*!<  */
4748 #define RTC_ISR_WUTWF_Pos              (2U)
4749 #define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
4750 #define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk                       /*!<  */
4751 #define RTC_ISR_ALRBWF_Pos             (1U)
4752 #define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
4753 #define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk                      /*!<  */
4754 #define RTC_ISR_ALRAWF_Pos             (0U)
4755 #define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
4756 #define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk                      /*!<  */
4757 
4758 /********************  Bits definition for RTC_PRER register  *****************/
4759 #define RTC_PRER_PREDIV_A_Pos          (16U)
4760 #define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
4761 #define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk                   /*!<  */
4762 #define RTC_PRER_PREDIV_S_Pos          (0U)
4763 #define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
4764 #define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk                   /*!<  */
4765 
4766 /********************  Bits definition for RTC_WUTR register  *****************/
4767 #define RTC_WUTR_WUT_Pos               (0U)
4768 #define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
4769 #define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk
4770 
4771 /********************  Bits definition for RTC_ALRMAR register  ***************/
4772 #define RTC_ALRMAR_MSK4_Pos            (31U)
4773 #define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
4774 #define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk                     /*!<  */
4775 #define RTC_ALRMAR_WDSEL_Pos           (30U)
4776 #define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
4777 #define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk                    /*!<  */
4778 #define RTC_ALRMAR_DT_Pos              (28U)
4779 #define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
4780 #define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk                       /*!<  */
4781 #define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
4782 #define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
4783 #define RTC_ALRMAR_DU_Pos              (24U)
4784 #define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
4785 #define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk                       /*!<  */
4786 #define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
4787 #define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
4788 #define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
4789 #define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
4790 #define RTC_ALRMAR_MSK3_Pos            (23U)
4791 #define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
4792 #define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk                     /*!<  */
4793 #define RTC_ALRMAR_PM_Pos              (22U)
4794 #define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
4795 #define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk                       /*!<  */
4796 #define RTC_ALRMAR_HT_Pos              (20U)
4797 #define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
4798 #define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk                       /*!<  */
4799 #define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
4800 #define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
4801 #define RTC_ALRMAR_HU_Pos              (16U)
4802 #define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
4803 #define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk                       /*!<  */
4804 #define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
4805 #define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
4806 #define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
4807 #define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
4808 #define RTC_ALRMAR_MSK2_Pos            (15U)
4809 #define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
4810 #define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk                     /*!<  */
4811 #define RTC_ALRMAR_MNT_Pos             (12U)
4812 #define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
4813 #define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk                      /*!<  */
4814 #define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
4815 #define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
4816 #define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
4817 #define RTC_ALRMAR_MNU_Pos             (8U)
4818 #define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
4819 #define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk                      /*!<  */
4820 #define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
4821 #define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
4822 #define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
4823 #define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
4824 #define RTC_ALRMAR_MSK1_Pos            (7U)
4825 #define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
4826 #define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk                     /*!<  */
4827 #define RTC_ALRMAR_ST_Pos              (4U)
4828 #define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
4829 #define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk                       /*!<  */
4830 #define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
4831 #define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
4832 #define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
4833 #define RTC_ALRMAR_SU_Pos              (0U)
4834 #define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
4835 #define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk                       /*!<  */
4836 #define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
4837 #define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
4838 #define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
4839 #define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
4840 
4841 /********************  Bits definition for RTC_ALRMBR register  ***************/
4842 #define RTC_ALRMBR_MSK4_Pos            (31U)
4843 #define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
4844 #define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk                     /*!<  */
4845 #define RTC_ALRMBR_WDSEL_Pos           (30U)
4846 #define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
4847 #define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk                    /*!<  */
4848 #define RTC_ALRMBR_DT_Pos              (28U)
4849 #define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
4850 #define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk                       /*!<  */
4851 #define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
4852 #define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
4853 #define RTC_ALRMBR_DU_Pos              (24U)
4854 #define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
4855 #define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk                       /*!<  */
4856 #define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
4857 #define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
4858 #define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
4859 #define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
4860 #define RTC_ALRMBR_MSK3_Pos            (23U)
4861 #define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
4862 #define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk                     /*!<  */
4863 #define RTC_ALRMBR_PM_Pos              (22U)
4864 #define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
4865 #define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk                       /*!<  */
4866 #define RTC_ALRMBR_HT_Pos              (20U)
4867 #define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
4868 #define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk                       /*!<  */
4869 #define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
4870 #define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
4871 #define RTC_ALRMBR_HU_Pos              (16U)
4872 #define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
4873 #define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk                       /*!<  */
4874 #define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
4875 #define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
4876 #define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
4877 #define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
4878 #define RTC_ALRMBR_MSK2_Pos            (15U)
4879 #define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
4880 #define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk                     /*!<  */
4881 #define RTC_ALRMBR_MNT_Pos             (12U)
4882 #define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
4883 #define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk                      /*!<  */
4884 #define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
4885 #define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
4886 #define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
4887 #define RTC_ALRMBR_MNU_Pos             (8U)
4888 #define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
4889 #define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk                      /*!<  */
4890 #define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
4891 #define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
4892 #define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
4893 #define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
4894 #define RTC_ALRMBR_MSK1_Pos            (7U)
4895 #define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
4896 #define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk                     /*!<  */
4897 #define RTC_ALRMBR_ST_Pos              (4U)
4898 #define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
4899 #define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk                       /*!<  */
4900 #define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
4901 #define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
4902 #define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
4903 #define RTC_ALRMBR_SU_Pos              (0U)
4904 #define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
4905 #define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk                       /*!<  */
4906 #define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
4907 #define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
4908 #define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
4909 #define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
4910 
4911 /********************  Bits definition for RTC_WPR register  ******************/
4912 #define RTC_WPR_KEY_Pos                (0U)
4913 #define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
4914 #define RTC_WPR_KEY                    RTC_WPR_KEY_Msk                         /*!<  */
4915 
4916 /********************  Bits definition for RTC_SSR register  ******************/
4917 #define RTC_SSR_SS_Pos                 (0U)
4918 #define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
4919 #define RTC_SSR_SS                     RTC_SSR_SS_Msk                          /*!<  */
4920 
4921 /********************  Bits definition for RTC_SHIFTR register  ***************/
4922 #define RTC_SHIFTR_SUBFS_Pos           (0U)
4923 #define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
4924 #define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk                    /*!<  */
4925 #define RTC_SHIFTR_ADD1S_Pos           (31U)
4926 #define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
4927 #define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk                    /*!<  */
4928 
4929 /********************  Bits definition for RTC_TSTR register  *****************/
4930 #define RTC_TSTR_PM_Pos                (22U)
4931 #define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
4932 #define RTC_TSTR_PM                    RTC_TSTR_PM_Msk                         /*!<  */
4933 #define RTC_TSTR_HT_Pos                (20U)
4934 #define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
4935 #define RTC_TSTR_HT                    RTC_TSTR_HT_Msk                         /*!<  */
4936 #define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
4937 #define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
4938 #define RTC_TSTR_HU_Pos                (16U)
4939 #define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
4940 #define RTC_TSTR_HU                    RTC_TSTR_HU_Msk                         /*!<  */
4941 #define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
4942 #define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
4943 #define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
4944 #define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
4945 #define RTC_TSTR_MNT_Pos               (12U)
4946 #define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
4947 #define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk                        /*!<  */
4948 #define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
4949 #define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
4950 #define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
4951 #define RTC_TSTR_MNU_Pos               (8U)
4952 #define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
4953 #define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk                        /*!<  */
4954 #define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
4955 #define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
4956 #define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
4957 #define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
4958 #define RTC_TSTR_ST_Pos                (4U)
4959 #define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
4960 #define RTC_TSTR_ST                    RTC_TSTR_ST_Msk                         /*!<  */
4961 #define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
4962 #define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
4963 #define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
4964 #define RTC_TSTR_SU_Pos                (0U)
4965 #define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
4966 #define RTC_TSTR_SU                    RTC_TSTR_SU_Msk                         /*!<  */
4967 #define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
4968 #define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
4969 #define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
4970 #define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
4971 
4972 /********************  Bits definition for RTC_TSDR register  *****************/
4973 #define RTC_TSDR_WDU_Pos               (13U)
4974 #define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
4975 #define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk                        /*!<  */
4976 #define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
4977 #define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
4978 #define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
4979 #define RTC_TSDR_MT_Pos                (12U)
4980 #define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
4981 #define RTC_TSDR_MT                    RTC_TSDR_MT_Msk                         /*!<  */
4982 #define RTC_TSDR_MU_Pos                (8U)
4983 #define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
4984 #define RTC_TSDR_MU                    RTC_TSDR_MU_Msk                         /*!<  */
4985 #define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
4986 #define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
4987 #define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
4988 #define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
4989 #define RTC_TSDR_DT_Pos                (4U)
4990 #define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
4991 #define RTC_TSDR_DT                    RTC_TSDR_DT_Msk                         /*!<  */
4992 #define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
4993 #define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
4994 #define RTC_TSDR_DU_Pos                (0U)
4995 #define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
4996 #define RTC_TSDR_DU                    RTC_TSDR_DU_Msk                         /*!<  */
4997 #define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
4998 #define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
4999 #define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
5000 #define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
5001 
5002 /********************  Bits definition for RTC_TSSSR register  ****************/
5003 #define RTC_TSSSR_SS_Pos               (0U)
5004 #define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
5005 #define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk
5006 
5007 /********************  Bits definition for RTC_CALR register  *****************/
5008 #define RTC_CALR_CALP_Pos              (15U)
5009 #define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
5010 #define RTC_CALR_CALP                  RTC_CALR_CALP_Msk                       /*!<  */
5011 #define RTC_CALR_CALW8_Pos             (14U)
5012 #define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
5013 #define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk                      /*!<  */
5014 #define RTC_CALR_CALW16_Pos            (13U)
5015 #define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
5016 #define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk                     /*!<  */
5017 #define RTC_CALR_CALM_Pos              (0U)
5018 #define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
5019 #define RTC_CALR_CALM                  RTC_CALR_CALM_Msk                       /*!<  */
5020 #define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
5021 #define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
5022 #define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
5023 #define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
5024 #define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
5025 #define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
5026 #define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
5027 #define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
5028 #define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
5029 
5030 /* Legacy defines */
5031 #define RTC_CAL_CALP     RTC_CALR_CALP
5032 #define RTC_CAL_CALW8    RTC_CALR_CALW8
5033 #define RTC_CAL_CALW16   RTC_CALR_CALW16
5034 #define RTC_CAL_CALM     RTC_CALR_CALM
5035 #define RTC_CAL_CALM_0   RTC_CALR_CALM_0
5036 #define RTC_CAL_CALM_1   RTC_CALR_CALM_1
5037 #define RTC_CAL_CALM_2   RTC_CALR_CALM_2
5038 #define RTC_CAL_CALM_3   RTC_CALR_CALM_3
5039 #define RTC_CAL_CALM_4   RTC_CALR_CALM_4
5040 #define RTC_CAL_CALM_5   RTC_CALR_CALM_5
5041 #define RTC_CAL_CALM_6   RTC_CALR_CALM_6
5042 #define RTC_CAL_CALM_7   RTC_CALR_CALM_7
5043 #define RTC_CAL_CALM_8   RTC_CALR_CALM_8
5044 
5045 /********************  Bits definition for RTC_TAMPCR register  ****************/
5046 #define RTC_TAMPCR_TAMP2MF_Pos         (21U)
5047 #define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
5048 #define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk                  /*!<  */
5049 #define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)
5050 #define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
5051 #define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk             /*!<  */
5052 #define RTC_TAMPCR_TAMP2IE_Pos         (19U)
5053 #define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
5054 #define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk                  /*!<  */
5055 #define RTC_TAMPCR_TAMP1MF_Pos         (18U)
5056 #define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
5057 #define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk                  /*!<  */
5058 #define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)
5059 #define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
5060 #define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk             /*!<  */
5061 #define RTC_TAMPCR_TAMP1IE_Pos         (16U)
5062 #define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
5063 #define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk                  /*!<  */
5064 #define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)
5065 #define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
5066 #define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk                /*!<  */
5067 #define RTC_TAMPCR_TAMPPRCH_Pos        (13U)
5068 #define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
5069 #define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk                 /*!<  */
5070 #define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
5071 #define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
5072 #define RTC_TAMPCR_TAMPFLT_Pos         (11U)
5073 #define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
5074 #define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk                  /*!<  */
5075 #define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
5076 #define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
5077 #define RTC_TAMPCR_TAMPFREQ_Pos        (8U)
5078 #define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
5079 #define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk                 /*!<  */
5080 #define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
5081 #define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
5082 #define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
5083 #define RTC_TAMPCR_TAMPTS_Pos          (7U)
5084 #define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
5085 #define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk                   /*!<  */
5086 #define RTC_TAMPCR_TAMP2TRG_Pos        (4U)
5087 #define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
5088 #define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk                 /*!<  */
5089 #define RTC_TAMPCR_TAMP2E_Pos          (3U)
5090 #define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
5091 #define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk                   /*!<  */
5092 #define RTC_TAMPCR_TAMPIE_Pos          (2U)
5093 #define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
5094 #define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk                   /*!<  */
5095 #define RTC_TAMPCR_TAMP1TRG_Pos        (1U)
5096 #define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
5097 #define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk                 /*!<  */
5098 #define RTC_TAMPCR_TAMP1E_Pos          (0U)
5099 #define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
5100 #define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk                   /*!<  */
5101 
5102 /********************  Bits definition for RTC_ALRMASSR register  *************/
5103 #define RTC_ALRMASSR_MASKSS_Pos        (24U)
5104 #define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
5105 #define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk
5106 #define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
5107 #define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
5108 #define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
5109 #define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
5110 #define RTC_ALRMASSR_SS_Pos            (0U)
5111 #define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
5112 #define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
5113 
5114 /********************  Bits definition for RTC_ALRMBSSR register  *************/
5115 #define RTC_ALRMBSSR_MASKSS_Pos        (24U)
5116 #define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
5117 #define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk
5118 #define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
5119 #define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
5120 #define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
5121 #define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
5122 #define RTC_ALRMBSSR_SS_Pos            (0U)
5123 #define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
5124 #define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
5125 
5126 /********************  Bits definition for RTC_OR register  ****************/
5127 #define RTC_OR_OUT_RMP_Pos             (1U)
5128 #define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
5129 #define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk                      /*!<  */
5130 #define RTC_OR_ALARMOUTTYPE_Pos        (0U)
5131 #define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
5132 #define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk                 /*!<  */
5133 
5134 /* Legacy defines */
5135 #define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
5136 
5137 /********************  Bits definition for RTC_BKP0R register  ****************/
5138 #define RTC_BKP0R_Pos                  (0U)
5139 #define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
5140 #define RTC_BKP0R                      RTC_BKP0R_Msk                           /*!<  */
5141 
5142 /********************  Bits definition for RTC_BKP1R register  ****************/
5143 #define RTC_BKP1R_Pos                  (0U)
5144 #define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
5145 #define RTC_BKP1R                      RTC_BKP1R_Msk                           /*!<  */
5146 
5147 /********************  Bits definition for RTC_BKP2R register  ****************/
5148 #define RTC_BKP2R_Pos                  (0U)
5149 #define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
5150 #define RTC_BKP2R                      RTC_BKP2R_Msk                           /*!<  */
5151 
5152 /********************  Bits definition for RTC_BKP3R register  ****************/
5153 #define RTC_BKP3R_Pos                  (0U)
5154 #define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
5155 #define RTC_BKP3R                      RTC_BKP3R_Msk                           /*!<  */
5156 
5157 /********************  Bits definition for RTC_BKP4R register  ****************/
5158 #define RTC_BKP4R_Pos                  (0U)
5159 #define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
5160 #define RTC_BKP4R                      RTC_BKP4R_Msk                           /*!<  */
5161 
5162 /******************** Number of backup registers ******************************/
5163 #define RTC_BKP_NUMBER                       (0x00000005U)                  /*!<  */
5164 
5165 /******************************************************************************/
5166 /*                                                                            */
5167 /*                        Serial Peripheral Interface (SPI)                   */
5168 /*                                                                            */
5169 /******************************************************************************/
5170 
5171 /*
5172  * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
5173  */
5174 #define SPI_I2S_SUPPORT                       /*!< I2S support */
5175 
5176 /*******************  Bit definition for SPI_CR1 register  ********************/
5177 #define SPI_CR1_CPHA_Pos            (0U)
5178 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
5179 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!< Clock Phase */
5180 #define SPI_CR1_CPOL_Pos            (1U)
5181 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
5182 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!< Clock Polarity */
5183 #define SPI_CR1_MSTR_Pos            (2U)
5184 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
5185 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!< Master Selection */
5186 #define SPI_CR1_BR_Pos              (3U)
5187 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
5188 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!< BR[2:0] bits (Baud Rate Control) */
5189 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
5190 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
5191 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
5192 #define SPI_CR1_SPE_Pos             (6U)
5193 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
5194 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!< SPI Enable */
5195 #define SPI_CR1_LSBFIRST_Pos        (7U)
5196 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
5197 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!< Frame Format */
5198 #define SPI_CR1_SSI_Pos             (8U)
5199 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
5200 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!< Internal slave select */
5201 #define SPI_CR1_SSM_Pos             (9U)
5202 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
5203 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!< Software slave management */
5204 #define SPI_CR1_RXONLY_Pos          (10U)
5205 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
5206 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!< Receive only */
5207 #define SPI_CR1_DFF_Pos             (11U)
5208 #define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
5209 #define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!< Data Frame Format */
5210 #define SPI_CR1_CRCNEXT_Pos         (12U)
5211 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
5212 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!< Transmit CRC next */
5213 #define SPI_CR1_CRCEN_Pos           (13U)
5214 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
5215 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!< Hardware CRC calculation enable */
5216 #define SPI_CR1_BIDIOE_Pos          (14U)
5217 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
5218 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!< Output enable in bidirectional mode */
5219 #define SPI_CR1_BIDIMODE_Pos        (15U)
5220 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
5221 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!< Bidirectional data mode enable */
5222 
5223 /*******************  Bit definition for SPI_CR2 register  ********************/
5224 #define SPI_CR2_RXDMAEN_Pos         (0U)
5225 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
5226 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
5227 #define SPI_CR2_TXDMAEN_Pos         (1U)
5228 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
5229 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
5230 #define SPI_CR2_SSOE_Pos            (2U)
5231 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
5232 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
5233 #define SPI_CR2_FRF_Pos             (4U)
5234 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
5235 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
5236 #define SPI_CR2_ERRIE_Pos           (5U)
5237 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
5238 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
5239 #define SPI_CR2_RXNEIE_Pos          (6U)
5240 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
5241 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
5242 #define SPI_CR2_TXEIE_Pos           (7U)
5243 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
5244 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
5245 
5246 /********************  Bit definition for SPI_SR register  ********************/
5247 #define SPI_SR_RXNE_Pos             (0U)
5248 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
5249 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
5250 #define SPI_SR_TXE_Pos              (1U)
5251 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
5252 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
5253 #define SPI_SR_CHSIDE_Pos           (2U)
5254 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
5255 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
5256 #define SPI_SR_UDR_Pos              (3U)
5257 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
5258 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
5259 #define SPI_SR_CRCERR_Pos           (4U)
5260 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
5261 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
5262 #define SPI_SR_MODF_Pos             (5U)
5263 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
5264 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
5265 #define SPI_SR_OVR_Pos              (6U)
5266 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
5267 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
5268 #define SPI_SR_BSY_Pos              (7U)
5269 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
5270 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
5271 #define SPI_SR_FRE_Pos              (8U)
5272 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
5273 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
5274 
5275 /********************  Bit definition for SPI_DR register  ********************/
5276 #define SPI_DR_DR_Pos               (0U)
5277 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
5278 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!< Data Register */
5279 
5280 /*******************  Bit definition for SPI_CRCPR register  ******************/
5281 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
5282 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
5283 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!< CRC polynomial register */
5284 
5285 /******************  Bit definition for SPI_RXCRCR register  ******************/
5286 #define SPI_RXCRCR_RXCRC_Pos        (0U)
5287 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
5288 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!< Rx CRC Register */
5289 
5290 /******************  Bit definition for SPI_TXCRCR register  ******************/
5291 #define SPI_TXCRCR_TXCRC_Pos        (0U)
5292 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
5293 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!< Tx CRC Register */
5294 
5295 /******************  Bit definition for SPI_I2SCFGR register  *****************/
5296 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
5297 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
5298 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
5299 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
5300 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
5301 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
5302 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
5303 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
5304 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
5305 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
5306 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
5307 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
5308 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
5309 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
5310 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
5311 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
5312 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
5313 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
5314 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
5315 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
5316 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
5317 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5318 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
5319 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
5320 #define SPI_I2SCFGR_I2SE_Pos        (10U)
5321 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
5322 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
5323 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
5324 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
5325 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
5326 /******************  Bit definition for SPI_I2SPR register  *******************/
5327 #define SPI_I2SPR_I2SDIV_Pos        (0U)
5328 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
5329 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
5330 #define SPI_I2SPR_ODD_Pos           (8U)
5331 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
5332 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
5333 #define SPI_I2SPR_MCKOE_Pos         (9U)
5334 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
5335 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
5336 
5337 /******************************************************************************/
5338 /*                                                                            */
5339 /*                       System Configuration (SYSCFG)                        */
5340 /*                                                                            */
5341 /******************************************************************************/
5342 /*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
5343 #define SYSCFG_CFGR1_MEM_MODE_Pos                (0U)
5344 #define SYSCFG_CFGR1_MEM_MODE_Msk                (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
5345 #define SYSCFG_CFGR1_MEM_MODE                    SYSCFG_CFGR1_MEM_MODE_Msk     /*!< SYSCFG_Memory Remap Config */
5346 #define SYSCFG_CFGR1_MEM_MODE_0                  (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
5347 #define SYSCFG_CFGR1_MEM_MODE_1                  (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
5348 #define SYSCFG_CFGR1_BOOT_MODE_Pos               (8U)
5349 #define SYSCFG_CFGR1_BOOT_MODE_Msk               (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
5350 #define SYSCFG_CFGR1_BOOT_MODE                   SYSCFG_CFGR1_BOOT_MODE_Msk    /*!< SYSCFG_Boot mode Config */
5351 #define SYSCFG_CFGR1_BOOT_MODE_0                 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
5352 #define SYSCFG_CFGR1_BOOT_MODE_1                 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
5353 
5354 /*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
5355 #define SYSCFG_CFGR2_FWDISEN_Pos                 (0U)
5356 #define SYSCFG_CFGR2_FWDISEN_Msk                 (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
5357 #define SYSCFG_CFGR2_FWDISEN                     SYSCFG_CFGR2_FWDISEN_Msk      /*!< Firewall disable bit */
5358 #define SYSCFG_CFGR2_I2C_PB6_FMP_Pos             (8U)
5359 #define SYSCFG_CFGR2_I2C_PB6_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
5360 #define SYSCFG_CFGR2_I2C_PB6_FMP                 SYSCFG_CFGR2_I2C_PB6_FMP_Msk  /*!< I2C PB6 Fast mode plus */
5361 #define SYSCFG_CFGR2_I2C_PB7_FMP_Pos             (9U)
5362 #define SYSCFG_CFGR2_I2C_PB7_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
5363 #define SYSCFG_CFGR2_I2C_PB7_FMP                 SYSCFG_CFGR2_I2C_PB7_FMP_Msk  /*!< I2C PB7 Fast mode plus */
5364 #define SYSCFG_CFGR2_I2C_PB8_FMP_Pos             (10U)
5365 #define SYSCFG_CFGR2_I2C_PB8_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
5366 #define SYSCFG_CFGR2_I2C_PB8_FMP                 SYSCFG_CFGR2_I2C_PB8_FMP_Msk  /*!< I2C PB8 Fast mode plus */
5367 #define SYSCFG_CFGR2_I2C_PB9_FMP_Pos             (11U)
5368 #define SYSCFG_CFGR2_I2C_PB9_FMP_Msk             (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
5369 #define SYSCFG_CFGR2_I2C_PB9_FMP                 SYSCFG_CFGR2_I2C_PB9_FMP_Msk  /*!< I2C PB9 Fast mode plus */
5370 #define SYSCFG_CFGR2_I2C1_FMP_Pos                (12U)
5371 #define SYSCFG_CFGR2_I2C1_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
5372 #define SYSCFG_CFGR2_I2C1_FMP                    SYSCFG_CFGR2_I2C1_FMP_Msk     /*!< I2C1 Fast mode plus */
5373 #define SYSCFG_CFGR2_I2C2_FMP_Pos                (13U)
5374 #define SYSCFG_CFGR2_I2C2_FMP_Msk                (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
5375 #define SYSCFG_CFGR2_I2C2_FMP                    SYSCFG_CFGR2_I2C2_FMP_Msk     /*!< I2C2 Fast mode plus */
5376 
5377 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
5378 #define SYSCFG_EXTICR1_EXTI0_Pos                 (0U)
5379 #define SYSCFG_EXTICR1_EXTI0_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
5380 #define SYSCFG_EXTICR1_EXTI0                     SYSCFG_EXTICR1_EXTI0_Msk      /*!< EXTI 0 configuration */
5381 #define SYSCFG_EXTICR1_EXTI1_Pos                 (4U)
5382 #define SYSCFG_EXTICR1_EXTI1_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
5383 #define SYSCFG_EXTICR1_EXTI1                     SYSCFG_EXTICR1_EXTI1_Msk      /*!< EXTI 1 configuration */
5384 #define SYSCFG_EXTICR1_EXTI2_Pos                 (8U)
5385 #define SYSCFG_EXTICR1_EXTI2_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
5386 #define SYSCFG_EXTICR1_EXTI2                     SYSCFG_EXTICR1_EXTI2_Msk      /*!< EXTI 2 configuration */
5387 #define SYSCFG_EXTICR1_EXTI3_Pos                 (12U)
5388 #define SYSCFG_EXTICR1_EXTI3_Msk                 (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
5389 #define SYSCFG_EXTICR1_EXTI3                     SYSCFG_EXTICR1_EXTI3_Msk      /*!< EXTI 3 configuration */
5390 
5391 /**
5392   * @brief  EXTI0 configuration
5393   */
5394 #define SYSCFG_EXTICR1_EXTI0_PA                  (0x00000000U)                 /*!< PA[0] pin */
5395 #define SYSCFG_EXTICR1_EXTI0_PB                  (0x00000001U)                 /*!< PB[0] pin */
5396 #define SYSCFG_EXTICR1_EXTI0_PC                  (0x00000002U)                 /*!< PC[0] pin */
5397 #define SYSCFG_EXTICR1_EXTI0_PH                  (0x00000005U)                 /*!< PH[0] pin */
5398 
5399 /**
5400   * @brief  EXTI1 configuration
5401   */
5402 #define SYSCFG_EXTICR1_EXTI1_PA                  (0x00000000U)                 /*!< PA[1] pin */
5403 #define SYSCFG_EXTICR1_EXTI1_PB                  (0x00000010U)                 /*!< PB[1] pin */
5404 #define SYSCFG_EXTICR1_EXTI1_PC                  (0x00000020U)                 /*!< PC[1] pin */
5405 #define SYSCFG_EXTICR1_EXTI1_PH                  (0x00000050U)                 /*!< PH[1] pin */
5406 
5407 /**
5408   * @brief  EXTI2 configuration
5409   */
5410 #define SYSCFG_EXTICR1_EXTI2_PA                  (0x00000000U)                 /*!< PA[2] pin */
5411 #define SYSCFG_EXTICR1_EXTI2_PB                  (0x00000100U)                 /*!< PB[2] pin */
5412 #define SYSCFG_EXTICR1_EXTI2_PC                  (0x00000200U)                 /*!< PC[2] pin */
5413 #define SYSCFG_EXTICR1_EXTI2_PD                  (0x00000300U)                 /*!< PD[2] pin */
5414 
5415 /**
5416   * @brief  EXTI3 configuration
5417   */
5418 #define SYSCFG_EXTICR1_EXTI3_PA                  (0x00000000U)                 /*!< PA[3] pin */
5419 #define SYSCFG_EXTICR1_EXTI3_PB                  (0x00001000U)                 /*!< PB[3] pin */
5420 #define SYSCFG_EXTICR1_EXTI3_PC                  (0x00002000U)                 /*!< PC[3] pin */
5421 
5422 /*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
5423 #define SYSCFG_EXTICR2_EXTI4_Pos                 (0U)
5424 #define SYSCFG_EXTICR2_EXTI4_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
5425 #define SYSCFG_EXTICR2_EXTI4                     SYSCFG_EXTICR2_EXTI4_Msk      /*!< EXTI 4 configuration */
5426 #define SYSCFG_EXTICR2_EXTI5_Pos                 (4U)
5427 #define SYSCFG_EXTICR2_EXTI5_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
5428 #define SYSCFG_EXTICR2_EXTI5                     SYSCFG_EXTICR2_EXTI5_Msk      /*!< EXTI 5 configuration */
5429 #define SYSCFG_EXTICR2_EXTI6_Pos                 (8U)
5430 #define SYSCFG_EXTICR2_EXTI6_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
5431 #define SYSCFG_EXTICR2_EXTI6                     SYSCFG_EXTICR2_EXTI6_Msk      /*!< EXTI 6 configuration */
5432 #define SYSCFG_EXTICR2_EXTI7_Pos                 (12U)
5433 #define SYSCFG_EXTICR2_EXTI7_Msk                 (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
5434 #define SYSCFG_EXTICR2_EXTI7                     SYSCFG_EXTICR2_EXTI7_Msk      /*!< EXTI 7 configuration */
5435 
5436 /**
5437   * @brief  EXTI4 configuration
5438   */
5439 #define SYSCFG_EXTICR2_EXTI4_PA                  (0x00000000U)                 /*!< PA[4] pin */
5440 #define SYSCFG_EXTICR2_EXTI4_PB                  (0x00000001U)                 /*!< PB[4] pin */
5441 #define SYSCFG_EXTICR2_EXTI4_PC                  (0x00000002U)                 /*!< PC[4] pin */
5442 
5443 /**
5444   * @brief  EXTI5 configuration
5445   */
5446 #define SYSCFG_EXTICR2_EXTI5_PA                  (0x00000000U)                 /*!< PA[5] pin */
5447 #define SYSCFG_EXTICR2_EXTI5_PB                  (0x00000010U)                 /*!< PB[5] pin */
5448 #define SYSCFG_EXTICR2_EXTI5_PC                  (0x00000020U)                 /*!< PC[5] pin */
5449 
5450 /**
5451   * @brief  EXTI6 configuration
5452   */
5453 #define SYSCFG_EXTICR2_EXTI6_PA                  (0x00000000U)                 /*!< PA[6] pin */
5454 #define SYSCFG_EXTICR2_EXTI6_PB                  (0x00000100U)                 /*!< PB[6] pin */
5455 #define SYSCFG_EXTICR2_EXTI6_PC                  (0x00000200U)                 /*!< PC[6] pin */
5456 
5457 /**
5458   * @brief  EXTI7 configuration
5459   */
5460 #define SYSCFG_EXTICR2_EXTI7_PA                  (0x00000000U)                 /*!< PA[7] pin */
5461 #define SYSCFG_EXTICR2_EXTI7_PB                  (0x00001000U)                 /*!< PB[7] pin */
5462 #define SYSCFG_EXTICR2_EXTI7_PC                  (0x00002000U)                 /*!< PC[7] pin */
5463 
5464 /*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
5465 #define SYSCFG_EXTICR3_EXTI8_Pos                 (0U)
5466 #define SYSCFG_EXTICR3_EXTI8_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
5467 #define SYSCFG_EXTICR3_EXTI8                     SYSCFG_EXTICR3_EXTI8_Msk      /*!< EXTI 8 configuration */
5468 #define SYSCFG_EXTICR3_EXTI9_Pos                 (4U)
5469 #define SYSCFG_EXTICR3_EXTI9_Msk                 (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
5470 #define SYSCFG_EXTICR3_EXTI9                     SYSCFG_EXTICR3_EXTI9_Msk      /*!< EXTI 9 configuration */
5471 #define SYSCFG_EXTICR3_EXTI10_Pos                (8U)
5472 #define SYSCFG_EXTICR3_EXTI10_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
5473 #define SYSCFG_EXTICR3_EXTI10                    SYSCFG_EXTICR3_EXTI10_Msk     /*!< EXTI 10 configuration */
5474 #define SYSCFG_EXTICR3_EXTI11_Pos                (12U)
5475 #define SYSCFG_EXTICR3_EXTI11_Msk                (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
5476 #define SYSCFG_EXTICR3_EXTI11                    SYSCFG_EXTICR3_EXTI11_Msk     /*!< EXTI 11 configuration */
5477 
5478 /**
5479   * @brief  EXTI8 configuration
5480   */
5481 #define SYSCFG_EXTICR3_EXTI8_PA                  (0x00000000U)                 /*!< PA[8] pin */
5482 #define SYSCFG_EXTICR3_EXTI8_PB                  (0x00000001U)                 /*!< PB[8] pin */
5483 #define SYSCFG_EXTICR3_EXTI8_PC                  (0x00000002U)                 /*!< PC[8] pin */
5484 
5485 /**
5486   * @brief  EXTI9 configuration
5487   */
5488 #define SYSCFG_EXTICR3_EXTI9_PA                  (0x00000000U)                 /*!< PA[9] pin */
5489 #define SYSCFG_EXTICR3_EXTI9_PB                  (0x00000010U)                 /*!< PB[9] pin */
5490 #define SYSCFG_EXTICR3_EXTI9_PC                  (0x00000020U)                 /*!< PC[9] pin */
5491 
5492 /**
5493   * @brief  EXTI10 configuration
5494   */
5495 #define SYSCFG_EXTICR3_EXTI10_PA                 (0x00000000U)                 /*!< PA[10] pin */
5496 #define SYSCFG_EXTICR3_EXTI10_PB                 (0x00000100U)                 /*!< PB[10] pin */
5497 #define SYSCFG_EXTICR3_EXTI10_PC                 (0x00000200U)                 /*!< PC[10] pin */
5498 
5499 /**
5500   * @brief  EXTI11 configuration
5501   */
5502 #define SYSCFG_EXTICR3_EXTI11_PA                 (0x00000000U)                 /*!< PA[11] pin */
5503 #define SYSCFG_EXTICR3_EXTI11_PB                 (0x00001000U)                 /*!< PB[11] pin */
5504 #define SYSCFG_EXTICR3_EXTI11_PC                 (0x00002000U)                 /*!< PC[11] pin */
5505 
5506 /*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
5507 #define SYSCFG_EXTICR4_EXTI12_Pos                (0U)
5508 #define SYSCFG_EXTICR4_EXTI12_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
5509 #define SYSCFG_EXTICR4_EXTI12                    SYSCFG_EXTICR4_EXTI12_Msk     /*!< EXTI 12 configuration */
5510 #define SYSCFG_EXTICR4_EXTI13_Pos                (4U)
5511 #define SYSCFG_EXTICR4_EXTI13_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
5512 #define SYSCFG_EXTICR4_EXTI13                    SYSCFG_EXTICR4_EXTI13_Msk     /*!< EXTI 13 configuration */
5513 #define SYSCFG_EXTICR4_EXTI14_Pos                (8U)
5514 #define SYSCFG_EXTICR4_EXTI14_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
5515 #define SYSCFG_EXTICR4_EXTI14                    SYSCFG_EXTICR4_EXTI14_Msk     /*!< EXTI 14 configuration */
5516 #define SYSCFG_EXTICR4_EXTI15_Pos                (12U)
5517 #define SYSCFG_EXTICR4_EXTI15_Msk                (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
5518 #define SYSCFG_EXTICR4_EXTI15                    SYSCFG_EXTICR4_EXTI15_Msk     /*!< EXTI 15 configuration */
5519 
5520 /**
5521   * @brief  EXTI12 configuration
5522   */
5523 #define SYSCFG_EXTICR4_EXTI12_PA                 (0x00000000U)                 /*!< PA[12] pin */
5524 #define SYSCFG_EXTICR4_EXTI12_PB                 (0x00000001U)                 /*!< PB[12] pin */
5525 #define SYSCFG_EXTICR4_EXTI12_PC                 (0x00000002U)                 /*!< PC[12] pin */
5526 
5527 /**
5528   * @brief  EXTI13 configuration
5529   */
5530 #define SYSCFG_EXTICR4_EXTI13_PA                 (0x00000000U)                 /*!< PA[13] pin */
5531 #define SYSCFG_EXTICR4_EXTI13_PB                 (0x00000010U)                 /*!< PB[13] pin */
5532 #define SYSCFG_EXTICR4_EXTI13_PC                 (0x00000020U)                 /*!< PC[13] pin */
5533 
5534 /**
5535   * @brief  EXTI14 configuration
5536   */
5537 #define SYSCFG_EXTICR4_EXTI14_PA                 (0x00000000U)                 /*!< PA[14] pin */
5538 #define SYSCFG_EXTICR4_EXTI14_PB                 (0x00000100U)                 /*!< PB[14] pin */
5539 #define SYSCFG_EXTICR4_EXTI14_PC                 (0x00000200U)                 /*!< PC[14] pin */
5540 
5541 /**
5542   * @brief  EXTI15 configuration
5543   */
5544 #define SYSCFG_EXTICR4_EXTI15_PA                 (0x00000000U)                 /*!< PA[15] pin */
5545 #define SYSCFG_EXTICR4_EXTI15_PB                 (0x00001000U)                 /*!< PB[15] pin */
5546 #define SYSCFG_EXTICR4_EXTI15_PC                 (0x00002000U)                 /*!< PC[15] pin */
5547 
5548 
5549 /*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
5550 #define SYSCFG_CFGR3_EN_VREFINT_Pos              (0U)
5551 #define SYSCFG_CFGR3_EN_VREFINT_Msk              (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
5552 #define SYSCFG_CFGR3_EN_VREFINT                  SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
5553 #define SYSCFG_CFGR3_VREF_OUT_Pos                (4U)
5554 #define SYSCFG_CFGR3_VREF_OUT_Msk                (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
5555 #define SYSCFG_CFGR3_VREF_OUT                    SYSCFG_CFGR3_VREF_OUT_Msk     /*!< Verf_ADC connection bit */
5556 #define SYSCFG_CFGR3_VREF_OUT_0                  (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
5557 #define SYSCFG_CFGR3_VREF_OUT_1                  (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
5558 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos       (8U)
5559 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk       (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
5560 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
5561 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos        (9U)
5562 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk        (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
5563 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC            SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
5564 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos    (12U)
5565 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk    (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
5566 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
5567 #define SYSCFG_CFGR3_ENREF_HSI48_Pos             (13U)
5568 #define SYSCFG_CFGR3_ENREF_HSI48_Msk             (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
5569 #define SYSCFG_CFGR3_ENREF_HSI48                 SYSCFG_CFGR3_ENREF_HSI48_Msk  /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
5570 #define SYSCFG_CFGR3_VREFINT_RDYF_Pos            (30U)
5571 #define SYSCFG_CFGR3_VREFINT_RDYF_Msk            (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
5572 #define SYSCFG_CFGR3_VREFINT_RDYF                SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
5573 #define SYSCFG_CFGR3_REF_LOCK_Pos                (31U)
5574 #define SYSCFG_CFGR3_REF_LOCK_Msk                (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
5575 #define SYSCFG_CFGR3_REF_LOCK                    SYSCFG_CFGR3_REF_LOCK_Msk     /*!< CFGR3 lock bit */
5576 
5577 /* Legacy defines */
5578 
5579 #define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
5580 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
5581 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
5582 #define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
5583 #define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
5584 #define SYSCFG_CFGR3_REF_HSI48_RDYF           SYSCFG_CFGR3_VREFINT_RDYF
5585 #define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_RDYF
5586 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF          SYSCFG_CFGR3_VREFINT_RDYF
5587 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF         SYSCFG_CFGR3_VREFINT_RDYF
5588 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF        SYSCFG_CFGR3_VREFINT_RDYF
5589 
5590 /******************************************************************************/
5591 /*                                                                            */
5592 /*                               Timers (TIM)*/
5593 /*                                                                            */
5594 /******************************************************************************/
5595 /*
5596 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
5597 */
5598 #define TIM_TIM2_REMAP_HSI48_SUPPORT     /*!<Support remap HSI48 on TIM2 */
5599 
5600 /*******************  Bit definition for TIM_CR1 register  ********************/
5601 #define TIM_CR1_CEN_Pos           (0U)
5602 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
5603 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
5604 #define TIM_CR1_UDIS_Pos          (1U)
5605 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
5606 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
5607 #define TIM_CR1_URS_Pos           (2U)
5608 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
5609 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
5610 #define TIM_CR1_OPM_Pos           (3U)
5611 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
5612 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
5613 #define TIM_CR1_DIR_Pos           (4U)
5614 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
5615 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
5616 
5617 #define TIM_CR1_CMS_Pos           (5U)
5618 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
5619 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
5620 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
5621 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
5622 
5623 #define TIM_CR1_ARPE_Pos          (7U)
5624 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
5625 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
5626 
5627 #define TIM_CR1_CKD_Pos           (8U)
5628 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
5629 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
5630 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
5631 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
5632 
5633 /*******************  Bit definition for TIM_CR2 register  ********************/
5634 #define TIM_CR2_CCDS_Pos          (3U)
5635 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
5636 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
5637 
5638 #define TIM_CR2_MMS_Pos           (4U)
5639 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
5640 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
5641 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
5642 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
5643 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
5644 
5645 #define TIM_CR2_TI1S_Pos          (7U)
5646 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
5647 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
5648 
5649 /*******************  Bit definition for TIM_SMCR register  *******************/
5650 #define TIM_SMCR_SMS_Pos          (0U)
5651 #define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
5652 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
5653 #define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
5654 #define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
5655 #define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
5656 
5657 #define TIM_SMCR_TS_Pos           (4U)
5658 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
5659 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
5660 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
5661 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
5662 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
5663 
5664 #define TIM_SMCR_MSM_Pos          (7U)
5665 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
5666 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
5667 
5668 #define TIM_SMCR_ETF_Pos          (8U)
5669 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
5670 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
5671 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
5672 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
5673 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
5674 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
5675 
5676 #define TIM_SMCR_ETPS_Pos         (12U)
5677 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
5678 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
5679 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
5680 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
5681 
5682 #define TIM_SMCR_ECE_Pos          (14U)
5683 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
5684 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
5685 #define TIM_SMCR_ETP_Pos          (15U)
5686 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
5687 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
5688 
5689 /*******************  Bit definition for TIM_DIER register  *******************/
5690 #define TIM_DIER_UIE_Pos          (0U)
5691 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
5692 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
5693 #define TIM_DIER_CC1IE_Pos        (1U)
5694 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
5695 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
5696 #define TIM_DIER_CC2IE_Pos        (2U)
5697 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
5698 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
5699 #define TIM_DIER_CC3IE_Pos        (3U)
5700 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
5701 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
5702 #define TIM_DIER_CC4IE_Pos        (4U)
5703 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
5704 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
5705 #define TIM_DIER_TIE_Pos          (6U)
5706 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
5707 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
5708 #define TIM_DIER_UDE_Pos          (8U)
5709 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
5710 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
5711 #define TIM_DIER_CC1DE_Pos        (9U)
5712 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
5713 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
5714 #define TIM_DIER_CC2DE_Pos        (10U)
5715 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
5716 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
5717 #define TIM_DIER_CC3DE_Pos        (11U)
5718 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
5719 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
5720 #define TIM_DIER_CC4DE_Pos        (12U)
5721 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
5722 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
5723 #define TIM_DIER_TDE_Pos          (14U)
5724 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
5725 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
5726 
5727 /********************  Bit definition for TIM_SR register  ********************/
5728 #define TIM_SR_UIF_Pos            (0U)
5729 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
5730 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
5731 #define TIM_SR_CC1IF_Pos          (1U)
5732 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
5733 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
5734 #define TIM_SR_CC2IF_Pos          (2U)
5735 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
5736 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
5737 #define TIM_SR_CC3IF_Pos          (3U)
5738 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
5739 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
5740 #define TIM_SR_CC4IF_Pos          (4U)
5741 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
5742 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
5743 #define TIM_SR_TIF_Pos            (6U)
5744 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
5745 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
5746 #define TIM_SR_CC1OF_Pos          (9U)
5747 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
5748 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
5749 #define TIM_SR_CC2OF_Pos          (10U)
5750 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
5751 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
5752 #define TIM_SR_CC3OF_Pos          (11U)
5753 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
5754 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
5755 #define TIM_SR_CC4OF_Pos          (12U)
5756 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
5757 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
5758 
5759 /*******************  Bit definition for TIM_EGR register  ********************/
5760 #define TIM_EGR_UG_Pos            (0U)
5761 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
5762 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
5763 #define TIM_EGR_CC1G_Pos          (1U)
5764 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
5765 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
5766 #define TIM_EGR_CC2G_Pos          (2U)
5767 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
5768 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
5769 #define TIM_EGR_CC3G_Pos          (3U)
5770 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
5771 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
5772 #define TIM_EGR_CC4G_Pos          (4U)
5773 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
5774 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
5775 #define TIM_EGR_TG_Pos            (6U)
5776 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
5777 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
5778 
5779 /******************  Bit definition for TIM_CCMR1 register  *******************/
5780 #define TIM_CCMR1_CC1S_Pos        (0U)
5781 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
5782 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
5783 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
5784 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
5785 
5786 #define TIM_CCMR1_OC1FE_Pos       (2U)
5787 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
5788 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
5789 #define TIM_CCMR1_OC1PE_Pos       (3U)
5790 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
5791 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
5792 
5793 #define TIM_CCMR1_OC1M_Pos        (4U)
5794 #define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
5795 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
5796 #define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
5797 #define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
5798 #define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
5799 
5800 #define TIM_CCMR1_OC1CE_Pos       (7U)
5801 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
5802 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
5803 
5804 #define TIM_CCMR1_CC2S_Pos        (8U)
5805 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
5806 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
5807 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
5808 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
5809 
5810 #define TIM_CCMR1_OC2FE_Pos       (10U)
5811 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
5812 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
5813 #define TIM_CCMR1_OC2PE_Pos       (11U)
5814 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
5815 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
5816 
5817 #define TIM_CCMR1_OC2M_Pos        (12U)
5818 #define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
5819 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
5820 #define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
5821 #define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
5822 #define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
5823 
5824 #define TIM_CCMR1_OC2CE_Pos       (15U)
5825 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
5826 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
5827 
5828 /*----------------------------------------------------------------------------*/
5829 
5830 #define TIM_CCMR1_IC1PSC_Pos      (2U)
5831 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
5832 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
5833 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
5834 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
5835 
5836 #define TIM_CCMR1_IC1F_Pos        (4U)
5837 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
5838 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
5839 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
5840 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
5841 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
5842 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
5843 
5844 #define TIM_CCMR1_IC2PSC_Pos      (10U)
5845 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
5846 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
5847 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
5848 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
5849 
5850 #define TIM_CCMR1_IC2F_Pos        (12U)
5851 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
5852 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
5853 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
5854 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
5855 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
5856 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
5857 
5858 /******************  Bit definition for TIM_CCMR2 register  *******************/
5859 #define TIM_CCMR2_CC3S_Pos        (0U)
5860 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
5861 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
5862 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
5863 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
5864 
5865 #define TIM_CCMR2_OC3FE_Pos       (2U)
5866 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
5867 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
5868 #define TIM_CCMR2_OC3PE_Pos       (3U)
5869 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
5870 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
5871 
5872 #define TIM_CCMR2_OC3M_Pos        (4U)
5873 #define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
5874 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
5875 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
5876 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
5877 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
5878 
5879 #define TIM_CCMR2_OC3CE_Pos       (7U)
5880 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
5881 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
5882 
5883 #define TIM_CCMR2_CC4S_Pos        (8U)
5884 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
5885 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
5886 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
5887 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
5888 
5889 #define TIM_CCMR2_OC4FE_Pos       (10U)
5890 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
5891 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
5892 #define TIM_CCMR2_OC4PE_Pos       (11U)
5893 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
5894 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
5895 
5896 #define TIM_CCMR2_OC4M_Pos        (12U)
5897 #define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
5898 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
5899 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
5900 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
5901 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
5902 
5903 #define TIM_CCMR2_OC4CE_Pos       (15U)
5904 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
5905 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
5906 
5907 /*----------------------------------------------------------------------------*/
5908 
5909 #define TIM_CCMR2_IC3PSC_Pos      (2U)
5910 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
5911 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
5912 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
5913 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
5914 
5915 #define TIM_CCMR2_IC3F_Pos        (4U)
5916 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
5917 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
5918 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
5919 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
5920 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
5921 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
5922 
5923 #define TIM_CCMR2_IC4PSC_Pos      (10U)
5924 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
5925 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
5926 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
5927 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
5928 
5929 #define TIM_CCMR2_IC4F_Pos        (12U)
5930 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
5931 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
5932 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
5933 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
5934 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
5935 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
5936 
5937 /*******************  Bit definition for TIM_CCER register  *******************/
5938 #define TIM_CCER_CC1E_Pos         (0U)
5939 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
5940 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
5941 #define TIM_CCER_CC1P_Pos         (1U)
5942 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
5943 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
5944 #define TIM_CCER_CC1NP_Pos        (3U)
5945 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
5946 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
5947 #define TIM_CCER_CC2E_Pos         (4U)
5948 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
5949 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
5950 #define TIM_CCER_CC2P_Pos         (5U)
5951 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
5952 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
5953 #define TIM_CCER_CC2NP_Pos        (7U)
5954 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
5955 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
5956 #define TIM_CCER_CC3E_Pos         (8U)
5957 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
5958 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
5959 #define TIM_CCER_CC3P_Pos         (9U)
5960 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
5961 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
5962 #define TIM_CCER_CC3NP_Pos        (11U)
5963 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
5964 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
5965 #define TIM_CCER_CC4E_Pos         (12U)
5966 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
5967 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
5968 #define TIM_CCER_CC4P_Pos         (13U)
5969 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
5970 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
5971 #define TIM_CCER_CC4NP_Pos        (15U)
5972 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
5973 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
5974 
5975 /*******************  Bit definition for TIM_CNT register  ********************/
5976 #define TIM_CNT_CNT_Pos           (0U)
5977 #define TIM_CNT_CNT_Msk           (0xFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0x0000FFFF */
5978 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
5979 
5980 /*******************  Bit definition for TIM_PSC register  ********************/
5981 #define TIM_PSC_PSC_Pos           (0U)
5982 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
5983 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
5984 
5985 /*******************  Bit definition for TIM_ARR register  ********************/
5986 #define TIM_ARR_ARR_Pos           (0U)
5987 #define TIM_ARR_ARR_Msk           (0xFFFFUL << TIM_ARR_ARR_Pos)                 /*!< 0x0000FFFF */
5988 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
5989 
5990 /*******************  Bit definition for TIM_CCR1 register  *******************/
5991 #define TIM_CCR1_CCR1_Pos         (0U)
5992 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
5993 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
5994 
5995 /*******************  Bit definition for TIM_CCR2 register  *******************/
5996 #define TIM_CCR2_CCR2_Pos         (0U)
5997 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
5998 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
5999 
6000 /*******************  Bit definition for TIM_CCR3 register  *******************/
6001 #define TIM_CCR3_CCR3_Pos         (0U)
6002 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
6003 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
6004 
6005 /*******************  Bit definition for TIM_CCR4 register  *******************/
6006 #define TIM_CCR4_CCR4_Pos         (0U)
6007 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
6008 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
6009 
6010 /*******************  Bit definition for TIM_DCR register  ********************/
6011 #define TIM_DCR_DBA_Pos           (0U)
6012 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
6013 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
6014 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
6015 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
6016 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
6017 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
6018 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
6019 
6020 #define TIM_DCR_DBL_Pos           (8U)
6021 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
6022 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
6023 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
6024 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
6025 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
6026 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
6027 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
6028 
6029 /*******************  Bit definition for TIM_DMAR register  *******************/
6030 #define TIM_DMAR_DMAB_Pos         (0U)
6031 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
6032 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
6033 
6034 /*******************  Bit definition for TIM_OR register  *********************/
6035 #define TIM2_OR_ETR_RMP_Pos      (0U)
6036 #define TIM2_OR_ETR_RMP_Msk      (0x7UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000007 */
6037 #define TIM2_OR_ETR_RMP          TIM2_OR_ETR_RMP_Msk                           /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
6038 #define TIM2_OR_ETR_RMP_0        (0x1UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000001 */
6039 #define TIM2_OR_ETR_RMP_1        (0x2UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000002 */
6040 #define TIM2_OR_ETR_RMP_2        (0x4UL << TIM2_OR_ETR_RMP_Pos)                 /*!< 0x00000004 */
6041 #define TIM2_OR_TI4_RMP_Pos      (3U)
6042 #define TIM2_OR_TI4_RMP_Msk      (0x3UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000018 */
6043 #define TIM2_OR_TI4_RMP          TIM2_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
6044 #define TIM2_OR_TI4_RMP_0        (0x1UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000008 */
6045 #define TIM2_OR_TI4_RMP_1        (0x2UL << TIM2_OR_TI4_RMP_Pos)                 /*!< 0x00000010 */
6046 
6047 #define TIM21_OR_ETR_RMP_Pos      (0U)
6048 #define TIM21_OR_ETR_RMP_Msk      (0x3UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
6049 #define TIM21_OR_ETR_RMP          TIM21_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
6050 #define TIM21_OR_ETR_RMP_0        (0x1UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
6051 #define TIM21_OR_ETR_RMP_1        (0x2UL << TIM21_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
6052 #define TIM21_OR_TI1_RMP_Pos      (2U)
6053 #define TIM21_OR_TI1_RMP_Msk      (0x7UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x0000001C */
6054 #define TIM21_OR_TI1_RMP          TIM21_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
6055 #define TIM21_OR_TI1_RMP_0        (0x1UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
6056 #define TIM21_OR_TI1_RMP_1        (0x2UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
6057 #define TIM21_OR_TI1_RMP_2        (0x4UL << TIM21_OR_TI1_RMP_Pos)               /*!< 0x00000010 */
6058 #define TIM21_OR_TI2_RMP_Pos      (5U)
6059 #define TIM21_OR_TI2_RMP_Msk      (0x1UL << TIM21_OR_TI2_RMP_Pos)               /*!< 0x00000020 */
6060 #define TIM21_OR_TI2_RMP          TIM21_OR_TI2_RMP_Msk                         /*!<TI2_RMP bit (TIM21 Input 2 remap) */
6061 
6062 #define TIM22_OR_ETR_RMP_Pos      (0U)
6063 #define TIM22_OR_ETR_RMP_Msk      (0x3UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000003 */
6064 #define TIM22_OR_ETR_RMP          TIM22_OR_ETR_RMP_Msk                         /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
6065 #define TIM22_OR_ETR_RMP_0        (0x1UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000001 */
6066 #define TIM22_OR_ETR_RMP_1        (0x2UL << TIM22_OR_ETR_RMP_Pos)               /*!< 0x00000002 */
6067 #define TIM22_OR_TI1_RMP_Pos      (2U)
6068 #define TIM22_OR_TI1_RMP_Msk      (0x3UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x0000000C */
6069 #define TIM22_OR_TI1_RMP          TIM22_OR_TI1_RMP_Msk                         /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
6070 #define TIM22_OR_TI1_RMP_0        (0x1UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000004 */
6071 #define TIM22_OR_TI1_RMP_1        (0x2UL << TIM22_OR_TI1_RMP_Pos)               /*!< 0x00000008 */
6072 
6073 
6074 /******************************************************************************/
6075 /*                                                                            */
6076 /*                          Touch Sensing Controller (TSC)                    */
6077 /*                                                                            */
6078 /******************************************************************************/
6079 /*******************  Bit definition for TSC_CR register  *********************/
6080 #define TSC_CR_TSCE_Pos          (0U)
6081 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
6082 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
6083 #define TSC_CR_START_Pos         (1U)
6084 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                    /*!< 0x00000002 */
6085 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
6086 #define TSC_CR_AM_Pos            (2U)
6087 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
6088 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
6089 #define TSC_CR_SYNCPOL_Pos       (3U)
6090 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
6091 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
6092 #define TSC_CR_IODEF_Pos         (4U)
6093 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
6094 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
6095 
6096 #define TSC_CR_MCV_Pos           (5U)
6097 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
6098 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
6099 #define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
6100 #define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
6101 #define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
6102 
6103 #define TSC_CR_PGPSC_Pos         (12U)
6104 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
6105 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
6106 #define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
6107 #define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
6108 #define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
6109 
6110 #define TSC_CR_SSPSC_Pos         (15U)
6111 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
6112 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
6113 #define TSC_CR_SSE_Pos           (16U)
6114 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
6115 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
6116 
6117 #define TSC_CR_SSD_Pos           (17U)
6118 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
6119 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
6120 #define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
6121 #define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
6122 #define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
6123 #define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
6124 #define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
6125 #define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
6126 #define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
6127 
6128 #define TSC_CR_CTPL_Pos          (24U)
6129 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
6130 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
6131 #define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
6132 #define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
6133 #define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
6134 #define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
6135 
6136 #define TSC_CR_CTPH_Pos          (28U)
6137 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
6138 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
6139 #define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
6140 #define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
6141 #define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
6142 #define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
6143 
6144 /*******************  Bit definition for TSC_IER register  ********************/
6145 #define TSC_IER_EOAIE_Pos        (0U)
6146 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
6147 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
6148 #define TSC_IER_MCEIE_Pos        (1U)
6149 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
6150 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
6151 
6152 /*******************  Bit definition for TSC_ICR register  ********************/
6153 #define TSC_ICR_EOAIC_Pos        (0U)
6154 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
6155 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
6156 #define TSC_ICR_MCEIC_Pos        (1U)
6157 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
6158 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
6159 
6160 /*******************  Bit definition for TSC_ISR register  ********************/
6161 #define TSC_ISR_EOAF_Pos         (0U)
6162 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
6163 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
6164 #define TSC_ISR_MCEF_Pos         (1U)
6165 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
6166 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
6167 
6168 /*******************  Bit definition for TSC_IOHCR register  ******************/
6169 #define TSC_IOHCR_G1_IO1_Pos     (0U)
6170 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
6171 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
6172 #define TSC_IOHCR_G1_IO2_Pos     (1U)
6173 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
6174 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
6175 #define TSC_IOHCR_G1_IO3_Pos     (2U)
6176 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
6177 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
6178 #define TSC_IOHCR_G1_IO4_Pos     (3U)
6179 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
6180 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
6181 #define TSC_IOHCR_G2_IO1_Pos     (4U)
6182 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
6183 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
6184 #define TSC_IOHCR_G2_IO2_Pos     (5U)
6185 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
6186 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
6187 #define TSC_IOHCR_G2_IO3_Pos     (6U)
6188 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
6189 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
6190 #define TSC_IOHCR_G2_IO4_Pos     (7U)
6191 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
6192 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
6193 #define TSC_IOHCR_G3_IO1_Pos     (8U)
6194 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
6195 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
6196 #define TSC_IOHCR_G3_IO2_Pos     (9U)
6197 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
6198 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
6199 #define TSC_IOHCR_G3_IO3_Pos     (10U)
6200 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
6201 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
6202 #define TSC_IOHCR_G3_IO4_Pos     (11U)
6203 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
6204 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
6205 #define TSC_IOHCR_G4_IO1_Pos     (12U)
6206 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
6207 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
6208 #define TSC_IOHCR_G4_IO2_Pos     (13U)
6209 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
6210 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
6211 #define TSC_IOHCR_G4_IO3_Pos     (14U)
6212 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
6213 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
6214 #define TSC_IOHCR_G4_IO4_Pos     (15U)
6215 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
6216 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
6217 #define TSC_IOHCR_G5_IO1_Pos     (16U)
6218 #define TSC_IOHCR_G5_IO1_Msk     (0x1UL << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
6219 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
6220 #define TSC_IOHCR_G5_IO2_Pos     (17U)
6221 #define TSC_IOHCR_G5_IO2_Msk     (0x1UL << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
6222 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
6223 #define TSC_IOHCR_G5_IO3_Pos     (18U)
6224 #define TSC_IOHCR_G5_IO3_Msk     (0x1UL << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
6225 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
6226 #define TSC_IOHCR_G5_IO4_Pos     (19U)
6227 #define TSC_IOHCR_G5_IO4_Msk     (0x1UL << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
6228 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
6229 #define TSC_IOHCR_G6_IO1_Pos     (20U)
6230 #define TSC_IOHCR_G6_IO1_Msk     (0x1UL << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
6231 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
6232 #define TSC_IOHCR_G6_IO2_Pos     (21U)
6233 #define TSC_IOHCR_G6_IO2_Msk     (0x1UL << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
6234 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
6235 #define TSC_IOHCR_G6_IO3_Pos     (22U)
6236 #define TSC_IOHCR_G6_IO3_Msk     (0x1UL << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
6237 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
6238 #define TSC_IOHCR_G6_IO4_Pos     (23U)
6239 #define TSC_IOHCR_G6_IO4_Msk     (0x1UL << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
6240 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
6241 #define TSC_IOHCR_G7_IO1_Pos     (24U)
6242 #define TSC_IOHCR_G7_IO1_Msk     (0x1UL << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
6243 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
6244 #define TSC_IOHCR_G7_IO2_Pos     (25U)
6245 #define TSC_IOHCR_G7_IO2_Msk     (0x1UL << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
6246 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
6247 #define TSC_IOHCR_G7_IO3_Pos     (26U)
6248 #define TSC_IOHCR_G7_IO3_Msk     (0x1UL << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
6249 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
6250 #define TSC_IOHCR_G7_IO4_Pos     (27U)
6251 #define TSC_IOHCR_G7_IO4_Msk     (0x1UL << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
6252 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
6253 #define TSC_IOHCR_G8_IO1_Pos     (28U)
6254 #define TSC_IOHCR_G8_IO1_Msk     (0x1UL << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
6255 #define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
6256 #define TSC_IOHCR_G8_IO2_Pos     (29U)
6257 #define TSC_IOHCR_G8_IO2_Msk     (0x1UL << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
6258 #define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
6259 #define TSC_IOHCR_G8_IO3_Pos     (30U)
6260 #define TSC_IOHCR_G8_IO3_Msk     (0x1UL << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
6261 #define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
6262 #define TSC_IOHCR_G8_IO4_Pos     (31U)
6263 #define TSC_IOHCR_G8_IO4_Msk     (0x1UL << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
6264 #define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
6265 
6266 /*******************  Bit definition for TSC_IOASCR register  *****************/
6267 #define TSC_IOASCR_G1_IO1_Pos    (0U)
6268 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
6269 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
6270 #define TSC_IOASCR_G1_IO2_Pos    (1U)
6271 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
6272 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
6273 #define TSC_IOASCR_G1_IO3_Pos    (2U)
6274 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
6275 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
6276 #define TSC_IOASCR_G1_IO4_Pos    (3U)
6277 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
6278 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
6279 #define TSC_IOASCR_G2_IO1_Pos    (4U)
6280 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
6281 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
6282 #define TSC_IOASCR_G2_IO2_Pos    (5U)
6283 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
6284 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
6285 #define TSC_IOASCR_G2_IO3_Pos    (6U)
6286 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
6287 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
6288 #define TSC_IOASCR_G2_IO4_Pos    (7U)
6289 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
6290 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
6291 #define TSC_IOASCR_G3_IO1_Pos    (8U)
6292 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
6293 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
6294 #define TSC_IOASCR_G3_IO2_Pos    (9U)
6295 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
6296 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
6297 #define TSC_IOASCR_G3_IO3_Pos    (10U)
6298 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
6299 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
6300 #define TSC_IOASCR_G3_IO4_Pos    (11U)
6301 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
6302 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
6303 #define TSC_IOASCR_G4_IO1_Pos    (12U)
6304 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
6305 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
6306 #define TSC_IOASCR_G4_IO2_Pos    (13U)
6307 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
6308 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
6309 #define TSC_IOASCR_G4_IO3_Pos    (14U)
6310 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
6311 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
6312 #define TSC_IOASCR_G4_IO4_Pos    (15U)
6313 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
6314 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
6315 #define TSC_IOASCR_G5_IO1_Pos    (16U)
6316 #define TSC_IOASCR_G5_IO1_Msk    (0x1UL << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
6317 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
6318 #define TSC_IOASCR_G5_IO2_Pos    (17U)
6319 #define TSC_IOASCR_G5_IO2_Msk    (0x1UL << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
6320 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
6321 #define TSC_IOASCR_G5_IO3_Pos    (18U)
6322 #define TSC_IOASCR_G5_IO3_Msk    (0x1UL << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
6323 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
6324 #define TSC_IOASCR_G5_IO4_Pos    (19U)
6325 #define TSC_IOASCR_G5_IO4_Msk    (0x1UL << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
6326 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
6327 #define TSC_IOASCR_G6_IO1_Pos    (20U)
6328 #define TSC_IOASCR_G6_IO1_Msk    (0x1UL << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
6329 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
6330 #define TSC_IOASCR_G6_IO2_Pos    (21U)
6331 #define TSC_IOASCR_G6_IO2_Msk    (0x1UL << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
6332 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
6333 #define TSC_IOASCR_G6_IO3_Pos    (22U)
6334 #define TSC_IOASCR_G6_IO3_Msk    (0x1UL << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
6335 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
6336 #define TSC_IOASCR_G6_IO4_Pos    (23U)
6337 #define TSC_IOASCR_G6_IO4_Msk    (0x1UL << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
6338 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
6339 #define TSC_IOASCR_G7_IO1_Pos    (24U)
6340 #define TSC_IOASCR_G7_IO1_Msk    (0x1UL << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
6341 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
6342 #define TSC_IOASCR_G7_IO2_Pos    (25U)
6343 #define TSC_IOASCR_G7_IO2_Msk    (0x1UL << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
6344 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
6345 #define TSC_IOASCR_G7_IO3_Pos    (26U)
6346 #define TSC_IOASCR_G7_IO3_Msk    (0x1UL << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
6347 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
6348 #define TSC_IOASCR_G7_IO4_Pos    (27U)
6349 #define TSC_IOASCR_G7_IO4_Msk    (0x1UL << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
6350 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
6351 #define TSC_IOASCR_G8_IO1_Pos    (28U)
6352 #define TSC_IOASCR_G8_IO1_Msk    (0x1UL << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
6353 #define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
6354 #define TSC_IOASCR_G8_IO2_Pos    (29U)
6355 #define TSC_IOASCR_G8_IO2_Msk    (0x1UL << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
6356 #define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
6357 #define TSC_IOASCR_G8_IO3_Pos    (30U)
6358 #define TSC_IOASCR_G8_IO3_Msk    (0x1UL << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
6359 #define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
6360 #define TSC_IOASCR_G8_IO4_Pos    (31U)
6361 #define TSC_IOASCR_G8_IO4_Msk    (0x1UL << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
6362 #define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
6363 
6364 /*******************  Bit definition for TSC_IOSCR register  ******************/
6365 #define TSC_IOSCR_G1_IO1_Pos     (0U)
6366 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
6367 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
6368 #define TSC_IOSCR_G1_IO2_Pos     (1U)
6369 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
6370 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
6371 #define TSC_IOSCR_G1_IO3_Pos     (2U)
6372 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
6373 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
6374 #define TSC_IOSCR_G1_IO4_Pos     (3U)
6375 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
6376 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
6377 #define TSC_IOSCR_G2_IO1_Pos     (4U)
6378 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
6379 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
6380 #define TSC_IOSCR_G2_IO2_Pos     (5U)
6381 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
6382 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
6383 #define TSC_IOSCR_G2_IO3_Pos     (6U)
6384 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
6385 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
6386 #define TSC_IOSCR_G2_IO4_Pos     (7U)
6387 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
6388 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
6389 #define TSC_IOSCR_G3_IO1_Pos     (8U)
6390 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
6391 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
6392 #define TSC_IOSCR_G3_IO2_Pos     (9U)
6393 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
6394 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
6395 #define TSC_IOSCR_G3_IO3_Pos     (10U)
6396 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
6397 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
6398 #define TSC_IOSCR_G3_IO4_Pos     (11U)
6399 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
6400 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
6401 #define TSC_IOSCR_G4_IO1_Pos     (12U)
6402 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
6403 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
6404 #define TSC_IOSCR_G4_IO2_Pos     (13U)
6405 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
6406 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
6407 #define TSC_IOSCR_G4_IO3_Pos     (14U)
6408 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
6409 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
6410 #define TSC_IOSCR_G4_IO4_Pos     (15U)
6411 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
6412 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
6413 #define TSC_IOSCR_G5_IO1_Pos     (16U)
6414 #define TSC_IOSCR_G5_IO1_Msk     (0x1UL << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
6415 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
6416 #define TSC_IOSCR_G5_IO2_Pos     (17U)
6417 #define TSC_IOSCR_G5_IO2_Msk     (0x1UL << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
6418 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
6419 #define TSC_IOSCR_G5_IO3_Pos     (18U)
6420 #define TSC_IOSCR_G5_IO3_Msk     (0x1UL << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
6421 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
6422 #define TSC_IOSCR_G5_IO4_Pos     (19U)
6423 #define TSC_IOSCR_G5_IO4_Msk     (0x1UL << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
6424 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
6425 #define TSC_IOSCR_G6_IO1_Pos     (20U)
6426 #define TSC_IOSCR_G6_IO1_Msk     (0x1UL << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
6427 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
6428 #define TSC_IOSCR_G6_IO2_Pos     (21U)
6429 #define TSC_IOSCR_G6_IO2_Msk     (0x1UL << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
6430 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
6431 #define TSC_IOSCR_G6_IO3_Pos     (22U)
6432 #define TSC_IOSCR_G6_IO3_Msk     (0x1UL << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
6433 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
6434 #define TSC_IOSCR_G6_IO4_Pos     (23U)
6435 #define TSC_IOSCR_G6_IO4_Msk     (0x1UL << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
6436 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
6437 #define TSC_IOSCR_G7_IO1_Pos     (24U)
6438 #define TSC_IOSCR_G7_IO1_Msk     (0x1UL << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
6439 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
6440 #define TSC_IOSCR_G7_IO2_Pos     (25U)
6441 #define TSC_IOSCR_G7_IO2_Msk     (0x1UL << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
6442 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
6443 #define TSC_IOSCR_G7_IO3_Pos     (26U)
6444 #define TSC_IOSCR_G7_IO3_Msk     (0x1UL << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
6445 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
6446 #define TSC_IOSCR_G7_IO4_Pos     (27U)
6447 #define TSC_IOSCR_G7_IO4_Msk     (0x1UL << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
6448 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
6449 #define TSC_IOSCR_G8_IO1_Pos     (28U)
6450 #define TSC_IOSCR_G8_IO1_Msk     (0x1UL << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
6451 #define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
6452 #define TSC_IOSCR_G8_IO2_Pos     (29U)
6453 #define TSC_IOSCR_G8_IO2_Msk     (0x1UL << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
6454 #define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
6455 #define TSC_IOSCR_G8_IO3_Pos     (30U)
6456 #define TSC_IOSCR_G8_IO3_Msk     (0x1UL << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
6457 #define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
6458 #define TSC_IOSCR_G8_IO4_Pos     (31U)
6459 #define TSC_IOSCR_G8_IO4_Msk     (0x1UL << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
6460 #define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
6461 
6462 /*******************  Bit definition for TSC_IOCCR register  ******************/
6463 #define TSC_IOCCR_G1_IO1_Pos     (0U)
6464 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
6465 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
6466 #define TSC_IOCCR_G1_IO2_Pos     (1U)
6467 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
6468 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
6469 #define TSC_IOCCR_G1_IO3_Pos     (2U)
6470 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
6471 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
6472 #define TSC_IOCCR_G1_IO4_Pos     (3U)
6473 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
6474 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
6475 #define TSC_IOCCR_G2_IO1_Pos     (4U)
6476 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
6477 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
6478 #define TSC_IOCCR_G2_IO2_Pos     (5U)
6479 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
6480 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
6481 #define TSC_IOCCR_G2_IO3_Pos     (6U)
6482 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
6483 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
6484 #define TSC_IOCCR_G2_IO4_Pos     (7U)
6485 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
6486 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
6487 #define TSC_IOCCR_G3_IO1_Pos     (8U)
6488 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
6489 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
6490 #define TSC_IOCCR_G3_IO2_Pos     (9U)
6491 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
6492 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
6493 #define TSC_IOCCR_G3_IO3_Pos     (10U)
6494 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
6495 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
6496 #define TSC_IOCCR_G3_IO4_Pos     (11U)
6497 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
6498 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
6499 #define TSC_IOCCR_G4_IO1_Pos     (12U)
6500 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
6501 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
6502 #define TSC_IOCCR_G4_IO2_Pos     (13U)
6503 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
6504 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
6505 #define TSC_IOCCR_G4_IO3_Pos     (14U)
6506 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
6507 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
6508 #define TSC_IOCCR_G4_IO4_Pos     (15U)
6509 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
6510 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
6511 #define TSC_IOCCR_G5_IO1_Pos     (16U)
6512 #define TSC_IOCCR_G5_IO1_Msk     (0x1UL << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
6513 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
6514 #define TSC_IOCCR_G5_IO2_Pos     (17U)
6515 #define TSC_IOCCR_G5_IO2_Msk     (0x1UL << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
6516 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
6517 #define TSC_IOCCR_G5_IO3_Pos     (18U)
6518 #define TSC_IOCCR_G5_IO3_Msk     (0x1UL << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
6519 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
6520 #define TSC_IOCCR_G5_IO4_Pos     (19U)
6521 #define TSC_IOCCR_G5_IO4_Msk     (0x1UL << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
6522 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
6523 #define TSC_IOCCR_G6_IO1_Pos     (20U)
6524 #define TSC_IOCCR_G6_IO1_Msk     (0x1UL << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
6525 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
6526 #define TSC_IOCCR_G6_IO2_Pos     (21U)
6527 #define TSC_IOCCR_G6_IO2_Msk     (0x1UL << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
6528 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
6529 #define TSC_IOCCR_G6_IO3_Pos     (22U)
6530 #define TSC_IOCCR_G6_IO3_Msk     (0x1UL << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
6531 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
6532 #define TSC_IOCCR_G6_IO4_Pos     (23U)
6533 #define TSC_IOCCR_G6_IO4_Msk     (0x1UL << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
6534 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
6535 #define TSC_IOCCR_G7_IO1_Pos     (24U)
6536 #define TSC_IOCCR_G7_IO1_Msk     (0x1UL << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
6537 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
6538 #define TSC_IOCCR_G7_IO2_Pos     (25U)
6539 #define TSC_IOCCR_G7_IO2_Msk     (0x1UL << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
6540 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
6541 #define TSC_IOCCR_G7_IO3_Pos     (26U)
6542 #define TSC_IOCCR_G7_IO3_Msk     (0x1UL << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
6543 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
6544 #define TSC_IOCCR_G7_IO4_Pos     (27U)
6545 #define TSC_IOCCR_G7_IO4_Msk     (0x1UL << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
6546 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
6547 #define TSC_IOCCR_G8_IO1_Pos     (28U)
6548 #define TSC_IOCCR_G8_IO1_Msk     (0x1UL << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
6549 #define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
6550 #define TSC_IOCCR_G8_IO2_Pos     (29U)
6551 #define TSC_IOCCR_G8_IO2_Msk     (0x1UL << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
6552 #define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
6553 #define TSC_IOCCR_G8_IO3_Pos     (30U)
6554 #define TSC_IOCCR_G8_IO3_Msk     (0x1UL << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
6555 #define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
6556 #define TSC_IOCCR_G8_IO4_Pos     (31U)
6557 #define TSC_IOCCR_G8_IO4_Msk     (0x1UL << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
6558 #define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
6559 
6560 /*******************  Bit definition for TSC_IOGCSR register  *****************/
6561 #define TSC_IOGCSR_G1E_Pos       (0U)
6562 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
6563 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
6564 #define TSC_IOGCSR_G2E_Pos       (1U)
6565 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
6566 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
6567 #define TSC_IOGCSR_G3E_Pos       (2U)
6568 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
6569 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
6570 #define TSC_IOGCSR_G4E_Pos       (3U)
6571 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
6572 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
6573 #define TSC_IOGCSR_G5E_Pos       (4U)
6574 #define TSC_IOGCSR_G5E_Msk       (0x1UL << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
6575 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
6576 #define TSC_IOGCSR_G6E_Pos       (5U)
6577 #define TSC_IOGCSR_G6E_Msk       (0x1UL << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
6578 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
6579 #define TSC_IOGCSR_G7E_Pos       (6U)
6580 #define TSC_IOGCSR_G7E_Msk       (0x1UL << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
6581 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
6582 #define TSC_IOGCSR_G8E_Pos       (7U)
6583 #define TSC_IOGCSR_G8E_Msk       (0x1UL << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
6584 #define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
6585 #define TSC_IOGCSR_G1S_Pos       (16U)
6586 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
6587 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
6588 #define TSC_IOGCSR_G2S_Pos       (17U)
6589 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
6590 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
6591 #define TSC_IOGCSR_G3S_Pos       (18U)
6592 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
6593 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
6594 #define TSC_IOGCSR_G4S_Pos       (19U)
6595 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
6596 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
6597 #define TSC_IOGCSR_G5S_Pos       (20U)
6598 #define TSC_IOGCSR_G5S_Msk       (0x1UL << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
6599 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
6600 #define TSC_IOGCSR_G6S_Pos       (21U)
6601 #define TSC_IOGCSR_G6S_Msk       (0x1UL << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
6602 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
6603 #define TSC_IOGCSR_G7S_Pos       (22U)
6604 #define TSC_IOGCSR_G7S_Msk       (0x1UL << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
6605 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
6606 #define TSC_IOGCSR_G8S_Pos       (23U)
6607 #define TSC_IOGCSR_G8S_Msk       (0x1UL << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
6608 #define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
6609 
6610 /*******************  Bit definition for TSC_IOGXCR register  *****************/
6611 #define TSC_IOGXCR_CNT_Pos       (0U)
6612 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
6613 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
6614 
6615 /******************************************************************************/
6616 /*                                                                            */
6617 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
6618 /*                                                                            */
6619 /******************************************************************************/
6620 
6621 /*
6622  * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
6623  */
6624 /* Note: No specific macro feature on this device */
6625 
6626 /******************  Bit definition for USART_CR1 register  *******************/
6627 #define USART_CR1_UE_Pos              (0U)
6628 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
6629 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
6630 #define USART_CR1_UESM_Pos            (1U)
6631 #define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
6632 #define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
6633 #define USART_CR1_RE_Pos              (2U)
6634 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
6635 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
6636 #define USART_CR1_TE_Pos              (3U)
6637 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
6638 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
6639 #define USART_CR1_IDLEIE_Pos          (4U)
6640 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
6641 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
6642 #define USART_CR1_RXNEIE_Pos          (5U)
6643 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
6644 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
6645 #define USART_CR1_TCIE_Pos            (6U)
6646 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
6647 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
6648 #define USART_CR1_TXEIE_Pos           (7U)
6649 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
6650 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
6651 #define USART_CR1_PEIE_Pos            (8U)
6652 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
6653 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
6654 #define USART_CR1_PS_Pos              (9U)
6655 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
6656 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
6657 #define USART_CR1_PCE_Pos             (10U)
6658 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
6659 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
6660 #define USART_CR1_WAKE_Pos            (11U)
6661 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
6662 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
6663 #define USART_CR1_M_Pos               (12U)
6664 #define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
6665 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
6666 #define USART_CR1_M0_Pos              (12U)
6667 #define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
6668 #define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
6669 #define USART_CR1_MME_Pos             (13U)
6670 #define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
6671 #define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
6672 #define USART_CR1_CMIE_Pos            (14U)
6673 #define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
6674 #define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
6675 #define USART_CR1_OVER8_Pos           (15U)
6676 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
6677 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
6678 #define USART_CR1_DEDT_Pos            (16U)
6679 #define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
6680 #define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
6681 #define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
6682 #define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
6683 #define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
6684 #define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
6685 #define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
6686 #define USART_CR1_DEAT_Pos            (21U)
6687 #define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
6688 #define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
6689 #define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
6690 #define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
6691 #define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
6692 #define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
6693 #define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
6694 #define USART_CR1_RTOIE_Pos           (26U)
6695 #define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
6696 #define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
6697 #define USART_CR1_EOBIE_Pos           (27U)
6698 #define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
6699 #define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
6700 #define USART_CR1_M1_Pos              (28U)
6701 #define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
6702 #define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
6703 /******************  Bit definition for USART_CR2 register  *******************/
6704 #define USART_CR2_ADDM7_Pos           (4U)
6705 #define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
6706 #define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
6707 #define USART_CR2_LBDL_Pos            (5U)
6708 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
6709 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
6710 #define USART_CR2_LBDIE_Pos           (6U)
6711 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
6712 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
6713 #define USART_CR2_LBCL_Pos            (8U)
6714 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
6715 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
6716 #define USART_CR2_CPHA_Pos            (9U)
6717 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
6718 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
6719 #define USART_CR2_CPOL_Pos            (10U)
6720 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
6721 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
6722 #define USART_CR2_CLKEN_Pos           (11U)
6723 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
6724 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
6725 #define USART_CR2_STOP_Pos            (12U)
6726 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
6727 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
6728 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
6729 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
6730 #define USART_CR2_LINEN_Pos           (14U)
6731 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
6732 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
6733 #define USART_CR2_SWAP_Pos            (15U)
6734 #define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
6735 #define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
6736 #define USART_CR2_RXINV_Pos           (16U)
6737 #define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
6738 #define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
6739 #define USART_CR2_TXINV_Pos           (17U)
6740 #define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
6741 #define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
6742 #define USART_CR2_DATAINV_Pos         (18U)
6743 #define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
6744 #define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
6745 #define USART_CR2_MSBFIRST_Pos        (19U)
6746 #define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
6747 #define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
6748 #define USART_CR2_ABREN_Pos           (20U)
6749 #define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
6750 #define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
6751 #define USART_CR2_ABRMODE_Pos         (21U)
6752 #define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
6753 #define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
6754 #define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
6755 #define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
6756 #define USART_CR2_RTOEN_Pos           (23U)
6757 #define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
6758 #define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
6759 #define USART_CR2_ADD_Pos             (24U)
6760 #define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
6761 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
6762 
6763 /******************  Bit definition for USART_CR3 register  *******************/
6764 #define USART_CR3_EIE_Pos             (0U)
6765 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
6766 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
6767 #define USART_CR3_IREN_Pos            (1U)
6768 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
6769 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
6770 #define USART_CR3_IRLP_Pos            (2U)
6771 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
6772 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
6773 #define USART_CR3_HDSEL_Pos           (3U)
6774 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
6775 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
6776 #define USART_CR3_NACK_Pos            (4U)
6777 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
6778 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
6779 #define USART_CR3_SCEN_Pos            (5U)
6780 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
6781 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
6782 #define USART_CR3_DMAR_Pos            (6U)
6783 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
6784 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
6785 #define USART_CR3_DMAT_Pos            (7U)
6786 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
6787 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
6788 #define USART_CR3_RTSE_Pos            (8U)
6789 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
6790 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
6791 #define USART_CR3_CTSE_Pos            (9U)
6792 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
6793 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
6794 #define USART_CR3_CTSIE_Pos           (10U)
6795 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
6796 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
6797 #define USART_CR3_ONEBIT_Pos          (11U)
6798 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
6799 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
6800 #define USART_CR3_OVRDIS_Pos          (12U)
6801 #define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
6802 #define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
6803 #define USART_CR3_DDRE_Pos            (13U)
6804 #define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
6805 #define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
6806 #define USART_CR3_DEM_Pos             (14U)
6807 #define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
6808 #define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
6809 #define USART_CR3_DEP_Pos             (15U)
6810 #define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
6811 #define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
6812 #define USART_CR3_SCARCNT_Pos         (17U)
6813 #define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
6814 #define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
6815 #define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
6816 #define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
6817 #define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
6818 #define USART_CR3_WUS_Pos             (20U)
6819 #define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
6820 #define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
6821 #define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
6822 #define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
6823 #define USART_CR3_WUFIE_Pos           (22U)
6824 #define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
6825 #define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
6826 #define USART_CR3_UCESM_Pos           (23U)
6827 #define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)            /*!< 0x00800000 */
6828 #define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< Clock Enable in Stop mode */
6829 
6830 /******************  Bit definition for USART_BRR register  *******************/
6831 #define USART_BRR_DIV_FRACTION_Pos    (0U)
6832 #define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
6833 #define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
6834 #define USART_BRR_DIV_MANTISSA_Pos    (4U)
6835 #define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
6836 #define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
6837 
6838 /******************  Bit definition for USART_GTPR register  ******************/
6839 #define USART_GTPR_PSC_Pos            (0U)
6840 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
6841 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
6842 #define USART_GTPR_GT_Pos             (8U)
6843 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
6844 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
6845 
6846 
6847 /*******************  Bit definition for USART_RTOR register  *****************/
6848 #define USART_RTOR_RTO_Pos            (0U)
6849 #define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
6850 #define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
6851 #define USART_RTOR_BLEN_Pos           (24U)
6852 #define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
6853 #define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
6854 
6855 /*******************  Bit definition for USART_RQR register  ******************/
6856 #define USART_RQR_ABRRQ_Pos           (0U)
6857 #define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
6858 #define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
6859 #define USART_RQR_SBKRQ_Pos           (1U)
6860 #define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
6861 #define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
6862 #define USART_RQR_MMRQ_Pos            (2U)
6863 #define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
6864 #define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
6865 #define USART_RQR_RXFRQ_Pos           (3U)
6866 #define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
6867 #define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
6868 #define USART_RQR_TXFRQ_Pos           (4U)
6869 #define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
6870 #define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
6871 
6872 /*******************  Bit definition for USART_ISR register  ******************/
6873 #define USART_ISR_PE_Pos              (0U)
6874 #define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
6875 #define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
6876 #define USART_ISR_FE_Pos              (1U)
6877 #define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
6878 #define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
6879 #define USART_ISR_NE_Pos              (2U)
6880 #define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
6881 #define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise detected Flag */
6882 #define USART_ISR_ORE_Pos             (3U)
6883 #define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
6884 #define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
6885 #define USART_ISR_IDLE_Pos            (4U)
6886 #define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
6887 #define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
6888 #define USART_ISR_RXNE_Pos            (5U)
6889 #define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
6890 #define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
6891 #define USART_ISR_TC_Pos              (6U)
6892 #define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
6893 #define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
6894 #define USART_ISR_TXE_Pos             (7U)
6895 #define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
6896 #define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
6897 #define USART_ISR_LBDF_Pos            (8U)
6898 #define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
6899 #define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
6900 #define USART_ISR_CTSIF_Pos           (9U)
6901 #define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
6902 #define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
6903 #define USART_ISR_CTS_Pos             (10U)
6904 #define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
6905 #define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
6906 #define USART_ISR_RTOF_Pos            (11U)
6907 #define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
6908 #define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
6909 #define USART_ISR_EOBF_Pos            (12U)
6910 #define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
6911 #define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
6912 #define USART_ISR_ABRE_Pos            (14U)
6913 #define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
6914 #define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
6915 #define USART_ISR_ABRF_Pos            (15U)
6916 #define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
6917 #define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
6918 #define USART_ISR_BUSY_Pos            (16U)
6919 #define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
6920 #define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
6921 #define USART_ISR_CMF_Pos             (17U)
6922 #define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
6923 #define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
6924 #define USART_ISR_SBKF_Pos            (18U)
6925 #define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
6926 #define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
6927 #define USART_ISR_RWU_Pos             (19U)
6928 #define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
6929 #define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
6930 #define USART_ISR_WUF_Pos             (20U)
6931 #define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
6932 #define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
6933 #define USART_ISR_TEACK_Pos           (21U)
6934 #define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
6935 #define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
6936 #define USART_ISR_REACK_Pos           (22U)
6937 #define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
6938 #define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
6939 
6940 /*******************  Bit definition for USART_ICR register  ******************/
6941 #define USART_ICR_PECF_Pos            (0U)
6942 #define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
6943 #define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
6944 #define USART_ICR_FECF_Pos            (1U)
6945 #define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
6946 #define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
6947 #define USART_ICR_NCF_Pos             (2U)
6948 #define USART_ICR_NCF_Msk             (0x1UL << USART_ICR_NCF_Pos)              /*!< 0x00000004 */
6949 #define USART_ICR_NCF                 USART_ICR_NCF_Msk                        /*!< Noise detected Clear Flag */
6950 #define USART_ICR_ORECF_Pos           (3U)
6951 #define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
6952 #define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
6953 #define USART_ICR_IDLECF_Pos          (4U)
6954 #define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
6955 #define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
6956 #define USART_ICR_TCCF_Pos            (6U)
6957 #define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
6958 #define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
6959 #define USART_ICR_LBDCF_Pos           (8U)
6960 #define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
6961 #define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
6962 #define USART_ICR_CTSCF_Pos           (9U)
6963 #define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
6964 #define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
6965 #define USART_ICR_RTOCF_Pos           (11U)
6966 #define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
6967 #define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
6968 #define USART_ICR_EOBCF_Pos           (12U)
6969 #define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
6970 #define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
6971 #define USART_ICR_CMCF_Pos            (17U)
6972 #define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
6973 #define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
6974 #define USART_ICR_WUCF_Pos            (20U)
6975 #define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
6976 #define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
6977 
6978 /* Compatibility defines with other series */
6979 #define USART_ICR_NECF                USART_ICR_NCF
6980 
6981 /*******************  Bit definition for USART_RDR register  ******************/
6982 #define USART_RDR_RDR_Pos             (0U)
6983 #define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
6984 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
6985 
6986 /*******************  Bit definition for USART_TDR register  ******************/
6987 #define USART_TDR_TDR_Pos             (0U)
6988 #define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
6989 #define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
6990 
6991 /******************************************************************************/
6992 /*                                                                            */
6993 /*                         USB Device General registers                       */
6994 /*                                                                            */
6995 /******************************************************************************/
6996 #define USB_BASE                              (0x40005C00U)                    /*!< USB_IP Peripheral Registers base address */
6997 #define USB_PMAADDR_Pos           (13U)
6998 #define USB_PMAADDR_Msk           (0x20003UL << USB_PMAADDR_Pos)                /*!< 0x40006000 */
6999 #define USB_PMAADDR               USB_PMAADDR_Msk                              /*!< USB_IP Packet Memory Area base address */
7000 
7001 #define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
7002 #define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
7003 #define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
7004 #define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
7005 #define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
7006 #define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
7007 #define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
7008 
7009 /****************************  ISTR interrupt events  *************************/
7010 #define USB_ISTR_CTR                          ((uint16_t)0x8000U)              /*!< Correct TRansfer (clear-only bit) */
7011 #define USB_ISTR_PMAOVR                       ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun (clear-only bit) */
7012 #define USB_ISTR_ERR                          ((uint16_t)0x2000U)              /*!< ERRor (clear-only bit) */
7013 #define USB_ISTR_WKUP                         ((uint16_t)0x1000U)              /*!< WaKe UP (clear-only bit) */
7014 #define USB_ISTR_SUSP                         ((uint16_t)0x0800U)              /*!< SUSPend (clear-only bit) */
7015 #define USB_ISTR_RESET                        ((uint16_t)0x0400U)              /*!< RESET (clear-only bit) */
7016 #define USB_ISTR_SOF                          ((uint16_t)0x0200U)              /*!< Start Of Frame (clear-only bit) */
7017 #define USB_ISTR_ESOF                         ((uint16_t)0x0100U)              /*!< Expected Start Of Frame (clear-only bit) */
7018 #define USB_ISTR_L1REQ                        ((uint16_t)0x0080U)              /*!< LPM L1 state request  */
7019 #define USB_ISTR_DIR                          ((uint16_t)0x0010U)              /*!< DIRection of transaction (read-only bit)  */
7020 #define USB_ISTR_EP_ID                        ((uint16_t)0x000FU)              /*!< EndPoint IDentifier (read-only bit)  */
7021 
7022 #define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
7023 #define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
7024 #define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
7025 #define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
7026 #define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
7027 #define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
7028 #define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
7029 #define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
7030 #define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
7031 /*************************  CNTR control register bits definitions  ***********/
7032 #define USB_CNTR_CTRM                         ((uint16_t)0x8000U)              /*!< Correct TRansfer Mask */
7033 #define USB_CNTR_PMAOVRM                      ((uint16_t)0x4000U)              /*!< DMA OVeR/underrun Mask */
7034 #define USB_CNTR_ERRM                         ((uint16_t)0x2000U)              /*!< ERRor Mask */
7035 #define USB_CNTR_WKUPM                        ((uint16_t)0x1000U)              /*!< WaKe UP Mask */
7036 #define USB_CNTR_SUSPM                        ((uint16_t)0x0800U)              /*!< SUSPend Mask */
7037 #define USB_CNTR_RESETM                       ((uint16_t)0x0400U)              /*!< RESET Mask   */
7038 #define USB_CNTR_SOFM                         ((uint16_t)0x0200U)              /*!< Start Of Frame Mask */
7039 #define USB_CNTR_ESOFM                        ((uint16_t)0x0100U)              /*!< Expected Start Of Frame Mask */
7040 #define USB_CNTR_L1REQM                       ((uint16_t)0x0080U)              /*!< LPM L1 state request interrupt mask */
7041 #define USB_CNTR_L1RESUME                     ((uint16_t)0x0020U)              /*!< LPM L1 Resume request */
7042 #define USB_CNTR_RESUME                       ((uint16_t)0x0010U)              /*!< RESUME request */
7043 #define USB_CNTR_FSUSP                        ((uint16_t)0x0008U)              /*!< Force SUSPend */
7044 #define USB_CNTR_LPMODE                       ((uint16_t)0x0004U)              /*!< Low-power MODE */
7045 #define USB_CNTR_PDWN                         ((uint16_t)0x0002U)              /*!< Power DoWN */
7046 #define USB_CNTR_FRES                         ((uint16_t)0x0001U)              /*!< Force USB RESet */
7047 /*************************  BCDR control register bits definitions  ***********/
7048 #define USB_BCDR_DPPU                         ((uint16_t)0x8000U)              /*!< DP Pull-up Enable */
7049 #define USB_BCDR_PS2DET                       ((uint16_t)0x0080U)              /*!< PS2 port or proprietary charger detected */
7050 #define USB_BCDR_SDET                         ((uint16_t)0x0040U)              /*!< Secondary detection (SD) status */
7051 #define USB_BCDR_PDET                         ((uint16_t)0x0020U)              /*!< Primary detection (PD) status */
7052 #define USB_BCDR_DCDET                        ((uint16_t)0x0010U)              /*!< Data contact detection (DCD) status */
7053 #define USB_BCDR_SDEN                         ((uint16_t)0x0008U)              /*!< Secondary detection (SD) mode enable */
7054 #define USB_BCDR_PDEN                         ((uint16_t)0x0004U)              /*!< Primary detection (PD) mode enable */
7055 #define USB_BCDR_DCDEN                        ((uint16_t)0x0002U)              /*!< Data contact detection (DCD) mode enable */
7056 #define USB_BCDR_BCDEN                        ((uint16_t)0x0001U)              /*!< Battery charging detector (BCD) enable */
7057 /***************************  LPM register bits definitions  ******************/
7058 #define USB_LPMCSR_BESL                       ((uint16_t)0x00F0U)              /*!< BESL value received with last ACKed LPM Token  */
7059 #define USB_LPMCSR_REMWAKE                    ((uint16_t)0x0008U)              /*!< bRemoteWake value received with last ACKed LPM Token */
7060 #define USB_LPMCSR_LPMACK                     ((uint16_t)0x0002U)              /*!< LPM Token acknowledge enable*/
7061 #define USB_LPMCSR_LMPEN                      ((uint16_t)0x0001U)              /*!< LPM support enable  */
7062 /********************  FNR Frame Number Register bit definitions   ************/
7063 #define USB_FNR_RXDP                          ((uint16_t)0x8000U)              /*!< status of D+ data line */
7064 #define USB_FNR_RXDM                          ((uint16_t)0x4000U)              /*!< status of D- data line */
7065 #define USB_FNR_LCK                           ((uint16_t)0x2000U)              /*!< LoCKed */
7066 #define USB_FNR_LSOF                          ((uint16_t)0x1800U)              /*!< Lost SOF */
7067 #define USB_FNR_FN                            ((uint16_t)0x07FFU)              /*!< Frame Number */
7068 /********************  DADDR Device ADDRess bit definitions    ****************/
7069 #define USB_DADDR_EF                          ((uint8_t)0x80U)                 /*!< USB device address Enable Function */
7070 #define USB_DADDR_ADD                         ((uint8_t)0x7FU)                 /*!< USB device address */
7071 /******************************  Endpoint register    *************************/
7072 #define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
7073 #define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
7074 #define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
7075 #define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
7076 #define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
7077 #define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
7078 #define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
7079 #define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
7080 /* bit positions */
7081 #define USB_EP_CTR_RX                         ((uint16_t)0x8000U)              /*!<  EndPoint Correct TRansfer RX */
7082 #define USB_EP_DTOG_RX                        ((uint16_t)0x4000U)              /*!<  EndPoint Data TOGGLE RX */
7083 #define USB_EPRX_STAT                         ((uint16_t)0x3000U)              /*!<  EndPoint RX STATus bit field */
7084 #define USB_EP_SETUP                          ((uint16_t)0x0800U)              /*!<  EndPoint SETUP */
7085 #define USB_EP_T_FIELD                        ((uint16_t)0x0600U)              /*!<  EndPoint TYPE */
7086 #define USB_EP_KIND                           ((uint16_t)0x0100U)              /*!<  EndPoint KIND */
7087 #define USB_EP_CTR_TX                         ((uint16_t)0x0080U)              /*!<  EndPoint Correct TRansfer TX */
7088 #define USB_EP_DTOG_TX                        ((uint16_t)0x0040U)              /*!<  EndPoint Data TOGGLE TX */
7089 #define USB_EPTX_STAT                         ((uint16_t)0x0030U)              /*!<  EndPoint TX STATus bit field */
7090 #define USB_EPADDR_FIELD                      ((uint16_t)0x000FU)              /*!<  EndPoint ADDRess FIELD */
7091 
7092 /* EndPoint REGister MASK (no toggle fields) */
7093 #define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
7094                                                                          /*!< EP_TYPE[1:0] EndPoint TYPE */
7095 #define USB_EP_TYPE_MASK                      ((uint16_t)0x0600U)              /*!< EndPoint TYPE Mask */
7096 #define USB_EP_BULK                           ((uint16_t)0x0000U)              /*!< EndPoint BULK */
7097 #define USB_EP_CONTROL                        ((uint16_t)0x0200U)              /*!< EndPoint CONTROL */
7098 #define USB_EP_ISOCHRONOUS                    ((uint16_t)0x0400U)              /*!< EndPoint ISOCHRONOUS */
7099 #define USB_EP_INTERRUPT                      ((uint16_t)0x0600U)              /*!< EndPoint INTERRUPT */
7100 #define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
7101 
7102 #define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
7103                                                                          /*!< STAT_TX[1:0] STATus for TX transfer */
7104 #define USB_EP_TX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint TX DISabled */
7105 #define USB_EP_TX_STALL                       ((uint16_t)0x0010U)              /*!< EndPoint TX STALLed */
7106 #define USB_EP_TX_NAK                         ((uint16_t)0x0020U)              /*!< EndPoint TX NAKed */
7107 #define USB_EP_TX_VALID                       ((uint16_t)0x0030U)              /*!< EndPoint TX VALID */
7108 #define USB_EPTX_DTOG1                        ((uint16_t)0x0010U)              /*!< EndPoint TX Data TOGgle bit1 */
7109 #define USB_EPTX_DTOG2                        ((uint16_t)0x0020U)              /*!< EndPoint TX Data TOGgle bit2 */
7110 #define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
7111                                                                          /*!< STAT_RX[1:0] STATus for RX transfer */
7112 #define USB_EP_RX_DIS                         ((uint16_t)0x0000U)              /*!< EndPoint RX DISabled */
7113 #define USB_EP_RX_STALL                       ((uint16_t)0x1000U)              /*!< EndPoint RX STALLed */
7114 #define USB_EP_RX_NAK                         ((uint16_t)0x2000U)              /*!< EndPoint RX NAKed */
7115 #define USB_EP_RX_VALID                       ((uint16_t)0x3000U)              /*!< EndPoint RX VALID */
7116 #define USB_EPRX_DTOG1                        ((uint16_t)0x1000U)              /*!< EndPoint RX Data TOGgle bit1 */
7117 #define USB_EPRX_DTOG2                        ((uint16_t)0x2000U)              /*!< EndPoint RX Data TOGgle bit1 */
7118 #define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
7119 
7120 /******************************************************************************/
7121 /*                                                                            */
7122 /*                         Window WATCHDOG (WWDG)                             */
7123 /*                                                                            */
7124 /******************************************************************************/
7125 
7126 /*******************  Bit definition for WWDG_CR register  ********************/
7127 #define WWDG_CR_T_Pos           (0U)
7128 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
7129 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
7130 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
7131 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
7132 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
7133 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
7134 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
7135 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
7136 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
7137 
7138 /* Legacy defines */
7139 #define  WWDG_CR_T0    WWDG_CR_T_0
7140 #define  WWDG_CR_T1    WWDG_CR_T_1
7141 #define  WWDG_CR_T2    WWDG_CR_T_2
7142 #define  WWDG_CR_T3    WWDG_CR_T_3
7143 #define  WWDG_CR_T4    WWDG_CR_T_4
7144 #define  WWDG_CR_T5    WWDG_CR_T_5
7145 #define  WWDG_CR_T6    WWDG_CR_T_6
7146 
7147 #define WWDG_CR_WDGA_Pos        (7U)
7148 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
7149 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!< Activation bit */
7150 
7151 /*******************  Bit definition for WWDG_CFR register  *******************/
7152 #define WWDG_CFR_W_Pos          (0U)
7153 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
7154 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!< W[6:0] bits (7-bit window value) */
7155 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
7156 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
7157 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
7158 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
7159 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
7160 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
7161 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
7162 
7163 /* Legacy defines */
7164 #define  WWDG_CFR_W0    WWDG_CFR_W_0
7165 #define  WWDG_CFR_W1    WWDG_CFR_W_1
7166 #define  WWDG_CFR_W2    WWDG_CFR_W_2
7167 #define  WWDG_CFR_W3    WWDG_CFR_W_3
7168 #define  WWDG_CFR_W4    WWDG_CFR_W_4
7169 #define  WWDG_CFR_W5    WWDG_CFR_W_5
7170 #define  WWDG_CFR_W6    WWDG_CFR_W_6
7171 
7172 #define WWDG_CFR_WDGTB_Pos      (7U)
7173 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
7174 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!< WDGTB[1:0] bits (Timer Base) */
7175 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
7176 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
7177 
7178 /* Legacy defines */
7179 #define  WWDG_CFR_WDGTB0    WWDG_CFR_WDGTB_0
7180 #define  WWDG_CFR_WDGTB1    WWDG_CFR_WDGTB_1
7181 
7182 #define WWDG_CFR_EWI_Pos        (9U)
7183 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
7184 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!< Early Wakeup Interrupt */
7185 
7186 /*******************  Bit definition for WWDG_SR register  ********************/
7187 #define WWDG_SR_EWIF_Pos        (0U)
7188 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
7189 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!< Early Wakeup Interrupt Flag */
7190 
7191 /**
7192   * @}
7193   */
7194 
7195 /**
7196   * @}
7197   */
7198 
7199 /** @addtogroup Exported_macros
7200   * @{
7201   */
7202 
7203 /******************************* ADC Instances ********************************/
7204 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
7205 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
7206 
7207 /******************************* AES Instances ********************************/
7208 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
7209 
7210 /******************************* COMP Instances *******************************/
7211 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
7212                                        ((INSTANCE) == COMP2))
7213 
7214 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
7215 
7216 /******************************* CRC Instances ********************************/
7217 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7218 
7219 /******************************* DAC Instances *********************************/
7220 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
7221 
7222 /******************************* DMA Instances *********************************/
7223 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
7224                                        ((INSTANCE) == DMA1_Channel2) || \
7225                                        ((INSTANCE) == DMA1_Channel3) || \
7226                                        ((INSTANCE) == DMA1_Channel4) || \
7227                                        ((INSTANCE) == DMA1_Channel5) || \
7228                                        ((INSTANCE) == DMA1_Channel6) || \
7229                                        ((INSTANCE) == DMA1_Channel7))
7230 
7231 /******************************* GPIO Instances *******************************/
7232 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7233                                         ((INSTANCE) == GPIOB) || \
7234                                         ((INSTANCE) == GPIOC) || \
7235                                         ((INSTANCE) == GPIOD) || \
7236                                         ((INSTANCE) == GPIOH))
7237 
7238 #define IS_GPIO_AF_INSTANCE(INSTANCE)  (((INSTANCE) == GPIOA) || \
7239                                         ((INSTANCE) == GPIOB) || \
7240                                         ((INSTANCE) == GPIOC) || \
7241                                         ((INSTANCE) == GPIOD) || \
7242                                         ((INSTANCE) == GPIOH))
7243 
7244 /******************************** I2C Instances *******************************/
7245 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7246                                        ((INSTANCE) == I2C2))
7247 
7248 /****************** I2C Instances : wakeup capability from stop modes *********/
7249 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
7250 
7251 
7252 /******************************** I2S Instances *******************************/
7253 #define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
7254 
7255 /******************************* RNG Instances ********************************/
7256 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
7257 
7258 /****************************** RTC Instances *********************************/
7259 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
7260 
7261 /******************************** SMBUS Instances *****************************/
7262 #define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
7263 
7264 /******************************** SPI Instances *******************************/
7265 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7266                                        ((INSTANCE) == SPI2))
7267 
7268 /****************** LPTIM Instances : All supported instances *****************/
7269 #define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
7270 
7271 /************* LPTIM instances supporting the encoder mode feature ************/
7272 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
7273 
7274 /****************** TIM Instances : All supported instances *******************/
7275 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
7276                                          ((INSTANCE) == TIM6)   || \
7277                                          ((INSTANCE) == TIM21)  || \
7278                                          ((INSTANCE) == TIM22))
7279 
7280 /************* TIM Instances : at least 1 capture/compare channel *************/
7281 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
7282                                          ((INSTANCE) == TIM21) || \
7283                                          ((INSTANCE) == TIM22))
7284 
7285 /************ TIM Instances : at least 2 capture/compare channels *************/
7286 #define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
7287                                         ((INSTANCE) == TIM21) || \
7288                                         ((INSTANCE) == TIM22))
7289 
7290 /************ TIM Instances : at least 3 capture/compare channels *************/
7291 #define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
7292 
7293 /************ TIM Instances : at least 4 capture/compare channels *************/
7294 #define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
7295 
7296 /****************** TIM Instances : DMA requests generation (UDE) *************/
7297 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
7298                                             ((INSTANCE) == TIM6))
7299 
7300 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
7301 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
7302 
7303 /******************** TIM Instances : DMA burst feature ***********************/
7304 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
7305 
7306 /******************* TIM Instances : output(s) available **********************/
7307 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
7308     ((((INSTANCE) == TIM2) &&                  \
7309      (((CHANNEL) == TIM_CHANNEL_1) ||          \
7310       ((CHANNEL) == TIM_CHANNEL_2) ||          \
7311       ((CHANNEL) == TIM_CHANNEL_3) ||          \
7312       ((CHANNEL) == TIM_CHANNEL_4)))           \
7313      ||                                        \
7314      (((INSTANCE) == TIM21) &&                 \
7315       (((CHANNEL) == TIM_CHANNEL_1) ||         \
7316        ((CHANNEL) == TIM_CHANNEL_2)))          \
7317      ||                                        \
7318      (((INSTANCE) == TIM22) &&                 \
7319       (((CHANNEL) == TIM_CHANNEL_1) ||         \
7320        ((CHANNEL) == TIM_CHANNEL_2))))
7321 
7322 /****************** TIM Instances : supporting clock division *****************/
7323 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
7324                                                         ((INSTANCE) == TIM21)  || \
7325                                                         ((INSTANCE) == TIM22))
7326 
7327 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
7328 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
7329                                                           ((INSTANCE) == TIM21))
7330 
7331 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
7332 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)   || \
7333                                                           ((INSTANCE) == TIM21)  || \
7334                                                           ((INSTANCE) == TIM22))
7335 
7336 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
7337 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)        (((INSTANCE) == TIM2)   || \
7338                                                           ((INSTANCE) == TIM21))
7339 
7340 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
7341 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
7342                                                           ((INSTANCE) == TIM21)  || \
7343                                                           ((INSTANCE) == TIM22))
7344 
7345 /****************** TIM Instances : supporting counting mode selection ********/
7346 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
7347                                                              ((INSTANCE) == TIM21)  || \
7348                                                              ((INSTANCE) == TIM22))
7349 
7350 /****************** TIM Instances : supporting encoder interface **************/
7351 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
7352                                                      ((INSTANCE) == TIM21)  || \
7353                                                      ((INSTANCE) == TIM22))
7354 
7355 /***************** TIM Instances : external trigger input available ************/
7356 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
7357                                             ((INSTANCE) == TIM21) || \
7358                                             ((INSTANCE) == TIM22))
7359 
7360 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
7361 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
7362                                             ((INSTANCE) == TIM6)  || \
7363                                             ((INSTANCE) == TIM21) || \
7364                                             ((INSTANCE) == TIM22))
7365 
7366 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
7367 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
7368                                             ((INSTANCE) == TIM21) || \
7369                                             ((INSTANCE) == TIM22))
7370 
7371 /****************** TIM Instances : remapping capability **********************/
7372 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
7373                                          ((INSTANCE) == TIM21)  || \
7374                                          ((INSTANCE) == TIM22))
7375 
7376 /******************* TIM Instances : output(s) OCXEC register *****************/
7377 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
7378 
7379 /******************* TIM Instances : Timer input XOR function *****************/
7380 #define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
7381 
7382 /****************************** TSC Instances *********************************/
7383 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
7384 
7385 /******************** UART Instances : Asynchronous mode **********************/
7386 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7387                                     ((INSTANCE) == USART2))
7388 
7389 /******************** USART Instances : Synchronous mode **********************/
7390 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7391                                      ((INSTANCE) == USART2))
7392 
7393 /****************** USART Instances : Auto Baud Rate detection ****************/
7394 
7395 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7396                                                             ((INSTANCE) == USART2))
7397 
7398 /****************** UART Instances : Driver Enable *****************/
7399 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
7400                                                   ((INSTANCE) == USART2) || \
7401                                                   ((INSTANCE) == LPUART1))
7402 
7403 /******************** UART Instances : Half-Duplex mode **********************/
7404 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
7405                                                   ((INSTANCE) == USART2) || \
7406                                                   ((INSTANCE) == LPUART1))
7407 
7408 /******************** UART Instances : LIN mode **********************/
7409 #define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
7410                                            ((INSTANCE) == USART2))
7411 
7412 /******************** UART Instances : Wake-up from Stop mode **********************/
7413 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
7414                                                       ((INSTANCE) == USART2) || \
7415                                                       ((INSTANCE) == LPUART1))
7416 
7417 /****************** UART Instances : Hardware Flow control ********************/
7418 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7419                                            ((INSTANCE) == USART2) || \
7420                                            ((INSTANCE) == LPUART1))
7421 
7422 /********************* UART Instances : Smard card mode ***********************/
7423 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7424                                          ((INSTANCE) == USART2))
7425 
7426 /*********************** UART Instances : IRDA mode ***************************/
7427 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
7428                                     ((INSTANCE) == USART2))
7429 
7430 /******************** LPUART Instance *****************************************/
7431 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
7432 
7433 /****************************** IWDG Instances ********************************/
7434 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
7435 
7436 /******************************* USB Instances *******************************/
7437 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
7438 #define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
7439 
7440 /****************************** WWDG Instances ********************************/
7441 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
7442 
7443 /**
7444   * @}
7445   */
7446 
7447 /******************************************************************************/
7448 /*  For a painless codes migration between the STM32L0xx device product       */
7449 /*  lines, the aliases defined below are put in place to overcome the         */
7450 /*  differences in the interrupt handlers and IRQn definitions.               */
7451 /*  No need to update developed interrupt code when moving across             */
7452 /*  product lines within the same STM32L0 Family                              */
7453 /******************************************************************************/
7454 
7455 /* Aliases for __IRQn */
7456 
7457 #define LPUART1_IRQn                   AES_RNG_LPUART1_IRQn
7458 #define AES_LPUART1_IRQn               AES_RNG_LPUART1_IRQn
7459 #define RNG_LPUART1_IRQn               AES_RNG_LPUART1_IRQn
7460 #define TIM6_IRQn                      TIM6_DAC_IRQn
7461 #define RCC_IRQn                       RCC_CRS_IRQn
7462 #define DMA1_Channel4_5_IRQn           DMA1_Channel4_5_6_7_IRQn
7463 #define ADC1_IRQn                      ADC1_COMP_IRQn
7464 #define SVC_IRQn                       SVCall_IRQn
7465 
7466 /* Aliases for __IRQHandler */
7467 #define LPUART1_IRQHandler             AES_RNG_LPUART1_IRQHandler
7468 #define RNG_LPUART1_IRQHandler         AES_RNG_LPUART1_IRQHandler
7469 #define AES_LPUART1_IRQHandler         AES_RNG_LPUART1_IRQHandler
7470 #define TIM6_IRQHandler                TIM6_DAC_IRQHandler
7471 #define RCC_IRQHandler                 RCC_CRS_IRQHandler
7472 #define DMA1_Channel4_5_IRQHandler     DMA1_Channel4_5_6_7_IRQHandler
7473 #define ADC1_IRQHandler                ADC1_COMP_IRQHandler
7474 
7475 /**
7476   * @}
7477   */
7478 
7479 /**
7480   * @}
7481   */
7482 
7483 #ifdef __cplusplus
7484 }
7485 #endif /* __cplusplus */
7486 
7487 #endif /* __STM32L062xx_H */
7488 
7489 
7490 
7491