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Searched refs:tmpccmr2 (Results 1 – 25 of 40) sorted by relevance

12

/hal_stm32-3.6.0/stm32cube/stm32l0xx/drivers/src/
Dstm32l0xx_ll_tim.c595 uint32_t tmpccmr2; in OC3Config() local
615 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
618 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
621 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
633 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
654 uint32_t tmpccmr2; in OC4Config() local
674 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
677 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
680 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
692 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
Dstm32l0xx_hal_tim.c6974 uint32_t tmpccmr2; in TIM_TI3_SetConfig() local
6979 tmpccmr2 = TIMx->CCMR2; in TIM_TI3_SetConfig()
6983 tmpccmr2 &= ~TIM_CCMR2_CC3S; in TIM_TI3_SetConfig()
6984 tmpccmr2 |= TIM_ICSelection; in TIM_TI3_SetConfig()
6987 tmpccmr2 &= ~TIM_CCMR2_IC3F; in TIM_TI3_SetConfig()
6988 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); in TIM_TI3_SetConfig()
6995 TIMx->CCMR2 = tmpccmr2; in TIM_TI3_SetConfig()
7022 uint32_t tmpccmr2; in TIM_TI4_SetConfig() local
7027 tmpccmr2 = TIMx->CCMR2; in TIM_TI4_SetConfig()
7031 tmpccmr2 &= ~TIM_CCMR2_CC4S; in TIM_TI4_SetConfig()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32l1xx/drivers/src/
Dstm32l1xx_ll_tim.c618 uint32_t tmpccmr2; in OC3Config() local
638 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
641 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
644 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
656 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
677 uint32_t tmpccmr2; in OC4Config() local
697 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
700 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
703 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
715 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
Dstm32l1xx_hal_tim.c6981 uint32_t tmpccmr2; in TIM_TI3_SetConfig() local
6987 tmpccmr2 = TIMx->CCMR2; in TIM_TI3_SetConfig()
6990 tmpccmr2 &= ~TIM_CCMR2_CC3S; in TIM_TI3_SetConfig()
6991 tmpccmr2 |= TIM_ICSelection; in TIM_TI3_SetConfig()
6994 tmpccmr2 &= ~TIM_CCMR2_IC3F; in TIM_TI3_SetConfig()
6995 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); in TIM_TI3_SetConfig()
7002 TIMx->CCMR2 = tmpccmr2; in TIM_TI3_SetConfig()
7029 uint32_t tmpccmr2; in TIM_TI4_SetConfig() local
7035 tmpccmr2 = TIMx->CCMR2; in TIM_TI4_SetConfig()
7038 tmpccmr2 &= ~TIM_CCMR2_CC4S; in TIM_TI4_SetConfig()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32f0xx/drivers/src/
Dstm32f0xx_ll_tim.c880 uint32_t tmpccmr2; in OC3Config() local
902 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
905 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
908 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
938 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
959 uint32_t tmpccmr2; in OC4Config() local
981 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
984 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
987 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1008 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32f4xx/drivers/src/
Dstm32f4xx_ll_tim.c901 uint32_t tmpccmr2; in OC3Config() local
923 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
926 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
929 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
959 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
980 uint32_t tmpccmr2; in OC4Config() local
1002 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1005 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1008 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1029 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32f2xx/drivers/src/
Dstm32f2xx_ll_tim.c900 uint32_t tmpccmr2; in OC3Config() local
922 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
925 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
928 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
958 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
979 uint32_t tmpccmr2; in OC4Config() local
1001 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1004 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1007 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1028 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32f1xx/drivers/src/
Dstm32f1xx_ll_tim.c918 uint32_t tmpccmr2; in OC3Config() local
940 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
943 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
946 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
976 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
997 uint32_t tmpccmr2; in OC4Config() local
1019 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1022 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1025 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1046 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_ll_tim.c914 uint32_t tmpccmr2; in OC3Config() local
936 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
939 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
942 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
972 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
993 uint32_t tmpccmr2; in OC4Config() local
1015 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1018 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1021 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1042 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
Dstm32wlxx_hal_tim.c7690 uint32_t tmpccmr2; in TIM_TI3_SetConfig() local
7695 tmpccmr2 = TIMx->CCMR2; in TIM_TI3_SetConfig()
7699 tmpccmr2 &= ~TIM_CCMR2_CC3S; in TIM_TI3_SetConfig()
7700 tmpccmr2 |= TIM_ICSelection; in TIM_TI3_SetConfig()
7703 tmpccmr2 &= ~TIM_CCMR2_IC3F; in TIM_TI3_SetConfig()
7704 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); in TIM_TI3_SetConfig()
7711 TIMx->CCMR2 = tmpccmr2; in TIM_TI3_SetConfig()
7738 uint32_t tmpccmr2; in TIM_TI4_SetConfig() local
7743 tmpccmr2 = TIMx->CCMR2; in TIM_TI4_SetConfig()
7747 tmpccmr2 &= ~TIM_CCMR2_CC4S; in TIM_TI4_SetConfig()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_ll_tim.c925 uint32_t tmpccmr2; in OC3Config() local
947 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
950 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
953 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
983 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1004 uint32_t tmpccmr2; in OC4Config() local
1026 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1029 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1032 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1053 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_ll_tim.c930 uint32_t tmpccmr2; in OC3Config() local
950 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
953 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
956 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
988 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1009 uint32_t tmpccmr2; in OC4Config() local
1029 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1032 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1035 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1067 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_tim.c948 uint32_t tmpccmr2; in OC3Config() local
970 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
973 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
976 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1006 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1027 uint32_t tmpccmr2; in OC4Config() local
1049 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1052 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1055 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1076 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_tim.c979 uint32_t tmpccmr2; in OC3Config() local
1001 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
1004 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
1007 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1037 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1058 uint32_t tmpccmr2; in OC4Config() local
1080 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1083 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1086 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1107 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_ll_tim.c949 uint32_t tmpccmr2; in OC3Config() local
971 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
974 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
977 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1007 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1028 uint32_t tmpccmr2; in OC4Config() local
1050 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1053 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1056 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1077 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_ll_tim.c961 uint32_t tmpccmr2; in OC3Config() local
983 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
986 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
989 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1019 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1040 uint32_t tmpccmr2; in OC4Config() local
1062 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1065 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1068 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1089 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_ll_tim.c917 uint32_t tmpccmr2; in OC3Config() local
937 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
940 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
943 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
975 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
996 uint32_t tmpccmr2; in OC4Config() local
1016 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1019 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1022 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1042 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_ll_tim.c984 uint32_t tmpccmr2; in OC3Config() local
1006 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
1009 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
1012 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1042 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1063 uint32_t tmpccmr2; in OC4Config() local
1085 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1088 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1091 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1112 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
Dstm32mp1xx_hal_tim.c6693 uint32_t tmpccmr2; in TIM_TI3_SetConfig() local
6698 tmpccmr2 = TIMx->CCMR2; in TIM_TI3_SetConfig()
6702 tmpccmr2 &= ~TIM_CCMR2_CC3S; in TIM_TI3_SetConfig()
6703 tmpccmr2 |= TIM_ICSelection; in TIM_TI3_SetConfig()
6706 tmpccmr2 &= ~TIM_CCMR2_IC3F; in TIM_TI3_SetConfig()
6707 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); in TIM_TI3_SetConfig()
6714 TIMx->CCMR2 = tmpccmr2; in TIM_TI3_SetConfig()
6741 uint32_t tmpccmr2; in TIM_TI4_SetConfig() local
6746 tmpccmr2 = TIMx->CCMR2; in TIM_TI4_SetConfig()
6750 tmpccmr2 &= ~TIM_CCMR2_CC4S; in TIM_TI4_SetConfig()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_ll_tim.c1007 uint32_t tmpccmr2; in OC3Config() local
1029 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
1032 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
1035 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1065 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1086 uint32_t tmpccmr2; in OC4Config() local
1108 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1111 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1114 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1135 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
Dstm32h7xx_hal_tim.c7690 uint32_t tmpccmr2; in TIM_TI3_SetConfig() local
7695 tmpccmr2 = TIMx->CCMR2; in TIM_TI3_SetConfig()
7699 tmpccmr2 &= ~TIM_CCMR2_CC3S; in TIM_TI3_SetConfig()
7700 tmpccmr2 |= TIM_ICSelection; in TIM_TI3_SetConfig()
7703 tmpccmr2 &= ~TIM_CCMR2_IC3F; in TIM_TI3_SetConfig()
7704 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); in TIM_TI3_SetConfig()
7711 TIMx->CCMR2 = tmpccmr2; in TIM_TI3_SetConfig()
7738 uint32_t tmpccmr2; in TIM_TI4_SetConfig() local
7743 tmpccmr2 = TIMx->CCMR2; in TIM_TI4_SetConfig()
7747 tmpccmr2 &= ~TIM_CCMR2_CC4S; in TIM_TI4_SetConfig()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_tim.c969 uint32_t tmpccmr2; in OC3Config() local
991 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
994 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
997 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1027 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1048 uint32_t tmpccmr2; in OC4Config() local
1070 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1073 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1076 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1106 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_ll_tim.c1002 uint32_t tmpccmr2; in OC3Config() local
1024 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
1027 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
1030 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1060 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1081 uint32_t tmpccmr2; in OC4Config() local
1103 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1106 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1109 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1139 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_ll_tim.c967 uint32_t tmpccmr2; in OC3Config() local
989 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
992 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
995 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1025 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1046 uint32_t tmpccmr2; in OC4Config() local
1068 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1071 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1074 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1104 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()
/hal_stm32-3.6.0/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_tim.c1036 uint32_t tmpccmr2; in OC3Config() local
1058 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC3Config()
1061 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); in OC3Config()
1064 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
1097 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC3Config()
1118 uint32_t tmpccmr2; in OC4Config() local
1140 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); in OC4Config()
1143 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); in OC4Config()
1146 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); in OC4Config()
1170 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); in OC4Config()

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