1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2016 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32f3xx_ll_tim.h"
22 #include "stm32f3xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32F3xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #if defined(TIM_CCMR1_OC1M_3)
58 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
59 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
65 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
67 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
69 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
71 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
72 #else
73 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
74 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
75 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
76 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
77 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
78 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
79 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
80 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
81 #endif /* TIM_CCMR1_OC1M_3 */
82
83 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
84 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
85
86 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
87 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
88
89 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
90 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
91
92 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
93 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
94 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
95
96 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
97 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
98 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
99 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
100
101 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
108 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
109 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
117
118 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
119 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
120 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
121
122 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
123 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
124 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
125
126 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
127 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
128
129 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
130 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
131
132 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
133 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
134
135 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
136 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
137 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
138 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
139
140 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
141 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
142
143 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
144 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
145 #if defined(TIM_BDTR_BKF)
146
147 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
151 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
152 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
153 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
154 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
155 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
156 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
157 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
158 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
159 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
160 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
161 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
162 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
163 #endif /* TIM_BDTR_BKF */
164 #if defined(TIM_BDTR_BK2E)
165
166 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
167 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
168
169 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
170 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
171
172 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
177 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
178 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
179 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
180 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
181 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
182 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
183 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
184 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
185 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
186 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
187 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
188 #endif /* TIM_BDTR_BK2E */
189
190 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
191 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
192 /**
193 * @}
194 */
195
196
197 /* Private function prototypes -----------------------------------------------*/
198 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
199 * @{
200 */
201 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
202 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
203 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
204 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
205 #if defined(TIM_CCER_CC5E)
206 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
207 #endif /* TIM_CCER_CC5E */
208 #if defined(TIM_CCER_CC6E)
209 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
210 #endif /* TIM_CCER_CC6E */
211 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
212 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
213 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
214 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
215 /**
216 * @}
217 */
218
219 /* Exported functions --------------------------------------------------------*/
220 /** @addtogroup TIM_LL_Exported_Functions
221 * @{
222 */
223
224 /** @addtogroup TIM_LL_EF_Init
225 * @{
226 */
227
228 /**
229 * @brief Set TIMx registers to their reset values.
230 * @param TIMx Timer instance
231 * @retval An ErrorStatus enumeration value:
232 * - SUCCESS: TIMx registers are de-initialized
233 * - ERROR: invalid TIMx instance
234 */
LL_TIM_DeInit(const TIM_TypeDef * TIMx)235 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
236 {
237 ErrorStatus result = SUCCESS;
238
239 /* Check the parameters */
240 assert_param(IS_TIM_INSTANCE(TIMx));
241
242
243 if (TIMx == TIM2)
244 {
245 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
246 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
247 }
248
249 #if defined(TIM1)
250 else if (TIMx == TIM1)
251 {
252 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
253 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
254 }
255 #endif /* TIM1 */
256 #if defined(TIM3)
257 else if (TIMx == TIM3)
258 {
259 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
260 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
261 }
262 #endif /* TIM3 */
263 #if defined(TIM4)
264 else if (TIMx == TIM4)
265 {
266 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
267 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
268 }
269 #endif /* TIM4 */
270 #if defined(TIM5)
271 else if (TIMx == TIM5)
272 {
273 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
274 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
275 }
276 #endif /* TIM5 */
277 #if defined(TIM6)
278 else if (TIMx == TIM6)
279 {
280 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
281 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
282 }
283 #endif /* TIM6 */
284 #if defined(TIM7)
285 else if (TIMx == TIM7)
286 {
287 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
288 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
289 }
290 #endif /* TIM7 */
291 #if defined(TIM8)
292 else if (TIMx == TIM8)
293 {
294 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
295 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
296 }
297 #endif /* TIM8 */
298 #if defined(TIM12)
299 else if (TIMx == TIM12)
300 {
301 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
302 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
303 }
304 #endif /* TIM12 */
305 #if defined(TIM13)
306 else if (TIMx == TIM13)
307 {
308 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
309 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
310 }
311 #endif /* TIM13 */
312 #if defined(TIM14)
313 else if (TIMx == TIM14)
314 {
315 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
316 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
317 }
318 #endif /* TIM14 */
319 #if defined(TIM15)
320 else if (TIMx == TIM15)
321 {
322 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
323 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
324 }
325 #endif /* TIM15 */
326 #if defined(TIM16)
327 else if (TIMx == TIM16)
328 {
329 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
330 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
331 }
332 #endif /* TIM16 */
333 #if defined(TIM17)
334 else if (TIMx == TIM17)
335 {
336 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
337 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
338 }
339 #endif /* TIM17 */
340 #if defined(TIM18)
341 else if (TIMx == TIM18)
342 {
343 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM18);
344 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM18);
345 }
346 #endif /* TIM18 */
347 #if defined(TIM19)
348 else if (TIMx == TIM19)
349 {
350 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM19);
351 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM19);
352 }
353 #endif /* TIM19 */
354 #if defined(TIM20)
355 else if (TIMx == TIM20)
356 {
357 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
358 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
359 }
360 #endif /* TIM20 */
361 else
362 {
363 result = ERROR;
364 }
365
366 return result;
367 }
368
369 /**
370 * @brief Set the fields of the time base unit configuration data structure
371 * to their default values.
372 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
373 * @retval None
374 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)375 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
376 {
377 /* Set the default configuration */
378 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
379 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
380 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
381 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
382 TIM_InitStruct->RepetitionCounter = 0x00000000U;
383 }
384
385 /**
386 * @brief Configure the TIMx time base unit.
387 * @param TIMx Timer Instance
388 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
389 * (TIMx time base unit configuration data structure)
390 * @retval An ErrorStatus enumeration value:
391 * - SUCCESS: TIMx registers are de-initialized
392 * - ERROR: not applicable
393 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)394 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
395 {
396 uint32_t tmpcr1;
397
398 /* Check the parameters */
399 assert_param(IS_TIM_INSTANCE(TIMx));
400 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
401 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
402
403 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
404
405 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
406 {
407 /* Select the Counter Mode */
408 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
409 }
410
411 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
412 {
413 /* Set the clock division */
414 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
415 }
416
417 /* Write to TIMx CR1 */
418 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
419
420 /* Set the Autoreload value */
421 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
422
423 /* Set the Prescaler value */
424 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
425
426 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
427 {
428 /* Set the Repetition Counter value */
429 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
430 }
431
432 /* Generate an update event to reload the Prescaler
433 and the repetition counter value (if applicable) immediately */
434 LL_TIM_GenerateEvent_UPDATE(TIMx);
435
436 return SUCCESS;
437 }
438
439 /**
440 * @brief Set the fields of the TIMx output channel configuration data
441 * structure to their default values.
442 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
443 * (the output channel configuration data structure)
444 * @retval None
445 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)446 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
447 {
448 /* Set the default configuration */
449 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
450 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
451 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
452 TIM_OC_InitStruct->CompareValue = 0x00000000U;
453 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
454 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
455 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
456 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
457 }
458
459 /**
460 * @brief Configure the TIMx output channel.
461 * @param TIMx Timer Instance
462 * @param Channel This parameter can be one of the following values:
463 * @arg @ref LL_TIM_CHANNEL_CH1
464 * @arg @ref LL_TIM_CHANNEL_CH2
465 * @arg @ref LL_TIM_CHANNEL_CH3
466 * @arg @ref LL_TIM_CHANNEL_CH4
467 * @arg @ref LL_TIM_CHANNEL_CH5
468 * @arg @ref LL_TIM_CHANNEL_CH6
469 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
470 * data structure)
471 * @note OC5 and OC6 are not available for all F3 devices
472 * @retval An ErrorStatus enumeration value:
473 * - SUCCESS: TIMx output channel is initialized
474 * - ERROR: TIMx output channel is not initialized
475 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)476 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
477 {
478 ErrorStatus result = ERROR;
479
480 switch (Channel)
481 {
482 case LL_TIM_CHANNEL_CH1:
483 result = OC1Config(TIMx, TIM_OC_InitStruct);
484 break;
485 case LL_TIM_CHANNEL_CH2:
486 result = OC2Config(TIMx, TIM_OC_InitStruct);
487 break;
488 case LL_TIM_CHANNEL_CH3:
489 result = OC3Config(TIMx, TIM_OC_InitStruct);
490 break;
491 case LL_TIM_CHANNEL_CH4:
492 result = OC4Config(TIMx, TIM_OC_InitStruct);
493 break;
494 #if defined(TIM_CCER_CC5E)
495 case LL_TIM_CHANNEL_CH5:
496 result = OC5Config(TIMx, TIM_OC_InitStruct);
497 break;
498 case LL_TIM_CHANNEL_CH6:
499 result = OC6Config(TIMx, TIM_OC_InitStruct);
500 break;
501 #endif /* TIM_CCER_CC5E */
502 default:
503 break;
504 }
505
506 return result;
507 }
508
509 /**
510 * @brief Set the fields of the TIMx input channel configuration data
511 * structure to their default values.
512 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
513 * data structure)
514 * @retval None
515 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)516 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
517 {
518 /* Set the default configuration */
519 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
520 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
521 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
522 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
523 }
524
525 /**
526 * @brief Configure the TIMx input channel.
527 * @param TIMx Timer Instance
528 * @param Channel This parameter can be one of the following values:
529 * @arg @ref LL_TIM_CHANNEL_CH1
530 * @arg @ref LL_TIM_CHANNEL_CH2
531 * @arg @ref LL_TIM_CHANNEL_CH3
532 * @arg @ref LL_TIM_CHANNEL_CH4
533 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
534 * structure)
535 * @retval An ErrorStatus enumeration value:
536 * - SUCCESS: TIMx output channel is initialized
537 * - ERROR: TIMx output channel is not initialized
538 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)539 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
540 {
541 ErrorStatus result = ERROR;
542
543 switch (Channel)
544 {
545 case LL_TIM_CHANNEL_CH1:
546 result = IC1Config(TIMx, TIM_IC_InitStruct);
547 break;
548 case LL_TIM_CHANNEL_CH2:
549 result = IC2Config(TIMx, TIM_IC_InitStruct);
550 break;
551 case LL_TIM_CHANNEL_CH3:
552 result = IC3Config(TIMx, TIM_IC_InitStruct);
553 break;
554 case LL_TIM_CHANNEL_CH4:
555 result = IC4Config(TIMx, TIM_IC_InitStruct);
556 break;
557 default:
558 break;
559 }
560
561 return result;
562 }
563
564 /**
565 * @brief Fills each TIM_EncoderInitStruct field with its default value
566 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
567 * configuration data structure)
568 * @retval None
569 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)570 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
571 {
572 /* Set the default configuration */
573 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
574 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
575 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
576 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
577 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
578 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
579 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
580 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
581 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
582 }
583
584 /**
585 * @brief Configure the encoder interface of the timer instance.
586 * @param TIMx Timer Instance
587 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
588 * configuration data structure)
589 * @retval An ErrorStatus enumeration value:
590 * - SUCCESS: TIMx registers are de-initialized
591 * - ERROR: not applicable
592 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)593 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
594 {
595 uint32_t tmpccmr1;
596 uint32_t tmpccer;
597
598 /* Check the parameters */
599 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
600 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
601 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
602 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
603 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
604 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
605 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
606 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
607 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
608 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
609
610 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
611 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
612
613 /* Get the TIMx CCMR1 register value */
614 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
615
616 /* Get the TIMx CCER register value */
617 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
618
619 /* Configure TI1 */
620 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
621 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
622 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
623 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
624
625 /* Configure TI2 */
626 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
627 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
628 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
629 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
630
631 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
632 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
633 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
634 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
635 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
636
637 /* Set encoder mode */
638 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
639
640 /* Write to TIMx CCMR1 */
641 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
642
643 /* Write to TIMx CCER */
644 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
645
646 return SUCCESS;
647 }
648
649 #if defined TIM_CR2_MMS2
650 /**
651 * @brief Set the fields of the TIMx Hall sensor interface configuration data
652 * structure to their default values.
653 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
654 * configuration data structure)
655 * @retval None
656 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)657 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
658 {
659 /* Set the default configuration */
660 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
661 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
662 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
663 TIM_HallSensorInitStruct->CommutationDelay = 0U;
664 }
665
666 /**
667 * @brief Configure the Hall sensor interface of the timer instance.
668 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
669 * to the TI1 input channel
670 * @note TIMx slave mode controller is configured in reset mode.
671 Selected internal trigger is TI1F_ED.
672 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
673 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
674 * between 2 changes on the inputs. It gives information about motor speed.
675 * @note Channel 2 is configured in output PWM 2 mode.
676 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
677 * @note OC2REF is selected as trigger output on TRGO.
678 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
679 * when TIMx operates in Hall sensor interface mode.
680 * @param TIMx Timer Instance
681 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
682 * interface configuration data structure)
683 * @retval An ErrorStatus enumeration value:
684 * - SUCCESS: TIMx registers are de-initialized
685 * - ERROR: not applicable
686 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)687 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
688 {
689 uint32_t tmpcr2;
690 uint32_t tmpccmr1;
691 uint32_t tmpccer;
692 uint32_t tmpsmcr;
693
694 /* Check the parameters */
695 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
696 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
697 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
698 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
699
700 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
701 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
702
703 /* Get the TIMx CR2 register value */
704 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
705
706 /* Get the TIMx CCMR1 register value */
707 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
708
709 /* Get the TIMx CCER register value */
710 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
711
712 /* Get the TIMx SMCR register value */
713 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
714
715 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
716 tmpcr2 |= TIM_CR2_TI1S;
717
718 /* OC2REF signal is used as trigger output (TRGO) */
719 tmpcr2 |= LL_TIM_TRGO_OC2REF;
720
721 /* Configure the slave mode controller */
722 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
723 tmpsmcr |= LL_TIM_TS_TI1F_ED;
724 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
725
726 /* Configure input channel 1 */
727 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
728 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
729 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
730 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
731
732 /* Configure input channel 2 */
733 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
734 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
735
736 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
737 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
738 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
739 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
740
741 /* Write to TIMx CR2 */
742 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
743
744 /* Write to TIMx SMCR */
745 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
746
747 /* Write to TIMx CCMR1 */
748 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
749
750 /* Write to TIMx CCER */
751 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
752
753 /* Write to TIMx CCR2 */
754 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
755
756 return SUCCESS;
757 }
758 #endif /* TIM_CR2_MMS2 */
759
760 /**
761 * @brief Set the fields of the Break and Dead Time configuration data structure
762 * to their default values.
763 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
764 * data structure)
765 * @retval None
766 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)767 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
768 {
769 /* Set the default configuration */
770 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
771 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
772 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
773 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
774 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
775 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
776 #if defined(TIM_BDTR_BKF)
777 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
778 #endif /* TIM_BDTR_BKF */
779 #if defined(TIM_BDTR_BK2E)
780 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
781 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
782 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
783 #endif /* TIM_BDTR_BK2E */
784 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
785 }
786
787 /**
788 * @brief Configure the Break and Dead Time feature of the timer instance.
789 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
790 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
791 * can be necessary to configure all of them during the first write access to
792 * the TIMx_BDTR register.
793 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
794 * a timer instance provides a break input.
795 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
796 * a timer instance provides a second break input.
797 * @param TIMx Timer Instance
798 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
799 * data structure)
800 * @retval An ErrorStatus enumeration value:
801 * - SUCCESS: Break and Dead Time is initialized
802 * - ERROR: not applicable
803 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)804 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
805 {
806 uint32_t tmpbdtr = 0;
807
808 /* Check the parameters */
809 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
810 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
811 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
812 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
813 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
814 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
815 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
816
817 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
818 the OSSI State, the dead time value and the Automatic Output Enable Bit */
819
820 /* Set the BDTR bits */
821 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
822 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
823 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
824 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
825 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
826 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
827 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
828 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
829 #if defined(TIM_BDTR_BKF)
830 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
831 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
832 #endif /* TIM_BDTR_BKF */
833 #if defined(TIM_BDTR_BK2E)
834
835 if (IS_TIM_BKIN2_INSTANCE(TIMx))
836 {
837 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
838 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
839 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
840
841 /* Set the BREAK2 input related BDTR bit-fields */
842 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
843 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
844 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
845 }
846 #endif /* TIM_BDTR_BK2E */
847
848 /* Set TIMx_BDTR */
849 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
850
851 return SUCCESS;
852 }
853 /**
854 * @}
855 */
856
857 /**
858 * @}
859 */
860
861 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
862 * @brief Private functions
863 * @{
864 */
865 /**
866 * @brief Configure the TIMx output channel 1.
867 * @param TIMx Timer Instance
868 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
869 * @retval An ErrorStatus enumeration value:
870 * - SUCCESS: TIMx registers are de-initialized
871 * - ERROR: not applicable
872 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)873 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
874 {
875 uint32_t tmpccmr1;
876 uint32_t tmpccer;
877 uint32_t tmpcr2;
878
879 /* Check the parameters */
880 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
881 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
882 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
883 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
884 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
885 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
886
887 /* Disable the Channel 1: Reset the CC1E Bit */
888 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
889
890 /* Get the TIMx CCER register value */
891 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
892
893 /* Get the TIMx CR2 register value */
894 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
895
896 /* Get the TIMx CCMR1 register value */
897 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
898
899 /* Reset Capture/Compare selection Bits */
900 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
901
902 /* Set the Output Compare Mode */
903 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
904
905 /* Set the Output Compare Polarity */
906 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
907
908 /* Set the Output State */
909 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
910
911 if (IS_TIM_BREAK_INSTANCE(TIMx))
912 {
913 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
914 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
915
916 /* Set the complementary output Polarity */
917 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
918
919 /* Set the complementary output State */
920 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
921
922 /* Set the Output Idle state */
923 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
924
925 /* Set the complementary output Idle state */
926 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
927 }
928
929 /* Write to TIMx CR2 */
930 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
931
932 /* Write to TIMx CCMR1 */
933 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
934
935 /* Set the Capture Compare Register value */
936 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
937
938 /* Write to TIMx CCER */
939 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
940
941 return SUCCESS;
942 }
943
944 /**
945 * @brief Configure the TIMx output channel 2.
946 * @param TIMx Timer Instance
947 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
948 * @retval An ErrorStatus enumeration value:
949 * - SUCCESS: TIMx registers are de-initialized
950 * - ERROR: not applicable
951 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)952 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
953 {
954 uint32_t tmpccmr1;
955 uint32_t tmpccer;
956 uint32_t tmpcr2;
957
958 /* Check the parameters */
959 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
960 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
961 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
962 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
963 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
964 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
965
966 /* Disable the Channel 2: Reset the CC2E Bit */
967 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
968
969 /* Get the TIMx CCER register value */
970 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
971
972 /* Get the TIMx CR2 register value */
973 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
974
975 /* Get the TIMx CCMR1 register value */
976 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
977
978 /* Reset Capture/Compare selection Bits */
979 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
980
981 /* Select the Output Compare Mode */
982 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
983
984 /* Set the Output Compare Polarity */
985 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
986
987 /* Set the Output State */
988 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
989
990 if (IS_TIM_BREAK_INSTANCE(TIMx))
991 {
992 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
993 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
994
995 /* Set the complementary output Polarity */
996 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
997
998 /* Set the complementary output State */
999 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
1000
1001 /* Set the Output Idle state */
1002 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
1003
1004 #if defined(STM32F373xC) || defined(STM32F378xx)
1005 #else
1006 /* Set the complementary output Idle state */
1007 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
1008 #endif
1009 }
1010
1011 /* Write to TIMx CR2 */
1012 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1013
1014 /* Write to TIMx CCMR1 */
1015 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
1016
1017 /* Set the Capture Compare Register value */
1018 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
1019
1020 /* Write to TIMx CCER */
1021 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1022
1023 return SUCCESS;
1024 }
1025
1026 /**
1027 * @brief Configure the TIMx output channel 3.
1028 * @param TIMx Timer Instance
1029 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
1030 * @retval An ErrorStatus enumeration value:
1031 * - SUCCESS: TIMx registers are de-initialized
1032 * - ERROR: not applicable
1033 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1034 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1035 {
1036 uint32_t tmpccmr2;
1037 uint32_t tmpccer;
1038 uint32_t tmpcr2;
1039
1040 /* Check the parameters */
1041 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1042 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1043 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1044 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1045 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1046 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1047
1048 /* Disable the Channel 3: Reset the CC3E Bit */
1049 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
1050
1051 /* Get the TIMx CCER register value */
1052 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1053
1054 /* Get the TIMx CR2 register value */
1055 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1056
1057 /* Get the TIMx CCMR2 register value */
1058 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1059
1060 /* Reset Capture/Compare selection Bits */
1061 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
1062
1063 /* Select the Output Compare Mode */
1064 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
1065
1066 /* Set the Output Compare Polarity */
1067 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1068
1069 /* Set the Output State */
1070 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1071
1072 if (IS_TIM_BREAK_INSTANCE(TIMx))
1073 {
1074 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1075 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1076
1077 /* Set the complementary output Polarity */
1078 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1079
1080 /* Set the complementary output State */
1081 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1082
1083 #if defined(STM32F373xC) || defined(STM32F378xx)
1084 #else
1085 /* Set the Output Idle state */
1086 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1087
1088 /* Set the complementary output Idle state */
1089 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1090 #endif
1091 }
1092
1093 /* Write to TIMx CR2 */
1094 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1095
1096 /* Write to TIMx CCMR2 */
1097 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1098
1099 /* Set the Capture Compare Register value */
1100 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1101
1102 /* Write to TIMx CCER */
1103 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1104
1105 return SUCCESS;
1106 }
1107
1108 /**
1109 * @brief Configure the TIMx output channel 4.
1110 * @param TIMx Timer Instance
1111 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1112 * @retval An ErrorStatus enumeration value:
1113 * - SUCCESS: TIMx registers are de-initialized
1114 * - ERROR: not applicable
1115 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1116 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1117 {
1118 uint32_t tmpccmr2;
1119 uint32_t tmpccer;
1120 uint32_t tmpcr2;
1121
1122 /* Check the parameters */
1123 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1124 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1125 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1126 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1127 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1128 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1129
1130 /* Disable the Channel 4: Reset the CC4E Bit */
1131 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1132
1133 /* Get the TIMx CCER register value */
1134 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1135
1136 /* Get the TIMx CR2 register value */
1137 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1138
1139 /* Get the TIMx CCMR2 register value */
1140 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1141
1142 /* Reset Capture/Compare selection Bits */
1143 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1144
1145 /* Select the Output Compare Mode */
1146 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1147
1148 /* Set the Output Compare Polarity */
1149 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1150
1151 /* Set the Output State */
1152 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1153
1154 if (IS_TIM_BREAK_INSTANCE(TIMx))
1155 {
1156 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1157 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1158
1159 #if defined(STM32F373xC) || defined(STM32F378xx)
1160 #else
1161 /* Set the Output Idle state */
1162 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1163 #endif
1164 }
1165
1166 /* Write to TIMx CR2 */
1167 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1168
1169 /* Write to TIMx CCMR2 */
1170 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1171
1172 /* Set the Capture Compare Register value */
1173 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1174
1175 /* Write to TIMx CCER */
1176 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1177
1178 return SUCCESS;
1179 }
1180
1181 #if defined(TIM_CCER_CC5E)
1182 /**
1183 * @brief Configure the TIMx output channel 5.
1184 * @param TIMx Timer Instance
1185 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1186 * @note OC5 is not available for all F3 devices
1187 * @retval An ErrorStatus enumeration value:
1188 * - SUCCESS: TIMx registers are de-initialized
1189 * - ERROR: not applicable
1190 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1191 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1192 {
1193 uint32_t tmpccmr3;
1194 uint32_t tmpccer;
1195
1196 /* Check the parameters */
1197 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1198 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1199 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1200 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1201 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1202 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1203
1204 /* Disable the Channel 5: Reset the CC5E Bit */
1205 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1206
1207 /* Get the TIMx CCER register value */
1208 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1209
1210 /* Get the TIMx CCMR3 register value */
1211 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1212
1213 /* Select the Output Compare Mode */
1214 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1215
1216 /* Set the Output Compare Polarity */
1217 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1218
1219 /* Set the Output State */
1220 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1221
1222 if (IS_TIM_BREAK_INSTANCE(TIMx))
1223 {
1224 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1225 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1226
1227 /* Set the Output Idle state */
1228 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1229
1230 }
1231
1232 /* Write to TIMx CCMR3 */
1233 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1234
1235 /* Set the Capture Compare Register value */
1236 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1237
1238 /* Write to TIMx CCER */
1239 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1240
1241 return SUCCESS;
1242 }
1243
1244 /**
1245 * @brief Configure the TIMx output channel 6.
1246 * @param TIMx Timer Instance
1247 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1248 * @note OC6 is not available for all F3 devices
1249 * @retval An ErrorStatus enumeration value:
1250 * - SUCCESS: TIMx registers are de-initialized
1251 * - ERROR: not applicable
1252 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1253 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1254 {
1255 uint32_t tmpccmr3;
1256 uint32_t tmpccer;
1257
1258 /* Check the parameters */
1259 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1260 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1261 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1262 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1263 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1264 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1265
1266 /* Disable the Channel 5: Reset the CC6E Bit */
1267 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1268
1269 /* Get the TIMx CCER register value */
1270 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1271
1272 /* Get the TIMx CCMR3 register value */
1273 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1274
1275 /* Select the Output Compare Mode */
1276 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1277
1278 /* Set the Output Compare Polarity */
1279 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1280
1281 /* Set the Output State */
1282 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1283
1284 if (IS_TIM_BREAK_INSTANCE(TIMx))
1285 {
1286 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1287 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1288
1289 /* Set the Output Idle state */
1290 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1291 }
1292
1293 /* Write to TIMx CCMR3 */
1294 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1295
1296 /* Set the Capture Compare Register value */
1297 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1298
1299 /* Write to TIMx CCER */
1300 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1301
1302 return SUCCESS;
1303 }
1304 #endif /* TIM_CCER_CC5E */
1305
1306 /**
1307 * @brief Configure the TIMx input channel 1.
1308 * @param TIMx Timer Instance
1309 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1310 * @retval An ErrorStatus enumeration value:
1311 * - SUCCESS: TIMx registers are de-initialized
1312 * - ERROR: not applicable
1313 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1314 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1315 {
1316 /* Check the parameters */
1317 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1318 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1319 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1320 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1321 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1322
1323 /* Disable the Channel 1: Reset the CC1E Bit */
1324 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1325
1326 /* Select the Input and set the filter and the prescaler value */
1327 MODIFY_REG(TIMx->CCMR1,
1328 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1329 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1330
1331 /* Select the Polarity and set the CC1E Bit */
1332 MODIFY_REG(TIMx->CCER,
1333 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1334 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1335
1336 return SUCCESS;
1337 }
1338
1339 /**
1340 * @brief Configure the TIMx input channel 2.
1341 * @param TIMx Timer Instance
1342 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1343 * @retval An ErrorStatus enumeration value:
1344 * - SUCCESS: TIMx registers are de-initialized
1345 * - ERROR: not applicable
1346 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1347 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1348 {
1349 /* Check the parameters */
1350 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1351 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1352 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1353 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1354 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1355
1356 /* Disable the Channel 2: Reset the CC2E Bit */
1357 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1358
1359 /* Select the Input and set the filter and the prescaler value */
1360 MODIFY_REG(TIMx->CCMR1,
1361 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1362 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1363
1364 /* Select the Polarity and set the CC2E Bit */
1365 MODIFY_REG(TIMx->CCER,
1366 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1367 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1368
1369 return SUCCESS;
1370 }
1371
1372 /**
1373 * @brief Configure the TIMx input channel 3.
1374 * @param TIMx Timer Instance
1375 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1376 * @retval An ErrorStatus enumeration value:
1377 * - SUCCESS: TIMx registers are de-initialized
1378 * - ERROR: not applicable
1379 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1380 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1381 {
1382 /* Check the parameters */
1383 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1384 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1385 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1386 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1387 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1388
1389 /* Disable the Channel 3: Reset the CC3E Bit */
1390 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1391
1392 /* Select the Input and set the filter and the prescaler value */
1393 MODIFY_REG(TIMx->CCMR2,
1394 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1395 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1396
1397 /* Select the Polarity and set the CC3E Bit */
1398 MODIFY_REG(TIMx->CCER,
1399 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1400 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1401
1402 return SUCCESS;
1403 }
1404
1405 /**
1406 * @brief Configure the TIMx input channel 4.
1407 * @param TIMx Timer Instance
1408 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1409 * @retval An ErrorStatus enumeration value:
1410 * - SUCCESS: TIMx registers are de-initialized
1411 * - ERROR: not applicable
1412 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1413 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1414 {
1415 /* Check the parameters */
1416 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1417 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1418 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1419 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1420 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1421
1422 /* Disable the Channel 4: Reset the CC4E Bit */
1423 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1424
1425 /* Select the Input and set the filter and the prescaler value */
1426 MODIFY_REG(TIMx->CCMR2,
1427 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1428 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1429
1430 /* Select the Polarity and set the CC2E Bit */
1431 MODIFY_REG(TIMx->CCER,
1432 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1433 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1434
1435 return SUCCESS;
1436 }
1437
1438
1439 /**
1440 * @}
1441 */
1442
1443 /**
1444 * @}
1445 */
1446
1447 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
1448
1449 /**
1450 * @}
1451 */
1452
1453 #endif /* USE_FULL_LL_DRIVER */
1454
1455
