1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32l5xx_ll_tim.h"
22 #include "stm32l5xx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32L5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM7)
35
36 /** @addtogroup TIM_LL
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 /** @addtogroup TIM_LL_Private_Macros
45 * @{
46 */
47 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
65 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
66 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
67 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
68 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
69 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
70 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
71
72 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
73 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
74
75 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
76 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
77
78 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
79 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
80
81 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
82 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
83 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
84
85 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
86 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
87 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
88 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
89
90 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
100 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
101 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
106
107 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
108 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
109 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
110
111 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
112 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
113 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
114
115 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
116 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
117
118 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
119 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
120
121 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
122 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
123
124 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
125 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
126 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
127 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
128
129 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
130 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
131
132 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
133 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
134
135 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \
136 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \
137 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \
138 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \
139 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \
140 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \
141 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \
142 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \
143 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \
144 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \
145 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
146 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
147 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
148 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
149 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
150 || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
151
152 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \
153 || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
154
155 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
156 || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
157
158 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
159 || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
160
161 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
162 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
163 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
164 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
165 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
166 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
167 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
168 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
169 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
170 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
171 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
172 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
173 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
174 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
175 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
176 || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
177
178 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \
179 || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
180
181 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
182 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
183 /**
184 * @}
185 */
186
187
188 /* Private function prototypes -----------------------------------------------*/
189 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
190 * @{
191 */
192 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
193 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
194 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
195 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
196 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
197 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
198 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
199 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
200 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
201 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
202 /**
203 * @}
204 */
205
206 /* Exported functions --------------------------------------------------------*/
207 /** @addtogroup TIM_LL_Exported_Functions
208 * @{
209 */
210
211 /** @addtogroup TIM_LL_EF_Init
212 * @{
213 */
214
215 /**
216 * @brief Set TIMx registers to their reset values.
217 * @param TIMx Timer instance
218 * @retval An ErrorStatus enumeration value:
219 * - SUCCESS: TIMx registers are de-initialized
220 * - ERROR: invalid TIMx instance
221 */
LL_TIM_DeInit(TIM_TypeDef * TIMx)222 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
223 {
224 ErrorStatus result = SUCCESS;
225
226 /* Check the parameters */
227 assert_param(IS_TIM_INSTANCE(TIMx));
228
229 if (TIMx == TIM1)
230 {
231 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
232 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
233 }
234 else if (TIMx == TIM2)
235 {
236 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
237 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
238 }
239 else if (TIMx == TIM3)
240 {
241 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
242 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
243 }
244 else if (TIMx == TIM4)
245 {
246 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
247 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
248 }
249 else if (TIMx == TIM5)
250 {
251 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
252 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
253 }
254 else if (TIMx == TIM6)
255 {
256 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
257 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
258 }
259 else if (TIMx == TIM7)
260 {
261 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
262 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
263 }
264 else if (TIMx == TIM8)
265 {
266 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
267 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
268 }
269 else if (TIMx == TIM15)
270 {
271 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
272 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
273 }
274 else if (TIMx == TIM16)
275 {
276 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
277 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
278 }
279 else if (TIMx == TIM17)
280 {
281 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
282 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
283 }
284 else
285 {
286 result = ERROR;
287 }
288
289 return result;
290 }
291
292 /**
293 * @brief Set the fields of the time base unit configuration data structure
294 * to their default values.
295 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
296 * @retval None
297 */
LL_TIM_StructInit(LL_TIM_InitTypeDef * TIM_InitStruct)298 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
299 {
300 /* Set the default configuration */
301 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
302 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
303 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
304 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
305 TIM_InitStruct->RepetitionCounter = 0x00000000U;
306 }
307
308 /**
309 * @brief Configure the TIMx time base unit.
310 * @param TIMx Timer Instance
311 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
312 * (TIMx time base unit configuration data structure)
313 * @retval An ErrorStatus enumeration value:
314 * - SUCCESS: TIMx registers are de-initialized
315 * - ERROR: not applicable
316 */
LL_TIM_Init(TIM_TypeDef * TIMx,const LL_TIM_InitTypeDef * TIM_InitStruct)317 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
318 {
319 uint32_t tmpcr1;
320
321 /* Check the parameters */
322 assert_param(IS_TIM_INSTANCE(TIMx));
323 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
324 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
325
326 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
327
328 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
329 {
330 /* Select the Counter Mode */
331 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
332 }
333
334 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
335 {
336 /* Set the clock division */
337 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
338 }
339
340 /* Write to TIMx CR1 */
341 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
342
343 /* Set the Autoreload value */
344 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
345
346 /* Set the Prescaler value */
347 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
348
349 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
350 {
351 /* Set the Repetition Counter value */
352 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
353 }
354
355 /* Generate an update event to reload the Prescaler
356 and the repetition counter value (if applicable) immediately */
357 LL_TIM_GenerateEvent_UPDATE(TIMx);
358
359 return SUCCESS;
360 }
361
362 /**
363 * @brief Set the fields of the TIMx output channel configuration data
364 * structure to their default values.
365 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
366 * (the output channel configuration data structure)
367 * @retval None
368 */
LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)369 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
370 {
371 /* Set the default configuration */
372 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
373 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
374 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
375 TIM_OC_InitStruct->CompareValue = 0x00000000U;
376 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
377 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
378 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
379 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
380 }
381
382 /**
383 * @brief Configure the TIMx output channel.
384 * @param TIMx Timer Instance
385 * @param Channel This parameter can be one of the following values:
386 * @arg @ref LL_TIM_CHANNEL_CH1
387 * @arg @ref LL_TIM_CHANNEL_CH2
388 * @arg @ref LL_TIM_CHANNEL_CH3
389 * @arg @ref LL_TIM_CHANNEL_CH4
390 * @arg @ref LL_TIM_CHANNEL_CH5
391 * @arg @ref LL_TIM_CHANNEL_CH6
392 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
393 * data structure)
394 * @retval An ErrorStatus enumeration value:
395 * - SUCCESS: TIMx output channel is initialized
396 * - ERROR: TIMx output channel is not initialized
397 */
LL_TIM_OC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_OC_InitTypeDef * TIM_OC_InitStruct)398 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
399 {
400 ErrorStatus result = ERROR;
401
402 switch (Channel)
403 {
404 case LL_TIM_CHANNEL_CH1:
405 result = OC1Config(TIMx, TIM_OC_InitStruct);
406 break;
407 case LL_TIM_CHANNEL_CH2:
408 result = OC2Config(TIMx, TIM_OC_InitStruct);
409 break;
410 case LL_TIM_CHANNEL_CH3:
411 result = OC3Config(TIMx, TIM_OC_InitStruct);
412 break;
413 case LL_TIM_CHANNEL_CH4:
414 result = OC4Config(TIMx, TIM_OC_InitStruct);
415 break;
416 case LL_TIM_CHANNEL_CH5:
417 result = OC5Config(TIMx, TIM_OC_InitStruct);
418 break;
419 case LL_TIM_CHANNEL_CH6:
420 result = OC6Config(TIMx, TIM_OC_InitStruct);
421 break;
422 default:
423 break;
424 }
425
426 return result;
427 }
428
429 /**
430 * @brief Set the fields of the TIMx input channel configuration data
431 * structure to their default values.
432 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
433 * data structure)
434 * @retval None
435 */
LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)436 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
437 {
438 /* Set the default configuration */
439 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
440 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
441 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
442 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
443 }
444
445 /**
446 * @brief Configure the TIMx input channel.
447 * @param TIMx Timer Instance
448 * @param Channel This parameter can be one of the following values:
449 * @arg @ref LL_TIM_CHANNEL_CH1
450 * @arg @ref LL_TIM_CHANNEL_CH2
451 * @arg @ref LL_TIM_CHANNEL_CH3
452 * @arg @ref LL_TIM_CHANNEL_CH4
453 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
454 * structure)
455 * @retval An ErrorStatus enumeration value:
456 * - SUCCESS: TIMx output channel is initialized
457 * - ERROR: TIMx output channel is not initialized
458 */
LL_TIM_IC_Init(TIM_TypeDef * TIMx,uint32_t Channel,const LL_TIM_IC_InitTypeDef * TIM_IC_InitStruct)459 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
460 {
461 ErrorStatus result = ERROR;
462
463 switch (Channel)
464 {
465 case LL_TIM_CHANNEL_CH1:
466 result = IC1Config(TIMx, TIM_IC_InitStruct);
467 break;
468 case LL_TIM_CHANNEL_CH2:
469 result = IC2Config(TIMx, TIM_IC_InitStruct);
470 break;
471 case LL_TIM_CHANNEL_CH3:
472 result = IC3Config(TIMx, TIM_IC_InitStruct);
473 break;
474 case LL_TIM_CHANNEL_CH4:
475 result = IC4Config(TIMx, TIM_IC_InitStruct);
476 break;
477 default:
478 break;
479 }
480
481 return result;
482 }
483
484 /**
485 * @brief Fills each TIM_EncoderInitStruct field with its default value
486 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
487 * configuration data structure)
488 * @retval None
489 */
LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)490 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
491 {
492 /* Set the default configuration */
493 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
494 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
495 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
496 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
497 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
498 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
499 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
500 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
501 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
502 }
503
504 /**
505 * @brief Configure the encoder interface of the timer instance.
506 * @param TIMx Timer Instance
507 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
508 * configuration data structure)
509 * @retval An ErrorStatus enumeration value:
510 * - SUCCESS: TIMx registers are de-initialized
511 * - ERROR: not applicable
512 */
LL_TIM_ENCODER_Init(TIM_TypeDef * TIMx,const LL_TIM_ENCODER_InitTypeDef * TIM_EncoderInitStruct)513 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
514 {
515 uint32_t tmpccmr1;
516 uint32_t tmpccer;
517
518 /* Check the parameters */
519 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
520 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
521 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
522 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
523 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
524 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
525 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
526 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
527 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
528 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
529
530 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
531 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
532
533 /* Get the TIMx CCMR1 register value */
534 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
535
536 /* Get the TIMx CCER register value */
537 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
538
539 /* Configure TI1 */
540 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
541 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
542 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
543 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
544
545 /* Configure TI2 */
546 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
547 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
548 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
549 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
550
551 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
552 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
553 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
554 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
555 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
556
557 /* Set encoder mode */
558 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
559
560 /* Write to TIMx CCMR1 */
561 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
562
563 /* Write to TIMx CCER */
564 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
565
566 return SUCCESS;
567 }
568
569 /**
570 * @brief Set the fields of the TIMx Hall sensor interface configuration data
571 * structure to their default values.
572 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
573 * configuration data structure)
574 * @retval None
575 */
LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)576 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
577 {
578 /* Set the default configuration */
579 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
580 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
581 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
582 TIM_HallSensorInitStruct->CommutationDelay = 0U;
583 }
584
585 /**
586 * @brief Configure the Hall sensor interface of the timer instance.
587 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
588 * to the TI1 input channel
589 * @note TIMx slave mode controller is configured in reset mode.
590 Selected internal trigger is TI1F_ED.
591 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
592 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
593 * between 2 changes on the inputs. It gives information about motor speed.
594 * @note Channel 2 is configured in output PWM 2 mode.
595 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
596 * @note OC2REF is selected as trigger output on TRGO.
597 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
598 * when TIMx operates in Hall sensor interface mode.
599 * @param TIMx Timer Instance
600 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
601 * interface configuration data structure)
602 * @retval An ErrorStatus enumeration value:
603 * - SUCCESS: TIMx registers are de-initialized
604 * - ERROR: not applicable
605 */
LL_TIM_HALLSENSOR_Init(TIM_TypeDef * TIMx,const LL_TIM_HALLSENSOR_InitTypeDef * TIM_HallSensorInitStruct)606 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
607 {
608 uint32_t tmpcr2;
609 uint32_t tmpccmr1;
610 uint32_t tmpccer;
611 uint32_t tmpsmcr;
612
613 /* Check the parameters */
614 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
615 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
616 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
617 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
618
619 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
620 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
621
622 /* Get the TIMx CR2 register value */
623 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
624
625 /* Get the TIMx CCMR1 register value */
626 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
627
628 /* Get the TIMx CCER register value */
629 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
630
631 /* Get the TIMx SMCR register value */
632 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
633
634 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
635 tmpcr2 |= TIM_CR2_TI1S;
636
637 /* OC2REF signal is used as trigger output (TRGO) */
638 tmpcr2 |= LL_TIM_TRGO_OC2REF;
639
640 /* Configure the slave mode controller */
641 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
642 tmpsmcr |= LL_TIM_TS_TI1F_ED;
643 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
644
645 /* Configure input channel 1 */
646 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
647 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
648 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
649 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
650
651 /* Configure input channel 2 */
652 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
653 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
654
655 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
656 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
657 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
658 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
659
660 /* Write to TIMx CR2 */
661 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
662
663 /* Write to TIMx SMCR */
664 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
665
666 /* Write to TIMx CCMR1 */
667 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
668
669 /* Write to TIMx CCER */
670 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
671
672 /* Write to TIMx CCR2 */
673 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
674
675 return SUCCESS;
676 }
677
678 /**
679 * @brief Set the fields of the Break and Dead Time configuration data structure
680 * to their default values.
681 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
682 * data structure)
683 * @retval None
684 */
LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)685 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
686 {
687 /* Set the default configuration */
688 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
689 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
690 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
691 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
692 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
693 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
694 TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
695 TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
696 TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
697 TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
698 TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
699 TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT;
700 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
701 }
702
703 /**
704 * @brief Configure the Break and Dead Time feature of the timer instance.
705 * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
706 * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
707 * can be necessary to configure all of them during the first write access to
708 * the TIMx_BDTR register.
709 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
710 * a timer instance provides a break input.
711 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
712 * a timer instance provides a second break input.
713 * @param TIMx Timer Instance
714 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
715 * data structure)
716 * @retval An ErrorStatus enumeration value:
717 * - SUCCESS: Break and Dead Time is initialized
718 * - ERROR: not applicable
719 */
LL_TIM_BDTR_Init(TIM_TypeDef * TIMx,const LL_TIM_BDTR_InitTypeDef * TIM_BDTRInitStruct)720 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
721 {
722 uint32_t tmpbdtr = 0;
723
724 /* Check the parameters */
725 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
726 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
727 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
728 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
729 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
730 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
731 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
732
733 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
734 the OSSI State, the dead time value and the Automatic Output Enable Bit */
735
736 /* Set the BDTR bits */
737 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
738 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
739 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
740 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
741 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
742 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
743 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
744 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
745 assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
746 assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
747 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
748 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
749
750 if (IS_TIM_BKIN2_INSTANCE(TIMx))
751 {
752 assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
753 assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
754 assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
755 assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
756
757 /* Set the BREAK2 input related BDTR bit-fields */
758 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
759 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
760 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
761 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
762 }
763
764 /* Set TIMx_BDTR */
765 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
766
767 return SUCCESS;
768 }
769 /**
770 * @}
771 */
772
773 /**
774 * @}
775 */
776
777 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
778 * @brief Private functions
779 * @{
780 */
781 /**
782 * @brief Configure the TIMx output channel 1.
783 * @param TIMx Timer Instance
784 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
785 * @retval An ErrorStatus enumeration value:
786 * - SUCCESS: TIMx registers are de-initialized
787 * - ERROR: not applicable
788 */
OC1Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)789 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
790 {
791 uint32_t tmpccmr1;
792 uint32_t tmpccer;
793 uint32_t tmpcr2;
794
795 /* Check the parameters */
796 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
797 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
798 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
799 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
800 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
801 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
802
803 /* Disable the Channel 1: Reset the CC1E Bit */
804 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
805
806 /* Get the TIMx CCER register value */
807 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
808
809 /* Get the TIMx CR2 register value */
810 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
811
812 /* Get the TIMx CCMR1 register value */
813 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
814
815 /* Reset Capture/Compare selection Bits */
816 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
817
818 /* Set the Output Compare Mode */
819 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
820
821 /* Set the Output Compare Polarity */
822 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
823
824 /* Set the Output State */
825 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
826
827 if (IS_TIM_BREAK_INSTANCE(TIMx))
828 {
829 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
830 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
831
832 /* Set the complementary output Polarity */
833 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
834
835 /* Set the complementary output State */
836 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
837
838 /* Set the Output Idle state */
839 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
840
841 /* Set the complementary output Idle state */
842 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
843 }
844
845 /* Write to TIMx CR2 */
846 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
847
848 /* Write to TIMx CCMR1 */
849 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
850
851 /* Set the Capture Compare Register value */
852 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
853
854 /* Write to TIMx CCER */
855 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
856
857 return SUCCESS;
858 }
859
860 /**
861 * @brief Configure the TIMx output channel 2.
862 * @param TIMx Timer Instance
863 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
864 * @retval An ErrorStatus enumeration value:
865 * - SUCCESS: TIMx registers are de-initialized
866 * - ERROR: not applicable
867 */
OC2Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)868 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
869 {
870 uint32_t tmpccmr1;
871 uint32_t tmpccer;
872 uint32_t tmpcr2;
873
874 /* Check the parameters */
875 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
876 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
877 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
878 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
879 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
880 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
881
882 /* Disable the Channel 2: Reset the CC2E Bit */
883 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
884
885 /* Get the TIMx CCER register value */
886 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
887
888 /* Get the TIMx CR2 register value */
889 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
890
891 /* Get the TIMx CCMR1 register value */
892 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
893
894 /* Reset Capture/Compare selection Bits */
895 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
896
897 /* Select the Output Compare Mode */
898 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
899
900 /* Set the Output Compare Polarity */
901 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
902
903 /* Set the Output State */
904 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
905
906 if (IS_TIM_BREAK_INSTANCE(TIMx))
907 {
908 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
909 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
910
911 /* Set the complementary output Polarity */
912 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
913
914 /* Set the complementary output State */
915 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
916
917 /* Set the Output Idle state */
918 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
919
920 /* Set the complementary output Idle state */
921 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
922 }
923
924 /* Write to TIMx CR2 */
925 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
926
927 /* Write to TIMx CCMR1 */
928 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
929
930 /* Set the Capture Compare Register value */
931 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
932
933 /* Write to TIMx CCER */
934 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
935
936 return SUCCESS;
937 }
938
939 /**
940 * @brief Configure the TIMx output channel 3.
941 * @param TIMx Timer Instance
942 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
943 * @retval An ErrorStatus enumeration value:
944 * - SUCCESS: TIMx registers are de-initialized
945 * - ERROR: not applicable
946 */
OC3Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)947 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
948 {
949 uint32_t tmpccmr2;
950 uint32_t tmpccer;
951 uint32_t tmpcr2;
952
953 /* Check the parameters */
954 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
955 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
956 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
957 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
958 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
959 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
960
961 /* Disable the Channel 3: Reset the CC3E Bit */
962 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
963
964 /* Get the TIMx CCER register value */
965 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
966
967 /* Get the TIMx CR2 register value */
968 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
969
970 /* Get the TIMx CCMR2 register value */
971 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
972
973 /* Reset Capture/Compare selection Bits */
974 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
975
976 /* Select the Output Compare Mode */
977 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
978
979 /* Set the Output Compare Polarity */
980 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
981
982 /* Set the Output State */
983 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
984
985 if (IS_TIM_BREAK_INSTANCE(TIMx))
986 {
987 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
988 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
989
990 /* Set the complementary output Polarity */
991 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
992
993 /* Set the complementary output State */
994 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
995
996 /* Set the Output Idle state */
997 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
998
999 /* Set the complementary output Idle state */
1000 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1001 }
1002
1003 /* Write to TIMx CR2 */
1004 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1005
1006 /* Write to TIMx CCMR2 */
1007 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1008
1009 /* Set the Capture Compare Register value */
1010 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1011
1012 /* Write to TIMx CCER */
1013 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1014
1015 return SUCCESS;
1016 }
1017
1018 /**
1019 * @brief Configure the TIMx output channel 4.
1020 * @param TIMx Timer Instance
1021 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1022 * @retval An ErrorStatus enumeration value:
1023 * - SUCCESS: TIMx registers are de-initialized
1024 * - ERROR: not applicable
1025 */
OC4Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1026 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1027 {
1028 uint32_t tmpccmr2;
1029 uint32_t tmpccer;
1030 uint32_t tmpcr2;
1031
1032 /* Check the parameters */
1033 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1034 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1035 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1036 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1037 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1038 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1039
1040 /* Disable the Channel 4: Reset the CC4E Bit */
1041 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1042
1043 /* Get the TIMx CCER register value */
1044 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1045
1046 /* Get the TIMx CR2 register value */
1047 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1048
1049 /* Get the TIMx CCMR2 register value */
1050 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1051
1052 /* Reset Capture/Compare selection Bits */
1053 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1054
1055 /* Select the Output Compare Mode */
1056 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1057
1058 /* Set the Output Compare Polarity */
1059 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1060
1061 /* Set the Output State */
1062 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1063
1064 if (IS_TIM_BREAK_INSTANCE(TIMx))
1065 {
1066 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1067 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1068
1069 /* Set the Output Idle state */
1070 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1071 }
1072
1073 /* Write to TIMx CR2 */
1074 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1075
1076 /* Write to TIMx CCMR2 */
1077 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1078
1079 /* Set the Capture Compare Register value */
1080 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1081
1082 /* Write to TIMx CCER */
1083 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1084
1085 return SUCCESS;
1086 }
1087
1088 /**
1089 * @brief Configure the TIMx output channel 5.
1090 * @param TIMx Timer Instance
1091 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1092 * @retval An ErrorStatus enumeration value:
1093 * - SUCCESS: TIMx registers are de-initialized
1094 * - ERROR: not applicable
1095 */
OC5Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1096 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1097 {
1098 uint32_t tmpccmr3;
1099 uint32_t tmpccer;
1100
1101 /* Check the parameters */
1102 assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1103 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1104 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1105 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1106 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1107 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1108
1109 /* Disable the Channel 5: Reset the CC5E Bit */
1110 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1111
1112 /* Get the TIMx CCER register value */
1113 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1114
1115 /* Get the TIMx CCMR3 register value */
1116 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1117
1118 /* Select the Output Compare Mode */
1119 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1120
1121 /* Set the Output Compare Polarity */
1122 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1123
1124 /* Set the Output State */
1125 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1126
1127 if (IS_TIM_BREAK_INSTANCE(TIMx))
1128 {
1129 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1130 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1131
1132 /* Set the Output Idle state */
1133 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1134
1135 }
1136
1137 /* Write to TIMx CCMR3 */
1138 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1139
1140 /* Set the Capture Compare Register value */
1141 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1142
1143 /* Write to TIMx CCER */
1144 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1145
1146 return SUCCESS;
1147 }
1148
1149 /**
1150 * @brief Configure the TIMx output channel 6.
1151 * @param TIMx Timer Instance
1152 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1153 * @retval An ErrorStatus enumeration value:
1154 * - SUCCESS: TIMx registers are de-initialized
1155 * - ERROR: not applicable
1156 */
OC6Config(TIM_TypeDef * TIMx,const LL_TIM_OC_InitTypeDef * TIM_OCInitStruct)1157 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1158 {
1159 uint32_t tmpccmr3;
1160 uint32_t tmpccer;
1161
1162 /* Check the parameters */
1163 assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1164 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1165 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1166 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1167 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1168 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1169
1170 /* Disable the Channel 5: Reset the CC6E Bit */
1171 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1172
1173 /* Get the TIMx CCER register value */
1174 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1175
1176 /* Get the TIMx CCMR3 register value */
1177 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1178
1179 /* Select the Output Compare Mode */
1180 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1181
1182 /* Set the Output Compare Polarity */
1183 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1184
1185 /* Set the Output State */
1186 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1187
1188 if (IS_TIM_BREAK_INSTANCE(TIMx))
1189 {
1190 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1191 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1192
1193 /* Set the Output Idle state */
1194 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1195 }
1196
1197 /* Write to TIMx CCMR3 */
1198 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1199
1200 /* Set the Capture Compare Register value */
1201 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1202
1203 /* Write to TIMx CCER */
1204 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1205
1206 return SUCCESS;
1207 }
1208
1209 /**
1210 * @brief Configure the TIMx input channel 1.
1211 * @param TIMx Timer Instance
1212 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1213 * @retval An ErrorStatus enumeration value:
1214 * - SUCCESS: TIMx registers are de-initialized
1215 * - ERROR: not applicable
1216 */
IC1Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1217 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1218 {
1219 /* Check the parameters */
1220 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1221 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1222 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1223 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1224 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1225
1226 /* Disable the Channel 1: Reset the CC1E Bit */
1227 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1228
1229 /* Select the Input and set the filter and the prescaler value */
1230 MODIFY_REG(TIMx->CCMR1,
1231 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1232 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1233
1234 /* Select the Polarity and set the CC1E Bit */
1235 MODIFY_REG(TIMx->CCER,
1236 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1237 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1238
1239 return SUCCESS;
1240 }
1241
1242 /**
1243 * @brief Configure the TIMx input channel 2.
1244 * @param TIMx Timer Instance
1245 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1246 * @retval An ErrorStatus enumeration value:
1247 * - SUCCESS: TIMx registers are de-initialized
1248 * - ERROR: not applicable
1249 */
IC2Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1250 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1251 {
1252 /* Check the parameters */
1253 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1254 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1255 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1256 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1257 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1258
1259 /* Disable the Channel 2: Reset the CC2E Bit */
1260 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1261
1262 /* Select the Input and set the filter and the prescaler value */
1263 MODIFY_REG(TIMx->CCMR1,
1264 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1265 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1266
1267 /* Select the Polarity and set the CC2E Bit */
1268 MODIFY_REG(TIMx->CCER,
1269 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1270 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1271
1272 return SUCCESS;
1273 }
1274
1275 /**
1276 * @brief Configure the TIMx input channel 3.
1277 * @param TIMx Timer Instance
1278 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1279 * @retval An ErrorStatus enumeration value:
1280 * - SUCCESS: TIMx registers are de-initialized
1281 * - ERROR: not applicable
1282 */
IC3Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1283 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1284 {
1285 /* Check the parameters */
1286 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1287 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1288 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1289 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1290 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1291
1292 /* Disable the Channel 3: Reset the CC3E Bit */
1293 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1294
1295 /* Select the Input and set the filter and the prescaler value */
1296 MODIFY_REG(TIMx->CCMR2,
1297 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1298 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1299
1300 /* Select the Polarity and set the CC3E Bit */
1301 MODIFY_REG(TIMx->CCER,
1302 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1303 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1304
1305 return SUCCESS;
1306 }
1307
1308 /**
1309 * @brief Configure the TIMx input channel 4.
1310 * @param TIMx Timer Instance
1311 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1312 * @retval An ErrorStatus enumeration value:
1313 * - SUCCESS: TIMx registers are de-initialized
1314 * - ERROR: not applicable
1315 */
IC4Config(TIM_TypeDef * TIMx,const LL_TIM_IC_InitTypeDef * TIM_ICInitStruct)1316 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1317 {
1318 /* Check the parameters */
1319 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1320 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1321 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1322 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1323 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1324
1325 /* Disable the Channel 4: Reset the CC4E Bit */
1326 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1327
1328 /* Select the Input and set the filter and the prescaler value */
1329 MODIFY_REG(TIMx->CCMR2,
1330 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1331 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1332
1333 /* Select the Polarity and set the CC2E Bit */
1334 MODIFY_REG(TIMx->CCER,
1335 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1336 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1337
1338 return SUCCESS;
1339 }
1340
1341
1342 /**
1343 * @}
1344 */
1345
1346 /**
1347 * @}
1348 */
1349
1350 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 */
1351
1352 /**
1353 * @}
1354 */
1355
1356 #endif /* USE_FULL_LL_DRIVER */
1357
1358
