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Searched refs:tmpbdtr (Results 1 – 25 of 36) sorted by relevance

12

/hal_stm32-3.6.0/stm32cube/stm32mp1xx/drivers/src/
Dstm32mp1xx_hal_tim_ex.c1717 uint32_t tmpbdtr = 0U; in HAL_TIMEx_ConfigBreakDeadTime() local
1737 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
1738 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
1739 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
1740 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
1741 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
1742 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
1743 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
1744 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); in HAL_TIMEx_ConfigBreakDeadTime()
1752 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); in HAL_TIMEx_ConfigBreakDeadTime()
[all …]
Dstm32mp1xx_ll_tim.c754 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
769 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
770 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
771 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
772 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
773 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
774 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
775 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
776 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
781 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32wlxx/drivers/src/
Dstm32wlxx_hal_tim_ex.c2067 uint32_t tmpbdtr = 0U; in HAL_TIMEx_ConfigBreakDeadTime() local
2087 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
2088 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
2089 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
2090 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
2091 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
2092 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
2093 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
2094 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); in HAL_TIMEx_ConfigBreakDeadTime()
2102 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); in HAL_TIMEx_ConfigBreakDeadTime()
[all …]
Dstm32wlxx_ll_tim.c687 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
702 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
703 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
704 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
705 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
706 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
707 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
708 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
709 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
712 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32wbxx/drivers/src/
Dstm32wbxx_hal_tim_ex.c2070 uint32_t tmpbdtr = 0U; in HAL_TIMEx_ConfigBreakDeadTime() local
2091 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
2092 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
2093 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
2094 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
2095 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
2096 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
2097 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
2098 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); in HAL_TIMEx_ConfigBreakDeadTime()
2099 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); in HAL_TIMEx_ConfigBreakDeadTime()
[all …]
Dstm32wbxx_ll_tim.c691 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
708 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
709 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
710 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
711 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
712 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
713 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
714 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
715 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
716 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32h7xx/drivers/src/
Dstm32h7xx_hal_tim_ex.c2070 uint32_t tmpbdtr = 0U; in HAL_TIMEx_ConfigBreakDeadTime() local
2090 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
2091 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
2092 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
2093 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
2094 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
2095 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
2096 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
2097 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); in HAL_TIMEx_ConfigBreakDeadTime()
2106 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); in HAL_TIMEx_ConfigBreakDeadTime()
[all …]
Dstm32h7xx_ll_tim.c771 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
786 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
787 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
788 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
789 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
790 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
791 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
792 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
793 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
797 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32c0xx/drivers/src/
Dstm32c0xx_hal_tim_ex.c2087 uint32_t tmpbdtr = 0U; in HAL_TIMEx_ConfigBreakDeadTime() local
2107 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
2108 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
2109 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
2110 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
2111 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
2112 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
2113 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
2114 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); in HAL_TIMEx_ConfigBreakDeadTime()
2122 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); in HAL_TIMEx_ConfigBreakDeadTime()
[all …]
Dstm32c0xx_ll_tim.c699 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
714 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
715 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
716 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
717 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
718 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
719 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
720 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
723 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
724 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32l5xx/drivers/src/
Dstm32l5xx_hal_tim_ex.c2055 uint32_t tmpbdtr = 0U; in HAL_TIMEx_ConfigBreakDeadTime() local
2075 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
2076 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
2077 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
2078 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
2079 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
2080 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
2081 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
2082 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); in HAL_TIMEx_ConfigBreakDeadTime()
2090 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); in HAL_TIMEx_ConfigBreakDeadTime()
[all …]
Dstm32l5xx_ll_tim.c722 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
737 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
738 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
739 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
740 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
741 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
742 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
743 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
744 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
747 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32g0xx/drivers/src/
Dstm32g0xx_hal_tim_ex.c2057 uint32_t tmpbdtr = 0U; in HAL_TIMEx_ConfigBreakDeadTime() local
2077 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
2078 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
2079 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
2080 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
2081 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
2082 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
2083 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
2084 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); in HAL_TIMEx_ConfigBreakDeadTime()
2092 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); in HAL_TIMEx_ConfigBreakDeadTime()
[all …]
Dstm32g0xx_ll_tim.c731 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
746 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
747 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
748 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
749 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
750 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
751 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
752 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
753 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
758 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32g4xx/drivers/src/
Dstm32g4xx_ll_tim.c739 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
754 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
755 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
756 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
757 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
758 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
759 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
760 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
761 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
766 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
[all …]
Dstm32g4xx_hal_tim_ex.c2265 uint32_t tmpbdtr = 0U; in HAL_TIMEx_ConfigBreakDeadTime() local
2285 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
2286 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
2287 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
2288 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
2289 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
2290 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
2291 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
2292 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); in HAL_TIMEx_ConfigBreakDeadTime()
2300 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); in HAL_TIMEx_ConfigBreakDeadTime()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_tim_ex.c2187 uint32_t tmpbdtr = 0U; in HAL_TIMEx_ConfigBreakDeadTime() local
2207 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
2208 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
2209 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
2210 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
2211 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
2212 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
2213 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
2214 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); in HAL_TIMEx_ConfigBreakDeadTime()
2222 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); in HAL_TIMEx_ConfigBreakDeadTime()
[all …]
Dstm32h5xx_ll_tim.c776 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
791 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
792 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
793 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
794 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
795 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
796 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
797 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
800 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
801 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_tim_ex.c2146 uint32_t tmpbdtr = 0U; in HAL_TIMEx_ConfigBreakDeadTime() local
2167 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
2168 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
2169 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
2170 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
2171 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
2172 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
2173 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
2174 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); in HAL_TIMEx_ConfigBreakDeadTime()
2175 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); in HAL_TIMEx_ConfigBreakDeadTime()
[all …]
Dstm32wbaxx_ll_tim.c704 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
721 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
722 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
723 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
724 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
725 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
726 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
727 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
728 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
729 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_tim_ex.c2190 uint32_t tmpbdtr = 0U; in HAL_TIMEx_ConfigBreakDeadTime() local
2210 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
2211 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
2212 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
2213 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
2214 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
2215 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
2216 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
2217 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); in HAL_TIMEx_ConfigBreakDeadTime()
2225 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); in HAL_TIMEx_ConfigBreakDeadTime()
[all …]
Dstm32u5xx_ll_tim.c741 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
756 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
757 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
758 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
759 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
760 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
761 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
762 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
765 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
766 MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32f7xx/drivers/src/
Dstm32f7xx_ll_tim.c753 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
768 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
769 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
770 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
771 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
772 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
773 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
774 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
775 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
779 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32f3xx/drivers/src/
Dstm32f3xx_ll_tim.c806 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
821 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
822 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
823 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
824 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
825 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
826 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
827 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
828 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
831 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
[all …]
/hal_stm32-3.6.0/stm32cube/stm32l4xx/drivers/src/
Dstm32l4xx_ll_tim.c726 uint32_t tmpbdtr = 0; in LL_TIM_BDTR_Init() local
741 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); in LL_TIM_BDTR_Init()
742 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); in LL_TIM_BDTR_Init()
743 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); in LL_TIM_BDTR_Init()
744 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); in LL_TIM_BDTR_Init()
745 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); in LL_TIM_BDTR_Init()
746 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); in LL_TIM_BDTR_Init()
747 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); in LL_TIM_BDTR_Init()
749 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); in LL_TIM_BDTR_Init()
758 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); in LL_TIM_BDTR_Init()
[all …]

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