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Searched refs:WPR1 (Results 1 – 23 of 23) sorted by relevance

/hal_stm32-3.6.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_ramcfg.c698 WRITE_REG(hramcfg->Instance->WPR1, page_mask_0); in HAL_RAMCFG_EnableWriteProtection()
/hal_stm32-3.6.0/stm32cube/stm32h5xx/drivers/src/
Dstm32h5xx_hal_ramcfg.c629 SET_BIT(hramcfg->Instance->WPR1, page_mask_0); in HAL_RAMCFG_EnableWriteProtection()
/hal_stm32-3.6.0/stm32cube/stm32u5xx/drivers/src/
Dstm32u5xx_hal_ramcfg.c720 SET_BIT(hramcfg->Instance->WPR1, page_mask_0); in HAL_RAMCFG_EnableWriteProtection()
/hal_stm32-3.6.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h540 __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ member
Dstm32wba52xx.h633 __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ member
Dstm32wba54xx.h660 __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ member
Dstm32wba55xx.h660 __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ member
/hal_stm32-3.6.0/stm32cube/stm32h5xx/soc/
Dstm32h503xx.h696 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32h562xx.h901 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32h563xx.h1079 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32h573xx.h1144 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
/hal_stm32-3.6.0/stm32cube/stm32u5xx/soc/
Dstm32u535xx.h873 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32u545xx.h939 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32u575xx.h939 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32u5f7xx.h1142 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32u595xx.h980 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32u5a5xx.h1047 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32u585xx.h1006 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32u599xx.h1161 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32u5g7xx.h1209 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32u5a9xx.h1228 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32u5f9xx.h1246 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member
Dstm32u5g9xx.h1313 __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ member