/hal_stm32-3.6.0/stm32cube/stm32f0xx/soc/ |
D | stm32f051x8.h | 5842 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 5843 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32f058xx.h | 5811 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 5812 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32f071xb.h | 6395 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 6396 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32f042x6.h | 9617 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 9618 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32f048xx.h | 9581 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 9582 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32f072xb.h | 10192 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 10193 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32f078xx.h | 10162 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 10163 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32f098xx.h | 10816 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 10817 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32f091xc.h | 10849 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 10850 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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/hal_stm32-3.6.0/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6368 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 6369 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32l053xx.h | 6527 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 6528 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32l062xx.h | 6505 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 6506 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32l063xx.h | 6662 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 6663 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32l072xx.h | 6664 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 6665 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32l073xx.h | 6823 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 6824 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32l082xx.h | 6801 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 6802 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32l083xx.h | 6960 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 6961 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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/hal_stm32-3.6.0/stm32cube/stm32f3xx/soc/ |
D | stm32f318xx.h | 7616 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 7617 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32f301x8.h | 7629 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 7630 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32f373xc.h | 10803 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 10804 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32f378xx.h | 10701 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 10702 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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/hal_stm32-3.6.0/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9449 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 9450 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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/hal_stm32-3.6.0/stm32cube/stm32l4xx/soc/ |
D | stm32l412xx.h | 9298 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 9299 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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D | stm32l422xx.h | 9523 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 9524 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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/hal_stm32-3.6.0/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb15xx.h | 8258 #define TSC_IOCCR_G4_IO3_Pos (14U) macro 8259 #define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
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