1 /**
2   ******************************************************************************
3   * @file    stm32l412xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32L412xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral's registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * Copyright (c) 2017 STMicroelectronics.
16   * All rights reserved.
17   *
18   * This software is licensed under terms that can be found in the LICENSE file
19   * in the root directory of this software component.
20   * If no LICENSE file comes with this software, it is provided AS-IS.
21   *
22   ******************************************************************************
23   */
24 
25 /** @addtogroup CMSIS_Device
26   * @{
27   */
28 
29 /** @addtogroup stm32l412xx
30   * @{
31   */
32 
33 #ifndef __STM32L412xx_H
34 #define __STM32L412xx_H
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif /* __cplusplus */
39 
40 /** @addtogroup Configuration_section_for_CMSIS
41   * @{
42   */
43 
44 /**
45   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
46    */
47 #define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
48 #define __MPU_PRESENT             1U       /*!< STM32L4XX provides an MPU                     */
49 #define __NVIC_PRIO_BITS          4U       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
50 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
51 #define __FPU_PRESENT             1U       /*!< FPU present                                   */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32L4XX Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68   NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
69   HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
77 /******  STM32 specific Interrupt Numbers **********************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
79   PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM3/PVM4 through EXTI Line detection Interrupts         */
80   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
81   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
82   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
83   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
84   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
85   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
86   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
87   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
88   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
89   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
90   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
91   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
92   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
93   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
94   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
95   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
96   ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */
97   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
98   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
99   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
100   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
101   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
102   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
103   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
104   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
105   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
106   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
107   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
108   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
109   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
110   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
111   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
112   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
113   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
114   TIM6_IRQn                   = 54,     /*!< TIM6 global interrupt                                             */
115   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
116   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
117   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
118   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
119   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
120   COMP_IRQn                   = 64,     /*!< COMP1 Interrupt                                                   */
121   LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
122   LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
123   USB_IRQn                    = 67,     /*!< USB event Interrupt                                               */
124   DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
125   DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
126   LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
127   QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
128   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
129   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
130   TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
131   RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
132   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
133   CRS_IRQn                    = 82      /*!< CRS global interrupt                                              */
134 } IRQn_Type;
135 
136 /**
137   * @}
138   */
139 
140 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
141 #include "system_stm32l4xx.h"
142 #include <stdint.h>
143 
144 /** @addtogroup Peripheral_registers_structures
145   * @{
146   */
147 
148 /**
149   * @brief Analog to Digital Converter
150   */
151 
152 typedef struct
153 {
154   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
155   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
156   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
157   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
158   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
159   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
160   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
161        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
162   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
163   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
164   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
165        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
166   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
167   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
168   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
169   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
170   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
171        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
172        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
173   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
174        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
175   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
176   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
177   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
178   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
179        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
180   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
181   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
182   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
183   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
184        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
185   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
186   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
187        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
188        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
189   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
190   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
191 
192 } ADC_TypeDef;
193 
194 typedef struct
195 {
196   __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */
197   uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
198   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
199   __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */
200 } ADC_Common_TypeDef;
201 
202 
203 
204 
205 /**
206   * @brief Comparator
207   */
208 
209 typedef struct
210 {
211   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
212 } COMP_TypeDef;
213 
214 typedef struct
215 {
216   __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
217 } COMP_Common_TypeDef;
218 
219 /**
220   * @brief CRC calculation unit
221   */
222 
223 typedef struct
224 {
225   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
226   __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
227   uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
228   uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
229   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
230   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
231   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
232   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
233 } CRC_TypeDef;
234 
235 /**
236   * @brief Clock Recovery System
237   */
238 typedef struct
239 {
240 __IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
241 __IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
242 __IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
243 __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
244 } CRS_TypeDef;
245 
246 
247 
248 /**
249   * @brief Debug MCU
250   */
251 
252 typedef struct
253 {
254   __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
255   __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
256   __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
257   __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
258   __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
259 } DBGMCU_TypeDef;
260 
261 
262 /**
263   * @brief DMA Controller
264   */
265 
266 typedef struct
267 {
268   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
269   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
270   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
271   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
272 } DMA_Channel_TypeDef;
273 
274 typedef struct
275 {
276   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
277   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
278 } DMA_TypeDef;
279 
280 typedef struct
281 {
282   __IO uint32_t CSELR;       /*!< DMA channel selection register              */
283 } DMA_Request_TypeDef;
284 
285 /* Legacy define */
286 #define DMA_request_TypeDef  DMA_Request_TypeDef
287 
288 
289 /**
290   * @brief External Interrupt/Event Controller
291   */
292 
293 typedef struct
294 {
295   __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
296   __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
297   __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
298   __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
299   __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
300   __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
301   uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
302   uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
303   __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
304   __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
305   __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
306   __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
307   __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
308   __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
309 } EXTI_TypeDef;
310 
311 
312 /**
313   * @brief Firewall
314   */
315 
316 typedef struct
317 {
318   __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
319   __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
320   __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
321   __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
322   __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
323   __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
324   uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
325   uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
326   __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
327 } FIREWALL_TypeDef;
328 
329 
330 /**
331   * @brief FLASH Registers
332   */
333 
334 typedef struct
335 {
336   __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
337   __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
338   __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
339   __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
340   __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
341   __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
342   __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
343   __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
344   __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
345   __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
346   __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
347   __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
348   __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
349 } FLASH_TypeDef;
350 
351 
352 
353 /**
354   * @brief General Purpose I/O
355   */
356 
357 typedef struct
358 {
359   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
360   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
361   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
362   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
363   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
364   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
365   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
366   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
367   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
368   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
369 
370 } GPIO_TypeDef;
371 
372 
373 /**
374   * @brief Inter-integrated Circuit Interface
375   */
376 
377 typedef struct
378 {
379   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
380   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
381   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
382   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
383   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
384   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
385   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
386   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
387   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
388   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
389   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
390 } I2C_TypeDef;
391 
392 /**
393   * @brief Independent WATCHDOG
394   */
395 
396 typedef struct
397 {
398   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
399   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
400   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
401   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
402   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
403 } IWDG_TypeDef;
404 
405 /**
406   * @brief LPTIMER
407   */
408 typedef struct
409 {
410   __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
411   __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
412   __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
413   __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
414   __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
415   __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
416   __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
417   __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
418   __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
419   __IO uint32_t RESERVED;    /*!< Reserved,                                           Address offset: 0x24 */
420   __IO uint32_t RCR;         /*!< LPTIM repetition counter register,                  Address offset: 0x28 */
421 } LPTIM_TypeDef;
422 
423 /**
424   * @brief Operational Amplifier (OPAMP)
425   */
426 
427 typedef struct
428 {
429   __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
430   __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
431   __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
432 } OPAMP_TypeDef;
433 
434 typedef struct
435 {
436   __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
437 } OPAMP_Common_TypeDef;
438 
439 /**
440   * @brief Power Control
441   */
442 
443 typedef struct
444 {
445   __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
446   __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
447   __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
448   __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
449   __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
450   __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
451   __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
452   uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
453   __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
454   __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
455   __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
456   __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
457   __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
458   __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
459   __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
460   __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
461   __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
462   __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
463   uint32_t RESERVED1;  /*!< Reserved,                            Address offset: 0x48 */
464   uint32_t RESERVED2;  /*!< Reserved,                            Address offset: 0x4C */
465   uint32_t RESERVED3;  /*!< Reserved,                            Address offset: 0x50 */
466   uint32_t RESERVED4;  /*!< Reserved,                            Address offset: 0x54 */
467   __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
468   __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
469 } PWR_TypeDef;
470 
471 
472 /**
473   * @brief QUAD Serial Peripheral Interface
474   */
475 
476 typedef struct
477 {
478   __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
479   __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
480   __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
481   __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
482   __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
483   __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
484   __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
485   __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
486   __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
487   __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
488   __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
489   __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
490   __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
491 } QUADSPI_TypeDef;
492 
493 
494 /**
495   * @brief Reset and Clock Control
496   */
497 
498 typedef struct
499 {
500   __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
501   __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
502   __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
503   __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
504   uint32_t      RESERVED8;   /*!< Reserved,                                                                Address offset: 0x10 */
505   uint32_t      RESERVED;    /*!< Reserved,                                                                Address offset: 0x14 */
506   __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
507   __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
508   __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
509   uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
510   __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
511   __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
512   __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
513   uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
514   __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
515   __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
516   __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
517   uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
518   __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
519   __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
520   __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
521   uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
522   __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
523   __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
524   __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
525   uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
526   __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
527   __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
528   __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
529   uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
530   __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
531   __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
532   __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
533   uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
534   __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
535   uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
536   __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
537   __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
538   __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
539 } RCC_TypeDef;
540 
541 /**
542   * @brief Real-Time Clock
543   */
544 
545 typedef struct
546 {
547   __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
548   __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
549   __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
550   __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
551   __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
552   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
553   __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
554        uint32_t RESERVED0;   /*!< Reserved,                                       Address offset: 0x1C */
555        uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x20 */
556   __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
557   __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
558   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
559   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
560   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
561   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
562        uint32_t RESERVED2;   /*!< Reserved,                                       Address offset: 0x3C */
563   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
564   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
565   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
566   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
567   __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
568   __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
569        uint32_t RESERVED3;   /*!< Reserved,                                       Address offset: 0x58 */
570   __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
571 } RTC_TypeDef;
572 
573 /**
574   * @brief Tamper and backup registers
575   */
576 typedef struct
577 {
578   __IO uint32_t CR1;         /*!< TAMP configuration register 1,            Address offset: 0x00 */
579   __IO uint32_t CR2;         /*!< TAMP configuration register 2,            Address offset: 0x04 */
580        uint32_t RESERVED0;   /*!< Reserved,                                 Address offset: 0x08 */
581   __IO uint32_t FLTCR;       /*!< TAMP filter control register,             Address offset: 0x0C */
582        uint32_t RESERVED1[7];/*!< Reserved,                                 Address offset: 0x10 -- 0x28 */
583   __IO uint32_t IER;         /*!< TAMP interrupt enable register,           Address offset: 0x2C */
584   __IO uint32_t SR;          /*!< TAMP status register,                     Address offset: 0x30 */
585   __IO uint32_t MISR;        /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
586        uint32_t RESERVED2;   /*!< Reserved,                                 Address offset: 0x38 */
587   __IO uint32_t SCR;         /*!< TAMP status clear register,               Address offset: 0x3C */
588        uint32_t RESERVED3[48];/*!< Reserved,                                Address offset: 0x40 -- 0xFC */
589   __IO uint32_t BKP0R;       /*!< TAMP backup register 0,                   Address offset: 0x100 */
590   __IO uint32_t BKP1R;       /*!< TAMP backup register 1,                   Address offset: 0x104 */
591   __IO uint32_t BKP2R;       /*!< TAMP backup register 2,                   Address offset: 0x108 */
592   __IO uint32_t BKP3R;       /*!< TAMP backup register 3,                   Address offset: 0x10C */
593   __IO uint32_t BKP4R;       /*!< TAMP backup register 4,                   Address offset: 0x110 */
594   __IO uint32_t BKP5R;       /*!< TAMP backup register 5,                   Address offset: 0x114 */
595   __IO uint32_t BKP6R;       /*!< TAMP backup register 6,                   Address offset: 0x118 */
596   __IO uint32_t BKP7R;       /*!< TAMP backup register 7,                   Address offset: 0x11C */
597   __IO uint32_t BKP8R;       /*!< TAMP backup register 8,                   Address offset: 0x120 */
598   __IO uint32_t BKP9R;       /*!< TAMP backup register 9,                   Address offset: 0x124 */
599   __IO uint32_t BKP10R;      /*!< TAMP backup register 10,                  Address offset: 0x128 */
600   __IO uint32_t BKP11R;      /*!< TAMP backup register 11,                  Address offset: 0x12C */
601   __IO uint32_t BKP12R;      /*!< TAMP backup register 12,                  Address offset: 0x130 */
602   __IO uint32_t BKP13R;      /*!< TAMP backup register 13,                  Address offset: 0x134 */
603   __IO uint32_t BKP14R;      /*!< TAMP backup register 14,                  Address offset: 0x138 */
604   __IO uint32_t BKP15R;      /*!< TAMP backup register 15,                  Address offset: 0x13C */
605   __IO uint32_t BKP16R;      /*!< TAMP backup register 16,                  Address offset: 0x140 */
606   __IO uint32_t BKP17R;      /*!< TAMP backup register 17,                  Address offset: 0x144 */
607   __IO uint32_t BKP18R;      /*!< TAMP backup register 18,                  Address offset: 0x148 */
608   __IO uint32_t BKP19R;      /*!< TAMP backup register 19,                  Address offset: 0x14C */
609   __IO uint32_t BKP20R;      /*!< TAMP backup register 20,                  Address offset: 0x150 */
610   __IO uint32_t BKP21R;      /*!< TAMP backup register 21,                  Address offset: 0x154 */
611   __IO uint32_t BKP22R;      /*!< TAMP backup register 22,                  Address offset: 0x158 */
612   __IO uint32_t BKP23R;      /*!< TAMP backup register 23,                  Address offset: 0x15C */
613   __IO uint32_t BKP24R;      /*!< TAMP backup register 24,                  Address offset: 0x160 */
614   __IO uint32_t BKP25R;      /*!< TAMP backup register 25,                  Address offset: 0x164 */
615   __IO uint32_t BKP26R;      /*!< TAMP backup register 26,                  Address offset: 0x168 */
616   __IO uint32_t BKP27R;      /*!< TAMP backup register 27,                  Address offset: 0x16C */
617   __IO uint32_t BKP28R;      /*!< TAMP backup register 28,                  Address offset: 0x170 */
618   __IO uint32_t BKP29R;      /*!< TAMP backup register 29,                  Address offset: 0x174 */
619   __IO uint32_t BKP30R;      /*!< TAMP backup register 30,                  Address offset: 0x178 */
620   __IO uint32_t BKP31R;      /*!< TAMP backup register 31,                  Address offset: 0x17C */
621 } TAMP_TypeDef;
622 
623 
624 
625 /**
626   * @brief Serial Peripheral Interface
627   */
628 
629 typedef struct
630 {
631   __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
632   __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
633   __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
634   __IO uint32_t DR;          /*!< SPI data register,                                   Address offset: 0x0C */
635   __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
636   __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
637   __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
638 } SPI_TypeDef;
639 
640 
641 /**
642   * @brief System configuration controller
643   */
644 
645 typedef struct
646 {
647   __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
648   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
649   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
650   __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
651   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
652   __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
653   __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
654 } SYSCFG_TypeDef;
655 
656 
657 /**
658   * @brief TIM
659   */
660 
661 typedef struct
662 {
663   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
664   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
665   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
666   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
667   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
668   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
669   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
670   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
671   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
672   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
673   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
674   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
675   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
676   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
677   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
678   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
679   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
680   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
681   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
682   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
683   __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
684   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
685   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
686   __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
687   __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
688   __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
689 } TIM_TypeDef;
690 
691 
692 /**
693   * @brief Touch Sensing Controller (TSC)
694   */
695 
696 typedef struct
697 {
698   __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
699   __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
700   __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
701   __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
702   __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
703   uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
704   __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
705   uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
706   __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
707   uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
708   __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
709   uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
710   __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
711   __IO uint32_t IOGXCR[7];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-4C */
712 } TSC_TypeDef;
713 
714 /**
715   * @brief Universal Synchronous Asynchronous Receiver Transmitter
716   */
717 
718 typedef struct
719 {
720   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
721   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
722   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
723   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
724   __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
725   uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
726   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
727   __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
728   uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
729   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
730   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
731   __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
732   uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
733   __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
734   uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
735 } USART_TypeDef;
736 
737 /**
738   * @brief Universal Serial Bus Full Speed Device
739   */
740 
741 typedef struct
742 {
743   __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */
744   __IO uint16_t RESERVED0;       /*!< Reserved */
745   __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
746   __IO uint16_t RESERVED1;       /*!< Reserved */
747   __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
748   __IO uint16_t RESERVED2;       /*!< Reserved */
749   __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */
750   __IO uint16_t RESERVED3;       /*!< Reserved */
751   __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
752   __IO uint16_t RESERVED4;       /*!< Reserved */
753   __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
754   __IO uint16_t RESERVED5;       /*!< Reserved */
755   __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
756   __IO uint16_t RESERVED6;       /*!< Reserved */
757   __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
758   __IO uint16_t RESERVED7[17];   /*!< Reserved */
759   __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
760   __IO uint16_t RESERVED8;       /*!< Reserved */
761   __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
762   __IO uint16_t RESERVED9;       /*!< Reserved */
763   __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
764   __IO uint16_t RESERVEDA;       /*!< Reserved */
765   __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
766   __IO uint16_t RESERVEDB;       /*!< Reserved */
767   __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
768   __IO uint16_t RESERVEDC;       /*!< Reserved */
769   __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
770   __IO uint16_t RESERVEDD;       /*!< Reserved */
771   __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
772   __IO uint16_t RESERVEDE;       /*!< Reserved */
773 } USB_TypeDef;
774 
775 
776 /**
777   * @brief Window WATCHDOG
778   */
779 
780 typedef struct
781 {
782   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
783   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
784   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
785 } WWDG_TypeDef;
786 
787 /**
788   * @brief RNG
789   */
790 
791 typedef struct
792 {
793   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
794   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
795   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
796 } RNG_TypeDef;
797 
798 /**
799   * @}
800   */
801 
802 /** @addtogroup Peripheral_memory_map
803   * @{
804   */
805 #define FLASH_BASE            (0x08000000UL) /*!< FLASH(up to 128 KB) base address */
806 #define FLASH_END             (0x0801FFFFUL) /*!< FLASH END address                */
807 #define FLASH_BANK1_END       (0x0801FFFFUL) /*!< FLASH END address of bank1       */
808 #define SRAM1_BASE            (0x20000000UL) /*!< SRAM1(up to 32 KB) base address  */
809 #define SRAM2_BASE            (0x10000000UL) /*!< SRAM2(8 KB) base address */
810 #define PERIPH_BASE           (0x40000000UL) /*!< Peripheral base address */
811 #define QSPI_BASE             (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
812 
813 #define QSPI_R_BASE           (0xA0001000UL) /*!< QUADSPI control registers base address */
814 #define SRAM1_BB_BASE         (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */
815 #define PERIPH_BB_BASE        (0x42000000UL) /*!< Peripheral base address in the bit-band region */
816 
817 /* Legacy defines */
818 #define SRAM_BASE             SRAM1_BASE
819 #define SRAM_BB_BASE          SRAM1_BB_BASE
820 
821 #define SRAM1_SIZE_MAX        (0x00008000UL) /*!< maximum SRAM1 size (up to 32 KBytes) */
822 #define SRAM2_SIZE            (0x00002000UL) /*!< SRAM2 size (8 KBytes) */
823 
824 #define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
825 
826 #define FLASH_SIZE               (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) == 0x0000FFFFU)) ? (0x80U << 10U) :  \
827                                   (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
828 
829 /*!< Peripheral memory map */
830 #define APB1PERIPH_BASE        PERIPH_BASE
831 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
832 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
833 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
834 
835 
836 /*!< APB1 peripherals */
837 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
838 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
839 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
840 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
841 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
842 #define TAMP_BASE             (APB1PERIPH_BASE + 0x3400U)
843 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
844 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
845 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
846 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
847 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
848 #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
849 #define CRS_BASE              (APB1PERIPH_BASE + 0x6000UL)
850 #define USB_BASE              (APB1PERIPH_BASE + 0x6800UL)  /*!< USB_IP Peripheral Registers base address */
851 #define USB_PMAADDR           (APB1PERIPH_BASE + 0x6C00UL)  /*!< USB_IP Packet Memory Area base address */
852 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
853 #define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800UL)
854 #define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800UL)
855 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00UL)
856 #define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000UL)
857 #define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400UL)
858 
859 
860 /*!< APB2 peripherals */
861 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000UL)
862 #define COMP1_BASE            (APB2PERIPH_BASE + 0x0200UL)
863 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400UL)
864 #define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00UL)
865 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00UL)
866 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
867 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800UL)
868 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000UL)
869 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400UL)
870 
871 /*!< AHB1 peripherals */
872 #define DMA1_BASE             (AHB1PERIPH_BASE)
873 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400UL)
874 #define RCC_BASE              (AHB1PERIPH_BASE + 0x1000UL)
875 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000UL)
876 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
877 #define TSC_BASE              (AHB1PERIPH_BASE + 0x4000UL)
878 
879 
880 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008UL)
881 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CUL)
882 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030UL)
883 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044UL)
884 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058UL)
885 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CUL)
886 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080UL)
887 #define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8UL)
888 
889 
890 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008UL)
891 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CUL)
892 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030UL)
893 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044UL)
894 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058UL)
895 #define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CUL)
896 #define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080UL)
897 #define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8UL)
898 
899 
900 /*!< AHB2 peripherals */
901 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000UL)
902 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400UL)
903 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800UL)
904 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00UL)
905 #define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00UL)
906 
907 
908 #define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000UL)
909 #define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100UL)
910 #define ADC12_COMMON_BASE     (AHB2PERIPH_BASE + 0x08040300UL)
911 
912 
913 #define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800UL)
914 
915 
916 
917 /* Debug MCU registers base address */
918 #define DBGMCU_BASE           (0xE0042000UL)
919 
920 
921 #define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */
922 #define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */
923 #define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */
924 /**
925   * @}
926   */
927 
928 /** @addtogroup Peripheral_declaration
929   * @{
930   */
931 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
932 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
933 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
934 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
935 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
936 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
937 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
938 #define USART2              ((USART_TypeDef *) USART2_BASE)
939 #define USART3              ((USART_TypeDef *) USART3_BASE)
940 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
941 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
942 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
943 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
944 #define USB                 ((USB_TypeDef *) USB_BASE)
945 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
946 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
947 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
948 #define OPAMP1_COMMON       ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
949 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
950 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
951 #define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
952 
953 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
954 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
955 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
956 #define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
957 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
958 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
959 #define USART1              ((USART_TypeDef *) USART1_BASE)
960 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
961 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
962 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
963 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
964 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
965 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
966 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
967 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
968 
969 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
970 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
971 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
972 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
973 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
974 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
975 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
976 #define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
977 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
978 
979 
980 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
981 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
982 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
983 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
984 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
985 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
986 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
987 #define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
988 
989 
990 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
991 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
992 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
993 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
994 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
995 #define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
996 #define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
997 #define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
998 
999 
1000 
1001 #define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
1002 
1003 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1004 
1005 /**
1006   * @}
1007   */
1008 
1009 /** @addtogroup Exported_constants
1010   * @{
1011   */
1012 
1013 /** @addtogroup Hardware_Constant_Definition
1014   * @{
1015   */
1016 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
1017 
1018 /**
1019   * @}
1020   */
1021 
1022 /** @addtogroup Peripheral_Registers_Bits_Definition
1023   * @{
1024   */
1025 
1026 /******************************************************************************/
1027 /*                         Peripheral Registers_Bits_Definition               */
1028 /******************************************************************************/
1029 
1030 /******************************************************************************/
1031 /*                                                                            */
1032 /*                        Analog to Digital Converter                         */
1033 /*                                                                            */
1034 /******************************************************************************/
1035 
1036 /*
1037  * @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
1038  */
1039 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1040 
1041 /********************  Bit definition for ADC_ISR register  *******************/
1042 #define ADC_ISR_ADRDY_Pos              (0U)
1043 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
1044 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1045 #define ADC_ISR_EOSMP_Pos              (1U)
1046 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
1047 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1048 #define ADC_ISR_EOC_Pos                (2U)
1049 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
1050 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1051 #define ADC_ISR_EOS_Pos                (3U)
1052 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
1053 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1054 #define ADC_ISR_OVR_Pos                (4U)
1055 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
1056 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1057 #define ADC_ISR_JEOC_Pos               (5U)
1058 #define ADC_ISR_JEOC_Msk               (0x1UL << ADC_ISR_JEOC_Pos)             /*!< 0x00000020 */
1059 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
1060 #define ADC_ISR_JEOS_Pos               (6U)
1061 #define ADC_ISR_JEOS_Msk               (0x1UL << ADC_ISR_JEOS_Pos)             /*!< 0x00000040 */
1062 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
1063 #define ADC_ISR_AWD1_Pos               (7U)
1064 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
1065 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1066 #define ADC_ISR_AWD2_Pos               (8U)
1067 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
1068 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1069 #define ADC_ISR_AWD3_Pos               (9U)
1070 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
1071 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1072 #define ADC_ISR_JQOVF_Pos              (10U)
1073 #define ADC_ISR_JQOVF_Msk              (0x1UL << ADC_ISR_JQOVF_Pos)            /*!< 0x00000400 */
1074 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
1075 
1076 /********************  Bit definition for ADC_IER register  *******************/
1077 #define ADC_IER_ADRDYIE_Pos            (0U)
1078 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
1079 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1080 #define ADC_IER_EOSMPIE_Pos            (1U)
1081 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
1082 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1083 #define ADC_IER_EOCIE_Pos              (2U)
1084 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
1085 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1086 #define ADC_IER_EOSIE_Pos              (3U)
1087 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
1088 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1089 #define ADC_IER_OVRIE_Pos              (4U)
1090 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
1091 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1092 #define ADC_IER_JEOCIE_Pos             (5U)
1093 #define ADC_IER_JEOCIE_Msk             (0x1UL << ADC_IER_JEOCIE_Pos)           /*!< 0x00000020 */
1094 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
1095 #define ADC_IER_JEOSIE_Pos             (6U)
1096 #define ADC_IER_JEOSIE_Msk             (0x1UL << ADC_IER_JEOSIE_Pos)           /*!< 0x00000040 */
1097 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
1098 #define ADC_IER_AWD1IE_Pos             (7U)
1099 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
1100 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1101 #define ADC_IER_AWD2IE_Pos             (8U)
1102 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
1103 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1104 #define ADC_IER_AWD3IE_Pos             (9U)
1105 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
1106 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1107 #define ADC_IER_JQOVFIE_Pos            (10U)
1108 #define ADC_IER_JQOVFIE_Msk            (0x1UL << ADC_IER_JQOVFIE_Pos)          /*!< 0x00000400 */
1109 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1110 
1111 /* Legacy defines */
1112 #define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
1113 #define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
1114 #define ADC_IER_EOC             (ADC_IER_EOCIE)
1115 #define ADC_IER_EOS             (ADC_IER_EOSIE)
1116 #define ADC_IER_OVR             (ADC_IER_OVRIE)
1117 #define ADC_IER_JEOC            (ADC_IER_JEOCIE)
1118 #define ADC_IER_JEOS            (ADC_IER_JEOSIE)
1119 #define ADC_IER_AWD1            (ADC_IER_AWD1IE)
1120 #define ADC_IER_AWD2            (ADC_IER_AWD2IE)
1121 #define ADC_IER_AWD3            (ADC_IER_AWD3IE)
1122 #define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
1123 
1124 /********************  Bit definition for ADC_CR register  ********************/
1125 #define ADC_CR_ADEN_Pos                (0U)
1126 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
1127 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1128 #define ADC_CR_ADDIS_Pos               (1U)
1129 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
1130 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1131 #define ADC_CR_ADSTART_Pos             (2U)
1132 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
1133 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1134 #define ADC_CR_JADSTART_Pos            (3U)
1135 #define ADC_CR_JADSTART_Msk            (0x1UL << ADC_CR_JADSTART_Pos)          /*!< 0x00000008 */
1136 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1137 #define ADC_CR_ADSTP_Pos               (4U)
1138 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
1139 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1140 #define ADC_CR_JADSTP_Pos              (5U)
1141 #define ADC_CR_JADSTP_Msk              (0x1UL << ADC_CR_JADSTP_Pos)            /*!< 0x00000020 */
1142 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1143 #define ADC_CR_ADVREGEN_Pos            (28U)
1144 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
1145 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1146 #define ADC_CR_DEEPPWD_Pos             (29U)
1147 #define ADC_CR_DEEPPWD_Msk             (0x1UL << ADC_CR_DEEPPWD_Pos)           /*!< 0x20000000 */
1148 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
1149 #define ADC_CR_ADCALDIF_Pos            (30U)
1150 #define ADC_CR_ADCALDIF_Msk            (0x1UL << ADC_CR_ADCALDIF_Pos)          /*!< 0x40000000 */
1151 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1152 #define ADC_CR_ADCAL_Pos               (31U)
1153 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
1154 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1155 
1156 /********************  Bit definition for ADC_CFGR register  ******************/
1157 #define ADC_CFGR_DMAEN_Pos             (0U)
1158 #define ADC_CFGR_DMAEN_Msk             (0x1UL << ADC_CFGR_DMAEN_Pos)           /*!< 0x00000001 */
1159 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
1160 #define ADC_CFGR_DMACFG_Pos            (1U)
1161 #define ADC_CFGR_DMACFG_Msk            (0x1UL << ADC_CFGR_DMACFG_Pos)          /*!< 0x00000002 */
1162 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
1163 
1164 #define ADC_CFGR_RES_Pos               (3U)
1165 #define ADC_CFGR_RES_Msk               (0x3UL << ADC_CFGR_RES_Pos)             /*!< 0x00000018 */
1166 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1167 #define ADC_CFGR_RES_0                 (0x1UL << ADC_CFGR_RES_Pos)             /*!< 0x00000008 */
1168 #define ADC_CFGR_RES_1                 (0x2UL << ADC_CFGR_RES_Pos)             /*!< 0x00000010 */
1169 
1170 #define ADC_CFGR_ALIGN_Pos             (5U)
1171 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00000020 */
1172 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
1173 
1174 #define ADC_CFGR_EXTSEL_Pos            (6U)
1175 #define ADC_CFGR_EXTSEL_Msk            (0xFUL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x000003C0 */
1176 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1177 #define ADC_CFGR_EXTSEL_0              (0x1UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000040 */
1178 #define ADC_CFGR_EXTSEL_1              (0x2UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000080 */
1179 #define ADC_CFGR_EXTSEL_2              (0x4UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000100 */
1180 #define ADC_CFGR_EXTSEL_3              (0x8UL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x00000200 */
1181 
1182 #define ADC_CFGR_EXTEN_Pos             (10U)
1183 #define ADC_CFGR_EXTEN_Msk             (0x3UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000C00 */
1184 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1185 #define ADC_CFGR_EXTEN_0               (0x1UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000400 */
1186 #define ADC_CFGR_EXTEN_1               (0x2UL << ADC_CFGR_EXTEN_Pos)           /*!< 0x00000800 */
1187 
1188 #define ADC_CFGR_OVRMOD_Pos            (12U)
1189 #define ADC_CFGR_OVRMOD_Msk            (0x1UL << ADC_CFGR_OVRMOD_Pos)          /*!< 0x00001000 */
1190 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1191 #define ADC_CFGR_CONT_Pos              (13U)
1192 #define ADC_CFGR_CONT_Msk              (0x1UL << ADC_CFGR_CONT_Pos)            /*!< 0x00002000 */
1193 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1194 #define ADC_CFGR_AUTDLY_Pos            (14U)
1195 #define ADC_CFGR_AUTDLY_Msk            (0x1UL << ADC_CFGR_AUTDLY_Pos)          /*!< 0x00004000 */
1196 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1197 
1198 #define ADC_CFGR_DISCEN_Pos            (16U)
1199 #define ADC_CFGR_DISCEN_Msk            (0x1UL << ADC_CFGR_DISCEN_Pos)          /*!< 0x00010000 */
1200 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1201 
1202 #define ADC_CFGR_DISCNUM_Pos           (17U)
1203 #define ADC_CFGR_DISCNUM_Msk           (0x7UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x000E0000 */
1204 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
1205 #define ADC_CFGR_DISCNUM_0             (0x1UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00020000 */
1206 #define ADC_CFGR_DISCNUM_1             (0x2UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00040000 */
1207 #define ADC_CFGR_DISCNUM_2             (0x4UL << ADC_CFGR_DISCNUM_Pos)         /*!< 0x00080000 */
1208 
1209 #define ADC_CFGR_JDISCEN_Pos           (20U)
1210 #define ADC_CFGR_JDISCEN_Msk           (0x1UL << ADC_CFGR_JDISCEN_Pos)         /*!< 0x00100000 */
1211 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
1212 #define ADC_CFGR_JQM_Pos               (21U)
1213 #define ADC_CFGR_JQM_Msk               (0x1UL << ADC_CFGR_JQM_Pos)             /*!< 0x00200000 */
1214 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1215 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1216 #define ADC_CFGR_AWD1SGL_Msk           (0x1UL << ADC_CFGR_AWD1SGL_Pos)         /*!< 0x00400000 */
1217 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1218 #define ADC_CFGR_AWD1EN_Pos            (23U)
1219 #define ADC_CFGR_AWD1EN_Msk            (0x1UL << ADC_CFGR_AWD1EN_Pos)          /*!< 0x00800000 */
1220 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1221 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1222 #define ADC_CFGR_JAWD1EN_Msk           (0x1UL << ADC_CFGR_JAWD1EN_Pos)         /*!< 0x01000000 */
1223 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1224 #define ADC_CFGR_JAUTO_Pos             (25U)
1225 #define ADC_CFGR_JAUTO_Msk             (0x1UL << ADC_CFGR_JAUTO_Pos)           /*!< 0x02000000 */
1226 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1227 
1228 #define ADC_CFGR_AWD1CH_Pos            (26U)
1229 #define ADC_CFGR_AWD1CH_Msk            (0x1FUL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x7C000000 */
1230 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1231 #define ADC_CFGR_AWD1CH_0              (0x01UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x04000000 */
1232 #define ADC_CFGR_AWD1CH_1              (0x02UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x08000000 */
1233 #define ADC_CFGR_AWD1CH_2              (0x04UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x10000000 */
1234 #define ADC_CFGR_AWD1CH_3              (0x08UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x20000000 */
1235 #define ADC_CFGR_AWD1CH_4              (0x10UL << ADC_CFGR_AWD1CH_Pos)         /*!< 0x40000000 */
1236 
1237 #define ADC_CFGR_JQDIS_Pos             (31U)
1238 #define ADC_CFGR_JQDIS_Msk             (0x1UL << ADC_CFGR_JQDIS_Pos)           /*!< 0x80000000 */
1239 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
1240 
1241 /********************  Bit definition for ADC_CFGR2 register  *****************/
1242 #define ADC_CFGR2_ROVSE_Pos            (0U)
1243 #define ADC_CFGR2_ROVSE_Msk            (0x1UL << ADC_CFGR2_ROVSE_Pos)          /*!< 0x00000001 */
1244 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
1245 #define ADC_CFGR2_JOVSE_Pos            (1U)
1246 #define ADC_CFGR2_JOVSE_Msk            (0x1UL << ADC_CFGR2_JOVSE_Pos)          /*!< 0x00000002 */
1247 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
1248 
1249 #define ADC_CFGR2_OVSR_Pos             (2U)
1250 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1251 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1252 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1253 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1254 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1255 
1256 #define ADC_CFGR2_OVSS_Pos             (5U)
1257 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1258 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1259 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1260 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1261 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1262 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1263 
1264 #define ADC_CFGR2_TROVS_Pos            (9U)
1265 #define ADC_CFGR2_TROVS_Msk            (0x1UL << ADC_CFGR2_TROVS_Pos)          /*!< 0x00000200 */
1266 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1267 #define ADC_CFGR2_ROVSM_Pos            (10U)
1268 #define ADC_CFGR2_ROVSM_Msk            (0x1UL << ADC_CFGR2_ROVSM_Pos)          /*!< 0x00000400 */
1269 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1270 
1271 /********************  Bit definition for ADC_SMPR1 register  *****************/
1272 #define ADC_SMPR1_SMP0_Pos             (0U)
1273 #define ADC_SMPR1_SMP0_Msk             (0x7UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000007 */
1274 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1275 #define ADC_SMPR1_SMP0_0               (0x1UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000001 */
1276 #define ADC_SMPR1_SMP0_1               (0x2UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000002 */
1277 #define ADC_SMPR1_SMP0_2               (0x4UL << ADC_SMPR1_SMP0_Pos)           /*!< 0x00000004 */
1278 
1279 #define ADC_SMPR1_SMP1_Pos             (3U)
1280 #define ADC_SMPR1_SMP1_Msk             (0x7UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000038 */
1281 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1282 #define ADC_SMPR1_SMP1_0               (0x1UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000008 */
1283 #define ADC_SMPR1_SMP1_1               (0x2UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000010 */
1284 #define ADC_SMPR1_SMP1_2               (0x4UL << ADC_SMPR1_SMP1_Pos)           /*!< 0x00000020 */
1285 
1286 #define ADC_SMPR1_SMP2_Pos             (6U)
1287 #define ADC_SMPR1_SMP2_Msk             (0x7UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x000001C0 */
1288 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1289 #define ADC_SMPR1_SMP2_0               (0x1UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000040 */
1290 #define ADC_SMPR1_SMP2_1               (0x2UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000080 */
1291 #define ADC_SMPR1_SMP2_2               (0x4UL << ADC_SMPR1_SMP2_Pos)           /*!< 0x00000100 */
1292 
1293 #define ADC_SMPR1_SMP3_Pos             (9U)
1294 #define ADC_SMPR1_SMP3_Msk             (0x7UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000E00 */
1295 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1296 #define ADC_SMPR1_SMP3_0               (0x1UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000200 */
1297 #define ADC_SMPR1_SMP3_1               (0x2UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000400 */
1298 #define ADC_SMPR1_SMP3_2               (0x4UL << ADC_SMPR1_SMP3_Pos)           /*!< 0x00000800 */
1299 
1300 #define ADC_SMPR1_SMP4_Pos             (12U)
1301 #define ADC_SMPR1_SMP4_Msk             (0x7UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00007000 */
1302 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1303 #define ADC_SMPR1_SMP4_0               (0x1UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00001000 */
1304 #define ADC_SMPR1_SMP4_1               (0x2UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00002000 */
1305 #define ADC_SMPR1_SMP4_2               (0x4UL << ADC_SMPR1_SMP4_Pos)           /*!< 0x00004000 */
1306 
1307 #define ADC_SMPR1_SMP5_Pos             (15U)
1308 #define ADC_SMPR1_SMP5_Msk             (0x7UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00038000 */
1309 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1310 #define ADC_SMPR1_SMP5_0               (0x1UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00008000 */
1311 #define ADC_SMPR1_SMP5_1               (0x2UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00010000 */
1312 #define ADC_SMPR1_SMP5_2               (0x4UL << ADC_SMPR1_SMP5_Pos)           /*!< 0x00020000 */
1313 
1314 #define ADC_SMPR1_SMP6_Pos             (18U)
1315 #define ADC_SMPR1_SMP6_Msk             (0x7UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x001C0000 */
1316 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1317 #define ADC_SMPR1_SMP6_0               (0x1UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00040000 */
1318 #define ADC_SMPR1_SMP6_1               (0x2UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00080000 */
1319 #define ADC_SMPR1_SMP6_2               (0x4UL << ADC_SMPR1_SMP6_Pos)           /*!< 0x00100000 */
1320 
1321 #define ADC_SMPR1_SMP7_Pos             (21U)
1322 #define ADC_SMPR1_SMP7_Msk             (0x7UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00E00000 */
1323 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1324 #define ADC_SMPR1_SMP7_0               (0x1UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00200000 */
1325 #define ADC_SMPR1_SMP7_1               (0x2UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00400000 */
1326 #define ADC_SMPR1_SMP7_2               (0x4UL << ADC_SMPR1_SMP7_Pos)           /*!< 0x00800000 */
1327 
1328 #define ADC_SMPR1_SMP8_Pos             (24U)
1329 #define ADC_SMPR1_SMP8_Msk             (0x7UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x07000000 */
1330 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1331 #define ADC_SMPR1_SMP8_0               (0x1UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x01000000 */
1332 #define ADC_SMPR1_SMP8_1               (0x2UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x02000000 */
1333 #define ADC_SMPR1_SMP8_2               (0x4UL << ADC_SMPR1_SMP8_Pos)           /*!< 0x04000000 */
1334 
1335 #define ADC_SMPR1_SMP9_Pos             (27U)
1336 #define ADC_SMPR1_SMP9_Msk             (0x7UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x38000000 */
1337 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1338 #define ADC_SMPR1_SMP9_0               (0x1UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x08000000 */
1339 #define ADC_SMPR1_SMP9_1               (0x2UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x10000000 */
1340 #define ADC_SMPR1_SMP9_2               (0x4UL << ADC_SMPR1_SMP9_Pos)           /*!< 0x20000000 */
1341 
1342 #define ADC_SMPR1_SMPPLUS_Pos          (31U)
1343 #define ADC_SMPR1_SMPPLUS_Msk          (0x1UL << ADC_SMPR1_SMPPLUS_Pos)        /*!< 0x80000000 */
1344 #define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
1345 
1346 /********************  Bit definition for ADC_SMPR2 register  *****************/
1347 #define ADC_SMPR2_SMP10_Pos            (0U)
1348 #define ADC_SMPR2_SMP10_Msk            (0x7UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000007 */
1349 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
1350 #define ADC_SMPR2_SMP10_0              (0x1UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000001 */
1351 #define ADC_SMPR2_SMP10_1              (0x2UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000002 */
1352 #define ADC_SMPR2_SMP10_2              (0x4UL << ADC_SMPR2_SMP10_Pos)          /*!< 0x00000004 */
1353 
1354 #define ADC_SMPR2_SMP11_Pos            (3U)
1355 #define ADC_SMPR2_SMP11_Msk            (0x7UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000038 */
1356 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
1357 #define ADC_SMPR2_SMP11_0              (0x1UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000008 */
1358 #define ADC_SMPR2_SMP11_1              (0x2UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000010 */
1359 #define ADC_SMPR2_SMP11_2              (0x4UL << ADC_SMPR2_SMP11_Pos)          /*!< 0x00000020 */
1360 
1361 #define ADC_SMPR2_SMP12_Pos            (6U)
1362 #define ADC_SMPR2_SMP12_Msk            (0x7UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x000001C0 */
1363 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
1364 #define ADC_SMPR2_SMP12_0              (0x1UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000040 */
1365 #define ADC_SMPR2_SMP12_1              (0x2UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000080 */
1366 #define ADC_SMPR2_SMP12_2              (0x4UL << ADC_SMPR2_SMP12_Pos)          /*!< 0x00000100 */
1367 
1368 #define ADC_SMPR2_SMP13_Pos            (9U)
1369 #define ADC_SMPR2_SMP13_Msk            (0x7UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000E00 */
1370 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
1371 #define ADC_SMPR2_SMP13_0              (0x1UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000200 */
1372 #define ADC_SMPR2_SMP13_1              (0x2UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000400 */
1373 #define ADC_SMPR2_SMP13_2              (0x4UL << ADC_SMPR2_SMP13_Pos)          /*!< 0x00000800 */
1374 
1375 #define ADC_SMPR2_SMP14_Pos            (12U)
1376 #define ADC_SMPR2_SMP14_Msk            (0x7UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00007000 */
1377 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
1378 #define ADC_SMPR2_SMP14_0              (0x1UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00001000 */
1379 #define ADC_SMPR2_SMP14_1              (0x2UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00002000 */
1380 #define ADC_SMPR2_SMP14_2              (0x4UL << ADC_SMPR2_SMP14_Pos)          /*!< 0x00004000 */
1381 
1382 #define ADC_SMPR2_SMP15_Pos            (15U)
1383 #define ADC_SMPR2_SMP15_Msk            (0x7UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00038000 */
1384 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
1385 #define ADC_SMPR2_SMP15_0              (0x1UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00008000 */
1386 #define ADC_SMPR2_SMP15_1              (0x2UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00010000 */
1387 #define ADC_SMPR2_SMP15_2              (0x4UL << ADC_SMPR2_SMP15_Pos)          /*!< 0x00020000 */
1388 
1389 #define ADC_SMPR2_SMP16_Pos            (18U)
1390 #define ADC_SMPR2_SMP16_Msk            (0x7UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x001C0000 */
1391 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
1392 #define ADC_SMPR2_SMP16_0              (0x1UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00040000 */
1393 #define ADC_SMPR2_SMP16_1              (0x2UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00080000 */
1394 #define ADC_SMPR2_SMP16_2              (0x4UL << ADC_SMPR2_SMP16_Pos)          /*!< 0x00100000 */
1395 
1396 #define ADC_SMPR2_SMP17_Pos            (21U)
1397 #define ADC_SMPR2_SMP17_Msk            (0x7UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00E00000 */
1398 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
1399 #define ADC_SMPR2_SMP17_0              (0x1UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00200000 */
1400 #define ADC_SMPR2_SMP17_1              (0x2UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00400000 */
1401 #define ADC_SMPR2_SMP17_2              (0x4UL << ADC_SMPR2_SMP17_Pos)          /*!< 0x00800000 */
1402 
1403 #define ADC_SMPR2_SMP18_Pos            (24U)
1404 #define ADC_SMPR2_SMP18_Msk            (0x7UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x07000000 */
1405 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
1406 #define ADC_SMPR2_SMP18_0              (0x1UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x01000000 */
1407 #define ADC_SMPR2_SMP18_1              (0x2UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x02000000 */
1408 #define ADC_SMPR2_SMP18_2              (0x4UL << ADC_SMPR2_SMP18_Pos)          /*!< 0x04000000 */
1409 
1410 /********************  Bit definition for ADC_TR1 register  *******************/
1411 #define ADC_TR1_LT1_Pos                (0U)
1412 #define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
1413 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
1414 #define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)            /*!< 0x00000001 */
1415 #define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)            /*!< 0x00000002 */
1416 #define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)            /*!< 0x00000004 */
1417 #define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)            /*!< 0x00000008 */
1418 #define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)            /*!< 0x00000010 */
1419 #define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)            /*!< 0x00000020 */
1420 #define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)            /*!< 0x00000040 */
1421 #define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)            /*!< 0x00000080 */
1422 #define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)            /*!< 0x00000100 */
1423 #define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)            /*!< 0x00000200 */
1424 #define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)            /*!< 0x00000400 */
1425 #define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)            /*!< 0x00000800 */
1426 
1427 #define ADC_TR1_HT1_Pos                (16U)
1428 #define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
1429 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
1430 #define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)            /*!< 0x00010000 */
1431 #define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)            /*!< 0x00020000 */
1432 #define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)            /*!< 0x00040000 */
1433 #define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)            /*!< 0x00080000 */
1434 #define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)            /*!< 0x00100000 */
1435 #define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)            /*!< 0x00200000 */
1436 #define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)            /*!< 0x00400000 */
1437 #define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)            /*!< 0x00800000 */
1438 #define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)            /*!< 0x01000000 */
1439 #define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)            /*!< 0x02000000 */
1440 #define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)            /*!< 0x04000000 */
1441 #define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)            /*!< 0x08000000 */
1442 
1443 /********************  Bit definition for ADC_TR2 register  *******************/
1444 #define ADC_TR2_LT2_Pos                (0U)
1445 #define ADC_TR2_LT2_Msk                (0xFFUL << ADC_TR2_LT2_Pos)             /*!< 0x000000FF */
1446 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
1447 #define ADC_TR2_LT2_0                  (0x01UL << ADC_TR2_LT2_Pos)             /*!< 0x00000001 */
1448 #define ADC_TR2_LT2_1                  (0x02UL << ADC_TR2_LT2_Pos)             /*!< 0x00000002 */
1449 #define ADC_TR2_LT2_2                  (0x04UL << ADC_TR2_LT2_Pos)             /*!< 0x00000004 */
1450 #define ADC_TR2_LT2_3                  (0x08UL << ADC_TR2_LT2_Pos)             /*!< 0x00000008 */
1451 #define ADC_TR2_LT2_4                  (0x10UL << ADC_TR2_LT2_Pos)             /*!< 0x00000010 */
1452 #define ADC_TR2_LT2_5                  (0x20UL << ADC_TR2_LT2_Pos)             /*!< 0x00000020 */
1453 #define ADC_TR2_LT2_6                  (0x40UL << ADC_TR2_LT2_Pos)             /*!< 0x00000040 */
1454 #define ADC_TR2_LT2_7                  (0x80UL << ADC_TR2_LT2_Pos)             /*!< 0x00000080 */
1455 
1456 #define ADC_TR2_HT2_Pos                (16U)
1457 #define ADC_TR2_HT2_Msk                (0xFFUL << ADC_TR2_HT2_Pos)             /*!< 0x00FF0000 */
1458 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
1459 #define ADC_TR2_HT2_0                  (0x01UL << ADC_TR2_HT2_Pos)             /*!< 0x00010000 */
1460 #define ADC_TR2_HT2_1                  (0x02UL << ADC_TR2_HT2_Pos)             /*!< 0x00020000 */
1461 #define ADC_TR2_HT2_2                  (0x04UL << ADC_TR2_HT2_Pos)             /*!< 0x00040000 */
1462 #define ADC_TR2_HT2_3                  (0x08UL << ADC_TR2_HT2_Pos)             /*!< 0x00080000 */
1463 #define ADC_TR2_HT2_4                  (0x10UL << ADC_TR2_HT2_Pos)             /*!< 0x00100000 */
1464 #define ADC_TR2_HT2_5                  (0x20UL << ADC_TR2_HT2_Pos)             /*!< 0x00200000 */
1465 #define ADC_TR2_HT2_6                  (0x40UL << ADC_TR2_HT2_Pos)             /*!< 0x00400000 */
1466 #define ADC_TR2_HT2_7                  (0x80UL << ADC_TR2_HT2_Pos)             /*!< 0x00800000 */
1467 
1468 /********************  Bit definition for ADC_TR3 register  *******************/
1469 #define ADC_TR3_LT3_Pos                (0U)
1470 #define ADC_TR3_LT3_Msk                (0xFFUL << ADC_TR3_LT3_Pos)             /*!< 0x000000FF */
1471 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
1472 #define ADC_TR3_LT3_0                  (0x01UL << ADC_TR3_LT3_Pos)             /*!< 0x00000001 */
1473 #define ADC_TR3_LT3_1                  (0x02UL << ADC_TR3_LT3_Pos)             /*!< 0x00000002 */
1474 #define ADC_TR3_LT3_2                  (0x04UL << ADC_TR3_LT3_Pos)             /*!< 0x00000004 */
1475 #define ADC_TR3_LT3_3                  (0x08UL << ADC_TR3_LT3_Pos)             /*!< 0x00000008 */
1476 #define ADC_TR3_LT3_4                  (0x10UL << ADC_TR3_LT3_Pos)             /*!< 0x00000010 */
1477 #define ADC_TR3_LT3_5                  (0x20UL << ADC_TR3_LT3_Pos)             /*!< 0x00000020 */
1478 #define ADC_TR3_LT3_6                  (0x40UL << ADC_TR3_LT3_Pos)             /*!< 0x00000040 */
1479 #define ADC_TR3_LT3_7                  (0x80UL << ADC_TR3_LT3_Pos)             /*!< 0x00000080 */
1480 
1481 #define ADC_TR3_HT3_Pos                (16U)
1482 #define ADC_TR3_HT3_Msk                (0xFFUL << ADC_TR3_HT3_Pos)             /*!< 0x00FF0000 */
1483 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
1484 #define ADC_TR3_HT3_0                  (0x01UL << ADC_TR3_HT3_Pos)             /*!< 0x00010000 */
1485 #define ADC_TR3_HT3_1                  (0x02UL << ADC_TR3_HT3_Pos)             /*!< 0x00020000 */
1486 #define ADC_TR3_HT3_2                  (0x04UL << ADC_TR3_HT3_Pos)             /*!< 0x00040000 */
1487 #define ADC_TR3_HT3_3                  (0x08UL << ADC_TR3_HT3_Pos)             /*!< 0x00080000 */
1488 #define ADC_TR3_HT3_4                  (0x10UL << ADC_TR3_HT3_Pos)             /*!< 0x00100000 */
1489 #define ADC_TR3_HT3_5                  (0x20UL << ADC_TR3_HT3_Pos)             /*!< 0x00200000 */
1490 #define ADC_TR3_HT3_6                  (0x40UL << ADC_TR3_HT3_Pos)             /*!< 0x00400000 */
1491 #define ADC_TR3_HT3_7                  (0x80UL << ADC_TR3_HT3_Pos)             /*!< 0x00800000 */
1492 
1493 /********************  Bit definition for ADC_SQR1 register  ******************/
1494 #define ADC_SQR1_L_Pos                 (0U)
1495 #define ADC_SQR1_L_Msk                 (0xFUL << ADC_SQR1_L_Pos)               /*!< 0x0000000F */
1496 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
1497 #define ADC_SQR1_L_0                   (0x1UL << ADC_SQR1_L_Pos)               /*!< 0x00000001 */
1498 #define ADC_SQR1_L_1                   (0x2UL << ADC_SQR1_L_Pos)               /*!< 0x00000002 */
1499 #define ADC_SQR1_L_2                   (0x4UL << ADC_SQR1_L_Pos)               /*!< 0x00000004 */
1500 #define ADC_SQR1_L_3                   (0x8UL << ADC_SQR1_L_Pos)               /*!< 0x00000008 */
1501 
1502 #define ADC_SQR1_SQ1_Pos               (6U)
1503 #define ADC_SQR1_SQ1_Msk               (0x1FUL << ADC_SQR1_SQ1_Pos)            /*!< 0x000007C0 */
1504 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
1505 #define ADC_SQR1_SQ1_0                 (0x01UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000040 */
1506 #define ADC_SQR1_SQ1_1                 (0x02UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000080 */
1507 #define ADC_SQR1_SQ1_2                 (0x04UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000100 */
1508 #define ADC_SQR1_SQ1_3                 (0x08UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000200 */
1509 #define ADC_SQR1_SQ1_4                 (0x10UL << ADC_SQR1_SQ1_Pos)            /*!< 0x00000400 */
1510 
1511 #define ADC_SQR1_SQ2_Pos               (12U)
1512 #define ADC_SQR1_SQ2_Msk               (0x1FUL << ADC_SQR1_SQ2_Pos)            /*!< 0x0001F000 */
1513 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
1514 #define ADC_SQR1_SQ2_0                 (0x01UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00001000 */
1515 #define ADC_SQR1_SQ2_1                 (0x02UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00002000 */
1516 #define ADC_SQR1_SQ2_2                 (0x04UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00004000 */
1517 #define ADC_SQR1_SQ2_3                 (0x08UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00008000 */
1518 #define ADC_SQR1_SQ2_4                 (0x10UL << ADC_SQR1_SQ2_Pos)            /*!< 0x00010000 */
1519 
1520 #define ADC_SQR1_SQ3_Pos               (18U)
1521 #define ADC_SQR1_SQ3_Msk               (0x1FUL << ADC_SQR1_SQ3_Pos)            /*!< 0x007C0000 */
1522 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
1523 #define ADC_SQR1_SQ3_0                 (0x01UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00040000 */
1524 #define ADC_SQR1_SQ3_1                 (0x02UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00080000 */
1525 #define ADC_SQR1_SQ3_2                 (0x04UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00100000 */
1526 #define ADC_SQR1_SQ3_3                 (0x08UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00200000 */
1527 #define ADC_SQR1_SQ3_4                 (0x10UL << ADC_SQR1_SQ3_Pos)            /*!< 0x00400000 */
1528 
1529 #define ADC_SQR1_SQ4_Pos               (24U)
1530 #define ADC_SQR1_SQ4_Msk               (0x1FUL << ADC_SQR1_SQ4_Pos)            /*!< 0x1F000000 */
1531 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
1532 #define ADC_SQR1_SQ4_0                 (0x01UL << ADC_SQR1_SQ4_Pos)            /*!< 0x01000000 */
1533 #define ADC_SQR1_SQ4_1                 (0x02UL << ADC_SQR1_SQ4_Pos)            /*!< 0x02000000 */
1534 #define ADC_SQR1_SQ4_2                 (0x04UL << ADC_SQR1_SQ4_Pos)            /*!< 0x04000000 */
1535 #define ADC_SQR1_SQ4_3                 (0x08UL << ADC_SQR1_SQ4_Pos)            /*!< 0x08000000 */
1536 #define ADC_SQR1_SQ4_4                 (0x10UL << ADC_SQR1_SQ4_Pos)            /*!< 0x10000000 */
1537 
1538 /********************  Bit definition for ADC_SQR2 register  ******************/
1539 #define ADC_SQR2_SQ5_Pos               (0U)
1540 #define ADC_SQR2_SQ5_Msk               (0x1FUL << ADC_SQR2_SQ5_Pos)            /*!< 0x0000001F */
1541 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
1542 #define ADC_SQR2_SQ5_0                 (0x01UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000001 */
1543 #define ADC_SQR2_SQ5_1                 (0x02UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000002 */
1544 #define ADC_SQR2_SQ5_2                 (0x04UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000004 */
1545 #define ADC_SQR2_SQ5_3                 (0x08UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000008 */
1546 #define ADC_SQR2_SQ5_4                 (0x10UL << ADC_SQR2_SQ5_Pos)            /*!< 0x00000010 */
1547 
1548 #define ADC_SQR2_SQ6_Pos               (6U)
1549 #define ADC_SQR2_SQ6_Msk               (0x1FUL << ADC_SQR2_SQ6_Pos)            /*!< 0x000007C0 */
1550 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
1551 #define ADC_SQR2_SQ6_0                 (0x01UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000040 */
1552 #define ADC_SQR2_SQ6_1                 (0x02UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000080 */
1553 #define ADC_SQR2_SQ6_2                 (0x04UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000100 */
1554 #define ADC_SQR2_SQ6_3                 (0x08UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000200 */
1555 #define ADC_SQR2_SQ6_4                 (0x10UL << ADC_SQR2_SQ6_Pos)            /*!< 0x00000400 */
1556 
1557 #define ADC_SQR2_SQ7_Pos               (12U)
1558 #define ADC_SQR2_SQ7_Msk               (0x1FUL << ADC_SQR2_SQ7_Pos)            /*!< 0x0001F000 */
1559 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
1560 #define ADC_SQR2_SQ7_0                 (0x01UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00001000 */
1561 #define ADC_SQR2_SQ7_1                 (0x02UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00002000 */
1562 #define ADC_SQR2_SQ7_2                 (0x04UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00004000 */
1563 #define ADC_SQR2_SQ7_3                 (0x08UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00008000 */
1564 #define ADC_SQR2_SQ7_4                 (0x10UL << ADC_SQR2_SQ7_Pos)            /*!< 0x00010000 */
1565 
1566 #define ADC_SQR2_SQ8_Pos               (18U)
1567 #define ADC_SQR2_SQ8_Msk               (0x1FUL << ADC_SQR2_SQ8_Pos)            /*!< 0x007C0000 */
1568 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
1569 #define ADC_SQR2_SQ8_0                 (0x01UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00040000 */
1570 #define ADC_SQR2_SQ8_1                 (0x02UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00080000 */
1571 #define ADC_SQR2_SQ8_2                 (0x04UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00100000 */
1572 #define ADC_SQR2_SQ8_3                 (0x08UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00200000 */
1573 #define ADC_SQR2_SQ8_4                 (0x10UL << ADC_SQR2_SQ8_Pos)            /*!< 0x00400000 */
1574 
1575 #define ADC_SQR2_SQ9_Pos               (24U)
1576 #define ADC_SQR2_SQ9_Msk               (0x1FUL << ADC_SQR2_SQ9_Pos)            /*!< 0x1F000000 */
1577 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
1578 #define ADC_SQR2_SQ9_0                 (0x01UL << ADC_SQR2_SQ9_Pos)            /*!< 0x01000000 */
1579 #define ADC_SQR2_SQ9_1                 (0x02UL << ADC_SQR2_SQ9_Pos)            /*!< 0x02000000 */
1580 #define ADC_SQR2_SQ9_2                 (0x04UL << ADC_SQR2_SQ9_Pos)            /*!< 0x04000000 */
1581 #define ADC_SQR2_SQ9_3                 (0x08UL << ADC_SQR2_SQ9_Pos)            /*!< 0x08000000 */
1582 #define ADC_SQR2_SQ9_4                 (0x10UL << ADC_SQR2_SQ9_Pos)            /*!< 0x10000000 */
1583 
1584 /********************  Bit definition for ADC_SQR3 register  ******************/
1585 #define ADC_SQR3_SQ10_Pos              (0U)
1586 #define ADC_SQR3_SQ10_Msk              (0x1FUL << ADC_SQR3_SQ10_Pos)           /*!< 0x0000001F */
1587 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
1588 #define ADC_SQR3_SQ10_0                (0x01UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000001 */
1589 #define ADC_SQR3_SQ10_1                (0x02UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000002 */
1590 #define ADC_SQR3_SQ10_2                (0x04UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000004 */
1591 #define ADC_SQR3_SQ10_3                (0x08UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000008 */
1592 #define ADC_SQR3_SQ10_4                (0x10UL << ADC_SQR3_SQ10_Pos)           /*!< 0x00000010 */
1593 
1594 #define ADC_SQR3_SQ11_Pos              (6U)
1595 #define ADC_SQR3_SQ11_Msk              (0x1FUL << ADC_SQR3_SQ11_Pos)           /*!< 0x000007C0 */
1596 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
1597 #define ADC_SQR3_SQ11_0                (0x01UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000040 */
1598 #define ADC_SQR3_SQ11_1                (0x02UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000080 */
1599 #define ADC_SQR3_SQ11_2                (0x04UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000100 */
1600 #define ADC_SQR3_SQ11_3                (0x08UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000200 */
1601 #define ADC_SQR3_SQ11_4                (0x10UL << ADC_SQR3_SQ11_Pos)           /*!< 0x00000400 */
1602 
1603 #define ADC_SQR3_SQ12_Pos              (12U)
1604 #define ADC_SQR3_SQ12_Msk              (0x1FUL << ADC_SQR3_SQ12_Pos)           /*!< 0x0001F000 */
1605 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
1606 #define ADC_SQR3_SQ12_0                (0x01UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00001000 */
1607 #define ADC_SQR3_SQ12_1                (0x02UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00002000 */
1608 #define ADC_SQR3_SQ12_2                (0x04UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00004000 */
1609 #define ADC_SQR3_SQ12_3                (0x08UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00008000 */
1610 #define ADC_SQR3_SQ12_4                (0x10UL << ADC_SQR3_SQ12_Pos)           /*!< 0x00010000 */
1611 
1612 #define ADC_SQR3_SQ13_Pos              (18U)
1613 #define ADC_SQR3_SQ13_Msk              (0x1FUL << ADC_SQR3_SQ13_Pos)           /*!< 0x007C0000 */
1614 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
1615 #define ADC_SQR3_SQ13_0                (0x01UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00040000 */
1616 #define ADC_SQR3_SQ13_1                (0x02UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00080000 */
1617 #define ADC_SQR3_SQ13_2                (0x04UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00100000 */
1618 #define ADC_SQR3_SQ13_3                (0x08UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00200000 */
1619 #define ADC_SQR3_SQ13_4                (0x10UL << ADC_SQR3_SQ13_Pos)           /*!< 0x00400000 */
1620 
1621 #define ADC_SQR3_SQ14_Pos              (24U)
1622 #define ADC_SQR3_SQ14_Msk              (0x1FUL << ADC_SQR3_SQ14_Pos)           /*!< 0x1F000000 */
1623 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
1624 #define ADC_SQR3_SQ14_0                (0x01UL << ADC_SQR3_SQ14_Pos)           /*!< 0x01000000 */
1625 #define ADC_SQR3_SQ14_1                (0x02UL << ADC_SQR3_SQ14_Pos)           /*!< 0x02000000 */
1626 #define ADC_SQR3_SQ14_2                (0x04UL << ADC_SQR3_SQ14_Pos)           /*!< 0x04000000 */
1627 #define ADC_SQR3_SQ14_3                (0x08UL << ADC_SQR3_SQ14_Pos)           /*!< 0x08000000 */
1628 #define ADC_SQR3_SQ14_4                (0x10UL << ADC_SQR3_SQ14_Pos)           /*!< 0x10000000 */
1629 
1630 /********************  Bit definition for ADC_SQR4 register  ******************/
1631 #define ADC_SQR4_SQ15_Pos              (0U)
1632 #define ADC_SQR4_SQ15_Msk              (0x1FUL << ADC_SQR4_SQ15_Pos)           /*!< 0x0000001F */
1633 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
1634 #define ADC_SQR4_SQ15_0                (0x01UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000001 */
1635 #define ADC_SQR4_SQ15_1                (0x02UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000002 */
1636 #define ADC_SQR4_SQ15_2                (0x04UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000004 */
1637 #define ADC_SQR4_SQ15_3                (0x08UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000008 */
1638 #define ADC_SQR4_SQ15_4                (0x10UL << ADC_SQR4_SQ15_Pos)           /*!< 0x00000010 */
1639 
1640 #define ADC_SQR4_SQ16_Pos              (6U)
1641 #define ADC_SQR4_SQ16_Msk              (0x1FUL << ADC_SQR4_SQ16_Pos)           /*!< 0x000007C0 */
1642 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
1643 #define ADC_SQR4_SQ16_0                (0x01UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000040 */
1644 #define ADC_SQR4_SQ16_1                (0x02UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000080 */
1645 #define ADC_SQR4_SQ16_2                (0x04UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000100 */
1646 #define ADC_SQR4_SQ16_3                (0x08UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000200 */
1647 #define ADC_SQR4_SQ16_4                (0x10UL << ADC_SQR4_SQ16_Pos)           /*!< 0x00000400 */
1648 
1649 /********************  Bit definition for ADC_DR register  ********************/
1650 #define ADC_DR_RDATA_Pos               (0U)
1651 #define ADC_DR_RDATA_Msk               (0xFFFFUL << ADC_DR_RDATA_Pos)          /*!< 0x0000FFFF */
1652 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
1653 #define ADC_DR_RDATA_0                 (0x0001UL << ADC_DR_RDATA_Pos)          /*!< 0x00000001 */
1654 #define ADC_DR_RDATA_1                 (0x0002UL << ADC_DR_RDATA_Pos)          /*!< 0x00000002 */
1655 #define ADC_DR_RDATA_2                 (0x0004UL << ADC_DR_RDATA_Pos)          /*!< 0x00000004 */
1656 #define ADC_DR_RDATA_3                 (0x0008UL << ADC_DR_RDATA_Pos)          /*!< 0x00000008 */
1657 #define ADC_DR_RDATA_4                 (0x0010UL << ADC_DR_RDATA_Pos)          /*!< 0x00000010 */
1658 #define ADC_DR_RDATA_5                 (0x0020UL << ADC_DR_RDATA_Pos)          /*!< 0x00000020 */
1659 #define ADC_DR_RDATA_6                 (0x0040UL << ADC_DR_RDATA_Pos)          /*!< 0x00000040 */
1660 #define ADC_DR_RDATA_7                 (0x0080UL << ADC_DR_RDATA_Pos)          /*!< 0x00000080 */
1661 #define ADC_DR_RDATA_8                 (0x0100UL << ADC_DR_RDATA_Pos)          /*!< 0x00000100 */
1662 #define ADC_DR_RDATA_9                 (0x0200UL << ADC_DR_RDATA_Pos)          /*!< 0x00000200 */
1663 #define ADC_DR_RDATA_10                (0x0400UL << ADC_DR_RDATA_Pos)          /*!< 0x00000400 */
1664 #define ADC_DR_RDATA_11                (0x0800UL << ADC_DR_RDATA_Pos)          /*!< 0x00000800 */
1665 #define ADC_DR_RDATA_12                (0x1000UL << ADC_DR_RDATA_Pos)          /*!< 0x00001000 */
1666 #define ADC_DR_RDATA_13                (0x2000UL << ADC_DR_RDATA_Pos)          /*!< 0x00002000 */
1667 #define ADC_DR_RDATA_14                (0x4000UL << ADC_DR_RDATA_Pos)          /*!< 0x00004000 */
1668 #define ADC_DR_RDATA_15                (0x8000UL << ADC_DR_RDATA_Pos)          /*!< 0x00008000 */
1669 
1670 /********************  Bit definition for ADC_JSQR register  ******************/
1671 #define ADC_JSQR_JL_Pos                (0U)
1672 #define ADC_JSQR_JL_Msk                (0x3UL << ADC_JSQR_JL_Pos)              /*!< 0x00000003 */
1673 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
1674 #define ADC_JSQR_JL_0                  (0x1UL << ADC_JSQR_JL_Pos)              /*!< 0x00000001 */
1675 #define ADC_JSQR_JL_1                  (0x2UL << ADC_JSQR_JL_Pos)              /*!< 0x00000002 */
1676 
1677 #define ADC_JSQR_JEXTSEL_Pos           (2U)
1678 #define ADC_JSQR_JEXTSEL_Msk           (0xFUL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x0000003C */
1679 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
1680 #define ADC_JSQR_JEXTSEL_0             (0x1UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000004 */
1681 #define ADC_JSQR_JEXTSEL_1             (0x2UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000008 */
1682 #define ADC_JSQR_JEXTSEL_2             (0x4UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000010 */
1683 #define ADC_JSQR_JEXTSEL_3             (0x8UL << ADC_JSQR_JEXTSEL_Pos)         /*!< 0x00000020 */
1684 
1685 #define ADC_JSQR_JEXTEN_Pos            (6U)
1686 #define ADC_JSQR_JEXTEN_Msk            (0x3UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x000000C0 */
1687 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
1688 #define ADC_JSQR_JEXTEN_0              (0x1UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000040 */
1689 #define ADC_JSQR_JEXTEN_1              (0x2UL << ADC_JSQR_JEXTEN_Pos)          /*!< 0x00000080 */
1690 
1691 #define ADC_JSQR_JSQ1_Pos              (8U)
1692 #define ADC_JSQR_JSQ1_Msk              (0x1FUL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001F00 */
1693 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
1694 #define ADC_JSQR_JSQ1_0                (0x01UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000100 */
1695 #define ADC_JSQR_JSQ1_1                (0x02UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000200 */
1696 #define ADC_JSQR_JSQ1_2                (0x04UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000400 */
1697 #define ADC_JSQR_JSQ1_3                (0x08UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00000800 */
1698 #define ADC_JSQR_JSQ1_4                (0x10UL << ADC_JSQR_JSQ1_Pos)           /*!< 0x00001000 */
1699 
1700 #define ADC_JSQR_JSQ2_Pos              (14U)
1701 #define ADC_JSQR_JSQ2_Msk              (0x1FUL << ADC_JSQR_JSQ2_Pos)           /*!< 0x0007C000 */
1702 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
1703 #define ADC_JSQR_JSQ2_0                (0x01UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00004000 */
1704 #define ADC_JSQR_JSQ2_1                (0x02UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00008000 */
1705 #define ADC_JSQR_JSQ2_2                (0x04UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00010000 */
1706 #define ADC_JSQR_JSQ2_3                (0x08UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00020000 */
1707 #define ADC_JSQR_JSQ2_4                (0x10UL << ADC_JSQR_JSQ2_Pos)           /*!< 0x00040000 */
1708 
1709 #define ADC_JSQR_JSQ3_Pos              (20U)
1710 #define ADC_JSQR_JSQ3_Msk              (0x1FUL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01F00000 */
1711 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
1712 #define ADC_JSQR_JSQ3_0                (0x01UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00100000 */
1713 #define ADC_JSQR_JSQ3_1                (0x02UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00200000 */
1714 #define ADC_JSQR_JSQ3_2                (0x04UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00400000 */
1715 #define ADC_JSQR_JSQ3_3                (0x08UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x00800000 */
1716 #define ADC_JSQR_JSQ3_4                (0x10UL << ADC_JSQR_JSQ3_Pos)           /*!< 0x01000000 */
1717 
1718 #define ADC_JSQR_JSQ4_Pos              (26U)
1719 #define ADC_JSQR_JSQ4_Msk              (0x1FUL << ADC_JSQR_JSQ4_Pos)           /*!< 0x7C000000 */
1720 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
1721 #define ADC_JSQR_JSQ4_0                (0x01UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x04000000 */
1722 #define ADC_JSQR_JSQ4_1                (0x02UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x08000000 */
1723 #define ADC_JSQR_JSQ4_2                (0x04UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x10000000 */
1724 #define ADC_JSQR_JSQ4_3                (0x08UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x20000000 */
1725 #define ADC_JSQR_JSQ4_4                (0x10UL << ADC_JSQR_JSQ4_Pos)           /*!< 0x40000000 */
1726 
1727 /********************  Bit definition for ADC_OFR1 register  ******************/
1728 #define ADC_OFR1_OFFSET1_Pos           (0U)
1729 #define ADC_OFR1_OFFSET1_Msk           (0xFFFUL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000FFF */
1730 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
1731 #define ADC_OFR1_OFFSET1_0             (0x001UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000001 */
1732 #define ADC_OFR1_OFFSET1_1             (0x002UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000002 */
1733 #define ADC_OFR1_OFFSET1_2             (0x004UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000004 */
1734 #define ADC_OFR1_OFFSET1_3             (0x008UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000008 */
1735 #define ADC_OFR1_OFFSET1_4             (0x010UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000010 */
1736 #define ADC_OFR1_OFFSET1_5             (0x020UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000020 */
1737 #define ADC_OFR1_OFFSET1_6             (0x040UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000040 */
1738 #define ADC_OFR1_OFFSET1_7             (0x080UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000080 */
1739 #define ADC_OFR1_OFFSET1_8             (0x100UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000100 */
1740 #define ADC_OFR1_OFFSET1_9             (0x200UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000200 */
1741 #define ADC_OFR1_OFFSET1_10            (0x400UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000400 */
1742 #define ADC_OFR1_OFFSET1_11            (0x800UL << ADC_OFR1_OFFSET1_Pos)       /*!< 0x00000800 */
1743 
1744 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
1745 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x7C000000 */
1746 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
1747 #define ADC_OFR1_OFFSET1_CH_0          (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x04000000 */
1748 #define ADC_OFR1_OFFSET1_CH_1          (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x08000000 */
1749 #define ADC_OFR1_OFFSET1_CH_2          (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x10000000 */
1750 #define ADC_OFR1_OFFSET1_CH_3          (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x20000000 */
1751 #define ADC_OFR1_OFFSET1_CH_4          (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)     /*!< 0x40000000 */
1752 
1753 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
1754 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)      /*!< 0x80000000 */
1755 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
1756 
1757 /********************  Bit definition for ADC_OFR2 register  ******************/
1758 #define ADC_OFR2_OFFSET2_Pos           (0U)
1759 #define ADC_OFR2_OFFSET2_Msk           (0xFFFUL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000FFF */
1760 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
1761 #define ADC_OFR2_OFFSET2_0             (0x001UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000001 */
1762 #define ADC_OFR2_OFFSET2_1             (0x002UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000002 */
1763 #define ADC_OFR2_OFFSET2_2             (0x004UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000004 */
1764 #define ADC_OFR2_OFFSET2_3             (0x008UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000008 */
1765 #define ADC_OFR2_OFFSET2_4             (0x010UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000010 */
1766 #define ADC_OFR2_OFFSET2_5             (0x020UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000020 */
1767 #define ADC_OFR2_OFFSET2_6             (0x040UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000040 */
1768 #define ADC_OFR2_OFFSET2_7             (0x080UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000080 */
1769 #define ADC_OFR2_OFFSET2_8             (0x100UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000100 */
1770 #define ADC_OFR2_OFFSET2_9             (0x200UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000200 */
1771 #define ADC_OFR2_OFFSET2_10            (0x400UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000400 */
1772 #define ADC_OFR2_OFFSET2_11            (0x800UL << ADC_OFR2_OFFSET2_Pos)       /*!< 0x00000800 */
1773 
1774 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
1775 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x7C000000 */
1776 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
1777 #define ADC_OFR2_OFFSET2_CH_0          (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x04000000 */
1778 #define ADC_OFR2_OFFSET2_CH_1          (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x08000000 */
1779 #define ADC_OFR2_OFFSET2_CH_2          (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x10000000 */
1780 #define ADC_OFR2_OFFSET2_CH_3          (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x20000000 */
1781 #define ADC_OFR2_OFFSET2_CH_4          (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)     /*!< 0x40000000 */
1782 
1783 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
1784 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)      /*!< 0x80000000 */
1785 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
1786 
1787 /********************  Bit definition for ADC_OFR3 register  ******************/
1788 #define ADC_OFR3_OFFSET3_Pos           (0U)
1789 #define ADC_OFR3_OFFSET3_Msk           (0xFFFUL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000FFF */
1790 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
1791 #define ADC_OFR3_OFFSET3_0             (0x001UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000001 */
1792 #define ADC_OFR3_OFFSET3_1             (0x002UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000002 */
1793 #define ADC_OFR3_OFFSET3_2             (0x004UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000004 */
1794 #define ADC_OFR3_OFFSET3_3             (0x008UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000008 */
1795 #define ADC_OFR3_OFFSET3_4             (0x010UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000010 */
1796 #define ADC_OFR3_OFFSET3_5             (0x020UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000020 */
1797 #define ADC_OFR3_OFFSET3_6             (0x040UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000040 */
1798 #define ADC_OFR3_OFFSET3_7             (0x080UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000080 */
1799 #define ADC_OFR3_OFFSET3_8             (0x100UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000100 */
1800 #define ADC_OFR3_OFFSET3_9             (0x200UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000200 */
1801 #define ADC_OFR3_OFFSET3_10            (0x400UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000400 */
1802 #define ADC_OFR3_OFFSET3_11            (0x800UL << ADC_OFR3_OFFSET3_Pos)       /*!< 0x00000800 */
1803 
1804 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
1805 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x7C000000 */
1806 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
1807 #define ADC_OFR3_OFFSET3_CH_0          (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x04000000 */
1808 #define ADC_OFR3_OFFSET3_CH_1          (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x08000000 */
1809 #define ADC_OFR3_OFFSET3_CH_2          (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x10000000 */
1810 #define ADC_OFR3_OFFSET3_CH_3          (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x20000000 */
1811 #define ADC_OFR3_OFFSET3_CH_4          (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)     /*!< 0x40000000 */
1812 
1813 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
1814 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)      /*!< 0x80000000 */
1815 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
1816 
1817 /********************  Bit definition for ADC_OFR4 register  ******************/
1818 #define ADC_OFR4_OFFSET4_Pos           (0U)
1819 #define ADC_OFR4_OFFSET4_Msk           (0xFFFUL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000FFF */
1820 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
1821 #define ADC_OFR4_OFFSET4_0             (0x001UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000001 */
1822 #define ADC_OFR4_OFFSET4_1             (0x002UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000002 */
1823 #define ADC_OFR4_OFFSET4_2             (0x004UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000004 */
1824 #define ADC_OFR4_OFFSET4_3             (0x008UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000008 */
1825 #define ADC_OFR4_OFFSET4_4             (0x010UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000010 */
1826 #define ADC_OFR4_OFFSET4_5             (0x020UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000020 */
1827 #define ADC_OFR4_OFFSET4_6             (0x040UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000040 */
1828 #define ADC_OFR4_OFFSET4_7             (0x080UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000080 */
1829 #define ADC_OFR4_OFFSET4_8             (0x100UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000100 */
1830 #define ADC_OFR4_OFFSET4_9             (0x200UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000200 */
1831 #define ADC_OFR4_OFFSET4_10            (0x400UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000400 */
1832 #define ADC_OFR4_OFFSET4_11            (0x800UL << ADC_OFR4_OFFSET4_Pos)       /*!< 0x00000800 */
1833 
1834 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
1835 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x7C000000 */
1836 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
1837 #define ADC_OFR4_OFFSET4_CH_0          (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x04000000 */
1838 #define ADC_OFR4_OFFSET4_CH_1          (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x08000000 */
1839 #define ADC_OFR4_OFFSET4_CH_2          (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x10000000 */
1840 #define ADC_OFR4_OFFSET4_CH_3          (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x20000000 */
1841 #define ADC_OFR4_OFFSET4_CH_4          (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)     /*!< 0x40000000 */
1842 
1843 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
1844 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)      /*!< 0x80000000 */
1845 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
1846 
1847 /********************  Bit definition for ADC_JDR1 register  ******************/
1848 #define ADC_JDR1_JDATA_Pos             (0U)
1849 #define ADC_JDR1_JDATA_Msk             (0xFFFFUL << ADC_JDR1_JDATA_Pos)        /*!< 0x0000FFFF */
1850 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
1851 #define ADC_JDR1_JDATA_0               (0x0001UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000001 */
1852 #define ADC_JDR1_JDATA_1               (0x0002UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000002 */
1853 #define ADC_JDR1_JDATA_2               (0x0004UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000004 */
1854 #define ADC_JDR1_JDATA_3               (0x0008UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000008 */
1855 #define ADC_JDR1_JDATA_4               (0x0010UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000010 */
1856 #define ADC_JDR1_JDATA_5               (0x0020UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000020 */
1857 #define ADC_JDR1_JDATA_6               (0x0040UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000040 */
1858 #define ADC_JDR1_JDATA_7               (0x0080UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000080 */
1859 #define ADC_JDR1_JDATA_8               (0x0100UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000100 */
1860 #define ADC_JDR1_JDATA_9               (0x0200UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000200 */
1861 #define ADC_JDR1_JDATA_10              (0x0400UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000400 */
1862 #define ADC_JDR1_JDATA_11              (0x0800UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00000800 */
1863 #define ADC_JDR1_JDATA_12              (0x1000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00001000 */
1864 #define ADC_JDR1_JDATA_13              (0x2000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00002000 */
1865 #define ADC_JDR1_JDATA_14              (0x4000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00004000 */
1866 #define ADC_JDR1_JDATA_15              (0x8000UL << ADC_JDR1_JDATA_Pos)        /*!< 0x00008000 */
1867 
1868 /********************  Bit definition for ADC_JDR2 register  ******************/
1869 #define ADC_JDR2_JDATA_Pos             (0U)
1870 #define ADC_JDR2_JDATA_Msk             (0xFFFFUL << ADC_JDR2_JDATA_Pos)        /*!< 0x0000FFFF */
1871 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
1872 #define ADC_JDR2_JDATA_0               (0x0001UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000001 */
1873 #define ADC_JDR2_JDATA_1               (0x0002UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000002 */
1874 #define ADC_JDR2_JDATA_2               (0x0004UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000004 */
1875 #define ADC_JDR2_JDATA_3               (0x0008UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000008 */
1876 #define ADC_JDR2_JDATA_4               (0x0010UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000010 */
1877 #define ADC_JDR2_JDATA_5               (0x0020UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000020 */
1878 #define ADC_JDR2_JDATA_6               (0x0040UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000040 */
1879 #define ADC_JDR2_JDATA_7               (0x0080UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000080 */
1880 #define ADC_JDR2_JDATA_8               (0x0100UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000100 */
1881 #define ADC_JDR2_JDATA_9               (0x0200UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000200 */
1882 #define ADC_JDR2_JDATA_10              (0x0400UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000400 */
1883 #define ADC_JDR2_JDATA_11              (0x0800UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00000800 */
1884 #define ADC_JDR2_JDATA_12              (0x1000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00001000 */
1885 #define ADC_JDR2_JDATA_13              (0x2000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00002000 */
1886 #define ADC_JDR2_JDATA_14              (0x4000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00004000 */
1887 #define ADC_JDR2_JDATA_15              (0x8000UL << ADC_JDR2_JDATA_Pos)        /*!< 0x00008000 */
1888 
1889 /********************  Bit definition for ADC_JDR3 register  ******************/
1890 #define ADC_JDR3_JDATA_Pos             (0U)
1891 #define ADC_JDR3_JDATA_Msk             (0xFFFFUL << ADC_JDR3_JDATA_Pos)        /*!< 0x0000FFFF */
1892 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
1893 #define ADC_JDR3_JDATA_0               (0x0001UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000001 */
1894 #define ADC_JDR3_JDATA_1               (0x0002UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000002 */
1895 #define ADC_JDR3_JDATA_2               (0x0004UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000004 */
1896 #define ADC_JDR3_JDATA_3               (0x0008UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000008 */
1897 #define ADC_JDR3_JDATA_4               (0x0010UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000010 */
1898 #define ADC_JDR3_JDATA_5               (0x0020UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000020 */
1899 #define ADC_JDR3_JDATA_6               (0x0040UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000040 */
1900 #define ADC_JDR3_JDATA_7               (0x0080UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000080 */
1901 #define ADC_JDR3_JDATA_8               (0x0100UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000100 */
1902 #define ADC_JDR3_JDATA_9               (0x0200UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000200 */
1903 #define ADC_JDR3_JDATA_10              (0x0400UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000400 */
1904 #define ADC_JDR3_JDATA_11              (0x0800UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00000800 */
1905 #define ADC_JDR3_JDATA_12              (0x1000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00001000 */
1906 #define ADC_JDR3_JDATA_13              (0x2000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00002000 */
1907 #define ADC_JDR3_JDATA_14              (0x4000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00004000 */
1908 #define ADC_JDR3_JDATA_15              (0x8000UL << ADC_JDR3_JDATA_Pos)        /*!< 0x00008000 */
1909 
1910 /********************  Bit definition for ADC_JDR4 register  ******************/
1911 #define ADC_JDR4_JDATA_Pos             (0U)
1912 #define ADC_JDR4_JDATA_Msk             (0xFFFFUL << ADC_JDR4_JDATA_Pos)        /*!< 0x0000FFFF */
1913 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
1914 #define ADC_JDR4_JDATA_0               (0x0001UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000001 */
1915 #define ADC_JDR4_JDATA_1               (0x0002UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000002 */
1916 #define ADC_JDR4_JDATA_2               (0x0004UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000004 */
1917 #define ADC_JDR4_JDATA_3               (0x0008UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000008 */
1918 #define ADC_JDR4_JDATA_4               (0x0010UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000010 */
1919 #define ADC_JDR4_JDATA_5               (0x0020UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000020 */
1920 #define ADC_JDR4_JDATA_6               (0x0040UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000040 */
1921 #define ADC_JDR4_JDATA_7               (0x0080UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000080 */
1922 #define ADC_JDR4_JDATA_8               (0x0100UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000100 */
1923 #define ADC_JDR4_JDATA_9               (0x0200UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000200 */
1924 #define ADC_JDR4_JDATA_10              (0x0400UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000400 */
1925 #define ADC_JDR4_JDATA_11              (0x0800UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00000800 */
1926 #define ADC_JDR4_JDATA_12              (0x1000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00001000 */
1927 #define ADC_JDR4_JDATA_13              (0x2000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00002000 */
1928 #define ADC_JDR4_JDATA_14              (0x4000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00004000 */
1929 #define ADC_JDR4_JDATA_15              (0x8000UL << ADC_JDR4_JDATA_Pos)        /*!< 0x00008000 */
1930 
1931 /********************  Bit definition for ADC_AWD2CR register  ****************/
1932 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
1933 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
1934 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
1935 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
1936 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
1937 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
1938 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
1939 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
1940 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
1941 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
1942 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
1943 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
1944 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
1945 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
1946 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
1947 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
1948 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
1949 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
1950 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
1951 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
1952 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
1953 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
1954 
1955 /********************  Bit definition for ADC_AWD3CR register  ****************/
1956 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
1957 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
1958 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
1959 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
1960 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
1961 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
1962 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
1963 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
1964 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
1965 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
1966 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
1967 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
1968 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
1969 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
1970 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
1971 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
1972 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
1973 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
1974 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
1975 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
1976 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
1977 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
1978 
1979 /********************  Bit definition for ADC_DIFSEL register  ****************/
1980 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
1981 #define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x0007FFFF */
1982 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
1983 #define ADC_DIFSEL_DIFSEL_0            (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000001 */
1984 #define ADC_DIFSEL_DIFSEL_1            (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000002 */
1985 #define ADC_DIFSEL_DIFSEL_2            (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000004 */
1986 #define ADC_DIFSEL_DIFSEL_3            (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000008 */
1987 #define ADC_DIFSEL_DIFSEL_4            (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000010 */
1988 #define ADC_DIFSEL_DIFSEL_5            (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000020 */
1989 #define ADC_DIFSEL_DIFSEL_6            (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000040 */
1990 #define ADC_DIFSEL_DIFSEL_7            (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000080 */
1991 #define ADC_DIFSEL_DIFSEL_8            (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000100 */
1992 #define ADC_DIFSEL_DIFSEL_9            (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000200 */
1993 #define ADC_DIFSEL_DIFSEL_10           (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000400 */
1994 #define ADC_DIFSEL_DIFSEL_11           (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00000800 */
1995 #define ADC_DIFSEL_DIFSEL_12           (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00001000 */
1996 #define ADC_DIFSEL_DIFSEL_13           (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00002000 */
1997 #define ADC_DIFSEL_DIFSEL_14           (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00004000 */
1998 #define ADC_DIFSEL_DIFSEL_15           (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00008000 */
1999 #define ADC_DIFSEL_DIFSEL_16           (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00010000 */
2000 #define ADC_DIFSEL_DIFSEL_17           (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00020000 */
2001 #define ADC_DIFSEL_DIFSEL_18           (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)    /*!< 0x00040000 */
2002 
2003 /********************  Bit definition for ADC_CALFACT register  ***************/
2004 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
2005 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x0000007F */
2006 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
2007 #define ADC_CALFACT_CALFACT_S_0        (0x01UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000001 */
2008 #define ADC_CALFACT_CALFACT_S_1        (0x02UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000002 */
2009 #define ADC_CALFACT_CALFACT_S_2        (0x04UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000004 */
2010 #define ADC_CALFACT_CALFACT_S_3        (0x08UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000008 */
2011 #define ADC_CALFACT_CALFACT_S_4        (0x10UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000010 */
2012 #define ADC_CALFACT_CALFACT_S_5        (0x20UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000020 */
2013 #define ADC_CALFACT_CALFACT_S_6        (0x40UL << ADC_CALFACT_CALFACT_S_Pos)   /*!< 0x00000040 */
2014 
2015 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
2016 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x007F0000 */
2017 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
2018 #define ADC_CALFACT_CALFACT_D_0        (0x01UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00010000 */
2019 #define ADC_CALFACT_CALFACT_D_1        (0x02UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00020000 */
2020 #define ADC_CALFACT_CALFACT_D_2        (0x04UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00040000 */
2021 #define ADC_CALFACT_CALFACT_D_3        (0x08UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00080000 */
2022 #define ADC_CALFACT_CALFACT_D_4        (0x10UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00100000 */
2023 #define ADC_CALFACT_CALFACT_D_5        (0x20UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00200000 */
2024 #define ADC_CALFACT_CALFACT_D_6        (0x40UL << ADC_CALFACT_CALFACT_D_Pos)   /*!< 0x00400000 */
2025 
2026 /*************************  ADC Common registers  *****************************/
2027 /********************  Bit definition for ADC_CSR register  *******************/
2028 #define ADC_CSR_ADRDY_MST_Pos          (0U)
2029 #define ADC_CSR_ADRDY_MST_Msk          (0x1UL << ADC_CSR_ADRDY_MST_Pos)        /*!< 0x00000001 */
2030 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
2031 #define ADC_CSR_EOSMP_MST_Pos          (1U)
2032 #define ADC_CSR_EOSMP_MST_Msk          (0x1UL << ADC_CSR_EOSMP_MST_Pos)        /*!< 0x00000002 */
2033 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
2034 #define ADC_CSR_EOC_MST_Pos            (2U)
2035 #define ADC_CSR_EOC_MST_Msk            (0x1UL << ADC_CSR_EOC_MST_Pos)          /*!< 0x00000004 */
2036 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
2037 #define ADC_CSR_EOS_MST_Pos            (3U)
2038 #define ADC_CSR_EOS_MST_Msk            (0x1UL << ADC_CSR_EOS_MST_Pos)          /*!< 0x00000008 */
2039 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
2040 #define ADC_CSR_OVR_MST_Pos            (4U)
2041 #define ADC_CSR_OVR_MST_Msk            (0x1UL << ADC_CSR_OVR_MST_Pos)          /*!< 0x00000010 */
2042 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
2043 #define ADC_CSR_JEOC_MST_Pos           (5U)
2044 #define ADC_CSR_JEOC_MST_Msk           (0x1UL << ADC_CSR_JEOC_MST_Pos)         /*!< 0x00000020 */
2045 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
2046 #define ADC_CSR_JEOS_MST_Pos           (6U)
2047 #define ADC_CSR_JEOS_MST_Msk           (0x1UL << ADC_CSR_JEOS_MST_Pos)         /*!< 0x00000040 */
2048 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
2049 #define ADC_CSR_AWD1_MST_Pos           (7U)
2050 #define ADC_CSR_AWD1_MST_Msk           (0x1UL << ADC_CSR_AWD1_MST_Pos)         /*!< 0x00000080 */
2051 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
2052 #define ADC_CSR_AWD2_MST_Pos           (8U)
2053 #define ADC_CSR_AWD2_MST_Msk           (0x1UL << ADC_CSR_AWD2_MST_Pos)         /*!< 0x00000100 */
2054 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
2055 #define ADC_CSR_AWD3_MST_Pos           (9U)
2056 #define ADC_CSR_AWD3_MST_Msk           (0x1UL << ADC_CSR_AWD3_MST_Pos)         /*!< 0x00000200 */
2057 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
2058 #define ADC_CSR_JQOVF_MST_Pos          (10U)
2059 #define ADC_CSR_JQOVF_MST_Msk          (0x1UL << ADC_CSR_JQOVF_MST_Pos)        /*!< 0x00000400 */
2060 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
2061 
2062 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
2063 #define ADC_CSR_ADRDY_SLV_Msk          (0x1UL << ADC_CSR_ADRDY_SLV_Pos)        /*!< 0x00010000 */
2064 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
2065 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
2066 #define ADC_CSR_EOSMP_SLV_Msk          (0x1UL << ADC_CSR_EOSMP_SLV_Pos)        /*!< 0x00020000 */
2067 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
2068 #define ADC_CSR_EOC_SLV_Pos            (18U)
2069 #define ADC_CSR_EOC_SLV_Msk            (0x1UL << ADC_CSR_EOC_SLV_Pos)          /*!< 0x00040000 */
2070 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
2071 #define ADC_CSR_EOS_SLV_Pos            (19U)
2072 #define ADC_CSR_EOS_SLV_Msk            (0x1UL << ADC_CSR_EOS_SLV_Pos)          /*!< 0x00080000 */
2073 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
2074 #define ADC_CSR_OVR_SLV_Pos            (20U)
2075 #define ADC_CSR_OVR_SLV_Msk            (0x1UL << ADC_CSR_OVR_SLV_Pos)          /*!< 0x00100000 */
2076 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
2077 #define ADC_CSR_JEOC_SLV_Pos           (21U)
2078 #define ADC_CSR_JEOC_SLV_Msk           (0x1UL << ADC_CSR_JEOC_SLV_Pos)         /*!< 0x00200000 */
2079 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
2080 #define ADC_CSR_JEOS_SLV_Pos           (22U)
2081 #define ADC_CSR_JEOS_SLV_Msk           (0x1UL << ADC_CSR_JEOS_SLV_Pos)         /*!< 0x00400000 */
2082 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
2083 #define ADC_CSR_AWD1_SLV_Pos           (23U)
2084 #define ADC_CSR_AWD1_SLV_Msk           (0x1UL << ADC_CSR_AWD1_SLV_Pos)         /*!< 0x00800000 */
2085 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2086 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2087 #define ADC_CSR_AWD2_SLV_Msk           (0x1UL << ADC_CSR_AWD2_SLV_Pos)         /*!< 0x01000000 */
2088 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2089 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2090 #define ADC_CSR_AWD3_SLV_Msk           (0x1UL << ADC_CSR_AWD3_SLV_Pos)         /*!< 0x02000000 */
2091 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2092 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2093 #define ADC_CSR_JQOVF_SLV_Msk          (0x1UL << ADC_CSR_JQOVF_SLV_Pos)        /*!< 0x04000000 */
2094 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2095 
2096 /********************  Bit definition for ADC_CCR register  *******************/
2097 #define ADC_CCR_DUAL_Pos               (0U)
2098 #define ADC_CCR_DUAL_Msk               (0x1FUL << ADC_CCR_DUAL_Pos)            /*!< 0x0000001F */
2099 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2100 #define ADC_CCR_DUAL_0                 (0x01UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000001 */
2101 #define ADC_CCR_DUAL_1                 (0x02UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000002 */
2102 #define ADC_CCR_DUAL_2                 (0x04UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000004 */
2103 #define ADC_CCR_DUAL_3                 (0x08UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000008 */
2104 #define ADC_CCR_DUAL_4                 (0x10UL << ADC_CCR_DUAL_Pos)            /*!< 0x00000010 */
2105 
2106 #define ADC_CCR_DELAY_Pos              (8U)
2107 #define ADC_CCR_DELAY_Msk              (0xFUL << ADC_CCR_DELAY_Pos)            /*!< 0x00000F00 */
2108 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2109 #define ADC_CCR_DELAY_0                (0x1UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000100 */
2110 #define ADC_CCR_DELAY_1                (0x2UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000200 */
2111 #define ADC_CCR_DELAY_2                (0x4UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000400 */
2112 #define ADC_CCR_DELAY_3                (0x8UL << ADC_CCR_DELAY_Pos)            /*!< 0x00000800 */
2113 
2114 #define ADC_CCR_DMACFG_Pos             (13U)
2115 #define ADC_CCR_DMACFG_Msk             (0x1UL << ADC_CCR_DMACFG_Pos)           /*!< 0x00002000 */
2116 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2117 
2118 #define ADC_CCR_MDMA_Pos               (14U)
2119 #define ADC_CCR_MDMA_Msk               (0x3UL << ADC_CCR_MDMA_Pos)             /*!< 0x0000C000 */
2120 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2121 #define ADC_CCR_MDMA_0                 (0x1UL << ADC_CCR_MDMA_Pos)             /*!< 0x00004000 */
2122 #define ADC_CCR_MDMA_1                 (0x2UL << ADC_CCR_MDMA_Pos)             /*!< 0x00008000 */
2123 
2124 #define ADC_CCR_CKMODE_Pos             (16U)
2125 #define ADC_CCR_CKMODE_Msk             (0x3UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00030000 */
2126 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2127 #define ADC_CCR_CKMODE_0               (0x1UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00010000 */
2128 #define ADC_CCR_CKMODE_1               (0x2UL << ADC_CCR_CKMODE_Pos)           /*!< 0x00020000 */
2129 
2130 #define ADC_CCR_PRESC_Pos              (18U)
2131 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
2132 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
2133 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
2134 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
2135 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
2136 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
2137 
2138 #define ADC_CCR_VREFEN_Pos             (22U)
2139 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
2140 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2141 #define ADC_CCR_TSEN_Pos               (23U)
2142 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
2143 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
2144 #define ADC_CCR_VBATEN_Pos             (24U)
2145 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
2146 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
2147 
2148 /********************  Bit definition for ADC_CDR register  *******************/
2149 #define ADC_CDR_RDATA_MST_Pos          (0U)
2150 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x0000FFFF */
2151 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2152 #define ADC_CDR_RDATA_MST_0            (0x0001UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000001 */
2153 #define ADC_CDR_RDATA_MST_1            (0x0002UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000002 */
2154 #define ADC_CDR_RDATA_MST_2            (0x0004UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000004 */
2155 #define ADC_CDR_RDATA_MST_3            (0x0008UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000008 */
2156 #define ADC_CDR_RDATA_MST_4            (0x0010UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000010 */
2157 #define ADC_CDR_RDATA_MST_5            (0x0020UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000020 */
2158 #define ADC_CDR_RDATA_MST_6            (0x0040UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000040 */
2159 #define ADC_CDR_RDATA_MST_7            (0x0080UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000080 */
2160 #define ADC_CDR_RDATA_MST_8            (0x0100UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000100 */
2161 #define ADC_CDR_RDATA_MST_9            (0x0200UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000200 */
2162 #define ADC_CDR_RDATA_MST_10           (0x0400UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000400 */
2163 #define ADC_CDR_RDATA_MST_11           (0x0800UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00000800 */
2164 #define ADC_CDR_RDATA_MST_12           (0x1000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00001000 */
2165 #define ADC_CDR_RDATA_MST_13           (0x2000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00002000 */
2166 #define ADC_CDR_RDATA_MST_14           (0x4000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00004000 */
2167 #define ADC_CDR_RDATA_MST_15           (0x8000UL << ADC_CDR_RDATA_MST_Pos)     /*!< 0x00008000 */
2168 
2169 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2170 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0xFFFF0000 */
2171 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2172 #define ADC_CDR_RDATA_SLV_0            (0x0001UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00010000 */
2173 #define ADC_CDR_RDATA_SLV_1            (0x0002UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00020000 */
2174 #define ADC_CDR_RDATA_SLV_2            (0x0004UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00040000 */
2175 #define ADC_CDR_RDATA_SLV_3            (0x0008UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00080000 */
2176 #define ADC_CDR_RDATA_SLV_4            (0x0010UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00100000 */
2177 #define ADC_CDR_RDATA_SLV_5            (0x0020UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00200000 */
2178 #define ADC_CDR_RDATA_SLV_6            (0x0040UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00400000 */
2179 #define ADC_CDR_RDATA_SLV_7            (0x0080UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x00800000 */
2180 #define ADC_CDR_RDATA_SLV_8            (0x0100UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x01000000 */
2181 #define ADC_CDR_RDATA_SLV_9            (0x0200UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x02000000 */
2182 #define ADC_CDR_RDATA_SLV_10           (0x0400UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x04000000 */
2183 #define ADC_CDR_RDATA_SLV_11           (0x0800UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x08000000 */
2184 #define ADC_CDR_RDATA_SLV_12           (0x1000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x10000000 */
2185 #define ADC_CDR_RDATA_SLV_13           (0x2000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x20000000 */
2186 #define ADC_CDR_RDATA_SLV_14           (0x4000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x40000000 */
2187 #define ADC_CDR_RDATA_SLV_15           (0x8000UL << ADC_CDR_RDATA_SLV_Pos)     /*!< 0x80000000 */
2188 
2189 
2190 /******************************************************************************/
2191 /*                                                                            */
2192 /*                          CRC calculation unit                              */
2193 /*                                                                            */
2194 /******************************************************************************/
2195 /*******************  Bit definition for CRC_DR register  *********************/
2196 #define CRC_DR_DR_Pos            (0U)
2197 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
2198 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
2199 
2200 /*******************  Bit definition for CRC_IDR register  ********************/
2201 #define CRC_IDR_IDR_Pos          (0U)
2202 #define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */
2203 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */
2204 
2205 /********************  Bit definition for CRC_CR register  ********************/
2206 #define CRC_CR_RESET_Pos         (0U)
2207 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
2208 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
2209 #define CRC_CR_POLYSIZE_Pos      (3U)
2210 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
2211 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
2212 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
2213 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
2214 #define CRC_CR_REV_IN_Pos        (5U)
2215 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
2216 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
2217 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
2218 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
2219 #define CRC_CR_REV_OUT_Pos       (7U)
2220 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
2221 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
2222 
2223 /*******************  Bit definition for CRC_INIT register  *******************/
2224 #define CRC_INIT_INIT_Pos        (0U)
2225 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
2226 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
2227 
2228 /*******************  Bit definition for CRC_POL register  ********************/
2229 #define CRC_POL_POL_Pos          (0U)
2230 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
2231 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
2232 
2233 /******************************************************************************/
2234 /*                                                                            */
2235 /*                          CRS Clock Recovery System                         */
2236 /******************************************************************************/
2237 
2238 /*******************  Bit definition for CRS_CR register  *********************/
2239 #define CRS_CR_SYNCOKIE_Pos       (0U)
2240 #define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
2241 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
2242 #define CRS_CR_SYNCWARNIE_Pos     (1U)
2243 #define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
2244 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
2245 #define CRS_CR_ERRIE_Pos          (2U)
2246 #define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
2247 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
2248 #define CRS_CR_ESYNCIE_Pos        (3U)
2249 #define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
2250 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
2251 #define CRS_CR_CEN_Pos            (5U)
2252 #define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
2253 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
2254 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
2255 #define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
2256 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
2257 #define CRS_CR_SWSYNC_Pos         (7U)
2258 #define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
2259 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
2260 #define CRS_CR_TRIM_Pos           (8U)
2261 #define CRS_CR_TRIM_Msk           (0x7FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00007F00 */
2262 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< TRIM[6:0] HSI48 oscillator smooth trimming */
2263 #define CRS_CR_TRIM_0             (0x01UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000100 */
2264 #define CRS_CR_TRIM_1             (0x02UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000200 */
2265 #define CRS_CR_TRIM_2             (0x04UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000400 */
2266 #define CRS_CR_TRIM_3             (0x08UL << CRS_CR_TRIM_Pos)                  /*!< 0x00000800 */
2267 #define CRS_CR_TRIM_4             (0x10UL << CRS_CR_TRIM_Pos)                  /*!< 0x00001000 */
2268 #define CRS_CR_TRIM_5             (0x20UL << CRS_CR_TRIM_Pos)                  /*!< 0x00002000 */
2269 #define CRS_CR_TRIM_6             (0x40UL << CRS_CR_TRIM_Pos)                  /*!< 0x00004000 */
2270 
2271 /*******************  Bit definition for CRS_CFGR register  *********************/
2272 #define CRS_CFGR_RELOAD_Pos       (0U)
2273 #define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
2274 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
2275 #define CRS_CFGR_FELIM_Pos        (16U)
2276 #define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
2277 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
2278 
2279 #define CRS_CFGR_SYNCDIV_Pos      (24U)
2280 #define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
2281 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
2282 #define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x01000000 */
2283 #define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x02000000 */
2284 #define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x04000000 */
2285 
2286 #define CRS_CFGR_SYNCSRC_Pos      (28U)
2287 #define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
2288 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
2289 #define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x10000000 */
2290 #define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x20000000 */
2291 
2292 #define CRS_CFGR_SYNCPOL_Pos      (31U)
2293 #define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
2294 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
2295 
2296 /*******************  Bit definition for CRS_ISR register  *********************/
2297 #define CRS_ISR_SYNCOKF_Pos       (0U)
2298 #define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
2299 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
2300 #define CRS_ISR_SYNCWARNF_Pos     (1U)
2301 #define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
2302 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
2303 #define CRS_ISR_ERRF_Pos          (2U)
2304 #define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
2305 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
2306 #define CRS_ISR_ESYNCF_Pos        (3U)
2307 #define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
2308 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
2309 #define CRS_ISR_SYNCERR_Pos       (8U)
2310 #define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
2311 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
2312 #define CRS_ISR_SYNCMISS_Pos      (9U)
2313 #define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
2314 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
2315 #define CRS_ISR_TRIMOVF_Pos       (10U)
2316 #define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
2317 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
2318 #define CRS_ISR_FEDIR_Pos         (15U)
2319 #define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
2320 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
2321 #define CRS_ISR_FECAP_Pos         (16U)
2322 #define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
2323 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
2324 
2325 /*******************  Bit definition for CRS_ICR register  *********************/
2326 #define CRS_ICR_SYNCOKC_Pos       (0U)
2327 #define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
2328 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
2329 #define CRS_ICR_SYNCWARNC_Pos     (1U)
2330 #define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
2331 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
2332 #define CRS_ICR_ERRC_Pos          (2U)
2333 #define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
2334 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
2335 #define CRS_ICR_ESYNCC_Pos        (3U)
2336 #define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
2337 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
2338 
2339 
2340 /******************************************************************************/
2341 /*                                                                            */
2342 /*                           DMA Controller (DMA)                             */
2343 /*                                                                            */
2344 /******************************************************************************/
2345 
2346 /*******************  Bit definition for DMA_ISR register  ********************/
2347 #define DMA_ISR_GIF1_Pos       (0U)
2348 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
2349 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
2350 #define DMA_ISR_TCIF1_Pos      (1U)
2351 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
2352 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
2353 #define DMA_ISR_HTIF1_Pos      (2U)
2354 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
2355 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
2356 #define DMA_ISR_TEIF1_Pos      (3U)
2357 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
2358 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
2359 #define DMA_ISR_GIF2_Pos       (4U)
2360 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
2361 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
2362 #define DMA_ISR_TCIF2_Pos      (5U)
2363 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
2364 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
2365 #define DMA_ISR_HTIF2_Pos      (6U)
2366 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
2367 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
2368 #define DMA_ISR_TEIF2_Pos      (7U)
2369 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
2370 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
2371 #define DMA_ISR_GIF3_Pos       (8U)
2372 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
2373 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
2374 #define DMA_ISR_TCIF3_Pos      (9U)
2375 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
2376 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
2377 #define DMA_ISR_HTIF3_Pos      (10U)
2378 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
2379 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
2380 #define DMA_ISR_TEIF3_Pos      (11U)
2381 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
2382 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
2383 #define DMA_ISR_GIF4_Pos       (12U)
2384 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
2385 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
2386 #define DMA_ISR_TCIF4_Pos      (13U)
2387 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
2388 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
2389 #define DMA_ISR_HTIF4_Pos      (14U)
2390 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
2391 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
2392 #define DMA_ISR_TEIF4_Pos      (15U)
2393 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
2394 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
2395 #define DMA_ISR_GIF5_Pos       (16U)
2396 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
2397 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
2398 #define DMA_ISR_TCIF5_Pos      (17U)
2399 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
2400 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
2401 #define DMA_ISR_HTIF5_Pos      (18U)
2402 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
2403 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
2404 #define DMA_ISR_TEIF5_Pos      (19U)
2405 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
2406 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
2407 #define DMA_ISR_GIF6_Pos       (20U)
2408 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
2409 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
2410 #define DMA_ISR_TCIF6_Pos      (21U)
2411 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
2412 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
2413 #define DMA_ISR_HTIF6_Pos      (22U)
2414 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
2415 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
2416 #define DMA_ISR_TEIF6_Pos      (23U)
2417 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
2418 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
2419 #define DMA_ISR_GIF7_Pos       (24U)
2420 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
2421 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
2422 #define DMA_ISR_TCIF7_Pos      (25U)
2423 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
2424 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
2425 #define DMA_ISR_HTIF7_Pos      (26U)
2426 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
2427 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
2428 #define DMA_ISR_TEIF7_Pos      (27U)
2429 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
2430 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
2431 
2432 /*******************  Bit definition for DMA_IFCR register  *******************/
2433 #define DMA_IFCR_CGIF1_Pos     (0U)
2434 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
2435 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
2436 #define DMA_IFCR_CTCIF1_Pos    (1U)
2437 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
2438 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
2439 #define DMA_IFCR_CHTIF1_Pos    (2U)
2440 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
2441 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
2442 #define DMA_IFCR_CTEIF1_Pos    (3U)
2443 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
2444 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
2445 #define DMA_IFCR_CGIF2_Pos     (4U)
2446 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
2447 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
2448 #define DMA_IFCR_CTCIF2_Pos    (5U)
2449 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
2450 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
2451 #define DMA_IFCR_CHTIF2_Pos    (6U)
2452 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
2453 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
2454 #define DMA_IFCR_CTEIF2_Pos    (7U)
2455 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
2456 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
2457 #define DMA_IFCR_CGIF3_Pos     (8U)
2458 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
2459 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
2460 #define DMA_IFCR_CTCIF3_Pos    (9U)
2461 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
2462 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
2463 #define DMA_IFCR_CHTIF3_Pos    (10U)
2464 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
2465 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
2466 #define DMA_IFCR_CTEIF3_Pos    (11U)
2467 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
2468 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
2469 #define DMA_IFCR_CGIF4_Pos     (12U)
2470 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
2471 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
2472 #define DMA_IFCR_CTCIF4_Pos    (13U)
2473 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
2474 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
2475 #define DMA_IFCR_CHTIF4_Pos    (14U)
2476 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
2477 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
2478 #define DMA_IFCR_CTEIF4_Pos    (15U)
2479 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
2480 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
2481 #define DMA_IFCR_CGIF5_Pos     (16U)
2482 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
2483 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
2484 #define DMA_IFCR_CTCIF5_Pos    (17U)
2485 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
2486 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
2487 #define DMA_IFCR_CHTIF5_Pos    (18U)
2488 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
2489 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
2490 #define DMA_IFCR_CTEIF5_Pos    (19U)
2491 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
2492 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
2493 #define DMA_IFCR_CGIF6_Pos     (20U)
2494 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
2495 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
2496 #define DMA_IFCR_CTCIF6_Pos    (21U)
2497 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
2498 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
2499 #define DMA_IFCR_CHTIF6_Pos    (22U)
2500 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
2501 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
2502 #define DMA_IFCR_CTEIF6_Pos    (23U)
2503 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
2504 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
2505 #define DMA_IFCR_CGIF7_Pos     (24U)
2506 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
2507 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
2508 #define DMA_IFCR_CTCIF7_Pos    (25U)
2509 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
2510 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
2511 #define DMA_IFCR_CHTIF7_Pos    (26U)
2512 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
2513 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
2514 #define DMA_IFCR_CTEIF7_Pos    (27U)
2515 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
2516 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
2517 
2518 /*******************  Bit definition for DMA_CCR register  ********************/
2519 #define DMA_CCR_EN_Pos         (0U)
2520 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
2521 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
2522 #define DMA_CCR_TCIE_Pos       (1U)
2523 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
2524 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
2525 #define DMA_CCR_HTIE_Pos       (2U)
2526 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
2527 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
2528 #define DMA_CCR_TEIE_Pos       (3U)
2529 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
2530 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
2531 #define DMA_CCR_DIR_Pos        (4U)
2532 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
2533 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
2534 #define DMA_CCR_CIRC_Pos       (5U)
2535 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
2536 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
2537 #define DMA_CCR_PINC_Pos       (6U)
2538 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
2539 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
2540 #define DMA_CCR_MINC_Pos       (7U)
2541 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
2542 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
2543 
2544 #define DMA_CCR_PSIZE_Pos      (8U)
2545 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
2546 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
2547 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
2548 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
2549 
2550 #define DMA_CCR_MSIZE_Pos      (10U)
2551 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
2552 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
2553 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
2554 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
2555 
2556 #define DMA_CCR_PL_Pos         (12U)
2557 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
2558 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
2559 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
2560 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
2561 
2562 #define DMA_CCR_MEM2MEM_Pos    (14U)
2563 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
2564 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
2565 
2566 /******************  Bit definition for DMA_CNDTR register  *******************/
2567 #define DMA_CNDTR_NDT_Pos      (0U)
2568 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
2569 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
2570 
2571 /******************  Bit definition for DMA_CPAR register  ********************/
2572 #define DMA_CPAR_PA_Pos        (0U)
2573 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
2574 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
2575 
2576 /******************  Bit definition for DMA_CMAR register  ********************/
2577 #define DMA_CMAR_MA_Pos        (0U)
2578 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
2579 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
2580 
2581 
2582 /*******************  Bit definition for DMA_CSELR register  *******************/
2583 #define DMA_CSELR_C1S_Pos      (0U)
2584 #define DMA_CSELR_C1S_Msk      (0xFUL << DMA_CSELR_C1S_Pos)                    /*!< 0x0000000F */
2585 #define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
2586 #define DMA_CSELR_C2S_Pos      (4U)
2587 #define DMA_CSELR_C2S_Msk      (0xFUL << DMA_CSELR_C2S_Pos)                    /*!< 0x000000F0 */
2588 #define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
2589 #define DMA_CSELR_C3S_Pos      (8U)
2590 #define DMA_CSELR_C3S_Msk      (0xFUL << DMA_CSELR_C3S_Pos)                    /*!< 0x00000F00 */
2591 #define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
2592 #define DMA_CSELR_C4S_Pos      (12U)
2593 #define DMA_CSELR_C4S_Msk      (0xFUL << DMA_CSELR_C4S_Pos)                    /*!< 0x0000F000 */
2594 #define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
2595 #define DMA_CSELR_C5S_Pos      (16U)
2596 #define DMA_CSELR_C5S_Msk      (0xFUL << DMA_CSELR_C5S_Pos)                    /*!< 0x000F0000 */
2597 #define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
2598 #define DMA_CSELR_C6S_Pos      (20U)
2599 #define DMA_CSELR_C6S_Msk      (0xFUL << DMA_CSELR_C6S_Pos)                    /*!< 0x00F00000 */
2600 #define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
2601 #define DMA_CSELR_C7S_Pos      (24U)
2602 #define DMA_CSELR_C7S_Msk      (0xFUL << DMA_CSELR_C7S_Pos)                    /*!< 0x0F000000 */
2603 #define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
2604 
2605 /******************************************************************************/
2606 /*                                                                            */
2607 /*                    External Interrupt/Event Controller                     */
2608 /*                                                                            */
2609 /******************************************************************************/
2610 /*******************  Bit definition for EXTI_IMR1 register  ******************/
2611 #define EXTI_IMR1_IM0_Pos        (0U)
2612 #define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
2613 #define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
2614 #define EXTI_IMR1_IM1_Pos        (1U)
2615 #define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
2616 #define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
2617 #define EXTI_IMR1_IM2_Pos        (2U)
2618 #define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
2619 #define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
2620 #define EXTI_IMR1_IM3_Pos        (3U)
2621 #define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
2622 #define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
2623 #define EXTI_IMR1_IM4_Pos        (4U)
2624 #define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
2625 #define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
2626 #define EXTI_IMR1_IM5_Pos        (5U)
2627 #define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
2628 #define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
2629 #define EXTI_IMR1_IM6_Pos        (6U)
2630 #define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
2631 #define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
2632 #define EXTI_IMR1_IM7_Pos        (7U)
2633 #define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
2634 #define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
2635 #define EXTI_IMR1_IM8_Pos        (8U)
2636 #define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
2637 #define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
2638 #define EXTI_IMR1_IM9_Pos        (9U)
2639 #define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
2640 #define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
2641 #define EXTI_IMR1_IM10_Pos       (10U)
2642 #define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
2643 #define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
2644 #define EXTI_IMR1_IM11_Pos       (11U)
2645 #define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
2646 #define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
2647 #define EXTI_IMR1_IM12_Pos       (12U)
2648 #define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
2649 #define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
2650 #define EXTI_IMR1_IM13_Pos       (13U)
2651 #define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
2652 #define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
2653 #define EXTI_IMR1_IM14_Pos       (14U)
2654 #define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
2655 #define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
2656 #define EXTI_IMR1_IM15_Pos       (15U)
2657 #define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
2658 #define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
2659 #define EXTI_IMR1_IM16_Pos       (16U)
2660 #define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
2661 #define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
2662 #define EXTI_IMR1_IM17_Pos       (17U)
2663 #define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
2664 #define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
2665 #define EXTI_IMR1_IM18_Pos       (18U)
2666 #define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
2667 #define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
2668 #define EXTI_IMR1_IM19_Pos       (19U)
2669 #define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
2670 #define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
2671 #define EXTI_IMR1_IM20_Pos       (20U)
2672 #define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
2673 #define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
2674 #define EXTI_IMR1_IM21_Pos       (21U)
2675 #define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
2676 #define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
2677 #define EXTI_IMR1_IM23_Pos       (23U)
2678 #define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
2679 #define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
2680 #define EXTI_IMR1_IM24_Pos       (24U)
2681 #define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
2682 #define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
2683 #define EXTI_IMR1_IM25_Pos       (25U)
2684 #define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
2685 #define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
2686 #define EXTI_IMR1_IM26_Pos       (26U)
2687 #define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
2688 #define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
2689 #define EXTI_IMR1_IM27_Pos       (27U)
2690 #define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
2691 #define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
2692 #define EXTI_IMR1_IM28_Pos       (28U)
2693 #define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
2694 #define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
2695 #define EXTI_IMR1_IM29_Pos       (29U)
2696 #define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
2697 #define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
2698 #define EXTI_IMR1_IM30_Pos       (30U)
2699 #define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
2700 #define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
2701 #define EXTI_IMR1_IM31_Pos       (31U)
2702 #define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */
2703 #define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
2704 #define EXTI_IMR1_IM_Pos         (0U)
2705 #define EXTI_IMR1_IM_Msk         (0x9FFFFFFFUL << EXTI_IMR1_IM_Pos)            /*!< 0x9FFFFFFF */
2706 #define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
2707 
2708 /*******************  Bit definition for EXTI_EMR1 register  ******************/
2709 #define EXTI_EMR1_EM0_Pos        (0U)
2710 #define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
2711 #define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
2712 #define EXTI_EMR1_EM1_Pos        (1U)
2713 #define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
2714 #define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
2715 #define EXTI_EMR1_EM2_Pos        (2U)
2716 #define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
2717 #define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
2718 #define EXTI_EMR1_EM3_Pos        (3U)
2719 #define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
2720 #define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
2721 #define EXTI_EMR1_EM4_Pos        (4U)
2722 #define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
2723 #define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
2724 #define EXTI_EMR1_EM5_Pos        (5U)
2725 #define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
2726 #define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
2727 #define EXTI_EMR1_EM6_Pos        (6U)
2728 #define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
2729 #define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
2730 #define EXTI_EMR1_EM7_Pos        (7U)
2731 #define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
2732 #define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
2733 #define EXTI_EMR1_EM8_Pos        (8U)
2734 #define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
2735 #define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
2736 #define EXTI_EMR1_EM9_Pos        (9U)
2737 #define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
2738 #define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
2739 #define EXTI_EMR1_EM10_Pos       (10U)
2740 #define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
2741 #define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
2742 #define EXTI_EMR1_EM11_Pos       (11U)
2743 #define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
2744 #define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
2745 #define EXTI_EMR1_EM12_Pos       (12U)
2746 #define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
2747 #define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
2748 #define EXTI_EMR1_EM13_Pos       (13U)
2749 #define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
2750 #define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
2751 #define EXTI_EMR1_EM14_Pos       (14U)
2752 #define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
2753 #define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
2754 #define EXTI_EMR1_EM15_Pos       (15U)
2755 #define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
2756 #define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
2757 #define EXTI_EMR1_EM16_Pos       (16U)
2758 #define EXTI_EMR1_EM16_Msk       (0x1UL << EXTI_EMR1_EM16_Pos)                 /*!< 0x00010000 */
2759 #define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
2760 #define EXTI_EMR1_EM17_Pos       (17U)
2761 #define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
2762 #define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
2763 #define EXTI_EMR1_EM18_Pos       (18U)
2764 #define EXTI_EMR1_EM18_Msk       (0x1UL << EXTI_EMR1_EM18_Pos)                 /*!< 0x00040000 */
2765 #define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
2766 #define EXTI_EMR1_EM19_Pos       (19U)
2767 #define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
2768 #define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
2769 #define EXTI_EMR1_EM20_Pos       (20U)
2770 #define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
2771 #define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
2772 #define EXTI_EMR1_EM21_Pos       (21U)
2773 #define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
2774 #define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
2775 #define EXTI_EMR1_EM23_Pos       (23U)
2776 #define EXTI_EMR1_EM23_Msk       (0x1UL << EXTI_EMR1_EM23_Pos)                 /*!< 0x00800000 */
2777 #define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
2778 #define EXTI_EMR1_EM24_Pos       (24U)
2779 #define EXTI_EMR1_EM24_Msk       (0x1UL << EXTI_EMR1_EM24_Pos)                 /*!< 0x01000000 */
2780 #define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
2781 #define EXTI_EMR1_EM25_Pos       (25U)
2782 #define EXTI_EMR1_EM25_Msk       (0x1UL << EXTI_EMR1_EM25_Pos)                 /*!< 0x02000000 */
2783 #define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
2784 #define EXTI_EMR1_EM26_Pos       (26U)
2785 #define EXTI_EMR1_EM26_Msk       (0x1UL << EXTI_EMR1_EM26_Pos)                 /*!< 0x04000000 */
2786 #define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
2787 #define EXTI_EMR1_EM27_Pos       (27U)
2788 #define EXTI_EMR1_EM27_Msk       (0x1UL << EXTI_EMR1_EM27_Pos)                 /*!< 0x08000000 */
2789 #define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
2790 #define EXTI_EMR1_EM28_Pos       (28U)
2791 #define EXTI_EMR1_EM28_Msk       (0x1UL << EXTI_EMR1_EM28_Pos)                 /*!< 0x10000000 */
2792 #define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
2793 #define EXTI_EMR1_EM31_Pos       (31U)
2794 #define EXTI_EMR1_EM31_Msk       (0x1UL << EXTI_EMR1_EM31_Pos)                 /*!< 0x80000000 */
2795 #define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
2796 
2797 /******************  Bit definition for EXTI_RTSR1 register  ******************/
2798 #define EXTI_RTSR1_RT0_Pos       (0U)
2799 #define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
2800 #define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
2801 #define EXTI_RTSR1_RT1_Pos       (1U)
2802 #define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
2803 #define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
2804 #define EXTI_RTSR1_RT2_Pos       (2U)
2805 #define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
2806 #define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
2807 #define EXTI_RTSR1_RT3_Pos       (3U)
2808 #define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
2809 #define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
2810 #define EXTI_RTSR1_RT4_Pos       (4U)
2811 #define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
2812 #define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
2813 #define EXTI_RTSR1_RT5_Pos       (5U)
2814 #define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
2815 #define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
2816 #define EXTI_RTSR1_RT6_Pos       (6U)
2817 #define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
2818 #define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
2819 #define EXTI_RTSR1_RT7_Pos       (7U)
2820 #define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
2821 #define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
2822 #define EXTI_RTSR1_RT8_Pos       (8U)
2823 #define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
2824 #define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
2825 #define EXTI_RTSR1_RT9_Pos       (9U)
2826 #define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
2827 #define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
2828 #define EXTI_RTSR1_RT10_Pos      (10U)
2829 #define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
2830 #define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
2831 #define EXTI_RTSR1_RT11_Pos      (11U)
2832 #define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
2833 #define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
2834 #define EXTI_RTSR1_RT12_Pos      (12U)
2835 #define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
2836 #define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
2837 #define EXTI_RTSR1_RT13_Pos      (13U)
2838 #define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
2839 #define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
2840 #define EXTI_RTSR1_RT14_Pos      (14U)
2841 #define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
2842 #define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
2843 #define EXTI_RTSR1_RT15_Pos      (15U)
2844 #define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
2845 #define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
2846 #define EXTI_RTSR1_RT16_Pos      (16U)
2847 #define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
2848 #define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
2849 #define EXTI_RTSR1_RT18_Pos      (18U)
2850 #define EXTI_RTSR1_RT18_Msk      (0x1UL << EXTI_RTSR1_RT18_Pos)                /*!< 0x00040000 */
2851 #define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
2852 #define EXTI_RTSR1_RT19_Pos      (19U)
2853 #define EXTI_RTSR1_RT19_Msk      (0x1UL << EXTI_RTSR1_RT19_Pos)                /*!< 0x00080000 */
2854 #define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
2855 #define EXTI_RTSR1_RT20_Pos      (20U)
2856 #define EXTI_RTSR1_RT20_Msk      (0x1UL << EXTI_RTSR1_RT20_Pos)                /*!< 0x00100000 */
2857 #define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
2858 #define EXTI_RTSR1_RT21_Pos      (21U)
2859 #define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
2860 #define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
2861 
2862 /******************  Bit definition for EXTI_FTSR1 register  ******************/
2863 #define EXTI_FTSR1_FT0_Pos       (0U)
2864 #define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
2865 #define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
2866 #define EXTI_FTSR1_FT1_Pos       (1U)
2867 #define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
2868 #define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
2869 #define EXTI_FTSR1_FT2_Pos       (2U)
2870 #define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
2871 #define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
2872 #define EXTI_FTSR1_FT3_Pos       (3U)
2873 #define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
2874 #define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
2875 #define EXTI_FTSR1_FT4_Pos       (4U)
2876 #define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
2877 #define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
2878 #define EXTI_FTSR1_FT5_Pos       (5U)
2879 #define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
2880 #define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
2881 #define EXTI_FTSR1_FT6_Pos       (6U)
2882 #define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
2883 #define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
2884 #define EXTI_FTSR1_FT7_Pos       (7U)
2885 #define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
2886 #define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
2887 #define EXTI_FTSR1_FT8_Pos       (8U)
2888 #define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
2889 #define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
2890 #define EXTI_FTSR1_FT9_Pos       (9U)
2891 #define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
2892 #define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
2893 #define EXTI_FTSR1_FT10_Pos      (10U)
2894 #define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
2895 #define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
2896 #define EXTI_FTSR1_FT11_Pos      (11U)
2897 #define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
2898 #define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
2899 #define EXTI_FTSR1_FT12_Pos      (12U)
2900 #define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
2901 #define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
2902 #define EXTI_FTSR1_FT13_Pos      (13U)
2903 #define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
2904 #define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
2905 #define EXTI_FTSR1_FT14_Pos      (14U)
2906 #define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
2907 #define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
2908 #define EXTI_FTSR1_FT15_Pos      (15U)
2909 #define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
2910 #define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
2911 #define EXTI_FTSR1_FT16_Pos      (16U)
2912 #define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
2913 #define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
2914 #define EXTI_FTSR1_FT18_Pos      (18U)
2915 #define EXTI_FTSR1_FT18_Msk      (0x1UL << EXTI_FTSR1_FT18_Pos)                /*!< 0x00040000 */
2916 #define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
2917 #define EXTI_FTSR1_FT19_Pos      (19U)
2918 #define EXTI_FTSR1_FT19_Msk      (0x1UL << EXTI_FTSR1_FT19_Pos)                /*!< 0x00080000 */
2919 #define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
2920 #define EXTI_FTSR1_FT20_Pos      (20U)
2921 #define EXTI_FTSR1_FT20_Msk      (0x1UL << EXTI_FTSR1_FT20_Pos)                /*!< 0x00100000 */
2922 #define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
2923 #define EXTI_FTSR1_FT21_Pos      (21U)
2924 #define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
2925 #define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
2926 
2927 /******************  Bit definition for EXTI_SWIER1 register  *****************/
2928 #define EXTI_SWIER1_SWI0_Pos     (0U)
2929 #define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
2930 #define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
2931 #define EXTI_SWIER1_SWI1_Pos     (1U)
2932 #define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
2933 #define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
2934 #define EXTI_SWIER1_SWI2_Pos     (2U)
2935 #define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
2936 #define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
2937 #define EXTI_SWIER1_SWI3_Pos     (3U)
2938 #define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
2939 #define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
2940 #define EXTI_SWIER1_SWI4_Pos     (4U)
2941 #define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
2942 #define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
2943 #define EXTI_SWIER1_SWI5_Pos     (5U)
2944 #define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
2945 #define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
2946 #define EXTI_SWIER1_SWI6_Pos     (6U)
2947 #define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
2948 #define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
2949 #define EXTI_SWIER1_SWI7_Pos     (7U)
2950 #define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
2951 #define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
2952 #define EXTI_SWIER1_SWI8_Pos     (8U)
2953 #define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
2954 #define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
2955 #define EXTI_SWIER1_SWI9_Pos     (9U)
2956 #define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
2957 #define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
2958 #define EXTI_SWIER1_SWI10_Pos    (10U)
2959 #define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
2960 #define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
2961 #define EXTI_SWIER1_SWI11_Pos    (11U)
2962 #define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
2963 #define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
2964 #define EXTI_SWIER1_SWI12_Pos    (12U)
2965 #define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
2966 #define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
2967 #define EXTI_SWIER1_SWI13_Pos    (13U)
2968 #define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
2969 #define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
2970 #define EXTI_SWIER1_SWI14_Pos    (14U)
2971 #define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
2972 #define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
2973 #define EXTI_SWIER1_SWI15_Pos    (15U)
2974 #define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
2975 #define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
2976 #define EXTI_SWIER1_SWI16_Pos    (16U)
2977 #define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
2978 #define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
2979 #define EXTI_SWIER1_SWI18_Pos    (18U)
2980 #define EXTI_SWIER1_SWI18_Msk    (0x1UL << EXTI_SWIER1_SWI18_Pos)              /*!< 0x00040000 */
2981 #define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */
2982 #define EXTI_SWIER1_SWI19_Pos    (19U)
2983 #define EXTI_SWIER1_SWI19_Msk    (0x1UL << EXTI_SWIER1_SWI19_Pos)              /*!< 0x00080000 */
2984 #define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
2985 #define EXTI_SWIER1_SWI20_Pos    (20U)
2986 #define EXTI_SWIER1_SWI20_Msk    (0x1UL << EXTI_SWIER1_SWI20_Pos)              /*!< 0x00100000 */
2987 #define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
2988 #define EXTI_SWIER1_SWI21_Pos    (21U)
2989 #define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
2990 #define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
2991 
2992 /*******************  Bit definition for EXTI_PR1 register  *******************/
2993 #define EXTI_PR1_PIF0_Pos        (0U)
2994 #define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
2995 #define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
2996 #define EXTI_PR1_PIF1_Pos        (1U)
2997 #define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
2998 #define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
2999 #define EXTI_PR1_PIF2_Pos        (2U)
3000 #define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
3001 #define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
3002 #define EXTI_PR1_PIF3_Pos        (3U)
3003 #define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
3004 #define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
3005 #define EXTI_PR1_PIF4_Pos        (4U)
3006 #define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
3007 #define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
3008 #define EXTI_PR1_PIF5_Pos        (5U)
3009 #define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
3010 #define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
3011 #define EXTI_PR1_PIF6_Pos        (6U)
3012 #define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
3013 #define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
3014 #define EXTI_PR1_PIF7_Pos        (7U)
3015 #define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
3016 #define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
3017 #define EXTI_PR1_PIF8_Pos        (8U)
3018 #define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
3019 #define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
3020 #define EXTI_PR1_PIF9_Pos        (9U)
3021 #define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
3022 #define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
3023 #define EXTI_PR1_PIF10_Pos       (10U)
3024 #define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
3025 #define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
3026 #define EXTI_PR1_PIF11_Pos       (11U)
3027 #define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
3028 #define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
3029 #define EXTI_PR1_PIF12_Pos       (12U)
3030 #define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
3031 #define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
3032 #define EXTI_PR1_PIF13_Pos       (13U)
3033 #define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
3034 #define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
3035 #define EXTI_PR1_PIF14_Pos       (14U)
3036 #define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
3037 #define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
3038 #define EXTI_PR1_PIF15_Pos       (15U)
3039 #define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
3040 #define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
3041 #define EXTI_PR1_PIF16_Pos       (16U)
3042 #define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
3043 #define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
3044 #define EXTI_PR1_PIF18_Pos       (18U)
3045 #define EXTI_PR1_PIF18_Msk       (0x1UL << EXTI_PR1_PIF18_Pos)                 /*!< 0x00040000 */
3046 #define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */
3047 #define EXTI_PR1_PIF19_Pos       (19U)
3048 #define EXTI_PR1_PIF19_Msk       (0x1UL << EXTI_PR1_PIF19_Pos)                 /*!< 0x00080000 */
3049 #define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
3050 #define EXTI_PR1_PIF20_Pos       (20U)
3051 #define EXTI_PR1_PIF20_Msk       (0x1UL << EXTI_PR1_PIF20_Pos)                 /*!< 0x00100000 */
3052 #define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
3053 #define EXTI_PR1_PIF21_Pos       (21U)
3054 #define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
3055 #define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
3056 
3057 /*******************  Bit definition for EXTI_IMR2 register  ******************/
3058 #define EXTI_IMR2_IM32_Pos       (0U)
3059 #define EXTI_IMR2_IM32_Msk       (0x1UL << EXTI_IMR2_IM32_Pos)                 /*!< 0x00000001 */
3060 #define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
3061 #define EXTI_IMR2_IM33_Pos       (1U)
3062 #define EXTI_IMR2_IM33_Msk       (0x1UL << EXTI_IMR2_IM33_Pos)                 /*!< 0x00000002 */
3063 #define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
3064 #define EXTI_IMR2_IM35_Pos       (3U)
3065 #define EXTI_IMR2_IM35_Msk       (0x1UL << EXTI_IMR2_IM35_Pos)                 /*!< 0x00000008 */
3066 #define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
3067 #define EXTI_IMR2_IM37_Pos       (5U)
3068 #define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
3069 #define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
3070 #define EXTI_IMR2_IM38_Pos       (6U)
3071 #define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
3072 #define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
3073 #define EXTI_IMR2_IM_Pos         (0U)
3074 #define EXTI_IMR2_IM_Msk         (0x6BUL << EXTI_IMR2_IM_Pos)                   /*!< 0x0000006B */
3075 #define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
3076 
3077 /*******************  Bit definition for EXTI_EMR2 register  ******************/
3078 #define EXTI_EMR2_EM32_Pos       (0U)
3079 #define EXTI_EMR2_EM32_Msk       (0x1UL << EXTI_EMR2_EM32_Pos)                 /*!< 0x00000001 */
3080 #define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
3081 #define EXTI_EMR2_EM33_Pos       (1U)
3082 #define EXTI_EMR2_EM33_Msk       (0x1UL << EXTI_EMR2_EM33_Pos)                 /*!< 0x00000002 */
3083 #define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
3084 #define EXTI_EMR2_EM35_Pos       (3U)
3085 #define EXTI_EMR2_EM35_Msk       (0x1UL << EXTI_EMR2_EM35_Pos)                 /*!< 0x00000008 */
3086 #define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
3087 #define EXTI_EMR2_EM37_Pos       (5U)
3088 #define EXTI_EMR2_EM37_Msk       (0x1UL << EXTI_EMR2_EM37_Pos)                 /*!< 0x00000020 */
3089 #define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
3090 #define EXTI_EMR2_EM38_Pos       (6U)
3091 #define EXTI_EMR2_EM38_Msk       (0x1UL << EXTI_EMR2_EM38_Pos)                 /*!< 0x00000040 */
3092 #define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
3093 #define EXTI_EMR2_EM_Pos         (0U)
3094 #define EXTI_EMR2_EM_Msk         (0x6BUL << EXTI_EMR2_EM_Pos)                   /*!< 0x0000006B */
3095 #define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */
3096 
3097 /******************  Bit definition for EXTI_RTSR2 register  ******************/
3098 #define EXTI_RTSR2_RT35_Pos      (3U)
3099 #define EXTI_RTSR2_RT35_Msk      (0x1UL << EXTI_RTSR2_RT35_Pos)                /*!< 0x00000008 */
3100 #define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */
3101 #define EXTI_RTSR2_RT37_Pos      (5U)
3102 #define EXTI_RTSR2_RT37_Msk      (0x1UL << EXTI_RTSR2_RT37_Pos)                /*!< 0x00000020 */
3103 #define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */
3104 #define EXTI_RTSR2_RT38_Pos      (6U)
3105 #define EXTI_RTSR2_RT38_Msk      (0x1UL << EXTI_RTSR2_RT38_Pos)                /*!< 0x00000040 */
3106 #define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
3107 
3108 /******************  Bit definition for EXTI_FTSR2 register  ******************/
3109 #define EXTI_FTSR2_FT35_Pos      (3U)
3110 #define EXTI_FTSR2_FT35_Msk      (0x1UL << EXTI_FTSR2_FT35_Pos)                /*!< 0x00000008 */
3111 #define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */
3112 #define EXTI_FTSR2_FT37_Pos      (5U)
3113 #define EXTI_FTSR2_FT37_Msk      (0x1UL << EXTI_FTSR2_FT37_Pos)                /*!< 0x00000020 */
3114 #define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */
3115 #define EXTI_FTSR2_FT38_Pos      (6U)
3116 #define EXTI_FTSR2_FT38_Msk      (0x1UL << EXTI_FTSR2_FT38_Pos)                /*!< 0x00000040 */
3117 #define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */
3118 
3119 /******************  Bit definition for EXTI_SWIER2 register  *****************/
3120 #define EXTI_SWIER2_SWI35_Pos    (3U)
3121 #define EXTI_SWIER2_SWI35_Msk    (0x1UL << EXTI_SWIER2_SWI35_Pos)              /*!< 0x00000008 */
3122 #define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */
3123 #define EXTI_SWIER2_SWI37_Pos    (5U)
3124 #define EXTI_SWIER2_SWI37_Msk    (0x1UL << EXTI_SWIER2_SWI37_Pos)              /*!< 0x00000020 */
3125 #define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */
3126 #define EXTI_SWIER2_SWI38_Pos    (6U)
3127 #define EXTI_SWIER2_SWI38_Msk    (0x1UL << EXTI_SWIER2_SWI38_Pos)              /*!< 0x00000040 */
3128 #define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
3129 
3130 /*******************  Bit definition for EXTI_PR2 register  *******************/
3131 #define EXTI_PR2_PIF35_Pos       (3U)
3132 #define EXTI_PR2_PIF35_Msk       (0x1UL << EXTI_PR2_PIF35_Pos)                 /*!< 0x00000008 */
3133 #define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */
3134 #define EXTI_PR2_PIF37_Pos       (5U)
3135 #define EXTI_PR2_PIF37_Msk       (0x1UL << EXTI_PR2_PIF37_Pos)                 /*!< 0x00000020 */
3136 #define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */
3137 #define EXTI_PR2_PIF38_Pos       (6U)
3138 #define EXTI_PR2_PIF38_Msk       (0x1UL << EXTI_PR2_PIF38_Pos)                 /*!< 0x00000040 */
3139 #define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
3140 
3141 
3142 /******************************************************************************/
3143 /*                                                                            */
3144 /*                                    FLASH                                   */
3145 /*                                                                            */
3146 /******************************************************************************/
3147 /*******************  Bits definition for FLASH_ACR register  *****************/
3148 #define FLASH_ACR_LATENCY_Pos             (0U)
3149 #define FLASH_ACR_LATENCY_Msk             (0x7UL << FLASH_ACR_LATENCY_Pos)     /*!< 0x00000007 */
3150 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk
3151 #define FLASH_ACR_LATENCY_0WS             (0x00000000UL)
3152 #define FLASH_ACR_LATENCY_1WS             (0x00000001UL)
3153 #define FLASH_ACR_LATENCY_2WS             (0x00000002UL)
3154 #define FLASH_ACR_LATENCY_3WS             (0x00000003UL)
3155 #define FLASH_ACR_LATENCY_4WS             (0x00000004UL)
3156 #define FLASH_ACR_PRFTEN_Pos              (8U)
3157 #define FLASH_ACR_PRFTEN_Msk              (0x1UL << FLASH_ACR_PRFTEN_Pos)      /*!< 0x00000100 */
3158 #define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk
3159 #define FLASH_ACR_ICEN_Pos                (9U)
3160 #define FLASH_ACR_ICEN_Msk                (0x1UL << FLASH_ACR_ICEN_Pos)        /*!< 0x00000200 */
3161 #define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk
3162 #define FLASH_ACR_DCEN_Pos                (10U)
3163 #define FLASH_ACR_DCEN_Msk                (0x1UL << FLASH_ACR_DCEN_Pos)        /*!< 0x00000400 */
3164 #define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk
3165 #define FLASH_ACR_ICRST_Pos               (11U)
3166 #define FLASH_ACR_ICRST_Msk               (0x1UL << FLASH_ACR_ICRST_Pos)       /*!< 0x00000800 */
3167 #define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk
3168 #define FLASH_ACR_DCRST_Pos               (12U)
3169 #define FLASH_ACR_DCRST_Msk               (0x1UL << FLASH_ACR_DCRST_Pos)       /*!< 0x00001000 */
3170 #define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk
3171 #define FLASH_ACR_RUN_PD_Pos              (13U)
3172 #define FLASH_ACR_RUN_PD_Msk              (0x1UL << FLASH_ACR_RUN_PD_Pos)      /*!< 0x00002000 */
3173 #define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
3174 #define FLASH_ACR_SLEEP_PD_Pos            (14U)
3175 #define FLASH_ACR_SLEEP_PD_Msk            (0x1UL << FLASH_ACR_SLEEP_PD_Pos)    /*!< 0x00004000 */
3176 #define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
3177 
3178 /*******************  Bits definition for FLASH_SR register  ******************/
3179 #define FLASH_SR_EOP_Pos                  (0U)
3180 #define FLASH_SR_EOP_Msk                  (0x1UL << FLASH_SR_EOP_Pos)          /*!< 0x00000001 */
3181 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk
3182 #define FLASH_SR_OPERR_Pos                (1U)
3183 #define FLASH_SR_OPERR_Msk                (0x1UL << FLASH_SR_OPERR_Pos)        /*!< 0x00000002 */
3184 #define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk
3185 #define FLASH_SR_PROGERR_Pos              (3U)
3186 #define FLASH_SR_PROGERR_Msk              (0x1UL << FLASH_SR_PROGERR_Pos)      /*!< 0x00000008 */
3187 #define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk
3188 #define FLASH_SR_WRPERR_Pos               (4U)
3189 #define FLASH_SR_WRPERR_Msk               (0x1UL << FLASH_SR_WRPERR_Pos)       /*!< 0x00000010 */
3190 #define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk
3191 #define FLASH_SR_PGAERR_Pos               (5U)
3192 #define FLASH_SR_PGAERR_Msk               (0x1UL << FLASH_SR_PGAERR_Pos)       /*!< 0x00000020 */
3193 #define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk
3194 #define FLASH_SR_SIZERR_Pos               (6U)
3195 #define FLASH_SR_SIZERR_Msk               (0x1UL << FLASH_SR_SIZERR_Pos)       /*!< 0x00000040 */
3196 #define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk
3197 #define FLASH_SR_PGSERR_Pos               (7U)
3198 #define FLASH_SR_PGSERR_Msk               (0x1UL << FLASH_SR_PGSERR_Pos)       /*!< 0x00000080 */
3199 #define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk
3200 #define FLASH_SR_MISERR_Pos               (8U)
3201 #define FLASH_SR_MISERR_Msk               (0x1UL << FLASH_SR_MISERR_Pos)       /*!< 0x00000100 */
3202 #define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk
3203 #define FLASH_SR_FASTERR_Pos              (9U)
3204 #define FLASH_SR_FASTERR_Msk              (0x1UL << FLASH_SR_FASTERR_Pos)      /*!< 0x00000200 */
3205 #define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk
3206 #define FLASH_SR_RDERR_Pos                (14U)
3207 #define FLASH_SR_RDERR_Msk                (0x1UL << FLASH_SR_RDERR_Pos)        /*!< 0x00004000 */
3208 #define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk
3209 #define FLASH_SR_OPTVERR_Pos              (15U)
3210 #define FLASH_SR_OPTVERR_Msk              (0x1UL << FLASH_SR_OPTVERR_Pos)      /*!< 0x00008000 */
3211 #define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk
3212 #define FLASH_SR_BSY_Pos                  (16U)
3213 #define FLASH_SR_BSY_Msk                  (0x1UL << FLASH_SR_BSY_Pos)          /*!< 0x00010000 */
3214 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk
3215 #define FLASH_SR_PEMPTY_Pos               (17U)
3216 #define FLASH_SR_PEMPTY_Msk               (0x1UL << FLASH_SR_PEMPTY_Pos)       /*!< 0x00020000 */
3217 #define FLASH_SR_PEMPTY                   FLASH_SR_PEMPTY_Msk
3218 
3219 /*******************  Bits definition for FLASH_CR register  ******************/
3220 #define FLASH_CR_PG_Pos                   (0U)
3221 #define FLASH_CR_PG_Msk                   (0x1UL << FLASH_CR_PG_Pos)           /*!< 0x00000001 */
3222 #define FLASH_CR_PG                       FLASH_CR_PG_Msk
3223 #define FLASH_CR_PER_Pos                  (1U)
3224 #define FLASH_CR_PER_Msk                  (0x1UL << FLASH_CR_PER_Pos)          /*!< 0x00000002 */
3225 #define FLASH_CR_PER                      FLASH_CR_PER_Msk
3226 #define FLASH_CR_MER1_Pos                 (2U)
3227 #define FLASH_CR_MER1_Msk                 (0x1UL << FLASH_CR_MER1_Pos)         /*!< 0x00000004 */
3228 #define FLASH_CR_MER1                     FLASH_CR_MER1_Msk
3229 #define FLASH_CR_PNB_Pos                  (3U)
3230 #define FLASH_CR_PNB_Msk                  (0x3FUL << FLASH_CR_PNB_Pos)         /*!< 0x000001F8 */
3231 #define FLASH_CR_PNB                      FLASH_CR_PNB_Msk
3232 #define FLASH_CR_STRT_Pos                 (16U)
3233 #define FLASH_CR_STRT_Msk                 (0x1UL << FLASH_CR_STRT_Pos)         /*!< 0x00010000 */
3234 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk
3235 #define FLASH_CR_OPTSTRT_Pos              (17U)
3236 #define FLASH_CR_OPTSTRT_Msk              (0x1UL << FLASH_CR_OPTSTRT_Pos)      /*!< 0x00020000 */
3237 #define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk
3238 #define FLASH_CR_FSTPG_Pos                (18U)
3239 #define FLASH_CR_FSTPG_Msk                (0x1UL << FLASH_CR_FSTPG_Pos)        /*!< 0x00040000 */
3240 #define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk
3241 #define FLASH_CR_EOPIE_Pos                (24U)
3242 #define FLASH_CR_EOPIE_Msk                (0x1UL << FLASH_CR_EOPIE_Pos)        /*!< 0x01000000 */
3243 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk
3244 #define FLASH_CR_ERRIE_Pos                (25U)
3245 #define FLASH_CR_ERRIE_Msk                (0x1UL << FLASH_CR_ERRIE_Pos)        /*!< 0x02000000 */
3246 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk
3247 #define FLASH_CR_RDERRIE_Pos              (26U)
3248 #define FLASH_CR_RDERRIE_Msk              (0x1UL << FLASH_CR_RDERRIE_Pos)      /*!< 0x04000000 */
3249 #define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk
3250 #define FLASH_CR_OBL_LAUNCH_Pos           (27U)
3251 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)   /*!< 0x08000000 */
3252 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk
3253 #define FLASH_CR_OPTLOCK_Pos              (30U)
3254 #define FLASH_CR_OPTLOCK_Msk              (0x1UL << FLASH_CR_OPTLOCK_Pos)      /*!< 0x40000000 */
3255 #define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk
3256 #define FLASH_CR_LOCK_Pos                 (31U)
3257 #define FLASH_CR_LOCK_Msk                 (0x1UL << FLASH_CR_LOCK_Pos)         /*!< 0x80000000 */
3258 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk
3259 
3260 /*******************  Bits definition for FLASH_ECCR register  ***************/
3261 #define FLASH_ECCR_ADDR_ECC_Pos           (0U)
3262 #define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
3263 #define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk
3264 #define FLASH_ECCR_SYSF_ECC_Pos           (20U)
3265 #define FLASH_ECCR_SYSF_ECC_Msk           (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)   /*!< 0x00100000 */
3266 #define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk
3267 #define FLASH_ECCR_ECCIE_Pos              (24U)
3268 #define FLASH_ECCR_ECCIE_Msk              (0x1UL << FLASH_ECCR_ECCIE_Pos)      /*!< 0x01000000 */
3269 #define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk
3270 #define FLASH_ECCR_ECCC_Pos               (30U)
3271 #define FLASH_ECCR_ECCC_Msk               (0x1UL << FLASH_ECCR_ECCC_Pos)       /*!< 0x40000000 */
3272 #define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk
3273 #define FLASH_ECCR_ECCD_Pos               (31U)
3274 #define FLASH_ECCR_ECCD_Msk               (0x1UL << FLASH_ECCR_ECCD_Pos)       /*!< 0x80000000 */
3275 #define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk
3276 
3277 /*******************  Bits definition for FLASH_OPTR register  ***************/
3278 #define FLASH_OPTR_RDP_Pos                (0U)
3279 #define FLASH_OPTR_RDP_Msk                (0xFFUL << FLASH_OPTR_RDP_Pos)       /*!< 0x000000FF */
3280 #define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk
3281 #define FLASH_OPTR_BOR_LEV_Pos            (8U)
3282 #define FLASH_OPTR_BOR_LEV_Msk            (0x7UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000700 */
3283 #define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk
3284 #define FLASH_OPTR_BOR_LEV_0              (0x0UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000000 */
3285 #define FLASH_OPTR_BOR_LEV_1              (0x1UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000100 */
3286 #define FLASH_OPTR_BOR_LEV_2              (0x2UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000200 */
3287 #define FLASH_OPTR_BOR_LEV_3              (0x3UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000300 */
3288 #define FLASH_OPTR_BOR_LEV_4              (0x4UL << FLASH_OPTR_BOR_LEV_Pos)    /*!< 0x00000400 */
3289 #define FLASH_OPTR_nRST_STOP_Pos          (12U)
3290 #define FLASH_OPTR_nRST_STOP_Msk          (0x1UL << FLASH_OPTR_nRST_STOP_Pos)  /*!< 0x00001000 */
3291 #define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk
3292 #define FLASH_OPTR_nRST_STDBY_Pos         (13U)
3293 #define FLASH_OPTR_nRST_STDBY_Msk         (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
3294 #define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk
3295 #define FLASH_OPTR_nRST_SHDW_Pos          (14U)
3296 #define FLASH_OPTR_nRST_SHDW_Msk          (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)  /*!< 0x00004000 */
3297 #define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk
3298 #define FLASH_OPTR_IWDG_SW_Pos            (16U)
3299 #define FLASH_OPTR_IWDG_SW_Msk            (0x1UL << FLASH_OPTR_IWDG_SW_Pos)    /*!< 0x00010000 */
3300 #define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk
3301 #define FLASH_OPTR_IWDG_STOP_Pos          (17U)
3302 #define FLASH_OPTR_IWDG_STOP_Msk          (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)  /*!< 0x00020000 */
3303 #define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk
3304 #define FLASH_OPTR_IWDG_STDBY_Pos         (18U)
3305 #define FLASH_OPTR_IWDG_STDBY_Msk         (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
3306 #define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk
3307 #define FLASH_OPTR_WWDG_SW_Pos            (19U)
3308 #define FLASH_OPTR_WWDG_SW_Msk            (0x1UL << FLASH_OPTR_WWDG_SW_Pos)    /*!< 0x00080000 */
3309 #define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk
3310 #define FLASH_OPTR_nBOOT1_Pos             (23U)
3311 #define FLASH_OPTR_nBOOT1_Msk             (0x1UL << FLASH_OPTR_nBOOT1_Pos)     /*!< 0x00800000 */
3312 #define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk
3313 #define FLASH_OPTR_SRAM2_PE_Pos           (24U)
3314 #define FLASH_OPTR_SRAM2_PE_Msk           (0x1UL << FLASH_OPTR_SRAM2_PE_Pos)   /*!< 0x01000000 */
3315 #define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk
3316 #define FLASH_OPTR_SRAM2_RST_Pos          (25U)
3317 #define FLASH_OPTR_SRAM2_RST_Msk          (0x1UL << FLASH_OPTR_SRAM2_RST_Pos)  /*!< 0x02000000 */
3318 #define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk
3319 #define FLASH_OPTR_nSWBOOT0_Pos           (26U)
3320 #define FLASH_OPTR_nSWBOOT0_Msk           (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)   /*!< 0x04000000 */
3321 #define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk
3322 #define FLASH_OPTR_nBOOT0_Pos             (27U)
3323 #define FLASH_OPTR_nBOOT0_Msk             (0x1UL << FLASH_OPTR_nBOOT0_Pos)     /*!< 0x08000000 */
3324 #define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk
3325 
3326 /******************  Bits definition for FLASH_PCROP1SR register  **********/
3327 #define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)
3328 #define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x00003FFF */
3329 #define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk
3330 
3331 /******************  Bits definition for FLASH_PCROP1ER register  ***********/
3332 #define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)
3333 #define FLASH_PCROP1ER_PCROP1_END_Msk     (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x00003FFF */
3334 #define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk
3335 #define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)
3336 #define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
3337 #define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk
3338 
3339 /******************  Bits definition for FLASH_WRP1AR register  ***************/
3340 #define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)
3341 #define FLASH_WRP1AR_WRP1A_STRT_Msk       (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000003F */
3342 #define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk
3343 #define FLASH_WRP1AR_WRP1A_END_Pos        (16U)
3344 #define FLASH_WRP1AR_WRP1A_END_Msk        (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos)  /*!< 0x003F0000 */
3345 #define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk
3346 
3347 /******************  Bits definition for FLASH_WRPB1R register  ***************/
3348 #define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)
3349 #define FLASH_WRP1BR_WRP1B_STRT_Msk       (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000003F */
3350 #define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk
3351 #define FLASH_WRP1BR_WRP1B_END_Pos        (16U)
3352 #define FLASH_WRP1BR_WRP1B_END_Msk        (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos)  /*!< 0x003F0000 */
3353 #define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk
3354 
3355 
3356 
3357 
3358 /******************************************************************************/
3359 /*                                                                            */
3360 /*                       General Purpose IOs (GPIO)                           */
3361 /*                                                                            */
3362 /******************************************************************************/
3363 /******************  Bits definition for GPIO_MODER register  *****************/
3364 #define GPIO_MODER_MODE0_Pos           (0U)
3365 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
3366 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
3367 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
3368 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
3369 #define GPIO_MODER_MODE1_Pos           (2U)
3370 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
3371 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
3372 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
3373 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
3374 #define GPIO_MODER_MODE2_Pos           (4U)
3375 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
3376 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
3377 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
3378 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
3379 #define GPIO_MODER_MODE3_Pos           (6U)
3380 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
3381 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
3382 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
3383 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
3384 #define GPIO_MODER_MODE4_Pos           (8U)
3385 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
3386 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
3387 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
3388 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
3389 #define GPIO_MODER_MODE5_Pos           (10U)
3390 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
3391 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
3392 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
3393 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
3394 #define GPIO_MODER_MODE6_Pos           (12U)
3395 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
3396 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
3397 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
3398 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
3399 #define GPIO_MODER_MODE7_Pos           (14U)
3400 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
3401 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
3402 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
3403 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
3404 #define GPIO_MODER_MODE8_Pos           (16U)
3405 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
3406 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
3407 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
3408 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
3409 #define GPIO_MODER_MODE9_Pos           (18U)
3410 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
3411 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
3412 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
3413 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
3414 #define GPIO_MODER_MODE10_Pos          (20U)
3415 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
3416 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
3417 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
3418 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
3419 #define GPIO_MODER_MODE11_Pos          (22U)
3420 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
3421 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
3422 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
3423 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
3424 #define GPIO_MODER_MODE12_Pos          (24U)
3425 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
3426 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
3427 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
3428 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
3429 #define GPIO_MODER_MODE13_Pos          (26U)
3430 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
3431 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
3432 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
3433 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
3434 #define GPIO_MODER_MODE14_Pos          (28U)
3435 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
3436 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
3437 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
3438 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
3439 #define GPIO_MODER_MODE15_Pos          (30U)
3440 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
3441 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
3442 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
3443 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
3444 
3445 /* Legacy defines */
3446 #define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
3447 #define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
3448 #define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
3449 #define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
3450 #define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
3451 #define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
3452 #define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
3453 #define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
3454 #define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
3455 #define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
3456 #define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
3457 #define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
3458 #define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
3459 #define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
3460 #define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
3461 #define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
3462 #define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
3463 #define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
3464 #define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
3465 #define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
3466 #define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
3467 #define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
3468 #define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
3469 #define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
3470 #define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
3471 #define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
3472 #define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
3473 #define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
3474 #define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
3475 #define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
3476 #define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
3477 #define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
3478 #define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
3479 #define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
3480 #define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
3481 #define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
3482 #define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
3483 #define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
3484 #define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
3485 #define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
3486 #define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
3487 #define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
3488 #define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
3489 #define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
3490 #define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
3491 #define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
3492 #define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
3493 #define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
3494 
3495 /******************  Bits definition for GPIO_OTYPER register  ****************/
3496 #define GPIO_OTYPER_OT0_Pos            (0U)
3497 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
3498 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
3499 #define GPIO_OTYPER_OT1_Pos            (1U)
3500 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
3501 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
3502 #define GPIO_OTYPER_OT2_Pos            (2U)
3503 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
3504 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
3505 #define GPIO_OTYPER_OT3_Pos            (3U)
3506 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
3507 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
3508 #define GPIO_OTYPER_OT4_Pos            (4U)
3509 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
3510 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
3511 #define GPIO_OTYPER_OT5_Pos            (5U)
3512 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
3513 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
3514 #define GPIO_OTYPER_OT6_Pos            (6U)
3515 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
3516 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
3517 #define GPIO_OTYPER_OT7_Pos            (7U)
3518 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
3519 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
3520 #define GPIO_OTYPER_OT8_Pos            (8U)
3521 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
3522 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
3523 #define GPIO_OTYPER_OT9_Pos            (9U)
3524 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
3525 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
3526 #define GPIO_OTYPER_OT10_Pos           (10U)
3527 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
3528 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
3529 #define GPIO_OTYPER_OT11_Pos           (11U)
3530 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
3531 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
3532 #define GPIO_OTYPER_OT12_Pos           (12U)
3533 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
3534 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
3535 #define GPIO_OTYPER_OT13_Pos           (13U)
3536 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
3537 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
3538 #define GPIO_OTYPER_OT14_Pos           (14U)
3539 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
3540 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
3541 #define GPIO_OTYPER_OT15_Pos           (15U)
3542 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
3543 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
3544 
3545 /* Legacy defines */
3546 #define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
3547 #define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
3548 #define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
3549 #define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
3550 #define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
3551 #define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
3552 #define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
3553 #define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
3554 #define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
3555 #define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
3556 #define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
3557 #define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
3558 #define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
3559 #define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
3560 #define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
3561 #define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
3562 
3563 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
3564 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
3565 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
3566 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
3567 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
3568 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
3569 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
3570 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
3571 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
3572 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
3573 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
3574 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
3575 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
3576 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
3577 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
3578 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
3579 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
3580 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
3581 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
3582 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
3583 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
3584 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
3585 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
3586 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
3587 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
3588 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
3589 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
3590 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
3591 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
3592 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
3593 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
3594 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
3595 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
3596 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
3597 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
3598 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
3599 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
3600 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
3601 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
3602 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
3603 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
3604 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
3605 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
3606 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
3607 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
3608 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
3609 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
3610 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
3611 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
3612 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
3613 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
3614 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
3615 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
3616 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
3617 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
3618 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
3619 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
3620 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
3621 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
3622 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
3623 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
3624 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
3625 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
3626 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
3627 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
3628 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
3629 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
3630 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
3631 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
3632 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
3633 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
3634 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
3635 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
3636 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
3637 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
3638 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
3639 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
3640 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
3641 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
3642 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
3643 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
3644 
3645 /* Legacy defines */
3646 #define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
3647 #define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
3648 #define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
3649 #define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
3650 #define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
3651 #define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
3652 #define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
3653 #define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
3654 #define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
3655 #define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
3656 #define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
3657 #define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
3658 #define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
3659 #define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
3660 #define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
3661 #define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
3662 #define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
3663 #define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
3664 #define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
3665 #define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
3666 #define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
3667 #define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
3668 #define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
3669 #define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
3670 #define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
3671 #define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
3672 #define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
3673 #define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
3674 #define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
3675 #define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
3676 #define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
3677 #define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
3678 #define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
3679 #define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
3680 #define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
3681 #define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
3682 #define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
3683 #define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
3684 #define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
3685 #define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
3686 #define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
3687 #define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
3688 #define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
3689 #define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
3690 #define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
3691 #define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
3692 #define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
3693 #define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
3694 
3695 /******************  Bits definition for GPIO_PUPDR register  *****************/
3696 #define GPIO_PUPDR_PUPD0_Pos           (0U)
3697 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
3698 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
3699 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
3700 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
3701 #define GPIO_PUPDR_PUPD1_Pos           (2U)
3702 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
3703 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
3704 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
3705 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
3706 #define GPIO_PUPDR_PUPD2_Pos           (4U)
3707 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
3708 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
3709 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
3710 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
3711 #define GPIO_PUPDR_PUPD3_Pos           (6U)
3712 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
3713 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
3714 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
3715 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
3716 #define GPIO_PUPDR_PUPD4_Pos           (8U)
3717 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
3718 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
3719 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
3720 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
3721 #define GPIO_PUPDR_PUPD5_Pos           (10U)
3722 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
3723 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
3724 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
3725 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
3726 #define GPIO_PUPDR_PUPD6_Pos           (12U)
3727 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
3728 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
3729 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
3730 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
3731 #define GPIO_PUPDR_PUPD7_Pos           (14U)
3732 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
3733 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
3734 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
3735 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
3736 #define GPIO_PUPDR_PUPD8_Pos           (16U)
3737 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
3738 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
3739 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
3740 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
3741 #define GPIO_PUPDR_PUPD9_Pos           (18U)
3742 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
3743 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
3744 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
3745 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
3746 #define GPIO_PUPDR_PUPD10_Pos          (20U)
3747 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
3748 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
3749 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
3750 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
3751 #define GPIO_PUPDR_PUPD11_Pos          (22U)
3752 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
3753 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
3754 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
3755 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
3756 #define GPIO_PUPDR_PUPD12_Pos          (24U)
3757 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
3758 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
3759 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
3760 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
3761 #define GPIO_PUPDR_PUPD13_Pos          (26U)
3762 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
3763 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
3764 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
3765 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
3766 #define GPIO_PUPDR_PUPD14_Pos          (28U)
3767 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
3768 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
3769 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
3770 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
3771 #define GPIO_PUPDR_PUPD15_Pos          (30U)
3772 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
3773 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
3774 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
3775 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
3776 
3777 /* Legacy defines */
3778 #define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
3779 #define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
3780 #define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
3781 #define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
3782 #define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
3783 #define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
3784 #define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
3785 #define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
3786 #define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
3787 #define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
3788 #define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
3789 #define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
3790 #define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
3791 #define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
3792 #define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
3793 #define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
3794 #define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
3795 #define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
3796 #define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
3797 #define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
3798 #define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
3799 #define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
3800 #define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
3801 #define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
3802 #define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
3803 #define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
3804 #define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
3805 #define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
3806 #define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
3807 #define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
3808 #define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
3809 #define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
3810 #define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
3811 #define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
3812 #define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
3813 #define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
3814 #define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
3815 #define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
3816 #define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
3817 #define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
3818 #define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
3819 #define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
3820 #define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
3821 #define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
3822 #define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
3823 #define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
3824 #define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
3825 #define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
3826 
3827 /******************  Bits definition for GPIO_IDR register  *******************/
3828 #define GPIO_IDR_ID0_Pos               (0U)
3829 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
3830 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
3831 #define GPIO_IDR_ID1_Pos               (1U)
3832 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
3833 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
3834 #define GPIO_IDR_ID2_Pos               (2U)
3835 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
3836 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
3837 #define GPIO_IDR_ID3_Pos               (3U)
3838 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
3839 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
3840 #define GPIO_IDR_ID4_Pos               (4U)
3841 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
3842 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
3843 #define GPIO_IDR_ID5_Pos               (5U)
3844 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
3845 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
3846 #define GPIO_IDR_ID6_Pos               (6U)
3847 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
3848 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
3849 #define GPIO_IDR_ID7_Pos               (7U)
3850 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
3851 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
3852 #define GPIO_IDR_ID8_Pos               (8U)
3853 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
3854 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
3855 #define GPIO_IDR_ID9_Pos               (9U)
3856 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
3857 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
3858 #define GPIO_IDR_ID10_Pos              (10U)
3859 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
3860 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
3861 #define GPIO_IDR_ID11_Pos              (11U)
3862 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
3863 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
3864 #define GPIO_IDR_ID12_Pos              (12U)
3865 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
3866 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
3867 #define GPIO_IDR_ID13_Pos              (13U)
3868 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
3869 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
3870 #define GPIO_IDR_ID14_Pos              (14U)
3871 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
3872 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
3873 #define GPIO_IDR_ID15_Pos              (15U)
3874 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
3875 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
3876 
3877 /* Legacy defines */
3878 #define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
3879 #define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
3880 #define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
3881 #define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
3882 #define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
3883 #define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
3884 #define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
3885 #define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
3886 #define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
3887 #define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
3888 #define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
3889 #define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
3890 #define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
3891 #define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
3892 #define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
3893 #define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
3894 
3895 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
3896 #define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
3897 #define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
3898 #define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
3899 #define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
3900 #define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
3901 #define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
3902 #define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
3903 #define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
3904 #define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
3905 #define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
3906 #define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
3907 #define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
3908 #define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
3909 #define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
3910 #define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
3911 #define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
3912 
3913 /******************  Bits definition for GPIO_ODR register  *******************/
3914 #define GPIO_ODR_OD0_Pos               (0U)
3915 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
3916 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
3917 #define GPIO_ODR_OD1_Pos               (1U)
3918 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
3919 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
3920 #define GPIO_ODR_OD2_Pos               (2U)
3921 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
3922 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
3923 #define GPIO_ODR_OD3_Pos               (3U)
3924 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
3925 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
3926 #define GPIO_ODR_OD4_Pos               (4U)
3927 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
3928 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
3929 #define GPIO_ODR_OD5_Pos               (5U)
3930 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
3931 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
3932 #define GPIO_ODR_OD6_Pos               (6U)
3933 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
3934 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
3935 #define GPIO_ODR_OD7_Pos               (7U)
3936 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
3937 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
3938 #define GPIO_ODR_OD8_Pos               (8U)
3939 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
3940 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
3941 #define GPIO_ODR_OD9_Pos               (9U)
3942 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
3943 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
3944 #define GPIO_ODR_OD10_Pos              (10U)
3945 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
3946 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
3947 #define GPIO_ODR_OD11_Pos              (11U)
3948 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
3949 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
3950 #define GPIO_ODR_OD12_Pos              (12U)
3951 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
3952 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
3953 #define GPIO_ODR_OD13_Pos              (13U)
3954 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
3955 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
3956 #define GPIO_ODR_OD14_Pos              (14U)
3957 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
3958 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
3959 #define GPIO_ODR_OD15_Pos              (15U)
3960 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
3961 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
3962 
3963 /* Legacy defines */
3964 #define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
3965 #define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
3966 #define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
3967 #define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
3968 #define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
3969 #define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
3970 #define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
3971 #define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
3972 #define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
3973 #define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
3974 #define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
3975 #define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
3976 #define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
3977 #define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
3978 #define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
3979 #define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
3980 
3981 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
3982 #define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
3983 #define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
3984 #define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
3985 #define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
3986 #define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
3987 #define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
3988 #define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
3989 #define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
3990 #define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
3991 #define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
3992 #define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
3993 #define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
3994 #define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
3995 #define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
3996 #define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
3997 #define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
3998 
3999 /******************  Bits definition for GPIO_BSRR register  ******************/
4000 #define GPIO_BSRR_BS0_Pos              (0U)
4001 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
4002 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
4003 #define GPIO_BSRR_BS1_Pos              (1U)
4004 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
4005 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
4006 #define GPIO_BSRR_BS2_Pos              (2U)
4007 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
4008 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
4009 #define GPIO_BSRR_BS3_Pos              (3U)
4010 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
4011 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
4012 #define GPIO_BSRR_BS4_Pos              (4U)
4013 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
4014 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
4015 #define GPIO_BSRR_BS5_Pos              (5U)
4016 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
4017 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
4018 #define GPIO_BSRR_BS6_Pos              (6U)
4019 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
4020 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
4021 #define GPIO_BSRR_BS7_Pos              (7U)
4022 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
4023 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
4024 #define GPIO_BSRR_BS8_Pos              (8U)
4025 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
4026 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
4027 #define GPIO_BSRR_BS9_Pos              (9U)
4028 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
4029 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
4030 #define GPIO_BSRR_BS10_Pos             (10U)
4031 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
4032 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
4033 #define GPIO_BSRR_BS11_Pos             (11U)
4034 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
4035 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
4036 #define GPIO_BSRR_BS12_Pos             (12U)
4037 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
4038 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
4039 #define GPIO_BSRR_BS13_Pos             (13U)
4040 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
4041 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
4042 #define GPIO_BSRR_BS14_Pos             (14U)
4043 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
4044 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
4045 #define GPIO_BSRR_BS15_Pos             (15U)
4046 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
4047 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
4048 #define GPIO_BSRR_BR0_Pos              (16U)
4049 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
4050 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
4051 #define GPIO_BSRR_BR1_Pos              (17U)
4052 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
4053 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
4054 #define GPIO_BSRR_BR2_Pos              (18U)
4055 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
4056 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
4057 #define GPIO_BSRR_BR3_Pos              (19U)
4058 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
4059 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
4060 #define GPIO_BSRR_BR4_Pos              (20U)
4061 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
4062 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
4063 #define GPIO_BSRR_BR5_Pos              (21U)
4064 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
4065 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
4066 #define GPIO_BSRR_BR6_Pos              (22U)
4067 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
4068 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
4069 #define GPIO_BSRR_BR7_Pos              (23U)
4070 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
4071 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
4072 #define GPIO_BSRR_BR8_Pos              (24U)
4073 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
4074 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
4075 #define GPIO_BSRR_BR9_Pos              (25U)
4076 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
4077 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
4078 #define GPIO_BSRR_BR10_Pos             (26U)
4079 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
4080 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
4081 #define GPIO_BSRR_BR11_Pos             (27U)
4082 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
4083 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
4084 #define GPIO_BSRR_BR12_Pos             (28U)
4085 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
4086 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
4087 #define GPIO_BSRR_BR13_Pos             (29U)
4088 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
4089 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
4090 #define GPIO_BSRR_BR14_Pos             (30U)
4091 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
4092 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
4093 #define GPIO_BSRR_BR15_Pos             (31U)
4094 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
4095 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
4096 
4097 /* Legacy defines */
4098 #define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
4099 #define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
4100 #define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
4101 #define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
4102 #define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
4103 #define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
4104 #define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
4105 #define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
4106 #define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
4107 #define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
4108 #define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
4109 #define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
4110 #define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
4111 #define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
4112 #define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
4113 #define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
4114 #define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
4115 #define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
4116 #define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
4117 #define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
4118 #define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
4119 #define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
4120 #define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
4121 #define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
4122 #define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
4123 #define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
4124 #define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
4125 #define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
4126 #define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
4127 #define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
4128 #define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
4129 #define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
4130 
4131 /****************** Bit definition for GPIO_LCKR register *********************/
4132 #define GPIO_LCKR_LCK0_Pos             (0U)
4133 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
4134 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
4135 #define GPIO_LCKR_LCK1_Pos             (1U)
4136 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
4137 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
4138 #define GPIO_LCKR_LCK2_Pos             (2U)
4139 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
4140 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
4141 #define GPIO_LCKR_LCK3_Pos             (3U)
4142 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
4143 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
4144 #define GPIO_LCKR_LCK4_Pos             (4U)
4145 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
4146 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
4147 #define GPIO_LCKR_LCK5_Pos             (5U)
4148 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
4149 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
4150 #define GPIO_LCKR_LCK6_Pos             (6U)
4151 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
4152 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
4153 #define GPIO_LCKR_LCK7_Pos             (7U)
4154 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
4155 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
4156 #define GPIO_LCKR_LCK8_Pos             (8U)
4157 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
4158 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
4159 #define GPIO_LCKR_LCK9_Pos             (9U)
4160 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
4161 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
4162 #define GPIO_LCKR_LCK10_Pos            (10U)
4163 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
4164 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
4165 #define GPIO_LCKR_LCK11_Pos            (11U)
4166 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
4167 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
4168 #define GPIO_LCKR_LCK12_Pos            (12U)
4169 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
4170 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
4171 #define GPIO_LCKR_LCK13_Pos            (13U)
4172 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
4173 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
4174 #define GPIO_LCKR_LCK14_Pos            (14U)
4175 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
4176 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
4177 #define GPIO_LCKR_LCK15_Pos            (15U)
4178 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
4179 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
4180 #define GPIO_LCKR_LCKK_Pos             (16U)
4181 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
4182 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
4183 
4184 /****************** Bit definition for GPIO_AFRL register *********************/
4185 #define GPIO_AFRL_AFSEL0_Pos           (0U)
4186 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
4187 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
4188 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
4189 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
4190 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
4191 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
4192 #define GPIO_AFRL_AFSEL1_Pos           (4U)
4193 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
4194 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
4195 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
4196 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
4197 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
4198 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
4199 #define GPIO_AFRL_AFSEL2_Pos           (8U)
4200 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
4201 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
4202 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
4203 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
4204 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
4205 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
4206 #define GPIO_AFRL_AFSEL3_Pos           (12U)
4207 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
4208 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
4209 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
4210 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
4211 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
4212 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
4213 #define GPIO_AFRL_AFSEL4_Pos           (16U)
4214 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
4215 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
4216 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
4217 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
4218 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
4219 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
4220 #define GPIO_AFRL_AFSEL5_Pos           (20U)
4221 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
4222 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
4223 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
4224 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
4225 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
4226 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
4227 #define GPIO_AFRL_AFSEL6_Pos           (24U)
4228 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
4229 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
4230 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
4231 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
4232 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
4233 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
4234 #define GPIO_AFRL_AFSEL7_Pos           (28U)
4235 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
4236 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
4237 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
4238 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
4239 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
4240 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
4241 
4242 /* Legacy defines */
4243 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
4244 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
4245 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
4246 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
4247 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
4248 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
4249 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
4250 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
4251 
4252 /****************** Bit definition for GPIO_AFRH register *********************/
4253 #define GPIO_AFRH_AFSEL8_Pos           (0U)
4254 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
4255 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
4256 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
4257 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
4258 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
4259 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
4260 #define GPIO_AFRH_AFSEL9_Pos           (4U)
4261 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
4262 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
4263 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
4264 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
4265 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
4266 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
4267 #define GPIO_AFRH_AFSEL10_Pos          (8U)
4268 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
4269 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
4270 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
4271 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
4272 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
4273 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
4274 #define GPIO_AFRH_AFSEL11_Pos          (12U)
4275 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
4276 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
4277 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
4278 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
4279 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
4280 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
4281 #define GPIO_AFRH_AFSEL12_Pos          (16U)
4282 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
4283 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
4284 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
4285 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
4286 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
4287 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
4288 #define GPIO_AFRH_AFSEL13_Pos          (20U)
4289 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
4290 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
4291 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
4292 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
4293 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
4294 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
4295 #define GPIO_AFRH_AFSEL14_Pos          (24U)
4296 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
4297 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
4298 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
4299 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
4300 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
4301 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
4302 #define GPIO_AFRH_AFSEL15_Pos          (28U)
4303 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
4304 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
4305 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
4306 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
4307 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
4308 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
4309 
4310 /* Legacy defines */
4311 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
4312 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
4313 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
4314 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
4315 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
4316 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
4317 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
4318 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
4319 
4320 /******************  Bits definition for GPIO_BRR register  ******************/
4321 #define GPIO_BRR_BR0_Pos               (0U)
4322 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
4323 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
4324 #define GPIO_BRR_BR1_Pos               (1U)
4325 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
4326 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
4327 #define GPIO_BRR_BR2_Pos               (2U)
4328 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
4329 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
4330 #define GPIO_BRR_BR3_Pos               (3U)
4331 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
4332 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
4333 #define GPIO_BRR_BR4_Pos               (4U)
4334 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
4335 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
4336 #define GPIO_BRR_BR5_Pos               (5U)
4337 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
4338 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
4339 #define GPIO_BRR_BR6_Pos               (6U)
4340 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
4341 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
4342 #define GPIO_BRR_BR7_Pos               (7U)
4343 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
4344 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
4345 #define GPIO_BRR_BR8_Pos               (8U)
4346 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
4347 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
4348 #define GPIO_BRR_BR9_Pos               (9U)
4349 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
4350 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
4351 #define GPIO_BRR_BR10_Pos              (10U)
4352 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
4353 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
4354 #define GPIO_BRR_BR11_Pos              (11U)
4355 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
4356 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
4357 #define GPIO_BRR_BR12_Pos              (12U)
4358 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
4359 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
4360 #define GPIO_BRR_BR13_Pos              (13U)
4361 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
4362 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
4363 #define GPIO_BRR_BR14_Pos              (14U)
4364 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
4365 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
4366 #define GPIO_BRR_BR15_Pos              (15U)
4367 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
4368 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
4369 
4370 /* Legacy defines */
4371 #define GPIO_BRR_BR_0                       GPIO_BRR_BR0
4372 #define GPIO_BRR_BR_1                       GPIO_BRR_BR1
4373 #define GPIO_BRR_BR_2                       GPIO_BRR_BR2
4374 #define GPIO_BRR_BR_3                       GPIO_BRR_BR3
4375 #define GPIO_BRR_BR_4                       GPIO_BRR_BR4
4376 #define GPIO_BRR_BR_5                       GPIO_BRR_BR5
4377 #define GPIO_BRR_BR_6                       GPIO_BRR_BR6
4378 #define GPIO_BRR_BR_7                       GPIO_BRR_BR7
4379 #define GPIO_BRR_BR_8                       GPIO_BRR_BR8
4380 #define GPIO_BRR_BR_9                       GPIO_BRR_BR9
4381 #define GPIO_BRR_BR_10                      GPIO_BRR_BR10
4382 #define GPIO_BRR_BR_11                      GPIO_BRR_BR11
4383 #define GPIO_BRR_BR_12                      GPIO_BRR_BR12
4384 #define GPIO_BRR_BR_13                      GPIO_BRR_BR13
4385 #define GPIO_BRR_BR_14                      GPIO_BRR_BR14
4386 #define GPIO_BRR_BR_15                      GPIO_BRR_BR15
4387 
4388 
4389 
4390 /******************************************************************************/
4391 /*                                                                            */
4392 /*                      Inter-integrated Circuit Interface (I2C)              */
4393 /*                                                                            */
4394 /******************************************************************************/
4395 /*******************  Bit definition for I2C_CR1 register  *******************/
4396 #define I2C_CR1_PE_Pos               (0U)
4397 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
4398 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
4399 #define I2C_CR1_TXIE_Pos             (1U)
4400 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
4401 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
4402 #define I2C_CR1_RXIE_Pos             (2U)
4403 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
4404 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
4405 #define I2C_CR1_ADDRIE_Pos           (3U)
4406 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
4407 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
4408 #define I2C_CR1_NACKIE_Pos           (4U)
4409 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
4410 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
4411 #define I2C_CR1_STOPIE_Pos           (5U)
4412 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
4413 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
4414 #define I2C_CR1_TCIE_Pos             (6U)
4415 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
4416 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
4417 #define I2C_CR1_ERRIE_Pos            (7U)
4418 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
4419 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
4420 #define I2C_CR1_DNF_Pos              (8U)
4421 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
4422 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
4423 #define I2C_CR1_ANFOFF_Pos           (12U)
4424 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
4425 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
4426 #define I2C_CR1_SWRST_Pos            (13U)
4427 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
4428 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
4429 #define I2C_CR1_TXDMAEN_Pos          (14U)
4430 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
4431 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
4432 #define I2C_CR1_RXDMAEN_Pos          (15U)
4433 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
4434 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
4435 #define I2C_CR1_SBC_Pos              (16U)
4436 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
4437 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
4438 #define I2C_CR1_NOSTRETCH_Pos        (17U)
4439 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
4440 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
4441 #define I2C_CR1_WUPEN_Pos            (18U)
4442 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
4443 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
4444 #define I2C_CR1_GCEN_Pos             (19U)
4445 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
4446 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
4447 #define I2C_CR1_SMBHEN_Pos           (20U)
4448 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
4449 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
4450 #define I2C_CR1_SMBDEN_Pos           (21U)
4451 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
4452 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
4453 #define I2C_CR1_ALERTEN_Pos          (22U)
4454 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
4455 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
4456 #define I2C_CR1_PECEN_Pos            (23U)
4457 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
4458 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
4459 
4460 /******************  Bit definition for I2C_CR2 register  ********************/
4461 #define I2C_CR2_SADD_Pos             (0U)
4462 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
4463 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
4464 #define I2C_CR2_RD_WRN_Pos           (10U)
4465 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
4466 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
4467 #define I2C_CR2_ADD10_Pos            (11U)
4468 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
4469 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
4470 #define I2C_CR2_HEAD10R_Pos          (12U)
4471 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
4472 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
4473 #define I2C_CR2_START_Pos            (13U)
4474 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
4475 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
4476 #define I2C_CR2_STOP_Pos             (14U)
4477 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
4478 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
4479 #define I2C_CR2_NACK_Pos             (15U)
4480 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
4481 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
4482 #define I2C_CR2_NBYTES_Pos           (16U)
4483 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
4484 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
4485 #define I2C_CR2_RELOAD_Pos           (24U)
4486 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
4487 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
4488 #define I2C_CR2_AUTOEND_Pos          (25U)
4489 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
4490 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
4491 #define I2C_CR2_PECBYTE_Pos          (26U)
4492 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
4493 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
4494 
4495 /*******************  Bit definition for I2C_OAR1 register  ******************/
4496 #define I2C_OAR1_OA1_Pos             (0U)
4497 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
4498 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
4499 #define I2C_OAR1_OA1MODE_Pos         (10U)
4500 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
4501 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
4502 #define I2C_OAR1_OA1EN_Pos           (15U)
4503 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
4504 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
4505 
4506 /*******************  Bit definition for I2C_OAR2 register  ******************/
4507 #define I2C_OAR2_OA2_Pos             (1U)
4508 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
4509 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
4510 #define I2C_OAR2_OA2MSK_Pos          (8U)
4511 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
4512 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
4513 #define I2C_OAR2_OA2NOMASK           (0x00000000UL)                            /*!< No mask                                        */
4514 #define I2C_OAR2_OA2MASK01_Pos       (8U)
4515 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
4516 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
4517 #define I2C_OAR2_OA2MASK02_Pos       (9U)
4518 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
4519 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
4520 #define I2C_OAR2_OA2MASK03_Pos       (8U)
4521 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
4522 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
4523 #define I2C_OAR2_OA2MASK04_Pos       (10U)
4524 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
4525 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
4526 #define I2C_OAR2_OA2MASK05_Pos       (8U)
4527 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
4528 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
4529 #define I2C_OAR2_OA2MASK06_Pos       (9U)
4530 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
4531 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
4532 #define I2C_OAR2_OA2MASK07_Pos       (8U)
4533 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
4534 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
4535 #define I2C_OAR2_OA2EN_Pos           (15U)
4536 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
4537 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
4538 
4539 /*******************  Bit definition for I2C_TIMINGR register *******************/
4540 #define I2C_TIMINGR_SCLL_Pos         (0U)
4541 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
4542 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
4543 #define I2C_TIMINGR_SCLH_Pos         (8U)
4544 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
4545 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
4546 #define I2C_TIMINGR_SDADEL_Pos       (16U)
4547 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
4548 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
4549 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
4550 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
4551 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
4552 #define I2C_TIMINGR_PRESC_Pos        (28U)
4553 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
4554 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
4555 
4556 /******************* Bit definition for I2C_TIMEOUTR register *******************/
4557 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
4558 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
4559 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
4560 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
4561 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
4562 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
4563 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
4564 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
4565 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
4566 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
4567 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
4568 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
4569 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
4570 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
4571 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
4572 
4573 /******************  Bit definition for I2C_ISR register  *********************/
4574 #define I2C_ISR_TXE_Pos              (0U)
4575 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
4576 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
4577 #define I2C_ISR_TXIS_Pos             (1U)
4578 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
4579 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
4580 #define I2C_ISR_RXNE_Pos             (2U)
4581 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
4582 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
4583 #define I2C_ISR_ADDR_Pos             (3U)
4584 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
4585 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
4586 #define I2C_ISR_NACKF_Pos            (4U)
4587 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
4588 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
4589 #define I2C_ISR_STOPF_Pos            (5U)
4590 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
4591 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
4592 #define I2C_ISR_TC_Pos               (6U)
4593 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
4594 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
4595 #define I2C_ISR_TCR_Pos              (7U)
4596 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
4597 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
4598 #define I2C_ISR_BERR_Pos             (8U)
4599 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
4600 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
4601 #define I2C_ISR_ARLO_Pos             (9U)
4602 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
4603 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
4604 #define I2C_ISR_OVR_Pos              (10U)
4605 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
4606 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
4607 #define I2C_ISR_PECERR_Pos           (11U)
4608 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
4609 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
4610 #define I2C_ISR_TIMEOUT_Pos          (12U)
4611 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
4612 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
4613 #define I2C_ISR_ALERT_Pos            (13U)
4614 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
4615 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
4616 #define I2C_ISR_BUSY_Pos             (15U)
4617 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
4618 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
4619 #define I2C_ISR_DIR_Pos              (16U)
4620 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
4621 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
4622 #define I2C_ISR_ADDCODE_Pos          (17U)
4623 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
4624 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
4625 
4626 /******************  Bit definition for I2C_ICR register  *********************/
4627 #define I2C_ICR_ADDRCF_Pos           (3U)
4628 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
4629 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
4630 #define I2C_ICR_NACKCF_Pos           (4U)
4631 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
4632 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
4633 #define I2C_ICR_STOPCF_Pos           (5U)
4634 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
4635 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
4636 #define I2C_ICR_BERRCF_Pos           (8U)
4637 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
4638 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
4639 #define I2C_ICR_ARLOCF_Pos           (9U)
4640 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
4641 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
4642 #define I2C_ICR_OVRCF_Pos            (10U)
4643 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
4644 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
4645 #define I2C_ICR_PECCF_Pos            (11U)
4646 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
4647 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
4648 #define I2C_ICR_TIMOUTCF_Pos         (12U)
4649 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
4650 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
4651 #define I2C_ICR_ALERTCF_Pos          (13U)
4652 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
4653 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
4654 
4655 /******************  Bit definition for I2C_PECR register  *********************/
4656 #define I2C_PECR_PEC_Pos             (0U)
4657 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
4658 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
4659 
4660 /******************  Bit definition for I2C_RXDR register  *********************/
4661 #define I2C_RXDR_RXDATA_Pos          (0U)
4662 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
4663 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
4664 
4665 /******************  Bit definition for I2C_TXDR register  *********************/
4666 #define I2C_TXDR_TXDATA_Pos          (0U)
4667 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
4668 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
4669 
4670 /******************************************************************************/
4671 /*                                                                            */
4672 /*                           Independent WATCHDOG                             */
4673 /*                                                                            */
4674 /******************************************************************************/
4675 /*******************  Bit definition for IWDG_KR register  ********************/
4676 #define IWDG_KR_KEY_Pos      (0U)
4677 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
4678 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
4679 
4680 /*******************  Bit definition for IWDG_PR register  ********************/
4681 #define IWDG_PR_PR_Pos       (0U)
4682 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
4683 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
4684 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
4685 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
4686 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
4687 
4688 /*******************  Bit definition for IWDG_RLR register  *******************/
4689 #define IWDG_RLR_RL_Pos      (0U)
4690 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
4691 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
4692 
4693 /*******************  Bit definition for IWDG_SR register  ********************/
4694 #define IWDG_SR_PVU_Pos      (0U)
4695 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
4696 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
4697 #define IWDG_SR_RVU_Pos      (1U)
4698 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
4699 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
4700 #define IWDG_SR_WVU_Pos      (2U)
4701 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
4702 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
4703 
4704 /*******************  Bit definition for IWDG_KR register  ********************/
4705 #define IWDG_WINR_WIN_Pos    (0U)
4706 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
4707 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
4708 
4709 /******************************************************************************/
4710 /*                                                                            */
4711 /*                                     Firewall                               */
4712 /*                                                                            */
4713 /******************************************************************************/
4714 
4715 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */
4716 #define FW_CSSA_ADD_Pos      (8U)
4717 #define FW_CSSA_ADD_Msk      (0xFFFFUL << FW_CSSA_ADD_Pos)                     /*!< 0x00FFFF00 */
4718 #define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */
4719 #define FW_CSL_LENG_Pos      (8U)
4720 #define FW_CSL_LENG_Msk      (0x3FFFUL << FW_CSL_LENG_Pos)                     /*!< 0x003FFF00 */
4721 #define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */
4722 #define FW_NVDSSA_ADD_Pos    (8U)
4723 #define FW_NVDSSA_ADD_Msk    (0xFFFFUL << FW_NVDSSA_ADD_Pos)                   /*!< 0x00FFFF00 */
4724 #define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */
4725 #define FW_NVDSL_LENG_Pos    (8U)
4726 #define FW_NVDSL_LENG_Msk    (0x3FFFUL << FW_NVDSL_LENG_Pos)                   /*!< 0x003FFF00 */
4727 #define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */
4728 #define FW_VDSSA_ADD_Pos     (6U)
4729 #define FW_VDSSA_ADD_Msk     (0x7FFUL << FW_VDSSA_ADD_Pos)                     /*!< 0x0001FFC0 */
4730 #define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */
4731 #define FW_VDSL_LENG_Pos     (6U)
4732 #define FW_VDSL_LENG_Msk     (0x7FFUL << FW_VDSL_LENG_Pos)                     /*!< 0x0001FFC0 */
4733 #define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */
4734 
4735 /**************************Bit definition for CR register *********************/
4736 #define FW_CR_FPA_Pos        (0U)
4737 #define FW_CR_FPA_Msk        (0x1UL << FW_CR_FPA_Pos)                          /*!< 0x00000001 */
4738 #define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/
4739 #define FW_CR_VDS_Pos        (1U)
4740 #define FW_CR_VDS_Msk        (0x1UL << FW_CR_VDS_Pos)                          /*!< 0x00000002 */
4741 #define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/
4742 #define FW_CR_VDE_Pos        (2U)
4743 #define FW_CR_VDE_Msk        (0x1UL << FW_CR_VDE_Pos)                          /*!< 0x00000004 */
4744 #define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/
4745 
4746 /******************************************************************************/
4747 /*                                                                            */
4748 /*                             Power Control                                  */
4749 /*                                                                            */
4750 /******************************************************************************/
4751 
4752 /********************  Bit definition for PWR_CR1 register  ********************/
4753 
4754 #define PWR_CR1_LPR_Pos              (14U)
4755 #define PWR_CR1_LPR_Msk              (0x1UL << PWR_CR1_LPR_Pos)                /*!< 0x00004000 */
4756 #define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
4757 #define PWR_CR1_VOS_Pos              (9U)
4758 #define PWR_CR1_VOS_Msk              (0x3UL << PWR_CR1_VOS_Pos)                /*!< 0x00000600 */
4759 #define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
4760 #define PWR_CR1_VOS_0                (0x1UL << PWR_CR1_VOS_Pos)                /*!< 0x00000200 */
4761 #define PWR_CR1_VOS_1                (0x2UL << PWR_CR1_VOS_Pos)                /*!< 0x00000400 */
4762 #define PWR_CR1_DBP_Pos              (8U)
4763 #define PWR_CR1_DBP_Msk              (0x1UL << PWR_CR1_DBP_Pos)                /*!< 0x00000100 */
4764 #define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
4765 #define PWR_CR1_LPMS_Pos             (0U)
4766 #define PWR_CR1_LPMS_Msk             (0x7UL << PWR_CR1_LPMS_Pos)               /*!< 0x00000007 */
4767 #define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
4768 #define PWR_CR1_LPMS_STOP0           (0x00000000UL)                            /*!< Stop 0 mode */
4769 #define PWR_CR1_LPMS_STOP1_Pos       (0U)
4770 #define PWR_CR1_LPMS_STOP1_Msk       (0x1UL << PWR_CR1_LPMS_STOP1_Pos)         /*!< 0x00000001 */
4771 #define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
4772 #define PWR_CR1_LPMS_STOP2_Pos       (1U)
4773 #define PWR_CR1_LPMS_STOP2_Msk       (0x1UL << PWR_CR1_LPMS_STOP2_Pos)         /*!< 0x00000002 */
4774 #define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */
4775 #define PWR_CR1_LPMS_STANDBY_Pos     (0U)
4776 #define PWR_CR1_LPMS_STANDBY_Msk     (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)       /*!< 0x00000003 */
4777 #define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
4778 #define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)
4779 #define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)      /*!< 0x00000004 */
4780 #define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
4781 
4782 
4783 /********************  Bit definition for PWR_CR2 register  ********************/
4784 #define PWR_CR2_USV_Pos              (10U)
4785 #define PWR_CR2_USV_Msk              (0x1UL << PWR_CR2_USV_Pos)                /*!< 0x00000400 */
4786 #define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */
4787 /*!< PVME  Peripheral Voltage Monitor Enable */
4788 #define PWR_CR2_PVME_Pos             (4U)
4789 #define PWR_CR2_PVME_Msk             (0xDUL << PWR_CR2_PVME_Pos)               /*!< 0x000000D0 */
4790 #define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
4791 #define PWR_CR2_PVME4_Pos            (7U)
4792 #define PWR_CR2_PVME4_Msk            (0x1UL << PWR_CR2_PVME4_Pos)              /*!< 0x00000080 */
4793 #define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
4794 #define PWR_CR2_PVME3_Pos            (6U)
4795 #define PWR_CR2_PVME3_Msk            (0x1UL << PWR_CR2_PVME3_Pos)              /*!< 0x00000040 */
4796 #define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
4797 #define PWR_CR2_PVME1_Pos            (4U)
4798 #define PWR_CR2_PVME1_Msk            (0x1UL << PWR_CR2_PVME1_Pos)              /*!< 0x00000010 */
4799 #define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
4800 /*!< PVD level configuration */
4801 #define PWR_CR2_PLS_Pos              (1U)
4802 #define PWR_CR2_PLS_Msk              (0x7UL << PWR_CR2_PLS_Pos)                /*!< 0x0000000E */
4803 #define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
4804 #define PWR_CR2_PLS_LEV0             (0x00000000UL)                            /*!< PVD level 0 */
4805 #define PWR_CR2_PLS_LEV1_Pos         (1U)
4806 #define PWR_CR2_PLS_LEV1_Msk         (0x1UL << PWR_CR2_PLS_LEV1_Pos)           /*!< 0x00000002 */
4807 #define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
4808 #define PWR_CR2_PLS_LEV2_Pos         (2U)
4809 #define PWR_CR2_PLS_LEV2_Msk         (0x1UL << PWR_CR2_PLS_LEV2_Pos)           /*!< 0x00000004 */
4810 #define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
4811 #define PWR_CR2_PLS_LEV3_Pos         (1U)
4812 #define PWR_CR2_PLS_LEV3_Msk         (0x3UL << PWR_CR2_PLS_LEV3_Pos)           /*!< 0x00000006 */
4813 #define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
4814 #define PWR_CR2_PLS_LEV4_Pos         (3U)
4815 #define PWR_CR2_PLS_LEV4_Msk         (0x1UL << PWR_CR2_PLS_LEV4_Pos)           /*!< 0x00000008 */
4816 #define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
4817 #define PWR_CR2_PLS_LEV5_Pos         (1U)
4818 #define PWR_CR2_PLS_LEV5_Msk         (0x5UL << PWR_CR2_PLS_LEV5_Pos)           /*!< 0x0000000A */
4819 #define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
4820 #define PWR_CR2_PLS_LEV6_Pos         (2U)
4821 #define PWR_CR2_PLS_LEV6_Msk         (0x3UL << PWR_CR2_PLS_LEV6_Pos)           /*!< 0x0000000C */
4822 #define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
4823 #define PWR_CR2_PLS_LEV7_Pos         (1U)
4824 #define PWR_CR2_PLS_LEV7_Msk         (0x7UL << PWR_CR2_PLS_LEV7_Pos)           /*!< 0x0000000E */
4825 #define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
4826 #define PWR_CR2_PVDE_Pos             (0U)
4827 #define PWR_CR2_PVDE_Msk             (0x1UL << PWR_CR2_PVDE_Pos)               /*!< 0x00000001 */
4828 #define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
4829 
4830 /********************  Bit definition for PWR_CR3 register  ********************/
4831 #define PWR_CR3_EIWUL_Pos            (15U)
4832 #define PWR_CR3_EIWUL_Msk            (0x1UL << PWR_CR3_EIWUL_Pos)              /*!< 0x00008000 */
4833 #define PWR_CR3_EIWUL                PWR_CR3_EIWUL_Msk                         /*!< Enable Internal Wake-up line */
4834 #define PWR_CR3_ENULP_Pos            (11U)
4835 #define PWR_CR3_ENULP_Msk            (0x1UL << PWR_CR3_ENULP_Pos)              /*!< 0x00000800 */
4836 #define PWR_CR3_ENULP                PWR_CR3_ENULP_Msk                         /*!< Enable ULP BORL, BORH and PVD for STOP2 and Standby modes */
4837 #define PWR_CR3_APC_Pos              (10U)
4838 #define PWR_CR3_APC_Msk              (0x1UL << PWR_CR3_APC_Pos)                /*!< 0x00000400 */
4839 #define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
4840 #define PWR_CR3_RRS_Pos              (8U)
4841 #define PWR_CR3_RRS_Msk              (0x1UL << PWR_CR3_RRS_Pos)                /*!< 0x00000100 */
4842 #define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
4843 #define PWR_CR3_EWUP5_Pos            (4U)
4844 #define PWR_CR3_EWUP5_Msk            (0x1UL << PWR_CR3_EWUP5_Pos)              /*!< 0x00000010 */
4845 #define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
4846 #define PWR_CR3_EWUP4_Pos            (3U)
4847 #define PWR_CR3_EWUP4_Msk            (0x1UL << PWR_CR3_EWUP4_Pos)              /*!< 0x00000008 */
4848 #define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
4849 #define PWR_CR3_EWUP3_Pos            (2U)
4850 #define PWR_CR3_EWUP3_Msk            (0x1UL << PWR_CR3_EWUP3_Pos)              /*!< 0x00000004 */
4851 #define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
4852 #define PWR_CR3_EWUP2_Pos            (1U)
4853 #define PWR_CR3_EWUP2_Msk            (0x1UL << PWR_CR3_EWUP2_Pos)              /*!< 0x00000002 */
4854 #define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
4855 #define PWR_CR3_EWUP1_Pos            (0U)
4856 #define PWR_CR3_EWUP1_Msk            (0x1UL << PWR_CR3_EWUP1_Pos)              /*!< 0x00000001 */
4857 #define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
4858 #define PWR_CR3_EWUP_Pos             (0U)
4859 #define PWR_CR3_EWUP_Msk             (0x1FUL << PWR_CR3_EWUP_Pos)              /*!< 0x0000001F */
4860 #define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
4861 
4862 /* Legacy defines */
4863 #define PWR_CR3_EIWF_Pos             PWR_CR3_EIWUL_Pos
4864 #define PWR_CR3_EIWF_Msk             PWR_CR3_EIWUL_Msk
4865 #define PWR_CR3_EIWF                 PWR_CR3_EIWUL
4866 
4867 
4868 /********************  Bit definition for PWR_CR4 register  ********************/
4869 #define PWR_CR4_EXT_SMPS_ON_Pos      (13U)
4870 #define PWR_CR4_EXT_SMPS_ON_Msk      (0x1UL << PWR_CR4_EXT_SMPS_ON_Pos)         /*!< 0x00002000 */
4871 #define PWR_CR4_EXT_SMPS_ON          PWR_CR4_EXT_SMPS_ON_Msk                   /*!< Inform the internal regulator on external SMPS switch status */
4872 #define PWR_CR4_VBRS_Pos             (9U)
4873 #define PWR_CR4_VBRS_Msk             (0x1UL << PWR_CR4_VBRS_Pos)               /*!< 0x00000200 */
4874 #define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
4875 #define PWR_CR4_VBE_Pos              (8U)
4876 #define PWR_CR4_VBE_Msk              (0x1UL << PWR_CR4_VBE_Pos)                /*!< 0x00000100 */
4877 #define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
4878 #define PWR_CR4_WP5_Pos              (4U)
4879 #define PWR_CR4_WP5_Msk              (0x1UL << PWR_CR4_WP5_Pos)                /*!< 0x00000010 */
4880 #define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
4881 #define PWR_CR4_WP4_Pos              (3U)
4882 #define PWR_CR4_WP4_Msk              (0x1UL << PWR_CR4_WP4_Pos)                /*!< 0x00000008 */
4883 #define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
4884 #define PWR_CR4_WP3_Pos              (2U)
4885 #define PWR_CR4_WP3_Msk              (0x1UL << PWR_CR4_WP3_Pos)                /*!< 0x00000004 */
4886 #define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
4887 #define PWR_CR4_WP2_Pos              (1U)
4888 #define PWR_CR4_WP2_Msk              (0x1UL << PWR_CR4_WP2_Pos)                /*!< 0x00000002 */
4889 #define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
4890 #define PWR_CR4_WP1_Pos              (0U)
4891 #define PWR_CR4_WP1_Msk              (0x1UL << PWR_CR4_WP1_Pos)                /*!< 0x00000001 */
4892 #define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
4893 
4894 /********************  Bit definition for PWR_SR1 register  ********************/
4895 #define PWR_SR1_WUFI_Pos             (15U)
4896 #define PWR_SR1_WUFI_Msk             (0x1UL << PWR_SR1_WUFI_Pos)               /*!< 0x00008000 */
4897 #define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
4898 #define PWR_SR1_EXT_SMPS_RDY_Pos     (13U)
4899 #define PWR_SR1_EXT_SMPS_RDY_Msk     (0x1UL << PWR_SR1_EXT_SMPS_RDY_Pos)        /*!< 0x00002000 */
4900 #define PWR_SR1_EXT_SMPS_RDY         PWR_SR1_EXT_SMPS_RDY_Msk                  /*!< Switching to external SMPS Ready Flag */
4901 #define PWR_SR1_SBF_Pos              (8U)
4902 #define PWR_SR1_SBF_Msk              (0x1UL << PWR_SR1_SBF_Pos)                /*!< 0x00000100 */
4903 #define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
4904 #define PWR_SR1_WUF_Pos              (0U)
4905 #define PWR_SR1_WUF_Msk              (0x1FUL << PWR_SR1_WUF_Pos)               /*!< 0x0000001F */
4906 #define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
4907 #define PWR_SR1_WUF5_Pos             (4U)
4908 #define PWR_SR1_WUF5_Msk             (0x1UL << PWR_SR1_WUF5_Pos)               /*!< 0x00000010 */
4909 #define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
4910 #define PWR_SR1_WUF4_Pos             (3U)
4911 #define PWR_SR1_WUF4_Msk             (0x1UL << PWR_SR1_WUF4_Pos)               /*!< 0x00000008 */
4912 #define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
4913 #define PWR_SR1_WUF3_Pos             (2U)
4914 #define PWR_SR1_WUF3_Msk             (0x1UL << PWR_SR1_WUF3_Pos)               /*!< 0x00000004 */
4915 #define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
4916 #define PWR_SR1_WUF2_Pos             (1U)
4917 #define PWR_SR1_WUF2_Msk             (0x1UL << PWR_SR1_WUF2_Pos)               /*!< 0x00000002 */
4918 #define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
4919 #define PWR_SR1_WUF1_Pos             (0U)
4920 #define PWR_SR1_WUF1_Msk             (0x1UL << PWR_SR1_WUF1_Pos)               /*!< 0x00000001 */
4921 #define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
4922 
4923 /********************  Bit definition for PWR_SR2 register  ********************/
4924 #define PWR_SR2_PVMO4_Pos            (15U)
4925 #define PWR_SR2_PVMO4_Msk            (0x1UL << PWR_SR2_PVMO4_Pos)              /*!< 0x00008000 */
4926 #define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
4927 #define PWR_SR2_PVMO3_Pos            (14U)
4928 #define PWR_SR2_PVMO3_Msk            (0x1UL << PWR_SR2_PVMO3_Pos)              /*!< 0x00004000 */
4929 #define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
4930 #define PWR_SR2_PVMO1_Pos            (12U)
4931 #define PWR_SR2_PVMO1_Msk            (0x1UL << PWR_SR2_PVMO1_Pos)              /*!< 0x00001000 */
4932 #define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
4933 #define PWR_SR2_PVDO_Pos             (11U)
4934 #define PWR_SR2_PVDO_Msk             (0x1UL << PWR_SR2_PVDO_Pos)               /*!< 0x00000800 */
4935 #define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
4936 #define PWR_SR2_VOSF_Pos             (10U)
4937 #define PWR_SR2_VOSF_Msk             (0x1UL << PWR_SR2_VOSF_Pos)               /*!< 0x00000400 */
4938 #define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
4939 #define PWR_SR2_REGLPF_Pos           (9U)
4940 #define PWR_SR2_REGLPF_Msk           (0x1UL << PWR_SR2_REGLPF_Pos)             /*!< 0x00000200 */
4941 #define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
4942 #define PWR_SR2_REGLPS_Pos           (8U)
4943 #define PWR_SR2_REGLPS_Msk           (0x1UL << PWR_SR2_REGLPS_Pos)             /*!< 0x00000100 */
4944 #define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
4945 
4946 /********************  Bit definition for PWR_SCR register  ********************/
4947 #define PWR_SCR_CSBF_Pos             (8U)
4948 #define PWR_SCR_CSBF_Msk             (0x1UL << PWR_SCR_CSBF_Pos)               /*!< 0x00000100 */
4949 #define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
4950 #define PWR_SCR_CWUF_Pos             (0U)
4951 #define PWR_SCR_CWUF_Msk             (0x1FUL << PWR_SCR_CWUF_Pos)              /*!< 0x0000001F */
4952 #define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
4953 #define PWR_SCR_CWUF5_Pos            (4U)
4954 #define PWR_SCR_CWUF5_Msk            (0x1UL << PWR_SCR_CWUF5_Pos)              /*!< 0x00000010 */
4955 #define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
4956 #define PWR_SCR_CWUF4_Pos            (3U)
4957 #define PWR_SCR_CWUF4_Msk            (0x1UL << PWR_SCR_CWUF4_Pos)              /*!< 0x00000008 */
4958 #define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
4959 #define PWR_SCR_CWUF3_Pos            (2U)
4960 #define PWR_SCR_CWUF3_Msk            (0x1UL << PWR_SCR_CWUF3_Pos)              /*!< 0x00000004 */
4961 #define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
4962 #define PWR_SCR_CWUF2_Pos            (1U)
4963 #define PWR_SCR_CWUF2_Msk            (0x1UL << PWR_SCR_CWUF2_Pos)              /*!< 0x00000002 */
4964 #define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
4965 #define PWR_SCR_CWUF1_Pos            (0U)
4966 #define PWR_SCR_CWUF1_Msk            (0x1UL << PWR_SCR_CWUF1_Pos)              /*!< 0x00000001 */
4967 #define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
4968 
4969 /********************  Bit definition for PWR_PUCRA register  ********************/
4970 #define PWR_PUCRA_PA15_Pos           (15U)
4971 #define PWR_PUCRA_PA15_Msk           (0x1UL << PWR_PUCRA_PA15_Pos)             /*!< 0x00008000 */
4972 #define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
4973 #define PWR_PUCRA_PA13_Pos           (13U)
4974 #define PWR_PUCRA_PA13_Msk           (0x1UL << PWR_PUCRA_PA13_Pos)             /*!< 0x00002000 */
4975 #define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
4976 #define PWR_PUCRA_PA12_Pos           (12U)
4977 #define PWR_PUCRA_PA12_Msk           (0x1UL << PWR_PUCRA_PA12_Pos)             /*!< 0x00001000 */
4978 #define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
4979 #define PWR_PUCRA_PA11_Pos           (11U)
4980 #define PWR_PUCRA_PA11_Msk           (0x1UL << PWR_PUCRA_PA11_Pos)             /*!< 0x00000800 */
4981 #define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
4982 #define PWR_PUCRA_PA10_Pos           (10U)
4983 #define PWR_PUCRA_PA10_Msk           (0x1UL << PWR_PUCRA_PA10_Pos)             /*!< 0x00000400 */
4984 #define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
4985 #define PWR_PUCRA_PA9_Pos            (9U)
4986 #define PWR_PUCRA_PA9_Msk            (0x1UL << PWR_PUCRA_PA9_Pos)              /*!< 0x00000200 */
4987 #define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
4988 #define PWR_PUCRA_PA8_Pos            (8U)
4989 #define PWR_PUCRA_PA8_Msk            (0x1UL << PWR_PUCRA_PA8_Pos)              /*!< 0x00000100 */
4990 #define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
4991 #define PWR_PUCRA_PA7_Pos            (7U)
4992 #define PWR_PUCRA_PA7_Msk            (0x1UL << PWR_PUCRA_PA7_Pos)              /*!< 0x00000080 */
4993 #define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
4994 #define PWR_PUCRA_PA6_Pos            (6U)
4995 #define PWR_PUCRA_PA6_Msk            (0x1UL << PWR_PUCRA_PA6_Pos)              /*!< 0x00000040 */
4996 #define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
4997 #define PWR_PUCRA_PA5_Pos            (5U)
4998 #define PWR_PUCRA_PA5_Msk            (0x1UL << PWR_PUCRA_PA5_Pos)              /*!< 0x00000020 */
4999 #define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
5000 #define PWR_PUCRA_PA4_Pos            (4U)
5001 #define PWR_PUCRA_PA4_Msk            (0x1UL << PWR_PUCRA_PA4_Pos)              /*!< 0x00000010 */
5002 #define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
5003 #define PWR_PUCRA_PA3_Pos            (3U)
5004 #define PWR_PUCRA_PA3_Msk            (0x1UL << PWR_PUCRA_PA3_Pos)              /*!< 0x00000008 */
5005 #define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
5006 #define PWR_PUCRA_PA2_Pos            (2U)
5007 #define PWR_PUCRA_PA2_Msk            (0x1UL << PWR_PUCRA_PA2_Pos)              /*!< 0x00000004 */
5008 #define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
5009 #define PWR_PUCRA_PA1_Pos            (1U)
5010 #define PWR_PUCRA_PA1_Msk            (0x1UL << PWR_PUCRA_PA1_Pos)              /*!< 0x00000002 */
5011 #define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
5012 #define PWR_PUCRA_PA0_Pos            (0U)
5013 #define PWR_PUCRA_PA0_Msk            (0x1UL << PWR_PUCRA_PA0_Pos)              /*!< 0x00000001 */
5014 #define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
5015 
5016 /********************  Bit definition for PWR_PDCRA register  ********************/
5017 #define PWR_PDCRA_PA14_Pos           (14U)
5018 #define PWR_PDCRA_PA14_Msk           (0x1UL << PWR_PDCRA_PA14_Pos)             /*!< 0x00004000 */
5019 #define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
5020 #define PWR_PDCRA_PA12_Pos           (12U)
5021 #define PWR_PDCRA_PA12_Msk           (0x1UL << PWR_PDCRA_PA12_Pos)             /*!< 0x00001000 */
5022 #define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
5023 #define PWR_PDCRA_PA11_Pos           (11U)
5024 #define PWR_PDCRA_PA11_Msk           (0x1UL << PWR_PDCRA_PA11_Pos)             /*!< 0x00000800 */
5025 #define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
5026 #define PWR_PDCRA_PA10_Pos           (10U)
5027 #define PWR_PDCRA_PA10_Msk           (0x1UL << PWR_PDCRA_PA10_Pos)             /*!< 0x00000400 */
5028 #define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
5029 #define PWR_PDCRA_PA9_Pos            (9U)
5030 #define PWR_PDCRA_PA9_Msk            (0x1UL << PWR_PDCRA_PA9_Pos)              /*!< 0x00000200 */
5031 #define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
5032 #define PWR_PDCRA_PA8_Pos            (8U)
5033 #define PWR_PDCRA_PA8_Msk            (0x1UL << PWR_PDCRA_PA8_Pos)              /*!< 0x00000100 */
5034 #define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
5035 #define PWR_PDCRA_PA7_Pos            (7U)
5036 #define PWR_PDCRA_PA7_Msk            (0x1UL << PWR_PDCRA_PA7_Pos)              /*!< 0x00000080 */
5037 #define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
5038 #define PWR_PDCRA_PA6_Pos            (6U)
5039 #define PWR_PDCRA_PA6_Msk            (0x1UL << PWR_PDCRA_PA6_Pos)              /*!< 0x00000040 */
5040 #define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
5041 #define PWR_PDCRA_PA5_Pos            (5U)
5042 #define PWR_PDCRA_PA5_Msk            (0x1UL << PWR_PDCRA_PA5_Pos)              /*!< 0x00000020 */
5043 #define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
5044 #define PWR_PDCRA_PA4_Pos            (4U)
5045 #define PWR_PDCRA_PA4_Msk            (0x1UL << PWR_PDCRA_PA4_Pos)              /*!< 0x00000010 */
5046 #define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
5047 #define PWR_PDCRA_PA3_Pos            (3U)
5048 #define PWR_PDCRA_PA3_Msk            (0x1UL << PWR_PDCRA_PA3_Pos)              /*!< 0x00000008 */
5049 #define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
5050 #define PWR_PDCRA_PA2_Pos            (2U)
5051 #define PWR_PDCRA_PA2_Msk            (0x1UL << PWR_PDCRA_PA2_Pos)              /*!< 0x00000004 */
5052 #define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
5053 #define PWR_PDCRA_PA1_Pos            (1U)
5054 #define PWR_PDCRA_PA1_Msk            (0x1UL << PWR_PDCRA_PA1_Pos)              /*!< 0x00000002 */
5055 #define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
5056 #define PWR_PDCRA_PA0_Pos            (0U)
5057 #define PWR_PDCRA_PA0_Msk            (0x1UL << PWR_PDCRA_PA0_Pos)              /*!< 0x00000001 */
5058 #define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
5059 
5060 /********************  Bit definition for PWR_PUCRB register  ********************/
5061 #define PWR_PUCRB_PB15_Pos           (15U)
5062 #define PWR_PUCRB_PB15_Msk           (0x1UL << PWR_PUCRB_PB15_Pos)             /*!< 0x00008000 */
5063 #define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
5064 #define PWR_PUCRB_PB14_Pos           (14U)
5065 #define PWR_PUCRB_PB14_Msk           (0x1UL << PWR_PUCRB_PB14_Pos)             /*!< 0x00004000 */
5066 #define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
5067 #define PWR_PUCRB_PB13_Pos           (13U)
5068 #define PWR_PUCRB_PB13_Msk           (0x1UL << PWR_PUCRB_PB13_Pos)             /*!< 0x00002000 */
5069 #define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
5070 #define PWR_PUCRB_PB12_Pos           (12U)
5071 #define PWR_PUCRB_PB12_Msk           (0x1UL << PWR_PUCRB_PB12_Pos)             /*!< 0x00001000 */
5072 #define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
5073 #define PWR_PUCRB_PB11_Pos           (11U)
5074 #define PWR_PUCRB_PB11_Msk           (0x1UL << PWR_PUCRB_PB11_Pos)             /*!< 0x00000800 */
5075 #define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
5076 #define PWR_PUCRB_PB10_Pos           (10U)
5077 #define PWR_PUCRB_PB10_Msk           (0x1UL << PWR_PUCRB_PB10_Pos)             /*!< 0x00000400 */
5078 #define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
5079 #define PWR_PUCRB_PB9_Pos            (9U)
5080 #define PWR_PUCRB_PB9_Msk            (0x1UL << PWR_PUCRB_PB9_Pos)              /*!< 0x00000200 */
5081 #define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
5082 #define PWR_PUCRB_PB8_Pos            (8U)
5083 #define PWR_PUCRB_PB8_Msk            (0x1UL << PWR_PUCRB_PB8_Pos)              /*!< 0x00000100 */
5084 #define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
5085 #define PWR_PUCRB_PB7_Pos            (7U)
5086 #define PWR_PUCRB_PB7_Msk            (0x1UL << PWR_PUCRB_PB7_Pos)              /*!< 0x00000080 */
5087 #define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
5088 #define PWR_PUCRB_PB6_Pos            (6U)
5089 #define PWR_PUCRB_PB6_Msk            (0x1UL << PWR_PUCRB_PB6_Pos)              /*!< 0x00000040 */
5090 #define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
5091 #define PWR_PUCRB_PB5_Pos            (5U)
5092 #define PWR_PUCRB_PB5_Msk            (0x1UL << PWR_PUCRB_PB5_Pos)              /*!< 0x00000020 */
5093 #define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
5094 #define PWR_PUCRB_PB4_Pos            (4U)
5095 #define PWR_PUCRB_PB4_Msk            (0x1UL << PWR_PUCRB_PB4_Pos)              /*!< 0x00000010 */
5096 #define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
5097 #define PWR_PUCRB_PB3_Pos            (3U)
5098 #define PWR_PUCRB_PB3_Msk            (0x1UL << PWR_PUCRB_PB3_Pos)              /*!< 0x00000008 */
5099 #define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
5100 #define PWR_PUCRB_PB2_Pos            (2U)
5101 #define PWR_PUCRB_PB2_Msk            (0x1UL << PWR_PUCRB_PB2_Pos)              /*!< 0x00000004 */
5102 #define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
5103 #define PWR_PUCRB_PB1_Pos            (1U)
5104 #define PWR_PUCRB_PB1_Msk            (0x1UL << PWR_PUCRB_PB1_Pos)              /*!< 0x00000002 */
5105 #define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
5106 #define PWR_PUCRB_PB0_Pos            (0U)
5107 #define PWR_PUCRB_PB0_Msk            (0x1UL << PWR_PUCRB_PB0_Pos)              /*!< 0x00000001 */
5108 #define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
5109 
5110 /********************  Bit definition for PWR_PDCRB register  ********************/
5111 #define PWR_PDCRB_PB15_Pos           (15U)
5112 #define PWR_PDCRB_PB15_Msk           (0x1UL << PWR_PDCRB_PB15_Pos)             /*!< 0x00008000 */
5113 #define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
5114 #define PWR_PDCRB_PB14_Pos           (14U)
5115 #define PWR_PDCRB_PB14_Msk           (0x1UL << PWR_PDCRB_PB14_Pos)             /*!< 0x00004000 */
5116 #define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
5117 #define PWR_PDCRB_PB13_Pos           (13U)
5118 #define PWR_PDCRB_PB13_Msk           (0x1UL << PWR_PDCRB_PB13_Pos)             /*!< 0x00002000 */
5119 #define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
5120 #define PWR_PDCRB_PB12_Pos           (12U)
5121 #define PWR_PDCRB_PB12_Msk           (0x1UL << PWR_PDCRB_PB12_Pos)             /*!< 0x00001000 */
5122 #define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
5123 #define PWR_PDCRB_PB11_Pos           (11U)
5124 #define PWR_PDCRB_PB11_Msk           (0x1UL << PWR_PDCRB_PB11_Pos)             /*!< 0x00000800 */
5125 #define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
5126 #define PWR_PDCRB_PB10_Pos           (10U)
5127 #define PWR_PDCRB_PB10_Msk           (0x1UL << PWR_PDCRB_PB10_Pos)             /*!< 0x00000400 */
5128 #define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
5129 #define PWR_PDCRB_PB9_Pos            (9U)
5130 #define PWR_PDCRB_PB9_Msk            (0x1UL << PWR_PDCRB_PB9_Pos)              /*!< 0x00000200 */
5131 #define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
5132 #define PWR_PDCRB_PB8_Pos            (8U)
5133 #define PWR_PDCRB_PB8_Msk            (0x1UL << PWR_PDCRB_PB8_Pos)              /*!< 0x00000100 */
5134 #define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
5135 #define PWR_PDCRB_PB7_Pos            (7U)
5136 #define PWR_PDCRB_PB7_Msk            (0x1UL << PWR_PDCRB_PB7_Pos)              /*!< 0x00000080 */
5137 #define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
5138 #define PWR_PDCRB_PB6_Pos            (6U)
5139 #define PWR_PDCRB_PB6_Msk            (0x1UL << PWR_PDCRB_PB6_Pos)              /*!< 0x00000040 */
5140 #define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
5141 #define PWR_PDCRB_PB5_Pos            (5U)
5142 #define PWR_PDCRB_PB5_Msk            (0x1UL << PWR_PDCRB_PB5_Pos)              /*!< 0x00000020 */
5143 #define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
5144 #define PWR_PDCRB_PB3_Pos            (3U)
5145 #define PWR_PDCRB_PB3_Msk            (0x1UL << PWR_PDCRB_PB3_Pos)              /*!< 0x00000008 */
5146 #define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
5147 #define PWR_PDCRB_PB2_Pos            (2U)
5148 #define PWR_PDCRB_PB2_Msk            (0x1UL << PWR_PDCRB_PB2_Pos)              /*!< 0x00000004 */
5149 #define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
5150 #define PWR_PDCRB_PB1_Pos            (1U)
5151 #define PWR_PDCRB_PB1_Msk            (0x1UL << PWR_PDCRB_PB1_Pos)              /*!< 0x00000002 */
5152 #define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
5153 #define PWR_PDCRB_PB0_Pos            (0U)
5154 #define PWR_PDCRB_PB0_Msk            (0x1UL << PWR_PDCRB_PB0_Pos)              /*!< 0x00000001 */
5155 #define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
5156 
5157 /********************  Bit definition for PWR_PUCRC register  ********************/
5158 #define PWR_PUCRC_PC15_Pos           (15U)
5159 #define PWR_PUCRC_PC15_Msk           (0x1UL << PWR_PUCRC_PC15_Pos)             /*!< 0x00008000 */
5160 #define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
5161 #define PWR_PUCRC_PC14_Pos           (14U)
5162 #define PWR_PUCRC_PC14_Msk           (0x1UL << PWR_PUCRC_PC14_Pos)             /*!< 0x00004000 */
5163 #define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
5164 #define PWR_PUCRC_PC13_Pos           (13U)
5165 #define PWR_PUCRC_PC13_Msk           (0x1UL << PWR_PUCRC_PC13_Pos)             /*!< 0x00002000 */
5166 #define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
5167 #define PWR_PUCRC_PC12_Pos           (12U)
5168 #define PWR_PUCRC_PC12_Msk           (0x1UL << PWR_PUCRC_PC12_Pos)             /*!< 0x00001000 */
5169 #define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
5170 #define PWR_PUCRC_PC11_Pos           (11U)
5171 #define PWR_PUCRC_PC11_Msk           (0x1UL << PWR_PUCRC_PC11_Pos)             /*!< 0x00000800 */
5172 #define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
5173 #define PWR_PUCRC_PC10_Pos           (10U)
5174 #define PWR_PUCRC_PC10_Msk           (0x1UL << PWR_PUCRC_PC10_Pos)             /*!< 0x00000400 */
5175 #define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
5176 #define PWR_PUCRC_PC9_Pos            (9U)
5177 #define PWR_PUCRC_PC9_Msk            (0x1UL << PWR_PUCRC_PC9_Pos)              /*!< 0x00000200 */
5178 #define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
5179 #define PWR_PUCRC_PC8_Pos            (8U)
5180 #define PWR_PUCRC_PC8_Msk            (0x1UL << PWR_PUCRC_PC8_Pos)              /*!< 0x00000100 */
5181 #define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
5182 #define PWR_PUCRC_PC7_Pos            (7U)
5183 #define PWR_PUCRC_PC7_Msk            (0x1UL << PWR_PUCRC_PC7_Pos)              /*!< 0x00000080 */
5184 #define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
5185 #define PWR_PUCRC_PC6_Pos            (6U)
5186 #define PWR_PUCRC_PC6_Msk            (0x1UL << PWR_PUCRC_PC6_Pos)              /*!< 0x00000040 */
5187 #define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
5188 #define PWR_PUCRC_PC5_Pos            (5U)
5189 #define PWR_PUCRC_PC5_Msk            (0x1UL << PWR_PUCRC_PC5_Pos)              /*!< 0x00000020 */
5190 #define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
5191 #define PWR_PUCRC_PC4_Pos            (4U)
5192 #define PWR_PUCRC_PC4_Msk            (0x1UL << PWR_PUCRC_PC4_Pos)              /*!< 0x00000010 */
5193 #define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
5194 #define PWR_PUCRC_PC3_Pos            (3U)
5195 #define PWR_PUCRC_PC3_Msk            (0x1UL << PWR_PUCRC_PC3_Pos)              /*!< 0x00000008 */
5196 #define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
5197 #define PWR_PUCRC_PC2_Pos            (2U)
5198 #define PWR_PUCRC_PC2_Msk            (0x1UL << PWR_PUCRC_PC2_Pos)              /*!< 0x00000004 */
5199 #define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
5200 #define PWR_PUCRC_PC1_Pos            (1U)
5201 #define PWR_PUCRC_PC1_Msk            (0x1UL << PWR_PUCRC_PC1_Pos)              /*!< 0x00000002 */
5202 #define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
5203 #define PWR_PUCRC_PC0_Pos            (0U)
5204 #define PWR_PUCRC_PC0_Msk            (0x1UL << PWR_PUCRC_PC0_Pos)              /*!< 0x00000001 */
5205 #define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
5206 
5207 /********************  Bit definition for PWR_PDCRC register  ********************/
5208 #define PWR_PDCRC_PC15_Pos           (15U)
5209 #define PWR_PDCRC_PC15_Msk           (0x1UL << PWR_PDCRC_PC15_Pos)             /*!< 0x00008000 */
5210 #define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
5211 #define PWR_PDCRC_PC14_Pos           (14U)
5212 #define PWR_PDCRC_PC14_Msk           (0x1UL << PWR_PDCRC_PC14_Pos)             /*!< 0x00004000 */
5213 #define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
5214 #define PWR_PDCRC_PC13_Pos           (13U)
5215 #define PWR_PDCRC_PC13_Msk           (0x1UL << PWR_PDCRC_PC13_Pos)             /*!< 0x00002000 */
5216 #define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
5217 #define PWR_PDCRC_PC12_Pos           (12U)
5218 #define PWR_PDCRC_PC12_Msk           (0x1UL << PWR_PDCRC_PC12_Pos)             /*!< 0x00001000 */
5219 #define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
5220 #define PWR_PDCRC_PC11_Pos           (11U)
5221 #define PWR_PDCRC_PC11_Msk           (0x1UL << PWR_PDCRC_PC11_Pos)             /*!< 0x00000800 */
5222 #define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
5223 #define PWR_PDCRC_PC10_Pos           (10U)
5224 #define PWR_PDCRC_PC10_Msk           (0x1UL << PWR_PDCRC_PC10_Pos)             /*!< 0x00000400 */
5225 #define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
5226 #define PWR_PDCRC_PC9_Pos            (9U)
5227 #define PWR_PDCRC_PC9_Msk            (0x1UL << PWR_PDCRC_PC9_Pos)              /*!< 0x00000200 */
5228 #define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
5229 #define PWR_PDCRC_PC8_Pos            (8U)
5230 #define PWR_PDCRC_PC8_Msk            (0x1UL << PWR_PDCRC_PC8_Pos)              /*!< 0x00000100 */
5231 #define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
5232 #define PWR_PDCRC_PC7_Pos            (7U)
5233 #define PWR_PDCRC_PC7_Msk            (0x1UL << PWR_PDCRC_PC7_Pos)              /*!< 0x00000080 */
5234 #define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
5235 #define PWR_PDCRC_PC6_Pos            (6U)
5236 #define PWR_PDCRC_PC6_Msk            (0x1UL << PWR_PDCRC_PC6_Pos)              /*!< 0x00000040 */
5237 #define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
5238 #define PWR_PDCRC_PC5_Pos            (5U)
5239 #define PWR_PDCRC_PC5_Msk            (0x1UL << PWR_PDCRC_PC5_Pos)              /*!< 0x00000020 */
5240 #define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
5241 #define PWR_PDCRC_PC4_Pos            (4U)
5242 #define PWR_PDCRC_PC4_Msk            (0x1UL << PWR_PDCRC_PC4_Pos)              /*!< 0x00000010 */
5243 #define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
5244 #define PWR_PDCRC_PC3_Pos            (3U)
5245 #define PWR_PDCRC_PC3_Msk            (0x1UL << PWR_PDCRC_PC3_Pos)              /*!< 0x00000008 */
5246 #define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
5247 #define PWR_PDCRC_PC2_Pos            (2U)
5248 #define PWR_PDCRC_PC2_Msk            (0x1UL << PWR_PDCRC_PC2_Pos)              /*!< 0x00000004 */
5249 #define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
5250 #define PWR_PDCRC_PC1_Pos            (1U)
5251 #define PWR_PDCRC_PC1_Msk            (0x1UL << PWR_PDCRC_PC1_Pos)              /*!< 0x00000002 */
5252 #define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
5253 #define PWR_PDCRC_PC0_Pos            (0U)
5254 #define PWR_PDCRC_PC0_Msk            (0x1UL << PWR_PDCRC_PC0_Pos)              /*!< 0x00000001 */
5255 #define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
5256 
5257 /********************  Bit definition for PWR_PUCRD register  ********************/
5258 #define PWR_PUCRD_PD15_Pos           (15U)
5259 #define PWR_PUCRD_PD15_Msk           (0x1UL << PWR_PUCRD_PD15_Pos)             /*!< 0x00008000 */
5260 #define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
5261 #define PWR_PUCRD_PD14_Pos           (14U)
5262 #define PWR_PUCRD_PD14_Msk           (0x1UL << PWR_PUCRD_PD14_Pos)             /*!< 0x00004000 */
5263 #define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
5264 #define PWR_PUCRD_PD13_Pos           (13U)
5265 #define PWR_PUCRD_PD13_Msk           (0x1UL << PWR_PUCRD_PD13_Pos)             /*!< 0x00002000 */
5266 #define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
5267 #define PWR_PUCRD_PD12_Pos           (12U)
5268 #define PWR_PUCRD_PD12_Msk           (0x1UL << PWR_PUCRD_PD12_Pos)             /*!< 0x00001000 */
5269 #define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
5270 #define PWR_PUCRD_PD11_Pos           (11U)
5271 #define PWR_PUCRD_PD11_Msk           (0x1UL << PWR_PUCRD_PD11_Pos)             /*!< 0x00000800 */
5272 #define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
5273 #define PWR_PUCRD_PD10_Pos           (10U)
5274 #define PWR_PUCRD_PD10_Msk           (0x1UL << PWR_PUCRD_PD10_Pos)             /*!< 0x00000400 */
5275 #define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
5276 #define PWR_PUCRD_PD9_Pos            (9U)
5277 #define PWR_PUCRD_PD9_Msk            (0x1UL << PWR_PUCRD_PD9_Pos)              /*!< 0x00000200 */
5278 #define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
5279 #define PWR_PUCRD_PD8_Pos            (8U)
5280 #define PWR_PUCRD_PD8_Msk            (0x1UL << PWR_PUCRD_PD8_Pos)              /*!< 0x00000100 */
5281 #define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
5282 #define PWR_PUCRD_PD7_Pos            (7U)
5283 #define PWR_PUCRD_PD7_Msk            (0x1UL << PWR_PUCRD_PD7_Pos)              /*!< 0x00000080 */
5284 #define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
5285 #define PWR_PUCRD_PD6_Pos            (6U)
5286 #define PWR_PUCRD_PD6_Msk            (0x1UL << PWR_PUCRD_PD6_Pos)              /*!< 0x00000040 */
5287 #define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
5288 #define PWR_PUCRD_PD5_Pos            (5U)
5289 #define PWR_PUCRD_PD5_Msk            (0x1UL << PWR_PUCRD_PD5_Pos)              /*!< 0x00000020 */
5290 #define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
5291 #define PWR_PUCRD_PD4_Pos            (4U)
5292 #define PWR_PUCRD_PD4_Msk            (0x1UL << PWR_PUCRD_PD4_Pos)              /*!< 0x00000010 */
5293 #define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
5294 #define PWR_PUCRD_PD3_Pos            (3U)
5295 #define PWR_PUCRD_PD3_Msk            (0x1UL << PWR_PUCRD_PD3_Pos)              /*!< 0x00000008 */
5296 #define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
5297 #define PWR_PUCRD_PD2_Pos            (2U)
5298 #define PWR_PUCRD_PD2_Msk            (0x1UL << PWR_PUCRD_PD2_Pos)              /*!< 0x00000004 */
5299 #define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
5300 #define PWR_PUCRD_PD1_Pos            (1U)
5301 #define PWR_PUCRD_PD1_Msk            (0x1UL << PWR_PUCRD_PD1_Pos)              /*!< 0x00000002 */
5302 #define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
5303 #define PWR_PUCRD_PD0_Pos            (0U)
5304 #define PWR_PUCRD_PD0_Msk            (0x1UL << PWR_PUCRD_PD0_Pos)              /*!< 0x00000001 */
5305 #define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
5306 
5307 /********************  Bit definition for PWR_PDCRD register  ********************/
5308 #define PWR_PDCRD_PD15_Pos           (15U)
5309 #define PWR_PDCRD_PD15_Msk           (0x1UL << PWR_PDCRD_PD15_Pos)             /*!< 0x00008000 */
5310 #define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
5311 #define PWR_PDCRD_PD14_Pos           (14U)
5312 #define PWR_PDCRD_PD14_Msk           (0x1UL << PWR_PDCRD_PD14_Pos)             /*!< 0x00004000 */
5313 #define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
5314 #define PWR_PDCRD_PD13_Pos           (13U)
5315 #define PWR_PDCRD_PD13_Msk           (0x1UL << PWR_PDCRD_PD13_Pos)             /*!< 0x00002000 */
5316 #define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
5317 #define PWR_PDCRD_PD12_Pos           (12U)
5318 #define PWR_PDCRD_PD12_Msk           (0x1UL << PWR_PDCRD_PD12_Pos)             /*!< 0x00001000 */
5319 #define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
5320 #define PWR_PDCRD_PD11_Pos           (11U)
5321 #define PWR_PDCRD_PD11_Msk           (0x1UL << PWR_PDCRD_PD11_Pos)             /*!< 0x00000800 */
5322 #define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
5323 #define PWR_PDCRD_PD10_Pos           (10U)
5324 #define PWR_PDCRD_PD10_Msk           (0x1UL << PWR_PDCRD_PD10_Pos)             /*!< 0x00000400 */
5325 #define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
5326 #define PWR_PDCRD_PD9_Pos            (9U)
5327 #define PWR_PDCRD_PD9_Msk            (0x1UL << PWR_PDCRD_PD9_Pos)              /*!< 0x00000200 */
5328 #define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
5329 #define PWR_PDCRD_PD8_Pos            (8U)
5330 #define PWR_PDCRD_PD8_Msk            (0x1UL << PWR_PDCRD_PD8_Pos)              /*!< 0x00000100 */
5331 #define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
5332 #define PWR_PDCRD_PD7_Pos            (7U)
5333 #define PWR_PDCRD_PD7_Msk            (0x1UL << PWR_PDCRD_PD7_Pos)              /*!< 0x00000080 */
5334 #define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
5335 #define PWR_PDCRD_PD6_Pos            (6U)
5336 #define PWR_PDCRD_PD6_Msk            (0x1UL << PWR_PDCRD_PD6_Pos)              /*!< 0x00000040 */
5337 #define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
5338 #define PWR_PDCRD_PD5_Pos            (5U)
5339 #define PWR_PDCRD_PD5_Msk            (0x1UL << PWR_PDCRD_PD5_Pos)              /*!< 0x00000020 */
5340 #define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
5341 #define PWR_PDCRD_PD4_Pos            (4U)
5342 #define PWR_PDCRD_PD4_Msk            (0x1UL << PWR_PDCRD_PD4_Pos)              /*!< 0x00000010 */
5343 #define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
5344 #define PWR_PDCRD_PD3_Pos            (3U)
5345 #define PWR_PDCRD_PD3_Msk            (0x1UL << PWR_PDCRD_PD3_Pos)              /*!< 0x00000008 */
5346 #define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
5347 #define PWR_PDCRD_PD2_Pos            (2U)
5348 #define PWR_PDCRD_PD2_Msk            (0x1UL << PWR_PDCRD_PD2_Pos)              /*!< 0x00000004 */
5349 #define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
5350 #define PWR_PDCRD_PD1_Pos            (1U)
5351 #define PWR_PDCRD_PD1_Msk            (0x1UL << PWR_PDCRD_PD1_Pos)              /*!< 0x00000002 */
5352 #define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
5353 #define PWR_PDCRD_PD0_Pos            (0U)
5354 #define PWR_PDCRD_PD0_Msk            (0x1UL << PWR_PDCRD_PD0_Pos)              /*!< 0x00000001 */
5355 #define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
5356 
5357 
5358 
5359 /********************  Bit definition for PWR_PUCRH register  ********************/
5360 #define PWR_PUCRH_PH3_Pos            (3U)
5361 #define PWR_PUCRH_PH3_Msk            (0x1UL << PWR_PUCRH_PH3_Pos)              /*!< 0x00000008 */
5362 #define PWR_PUCRH_PH3                PWR_PUCRH_PH3_Msk                         /*!< Port PH3 Pull-Up set  */
5363 #define PWR_PUCRH_PH1_Pos            (1U)
5364 #define PWR_PUCRH_PH1_Msk            (0x1UL << PWR_PUCRH_PH1_Pos)              /*!< 0x00000002 */
5365 #define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */
5366 #define PWR_PUCRH_PH0_Pos            (0U)
5367 #define PWR_PUCRH_PH0_Msk            (0x1UL << PWR_PUCRH_PH0_Pos)              /*!< 0x00000001 */
5368 #define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */
5369 
5370 /********************  Bit definition for PWR_PDCRH register  ********************/
5371 #define PWR_PDCRH_PH3_Pos            (3U)
5372 #define PWR_PDCRH_PH3_Msk            (0x1UL << PWR_PDCRH_PH3_Pos)              /*!< 0x00000008 */
5373 #define PWR_PDCRH_PH3                PWR_PDCRH_PH3_Msk                         /*!< Port PH3 Pull-Down set  */
5374 #define PWR_PDCRH_PH1_Pos            (1U)
5375 #define PWR_PDCRH_PH1_Msk            (0x1UL << PWR_PDCRH_PH1_Pos)              /*!< 0x00000002 */
5376 #define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */
5377 #define PWR_PDCRH_PH0_Pos            (0U)
5378 #define PWR_PDCRH_PH0_Msk            (0x1UL << PWR_PDCRH_PH0_Pos)              /*!< 0x00000001 */
5379 #define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */
5380 
5381 
5382 /******************************************************************************/
5383 /*                                                                            */
5384 /*                         Reset and Clock Control                            */
5385 /*                                                                            */
5386 /******************************************************************************/
5387 /*
5388 * @brief Specific device feature definitions  (not present on all devices in the STM32L4 series)
5389 */
5390 #define RCC_HSI48_SUPPORT
5391 
5392 /********************  Bit definition for RCC_CR register  ********************/
5393 #define RCC_CR_MSION_Pos                     (0U)
5394 #define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */
5395 #define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
5396 #define RCC_CR_MSIRDY_Pos                    (1U)
5397 #define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */
5398 #define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
5399 #define RCC_CR_MSIPLLEN_Pos                  (2U)
5400 #define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */
5401 #define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
5402 #define RCC_CR_MSIRGSEL_Pos                  (3U)
5403 #define RCC_CR_MSIRGSEL_Msk                  (0x1UL << RCC_CR_MSIRGSEL_Pos)    /*!< 0x00000008 */
5404 #define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
5405 
5406 /*!< MSIRANGE configuration : 12 frequency ranges available */
5407 #define RCC_CR_MSIRANGE_Pos                  (4U)
5408 #define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
5409 #define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
5410 #define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */
5411 #define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
5412 #define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
5413 #define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */
5414 #define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
5415 #define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */
5416 #define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */
5417 #define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */
5418 #define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
5419 #define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */
5420 #define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */
5421 #define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */
5422 
5423 #define RCC_CR_HSION_Pos                     (8U)
5424 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
5425 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
5426 #define RCC_CR_HSIKERON_Pos                  (9U)
5427 #define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
5428 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
5429 #define RCC_CR_HSIRDY_Pos                    (10U)
5430 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
5431 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
5432 #define RCC_CR_HSIASFS_Pos                   (11U)
5433 #define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */
5434 #define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
5435 
5436 #define RCC_CR_HSEON_Pos                     (16U)
5437 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
5438 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
5439 #define RCC_CR_HSERDY_Pos                    (17U)
5440 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
5441 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
5442 #define RCC_CR_HSEBYP_Pos                    (18U)
5443 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)      /*!< 0x00040000 */
5444 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
5445 #define RCC_CR_CSSON_Pos                     (19U)
5446 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
5447 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
5448 
5449 #define RCC_CR_PLLON_Pos                     (24U)
5450 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
5451 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
5452 #define RCC_CR_PLLRDY_Pos                    (25U)
5453 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
5454 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
5455 
5456 /********************  Bit definition for RCC_ICSCR register  ***************/
5457 /*!< MSICAL configuration */
5458 #define RCC_ICSCR_MSICAL_Pos                 (0U)
5459 #define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */
5460 #define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
5461 #define RCC_ICSCR_MSICAL_0                   (0x01UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000001 */
5462 #define RCC_ICSCR_MSICAL_1                   (0x02UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000002 */
5463 #define RCC_ICSCR_MSICAL_2                   (0x04UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000004 */
5464 #define RCC_ICSCR_MSICAL_3                   (0x08UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000008 */
5465 #define RCC_ICSCR_MSICAL_4                   (0x10UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000010 */
5466 #define RCC_ICSCR_MSICAL_5                   (0x20UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000020 */
5467 #define RCC_ICSCR_MSICAL_6                   (0x40UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000040 */
5468 #define RCC_ICSCR_MSICAL_7                   (0x80UL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x00000080 */
5469 
5470 /*!< MSITRIM configuration */
5471 #define RCC_ICSCR_MSITRIM_Pos                (8U)
5472 #define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
5473 #define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
5474 #define RCC_ICSCR_MSITRIM_0                  (0x01UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */
5475 #define RCC_ICSCR_MSITRIM_1                  (0x02UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */
5476 #define RCC_ICSCR_MSITRIM_2                  (0x04UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */
5477 #define RCC_ICSCR_MSITRIM_3                  (0x08UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */
5478 #define RCC_ICSCR_MSITRIM_4                  (0x10UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */
5479 #define RCC_ICSCR_MSITRIM_5                  (0x20UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */
5480 #define RCC_ICSCR_MSITRIM_6                  (0x40UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */
5481 #define RCC_ICSCR_MSITRIM_7                  (0x80UL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */
5482 
5483 /*!< HSICAL configuration */
5484 #define RCC_ICSCR_HSICAL_Pos                 (16U)
5485 #define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
5486 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
5487 #define RCC_ICSCR_HSICAL_0                   (0x01UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00010000 */
5488 #define RCC_ICSCR_HSICAL_1                   (0x02UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00020000 */
5489 #define RCC_ICSCR_HSICAL_2                   (0x04UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00040000 */
5490 #define RCC_ICSCR_HSICAL_3                   (0x08UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00080000 */
5491 #define RCC_ICSCR_HSICAL_4                   (0x10UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00100000 */
5492 #define RCC_ICSCR_HSICAL_5                   (0x20UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00200000 */
5493 #define RCC_ICSCR_HSICAL_6                   (0x40UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00400000 */
5494 #define RCC_ICSCR_HSICAL_7                   (0x80UL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00800000 */
5495 
5496 /*!< HSITRIM configuration */
5497 #define RCC_ICSCR_HSITRIM_Pos                (24U)
5498 #define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
5499 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
5500 #define RCC_ICSCR_HSITRIM_0                  (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
5501 #define RCC_ICSCR_HSITRIM_1                  (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
5502 #define RCC_ICSCR_HSITRIM_2                  (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
5503 #define RCC_ICSCR_HSITRIM_3                  (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
5504 #define RCC_ICSCR_HSITRIM_4                  (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
5505 #define RCC_ICSCR_HSITRIM_5                  (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
5506 #define RCC_ICSCR_HSITRIM_6                  (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
5507 
5508 /********************  Bit definition for RCC_CFGR register  ******************/
5509 /*!< SW configuration */
5510 #define RCC_CFGR_SW_Pos                      (0U)
5511 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
5512 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
5513 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
5514 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
5515 
5516 #define RCC_CFGR_SW_MSI                      (0x00000000UL)                    /*!< MSI oscillator selection as system clock */
5517 #define RCC_CFGR_SW_HSI                      (0x00000001UL)                    /*!< HSI16 oscillator selection as system clock */
5518 #define RCC_CFGR_SW_HSE                      (0x00000002UL)                    /*!< HSE oscillator selection as system clock */
5519 #define RCC_CFGR_SW_PLL                      (0x00000003UL)                    /*!< PLL selection as system clock */
5520 
5521 /*!< SWS configuration */
5522 #define RCC_CFGR_SWS_Pos                     (2U)
5523 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
5524 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
5525 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
5526 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
5527 
5528 #define RCC_CFGR_SWS_MSI                     (0x00000000UL)                    /*!< MSI oscillator used as system clock */
5529 #define RCC_CFGR_SWS_HSI                     (0x00000004UL)                    /*!< HSI16 oscillator used as system clock */
5530 #define RCC_CFGR_SWS_HSE                     (0x00000008UL)                    /*!< HSE oscillator used as system clock */
5531 #define RCC_CFGR_SWS_PLL                     (0x0000000CUL)                    /*!< PLL used as system clock */
5532 
5533 /*!< HPRE configuration */
5534 #define RCC_CFGR_HPRE_Pos                    (4U)
5535 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
5536 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
5537 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
5538 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
5539 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
5540 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
5541 
5542 #define RCC_CFGR_HPRE_DIV1                   (0x00000000UL)                    /*!< SYSCLK not divided */
5543 #define RCC_CFGR_HPRE_DIV2                   (0x00000080UL)                    /*!< SYSCLK divided by 2 */
5544 #define RCC_CFGR_HPRE_DIV4                   (0x00000090UL)                    /*!< SYSCLK divided by 4 */
5545 #define RCC_CFGR_HPRE_DIV8                   (0x000000A0UL)                    /*!< SYSCLK divided by 8 */
5546 #define RCC_CFGR_HPRE_DIV16                  (0x000000B0UL)                    /*!< SYSCLK divided by 16 */
5547 #define RCC_CFGR_HPRE_DIV64                  (0x000000C0UL)                    /*!< SYSCLK divided by 64 */
5548 #define RCC_CFGR_HPRE_DIV128                 (0x000000D0UL)                    /*!< SYSCLK divided by 128 */
5549 #define RCC_CFGR_HPRE_DIV256                 (0x000000E0UL)                    /*!< SYSCLK divided by 256 */
5550 #define RCC_CFGR_HPRE_DIV512                 (0x000000F0UL)                    /*!< SYSCLK divided by 512 */
5551 
5552 /*!< PPRE1 configuration */
5553 #define RCC_CFGR_PPRE1_Pos                   (8U)
5554 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
5555 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
5556 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
5557 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
5558 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
5559 
5560 #define RCC_CFGR_PPRE1_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */
5561 #define RCC_CFGR_PPRE1_DIV2                  (0x00000400UL)                    /*!< HCLK divided by 2 */
5562 #define RCC_CFGR_PPRE1_DIV4                  (0x00000500UL)                    /*!< HCLK divided by 4 */
5563 #define RCC_CFGR_PPRE1_DIV8                  (0x00000600UL)                    /*!< HCLK divided by 8 */
5564 #define RCC_CFGR_PPRE1_DIV16                 (0x00000700UL)                    /*!< HCLK divided by 16 */
5565 
5566 /*!< PPRE2 configuration */
5567 #define RCC_CFGR_PPRE2_Pos                   (11U)
5568 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
5569 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
5570 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
5571 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
5572 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
5573 
5574 #define RCC_CFGR_PPRE2_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */
5575 #define RCC_CFGR_PPRE2_DIV2                  (0x00002000UL)                    /*!< HCLK divided by 2 */
5576 #define RCC_CFGR_PPRE2_DIV4                  (0x00002800UL)                    /*!< HCLK divided by 4 */
5577 #define RCC_CFGR_PPRE2_DIV8                  (0x00003000UL)                    /*!< HCLK divided by 8 */
5578 #define RCC_CFGR_PPRE2_DIV16                 (0x00003800UL)                    /*!< HCLK divided by 16 */
5579 
5580 #define RCC_CFGR_STOPWUCK_Pos                (15U)
5581 #define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */
5582 #define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
5583 
5584 /*!< MCOSEL configuration */
5585 #define RCC_CFGR_MCOSEL_Pos                  (24U)
5586 #define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
5587 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
5588 #define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
5589 #define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
5590 #define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
5591 #define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
5592 
5593 #define RCC_CFGR_MCOPRE_Pos                  (28U)
5594 #define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
5595 #define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
5596 #define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
5597 #define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
5598 #define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
5599 
5600 #define RCC_CFGR_MCOPRE_DIV1                 (0x00000000UL)                    /*!< MCO is divided by 1 */
5601 #define RCC_CFGR_MCOPRE_DIV2                 (0x10000000UL)                    /*!< MCO is divided by 2 */
5602 #define RCC_CFGR_MCOPRE_DIV4                 (0x20000000UL)                    /*!< MCO is divided by 4 */
5603 #define RCC_CFGR_MCOPRE_DIV8                 (0x30000000UL)                    /*!< MCO is divided by 8 */
5604 #define RCC_CFGR_MCOPRE_DIV16                (0x40000000UL)                    /*!< MCO is divided by 16 */
5605 
5606 /* Legacy aliases */
5607 #define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
5608 #define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
5609 #define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
5610 #define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
5611 #define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
5612 #define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
5613 
5614 /********************  Bit definition for RCC_PLLCFGR register  ***************/
5615 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
5616 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
5617 #define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
5618 
5619 #define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)
5620 #define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
5621 #define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
5622 #define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
5623 #define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
5624 #define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
5625 #define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
5626 #define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
5627 #define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
5628 
5629 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
5630 #define RCC_PLLCFGR_PLLM_Msk                 (0x7UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000070 */
5631 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
5632 #define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000010 */
5633 #define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000020 */
5634 #define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x00000040 */
5635 
5636 #define RCC_PLLCFGR_PLLN_Pos                 (8U)
5637 #define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00007F00 */
5638 #define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
5639 #define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000100 */
5640 #define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000200 */
5641 #define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000400 */
5642 #define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00000800 */
5643 #define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00001000 */
5644 #define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00002000 */
5645 #define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)  /*!< 0x00004000 */
5646 
5647 #define RCC_PLLCFGR_PLLQEN_Pos               (20U)
5648 #define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
5649 #define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
5650 
5651 #define RCC_PLLCFGR_PLLQ_Pos                 (21U)
5652 #define RCC_PLLCFGR_PLLQ_Msk                 (0x3UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00600000 */
5653 #define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
5654 #define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00200000 */
5655 #define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)   /*!< 0x00400000 */
5656 
5657 #define RCC_PLLCFGR_PLLREN_Pos               (24U)
5658 #define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
5659 #define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
5660 #define RCC_PLLCFGR_PLLR_Pos                 (25U)
5661 #define RCC_PLLCFGR_PLLR_Msk                 (0x3UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x06000000 */
5662 #define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
5663 #define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x02000000 */
5664 #define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)   /*!< 0x04000000 */
5665 
5666 /********************  Bit definition for RCC_CIER register  ******************/
5667 #define RCC_CIER_LSIRDYIE_Pos                (0U)
5668 #define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
5669 #define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
5670 #define RCC_CIER_LSERDYIE_Pos                (1U)
5671 #define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)  /*!< 0x00000002 */
5672 #define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
5673 #define RCC_CIER_MSIRDYIE_Pos                (2U)
5674 #define RCC_CIER_MSIRDYIE_Msk                (0x1UL << RCC_CIER_MSIRDYIE_Pos)  /*!< 0x00000004 */
5675 #define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk
5676 #define RCC_CIER_HSIRDYIE_Pos                (3U)
5677 #define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)  /*!< 0x00000008 */
5678 #define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
5679 #define RCC_CIER_HSERDYIE_Pos                (4U)
5680 #define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)  /*!< 0x00000010 */
5681 #define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
5682 #define RCC_CIER_PLLRDYIE_Pos                (5U)
5683 #define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)  /*!< 0x00000020 */
5684 #define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
5685 #define RCC_CIER_LSECSSIE_Pos                (9U)
5686 #define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)  /*!< 0x00000200 */
5687 #define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
5688 #define RCC_CIER_HSI48RDYIE_Pos              (10U)
5689 #define RCC_CIER_HSI48RDYIE_Msk              (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
5690 #define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk
5691 
5692 /********************  Bit definition for RCC_CIFR register  ******************/
5693 #define RCC_CIFR_LSIRDYF_Pos                 (0U)
5694 #define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)   /*!< 0x00000001 */
5695 #define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
5696 #define RCC_CIFR_LSERDYF_Pos                 (1U)
5697 #define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
5698 #define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
5699 #define RCC_CIFR_MSIRDYF_Pos                 (2U)
5700 #define RCC_CIFR_MSIRDYF_Msk                 (0x1UL << RCC_CIFR_MSIRDYF_Pos)   /*!< 0x00000004 */
5701 #define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk
5702 #define RCC_CIFR_HSIRDYF_Pos                 (3U)
5703 #define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
5704 #define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
5705 #define RCC_CIFR_HSERDYF_Pos                 (4U)
5706 #define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
5707 #define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
5708 #define RCC_CIFR_PLLRDYF_Pos                 (5U)
5709 #define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)   /*!< 0x00000020 */
5710 #define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
5711 #define RCC_CIFR_CSSF_Pos                    (8U)
5712 #define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)      /*!< 0x00000100 */
5713 #define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
5714 #define RCC_CIFR_LSECSSF_Pos                 (9U)
5715 #define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
5716 #define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
5717 #define RCC_CIFR_HSI48RDYF_Pos               (10U)
5718 #define RCC_CIFR_HSI48RDYF_Msk               (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
5719 #define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk
5720 
5721 /********************  Bit definition for RCC_CICR register  ******************/
5722 #define RCC_CICR_LSIRDYC_Pos                 (0U)
5723 #define RCC_CICR_LSIRDYC_Msk                 (0x1UL << RCC_CICR_LSIRDYC_Pos)   /*!< 0x00000001 */
5724 #define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk
5725 #define RCC_CICR_LSERDYC_Pos                 (1U)
5726 #define RCC_CICR_LSERDYC_Msk                 (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
5727 #define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk
5728 #define RCC_CICR_MSIRDYC_Pos                 (2U)
5729 #define RCC_CICR_MSIRDYC_Msk                 (0x1UL << RCC_CICR_MSIRDYC_Pos)   /*!< 0x00000004 */
5730 #define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk
5731 #define RCC_CICR_HSIRDYC_Pos                 (3U)
5732 #define RCC_CICR_HSIRDYC_Msk                 (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
5733 #define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk
5734 #define RCC_CICR_HSERDYC_Pos                 (4U)
5735 #define RCC_CICR_HSERDYC_Msk                 (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
5736 #define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk
5737 #define RCC_CICR_PLLRDYC_Pos                 (5U)
5738 #define RCC_CICR_PLLRDYC_Msk                 (0x1UL << RCC_CICR_PLLRDYC_Pos)   /*!< 0x00000020 */
5739 #define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk
5740 #define RCC_CICR_CSSC_Pos                    (8U)
5741 #define RCC_CICR_CSSC_Msk                    (0x1UL << RCC_CICR_CSSC_Pos)      /*!< 0x00000100 */
5742 #define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk
5743 #define RCC_CICR_LSECSSC_Pos                 (9U)
5744 #define RCC_CICR_LSECSSC_Msk                 (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
5745 #define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk
5746 #define RCC_CICR_HSI48RDYC_Pos               (10U)
5747 #define RCC_CICR_HSI48RDYC_Msk               (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
5748 #define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk
5749 
5750 /********************  Bit definition for RCC_AHB1RSTR register  **************/
5751 #define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
5752 #define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
5753 #define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
5754 #define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
5755 #define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
5756 #define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
5757 #define RCC_AHB1RSTR_FLASHRST_Pos            (8U)
5758 #define RCC_AHB1RSTR_FLASHRST_Msk            (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
5759 #define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk
5760 #define RCC_AHB1RSTR_CRCRST_Pos              (12U)
5761 #define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
5762 #define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
5763 #define RCC_AHB1RSTR_TSCRST_Pos              (16U)
5764 #define RCC_AHB1RSTR_TSCRST_Msk              (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
5765 #define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk
5766 
5767 /********************  Bit definition for RCC_AHB2RSTR register  **************/
5768 #define RCC_AHB2RSTR_GPIOARST_Pos            (0U)
5769 #define RCC_AHB2RSTR_GPIOARST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
5770 #define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk
5771 #define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)
5772 #define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
5773 #define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk
5774 #define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)
5775 #define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
5776 #define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk
5777 #define RCC_AHB2RSTR_GPIODRST_Pos            (3U)
5778 #define RCC_AHB2RSTR_GPIODRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
5779 #define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk
5780 #define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)
5781 #define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
5782 #define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk
5783 #define RCC_AHB2RSTR_ADCRST_Pos              (13U)
5784 #define RCC_AHB2RSTR_ADCRST_Msk              (0x1UL << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
5785 #define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk
5786 #define RCC_AHB2RSTR_RNGRST_Pos              (18U)
5787 #define RCC_AHB2RSTR_RNGRST_Msk              (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
5788 #define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk
5789 
5790 /********************  Bit definition for RCC_AHB3RSTR register  **************/
5791 #define RCC_AHB3RSTR_QSPIRST_Pos             (8U)
5792 #define RCC_AHB3RSTR_QSPIRST_Msk             (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
5793 #define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk
5794 
5795 /********************  Bit definition for RCC_APB1RSTR1 register  **************/
5796 #define RCC_APB1RSTR1_TIM2RST_Pos            (0U)
5797 #define RCC_APB1RSTR1_TIM2RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
5798 #define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk
5799 #define RCC_APB1RSTR1_TIM6RST_Pos            (4U)
5800 #define RCC_APB1RSTR1_TIM6RST_Msk            (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
5801 #define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk
5802 #define RCC_APB1RSTR1_SPI2RST_Pos            (14U)
5803 #define RCC_APB1RSTR1_SPI2RST_Msk            (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
5804 #define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk
5805 #define RCC_APB1RSTR1_USART2RST_Pos          (17U)
5806 #define RCC_APB1RSTR1_USART2RST_Msk          (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
5807 #define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk
5808 #define RCC_APB1RSTR1_USART3RST_Pos          (18U)
5809 #define RCC_APB1RSTR1_USART3RST_Msk          (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
5810 #define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk
5811 #define RCC_APB1RSTR1_I2C1RST_Pos            (21U)
5812 #define RCC_APB1RSTR1_I2C1RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
5813 #define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk
5814 #define RCC_APB1RSTR1_I2C2RST_Pos            (22U)
5815 #define RCC_APB1RSTR1_I2C2RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
5816 #define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk
5817 #define RCC_APB1RSTR1_I2C3RST_Pos            (23U)
5818 #define RCC_APB1RSTR1_I2C3RST_Msk            (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
5819 #define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk
5820 #define RCC_APB1RSTR1_CRSRST_Pos             (24U)
5821 #define RCC_APB1RSTR1_CRSRST_Msk             (0x1UL << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
5822 #define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk
5823 #define RCC_APB1RSTR1_USBFSRST_Pos           (26U)
5824 #define RCC_APB1RSTR1_USBFSRST_Msk           (0x1UL << RCC_APB1RSTR1_USBFSRST_Pos) /*!< 0x04000000 */
5825 #define RCC_APB1RSTR1_USBFSRST               RCC_APB1RSTR1_USBFSRST_Msk
5826 #define RCC_APB1RSTR1_PWRRST_Pos             (28U)
5827 #define RCC_APB1RSTR1_PWRRST_Msk             (0x1UL << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
5828 #define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk
5829 #define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)
5830 #define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
5831 #define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk
5832 #define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)
5833 #define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
5834 #define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk
5835 
5836 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
5837 #define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)
5838 #define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
5839 #define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk
5840 #define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)
5841 #define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
5842 #define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk
5843 
5844 /********************  Bit definition for RCC_APB2RSTR register  **************/
5845 #define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)
5846 #define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
5847 #define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk
5848 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
5849 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
5850 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk
5851 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
5852 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
5853 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk
5854 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
5855 #define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
5856 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk
5857 #define RCC_APB2RSTR_TIM15RST_Pos            (16U)
5858 #define RCC_APB2RSTR_TIM15RST_Msk            (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
5859 #define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk
5860 #define RCC_APB2RSTR_TIM16RST_Pos            (17U)
5861 #define RCC_APB2RSTR_TIM16RST_Msk            (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
5862 #define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk
5863 
5864 /********************  Bit definition for RCC_AHB1ENR register  ***************/
5865 #define RCC_AHB1ENR_DMA1EN_Pos               (0U)
5866 #define RCC_AHB1ENR_DMA1EN_Msk               (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
5867 #define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk
5868 #define RCC_AHB1ENR_DMA2EN_Pos               (1U)
5869 #define RCC_AHB1ENR_DMA2EN_Msk               (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
5870 #define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk
5871 #define RCC_AHB1ENR_FLASHEN_Pos              (8U)
5872 #define RCC_AHB1ENR_FLASHEN_Msk              (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
5873 #define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk
5874 #define RCC_AHB1ENR_CRCEN_Pos                (12U)
5875 #define RCC_AHB1ENR_CRCEN_Msk                (0x1UL << RCC_AHB1ENR_CRCEN_Pos)  /*!< 0x00001000 */
5876 #define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk
5877 #define RCC_AHB1ENR_TSCEN_Pos                (16U)
5878 #define RCC_AHB1ENR_TSCEN_Msk                (0x1UL << RCC_AHB1ENR_TSCEN_Pos)  /*!< 0x00010000 */
5879 #define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk
5880 
5881 /********************  Bit definition for RCC_AHB2ENR register  ***************/
5882 #define RCC_AHB2ENR_GPIOAEN_Pos              (0U)
5883 #define RCC_AHB2ENR_GPIOAEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
5884 #define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk
5885 #define RCC_AHB2ENR_GPIOBEN_Pos              (1U)
5886 #define RCC_AHB2ENR_GPIOBEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
5887 #define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk
5888 #define RCC_AHB2ENR_GPIOCEN_Pos              (2U)
5889 #define RCC_AHB2ENR_GPIOCEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
5890 #define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk
5891 #define RCC_AHB2ENR_GPIODEN_Pos              (3U)
5892 #define RCC_AHB2ENR_GPIODEN_Msk              (0x1UL << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
5893 #define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk
5894 #define RCC_AHB2ENR_GPIOHEN_Pos              (7U)
5895 #define RCC_AHB2ENR_GPIOHEN_Msk              (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
5896 #define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk
5897 #define RCC_AHB2ENR_ADCEN_Pos                (13U)
5898 #define RCC_AHB2ENR_ADCEN_Msk                (0x1UL << RCC_AHB2ENR_ADCEN_Pos)  /*!< 0x00002000 */
5899 #define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk
5900 #define RCC_AHB2ENR_RNGEN_Pos                (18U)
5901 #define RCC_AHB2ENR_RNGEN_Msk                (0x1UL << RCC_AHB2ENR_RNGEN_Pos)  /*!< 0x00040000 */
5902 #define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk
5903 
5904 /********************  Bit definition for RCC_AHB3ENR register  ***************/
5905 #define RCC_AHB3ENR_QSPIEN_Pos               (8U)
5906 #define RCC_AHB3ENR_QSPIEN_Msk               (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
5907 #define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk
5908 
5909 /********************  Bit definition for RCC_APB1ENR1 register  ***************/
5910 #define RCC_APB1ENR1_TIM2EN_Pos              (0U)
5911 #define RCC_APB1ENR1_TIM2EN_Msk              (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
5912 #define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk
5913 #define RCC_APB1ENR1_TIM6EN_Pos              (4U)
5914 #define RCC_APB1ENR1_TIM6EN_Msk              (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
5915 #define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk
5916 #define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)
5917 #define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
5918 #define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk
5919 #define RCC_APB1ENR1_WWDGEN_Pos              (11U)
5920 #define RCC_APB1ENR1_WWDGEN_Msk              (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
5921 #define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk
5922 #define RCC_APB1ENR1_SPI2EN_Pos              (14U)
5923 #define RCC_APB1ENR1_SPI2EN_Msk              (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
5924 #define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk
5925 #define RCC_APB1ENR1_USART2EN_Pos            (17U)
5926 #define RCC_APB1ENR1_USART2EN_Msk            (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
5927 #define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk
5928 #define RCC_APB1ENR1_USART3EN_Pos            (18U)
5929 #define RCC_APB1ENR1_USART3EN_Msk            (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
5930 #define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk
5931 #define RCC_APB1ENR1_I2C1EN_Pos              (21U)
5932 #define RCC_APB1ENR1_I2C1EN_Msk              (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
5933 #define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk
5934 #define RCC_APB1ENR1_I2C2EN_Pos              (22U)
5935 #define RCC_APB1ENR1_I2C2EN_Msk              (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
5936 #define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk
5937 #define RCC_APB1ENR1_I2C3EN_Pos              (23U)
5938 #define RCC_APB1ENR1_I2C3EN_Msk              (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
5939 #define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk
5940 #define RCC_APB1ENR1_CRSEN_Pos               (24U)
5941 #define RCC_APB1ENR1_CRSEN_Msk               (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */
5942 #define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk
5943 #define RCC_APB1ENR1_USBFSEN_Pos             (26U)
5944 #define RCC_APB1ENR1_USBFSEN_Msk             (0x1UL << RCC_APB1ENR1_USBFSEN_Pos) /*!< 0x04000000 */
5945 #define RCC_APB1ENR1_USBFSEN                 RCC_APB1ENR1_USBFSEN_Msk
5946 #define RCC_APB1ENR1_PWREN_Pos               (28U)
5947 #define RCC_APB1ENR1_PWREN_Msk               (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
5948 #define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk
5949 #define RCC_APB1ENR1_OPAMPEN_Pos             (30U)
5950 #define RCC_APB1ENR1_OPAMPEN_Msk             (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
5951 #define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk
5952 #define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)
5953 #define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
5954 #define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk
5955 
5956 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
5957 #define RCC_APB1ENR2_LPUART1EN_Pos           (0U)
5958 #define RCC_APB1ENR2_LPUART1EN_Msk           (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
5959 #define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk
5960 #define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)
5961 #define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
5962 #define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk
5963 
5964 /********************  Bit definition for RCC_APB2ENR register  ***************/
5965 #define RCC_APB2ENR_SYSCFGEN_Pos             (0U)
5966 #define RCC_APB2ENR_SYSCFGEN_Msk             (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
5967 #define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk
5968 #define RCC_APB2ENR_FWEN_Pos                 (7U)
5969 #define RCC_APB2ENR_FWEN_Msk                 (0x1UL << RCC_APB2ENR_FWEN_Pos)   /*!< 0x00000080 */
5970 #define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk
5971 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
5972 #define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
5973 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk
5974 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
5975 #define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
5976 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk
5977 #define RCC_APB2ENR_USART1EN_Pos             (14U)
5978 #define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
5979 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk
5980 #define RCC_APB2ENR_TIM15EN_Pos              (16U)
5981 #define RCC_APB2ENR_TIM15EN_Msk              (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
5982 #define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk
5983 #define RCC_APB2ENR_TIM16EN_Pos              (17U)
5984 #define RCC_APB2ENR_TIM16EN_Msk              (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
5985 #define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk
5986 
5987 /********************  Bit definition for RCC_AHB1SMENR register  ***************/
5988 #define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)
5989 #define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
5990 #define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk
5991 #define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)
5992 #define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
5993 #define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk
5994 #define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)
5995 #define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
5996 #define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk
5997 #define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)
5998 #define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
5999 #define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk
6000 #define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)
6001 #define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
6002 #define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk
6003 #define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)
6004 #define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
6005 #define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk
6006 
6007 /********************  Bit definition for RCC_AHB2SMENR register  *************/
6008 #define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)
6009 #define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
6010 #define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk
6011 #define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)
6012 #define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
6013 #define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk
6014 #define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)
6015 #define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
6016 #define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk
6017 #define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)
6018 #define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
6019 #define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk
6020 #define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)
6021 #define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
6022 #define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk
6023 #define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)
6024 #define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
6025 #define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk
6026 #define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)
6027 #define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
6028 #define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk
6029 #define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)
6030 #define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
6031 #define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk
6032 
6033 /********************  Bit definition for RCC_AHB3SMENR register  *************/
6034 #define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)
6035 #define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
6036 #define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk
6037 
6038 /********************  Bit definition for RCC_APB1SMENR1 register  *************/
6039 #define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)
6040 #define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
6041 #define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk
6042 #define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)
6043 #define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
6044 #define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk
6045 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)
6046 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
6047 #define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk
6048 #define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)
6049 #define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
6050 #define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk
6051 #define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)
6052 #define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
6053 #define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk
6054 #define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)
6055 #define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
6056 #define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk
6057 #define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)
6058 #define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
6059 #define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk
6060 #define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)
6061 #define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
6062 #define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk
6063 #define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)
6064 #define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
6065 #define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk
6066 #define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)
6067 #define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
6068 #define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk
6069 #define RCC_APB1SMENR1_CRSSMEN_Pos           (24U)
6070 #define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
6071 #define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk
6072 #define RCC_APB1SMENR1_USBFSSMEN_Pos         (26U)
6073 #define RCC_APB1SMENR1_USBFSSMEN_Msk         (0x1UL << RCC_APB1SMENR1_USBFSSMEN_Pos) /*!< 0x04000000 */
6074 #define RCC_APB1SMENR1_USBFSSMEN             RCC_APB1SMENR1_USBFSSMEN_Msk
6075 #define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)
6076 #define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
6077 #define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk
6078 #define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)
6079 #define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1UL << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
6080 #define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk
6081 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)
6082 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
6083 #define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk
6084 
6085 /********************  Bit definition for RCC_APB1SMENR2 register  *************/
6086 #define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)
6087 #define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
6088 #define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk
6089 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)
6090 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
6091 #define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk
6092 
6093 /********************  Bit definition for RCC_APB2SMENR register  *************/
6094 #define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)
6095 #define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
6096 #define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk
6097 #define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)
6098 #define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
6099 #define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk
6100 #define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)
6101 #define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
6102 #define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk
6103 #define RCC_APB2SMENR_USART1SMEN_Pos         (14U)
6104 #define RCC_APB2SMENR_USART1SMEN_Msk         (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
6105 #define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk
6106 #define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)
6107 #define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
6108 #define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk
6109 #define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)
6110 #define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
6111 #define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk
6112 
6113 /********************  Bit definition for RCC_CCIPR register  ******************/
6114 #define RCC_CCIPR_USART1SEL_Pos              (0U)
6115 #define RCC_CCIPR_USART1SEL_Msk              (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
6116 #define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk
6117 #define RCC_CCIPR_USART1SEL_0                (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
6118 #define RCC_CCIPR_USART1SEL_1                (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
6119 
6120 #define RCC_CCIPR_USART2SEL_Pos              (2U)
6121 #define RCC_CCIPR_USART2SEL_Msk              (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
6122 #define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk
6123 #define RCC_CCIPR_USART2SEL_0                (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
6124 #define RCC_CCIPR_USART2SEL_1                (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
6125 
6126 #define RCC_CCIPR_USART3SEL_Pos              (4U)
6127 #define RCC_CCIPR_USART3SEL_Msk              (0x3UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
6128 #define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk
6129 #define RCC_CCIPR_USART3SEL_0                (0x1UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
6130 #define RCC_CCIPR_USART3SEL_1                (0x2UL << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
6131 
6132 #define RCC_CCIPR_LPUART1SEL_Pos             (10U)
6133 #define RCC_CCIPR_LPUART1SEL_Msk             (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
6134 #define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk
6135 #define RCC_CCIPR_LPUART1SEL_0               (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
6136 #define RCC_CCIPR_LPUART1SEL_1               (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
6137 
6138 #define RCC_CCIPR_I2C1SEL_Pos                (12U)
6139 #define RCC_CCIPR_I2C1SEL_Msk                (0x3UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00003000 */
6140 #define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk
6141 #define RCC_CCIPR_I2C1SEL_0                  (0x1UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00001000 */
6142 #define RCC_CCIPR_I2C1SEL_1                  (0x2UL << RCC_CCIPR_I2C1SEL_Pos)  /*!< 0x00002000 */
6143 
6144 #define RCC_CCIPR_I2C2SEL_Pos                (14U)
6145 #define RCC_CCIPR_I2C2SEL_Msk                (0x3UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x0000C000 */
6146 #define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk
6147 #define RCC_CCIPR_I2C2SEL_0                  (0x1UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00004000 */
6148 #define RCC_CCIPR_I2C2SEL_1                  (0x2UL << RCC_CCIPR_I2C2SEL_Pos)  /*!< 0x00008000 */
6149 
6150 #define RCC_CCIPR_I2C3SEL_Pos                (16U)
6151 #define RCC_CCIPR_I2C3SEL_Msk                (0x3UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00030000 */
6152 #define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk
6153 #define RCC_CCIPR_I2C3SEL_0                  (0x1UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00010000 */
6154 #define RCC_CCIPR_I2C3SEL_1                  (0x2UL << RCC_CCIPR_I2C3SEL_Pos)  /*!< 0x00020000 */
6155 
6156 #define RCC_CCIPR_LPTIM1SEL_Pos              (18U)
6157 #define RCC_CCIPR_LPTIM1SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
6158 #define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk
6159 #define RCC_CCIPR_LPTIM1SEL_0                (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
6160 #define RCC_CCIPR_LPTIM1SEL_1                (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
6161 
6162 #define RCC_CCIPR_LPTIM2SEL_Pos              (20U)
6163 #define RCC_CCIPR_LPTIM2SEL_Msk              (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
6164 #define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk
6165 #define RCC_CCIPR_LPTIM2SEL_0                (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
6166 #define RCC_CCIPR_LPTIM2SEL_1                (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
6167 
6168 #define RCC_CCIPR_CLK48SEL_Pos               (26U)
6169 #define RCC_CCIPR_CLK48SEL_Msk               (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
6170 #define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk
6171 #define RCC_CCIPR_CLK48SEL_0                 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
6172 #define RCC_CCIPR_CLK48SEL_1                 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
6173 
6174 
6175 /********************  Bit definition for RCC_BDCR register  ******************/
6176 #define RCC_BDCR_LSEON_Pos                   (0U)
6177 #define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)     /*!< 0x00000001 */
6178 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk
6179 #define RCC_BDCR_LSERDY_Pos                  (1U)
6180 #define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)    /*!< 0x00000002 */
6181 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk
6182 #define RCC_BDCR_LSEBYP_Pos                  (2U)
6183 #define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)    /*!< 0x00000004 */
6184 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk
6185 
6186 #define RCC_BDCR_LSEDRV_Pos                  (3U)
6187 #define RCC_BDCR_LSEDRV_Msk                  (0x3UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000018 */
6188 #define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk
6189 #define RCC_BDCR_LSEDRV_0                    (0x1UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000008 */
6190 #define RCC_BDCR_LSEDRV_1                    (0x2UL << RCC_BDCR_LSEDRV_Pos)    /*!< 0x00000010 */
6191 
6192 #define RCC_BDCR_LSECSSON_Pos                (5U)
6193 #define RCC_BDCR_LSECSSON_Msk                (0x1UL << RCC_BDCR_LSECSSON_Pos)  /*!< 0x00000020 */
6194 #define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk
6195 #define RCC_BDCR_LSECSSD_Pos                 (6U)
6196 #define RCC_BDCR_LSECSSD_Msk                 (0x1UL << RCC_BDCR_LSECSSD_Pos)   /*!< 0x00000040 */
6197 #define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk
6198 
6199 #define RCC_BDCR_LSESYSDIS_Pos               (7U)
6200 #define RCC_BDCR_LSESYSDIS_Msk               (0x1UL << RCC_BDCR_LSESYSDIS_Pos) /*!< 0x00000080 */
6201 #define RCC_BDCR_LSESYSDIS                   RCC_BDCR_LSESYSDIS_Msk
6202 
6203 #define RCC_BDCR_RTCSEL_Pos                  (8U)
6204 #define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000300 */
6205 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk
6206 #define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000100 */
6207 #define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)    /*!< 0x00000200 */
6208 
6209 #define RCC_BDCR_RTCEN_Pos                   (15U)
6210 #define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)     /*!< 0x00008000 */
6211 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk
6212 #define RCC_BDCR_BDRST_Pos                   (16U)
6213 #define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)     /*!< 0x00010000 */
6214 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk
6215 #define RCC_BDCR_LSCOEN_Pos                  (24U)
6216 #define RCC_BDCR_LSCOEN_Msk                  (0x1UL << RCC_BDCR_LSCOEN_Pos)    /*!< 0x01000000 */
6217 #define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk
6218 #define RCC_BDCR_LSCOSEL_Pos                 (25U)
6219 #define RCC_BDCR_LSCOSEL_Msk                 (0x1UL << RCC_BDCR_LSCOSEL_Pos)   /*!< 0x02000000 */
6220 #define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk
6221 
6222 /********************  Bit definition for RCC_CSR register  *******************/
6223 #define RCC_CSR_LSION_Pos                    (0U)
6224 #define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
6225 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk
6226 #define RCC_CSR_LSIRDY_Pos                   (1U)
6227 #define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
6228 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk
6229 
6230 #define RCC_CSR_LSIPREDIV_Pos                (4U)
6231 #define RCC_CSR_LSIPREDIV_Msk                (0x1UL << RCC_CSR_LSIPREDIV_Pos)  /*!< 0x00000010 */
6232 #define RCC_CSR_LSIPREDIV                    RCC_CSR_LSIPREDIV_Msk
6233 
6234 #define RCC_CSR_MSISRANGE_Pos                (8U)
6235 #define RCC_CSR_MSISRANGE_Msk                (0xFUL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000F00 */
6236 #define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk
6237 #define RCC_CSR_MSISRANGE_1                  (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */
6238 #define RCC_CSR_MSISRANGE_2                  (0x5UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000500 */
6239 #define RCC_CSR_MSISRANGE_4                  (0x6UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000600 */
6240 #define RCC_CSR_MSISRANGE_8                  (0x7UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000700 */
6241 
6242 #define RCC_CSR_RMVF_Pos                     (23U)
6243 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */
6244 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk
6245 #define RCC_CSR_FWRSTF_Pos                   (24U)
6246 #define RCC_CSR_FWRSTF_Msk                   (0x1UL << RCC_CSR_FWRSTF_Pos)     /*!< 0x01000000 */
6247 #define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk
6248 #define RCC_CSR_OBLRSTF_Pos                  (25U)
6249 #define RCC_CSR_OBLRSTF_Msk                  (0x1UL << RCC_CSR_OBLRSTF_Pos)    /*!< 0x02000000 */
6250 #define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk
6251 #define RCC_CSR_PINRSTF_Pos                  (26U)
6252 #define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)    /*!< 0x04000000 */
6253 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk
6254 #define RCC_CSR_BORRSTF_Pos                  (27U)
6255 #define RCC_CSR_BORRSTF_Msk                  (0x1UL << RCC_CSR_BORRSTF_Pos)    /*!< 0x08000000 */
6256 #define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk
6257 #define RCC_CSR_SFTRSTF_Pos                  (28U)
6258 #define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)    /*!< 0x10000000 */
6259 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk
6260 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
6261 #define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)   /*!< 0x20000000 */
6262 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk
6263 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
6264 #define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)   /*!< 0x40000000 */
6265 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk
6266 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
6267 #define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)   /*!< 0x80000000 */
6268 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk
6269 
6270 /********************  Bit definition for RCC_CRRCR register  *****************/
6271 #define RCC_CRRCR_HSI48ON_Pos                (0U)
6272 #define RCC_CRRCR_HSI48ON_Msk                (0x1UL << RCC_CRRCR_HSI48ON_Pos)  /*!< 0x00000001 */
6273 #define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk
6274 #define RCC_CRRCR_HSI48RDY_Pos               (1U)
6275 #define RCC_CRRCR_HSI48RDY_Msk               (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
6276 #define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk
6277 
6278 /*!< HSI48CAL configuration */
6279 #define RCC_CRRCR_HSI48CAL_Pos               (7U)
6280 #define RCC_CRRCR_HSI48CAL_Msk               (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
6281 #define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
6282 #define RCC_CRRCR_HSI48CAL_0                 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
6283 #define RCC_CRRCR_HSI48CAL_1                 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
6284 #define RCC_CRRCR_HSI48CAL_2                 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
6285 #define RCC_CRRCR_HSI48CAL_3                 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
6286 #define RCC_CRRCR_HSI48CAL_4                 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
6287 #define RCC_CRRCR_HSI48CAL_5                 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
6288 #define RCC_CRRCR_HSI48CAL_6                 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
6289 #define RCC_CRRCR_HSI48CAL_7                 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
6290 #define RCC_CRRCR_HSI48CAL_8                 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
6291 
6292 /******************************************************************************/
6293 /*                                                                            */
6294 /*                                    RNG                                     */
6295 /*                                                                            */
6296 /******************************************************************************/
6297 /********************  Bits definition for RNG_CR register  *******************/
6298 #define RNG_CR_RNGEN_Pos    (2U)
6299 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
6300 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
6301 #define RNG_CR_IE_Pos       (3U)
6302 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
6303 #define RNG_CR_IE           RNG_CR_IE_Msk
6304 
6305 /********************  Bits definition for RNG_SR register  *******************/
6306 #define RNG_SR_DRDY_Pos     (0U)
6307 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
6308 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
6309 #define RNG_SR_CECS_Pos     (1U)
6310 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
6311 #define RNG_SR_CECS         RNG_SR_CECS_Msk
6312 #define RNG_SR_SECS_Pos     (2U)
6313 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
6314 #define RNG_SR_SECS         RNG_SR_SECS_Msk
6315 #define RNG_SR_CEIS_Pos     (5U)
6316 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
6317 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
6318 #define RNG_SR_SEIS_Pos     (6U)
6319 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
6320 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
6321 
6322 /******************************************************************************/
6323 /*                                                                            */
6324 /*                           Real-Time Clock (RTC)                            */
6325 /*                                                                            */
6326 /******************************************************************************/
6327 /*
6328 * @brief Specific device feature definitions
6329 */
6330 #define RTC_TAMPER1_SUPPORT
6331 #define RTC_TAMPER2_SUPPORT
6332 
6333 #define RTC_WAKEUP_SUPPORT
6334 #define RTC_BACKUP_SUPPORT
6335 /******************** Number of backup registers ******************************/
6336 #define RTC_BKP_NUMBER                32U
6337 
6338 
6339 /********************  Bits definition for RTC_TR register  *******************/
6340 #define RTC_TR_PM_Pos                (22U)
6341 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
6342 #define RTC_TR_PM                    RTC_TR_PM_Msk
6343 #define RTC_TR_HT_Pos                (20U)
6344 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
6345 #define RTC_TR_HT                    RTC_TR_HT_Msk
6346 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
6347 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
6348 #define RTC_TR_HU_Pos                (16U)
6349 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
6350 #define RTC_TR_HU                    RTC_TR_HU_Msk
6351 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
6352 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
6353 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
6354 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
6355 #define RTC_TR_MNT_Pos               (12U)
6356 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
6357 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
6358 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
6359 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
6360 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
6361 #define RTC_TR_MNU_Pos               (8U)
6362 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
6363 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
6364 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
6365 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
6366 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
6367 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
6368 #define RTC_TR_ST_Pos                (4U)
6369 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
6370 #define RTC_TR_ST                    RTC_TR_ST_Msk
6371 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
6372 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
6373 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
6374 #define RTC_TR_SU_Pos                (0U)
6375 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
6376 #define RTC_TR_SU                    RTC_TR_SU_Msk
6377 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
6378 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
6379 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
6380 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
6381 
6382 /********************  Bits definition for RTC_DR register  *******************/
6383 #define RTC_DR_YT_Pos                (20U)
6384 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
6385 #define RTC_DR_YT                    RTC_DR_YT_Msk
6386 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
6387 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
6388 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
6389 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
6390 #define RTC_DR_YU_Pos                (16U)
6391 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
6392 #define RTC_DR_YU                    RTC_DR_YU_Msk
6393 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
6394 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
6395 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
6396 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
6397 #define RTC_DR_WDU_Pos               (13U)
6398 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
6399 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
6400 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
6401 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
6402 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
6403 #define RTC_DR_MT_Pos                (12U)
6404 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
6405 #define RTC_DR_MT                    RTC_DR_MT_Msk
6406 #define RTC_DR_MU_Pos                (8U)
6407 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
6408 #define RTC_DR_MU                    RTC_DR_MU_Msk
6409 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
6410 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
6411 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
6412 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
6413 #define RTC_DR_DT_Pos                (4U)
6414 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
6415 #define RTC_DR_DT                    RTC_DR_DT_Msk
6416 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
6417 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
6418 #define RTC_DR_DU_Pos                (0U)
6419 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
6420 #define RTC_DR_DU                    RTC_DR_DU_Msk
6421 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
6422 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
6423 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
6424 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
6425 
6426 /********************  Bits definition for RTC_SSR register  ******************/
6427 #define RTC_SSR_SS_Pos               (0U)
6428 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
6429 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
6430 
6431 /********************  Bits definition for RTC_ICSR register  ******************/
6432 #define RTC_ICSR_RECALPF_Pos         (16U)
6433 #define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
6434 #define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
6435 #define RTC_ICSR_INIT_Pos            (7U)
6436 #define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
6437 #define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
6438 #define RTC_ICSR_INITF_Pos           (6U)
6439 #define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
6440 #define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
6441 #define RTC_ICSR_RSF_Pos             (5U)
6442 #define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
6443 #define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
6444 #define RTC_ICSR_INITS_Pos           (4U)
6445 #define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
6446 #define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
6447 #define RTC_ICSR_SHPF_Pos            (3U)
6448 #define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
6449 #define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
6450 #define RTC_ICSR_WUTWF_Pos           (2U)
6451 #define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
6452 #define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
6453 
6454 /********************  Bits definition for RTC_PRER register  *****************/
6455 #define RTC_PRER_PREDIV_A_Pos        (16U)
6456 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
6457 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
6458 #define RTC_PRER_PREDIV_S_Pos        (0U)
6459 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
6460 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
6461 
6462 /********************  Bits definition for RTC_WUTR register  *****************/
6463 #define RTC_WUTR_WUTOCLR_Pos         (16U)
6464 #define RTC_WUTR_WUTOCLR_Msk         (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)        /*!< 0xFFFF0000 */
6465 #define RTC_WUTR_WUTOCLR             RTC_WUTR_WUTOCLR_Msk
6466 #define RTC_WUTR_WUT_Pos             (0U)
6467 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
6468 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
6469 
6470 /********************  Bits definition for RTC_CR register  *******************/
6471 #define RTC_CR_OUT2EN_Pos            (31U)
6472 #define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
6473 #define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
6474 #define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
6475 #define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
6476 #define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
6477 #define RTC_CR_TAMPALRM_PU_Pos       (29U)
6478 #define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
6479 #define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
6480 #define RTC_CR_TAMPOE_Pos            (26U)
6481 #define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
6482 #define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
6483 #define RTC_CR_TAMPTS_Pos            (25U)
6484 #define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
6485 #define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
6486 #define RTC_CR_ITSE_Pos              (24U)
6487 #define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
6488 #define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
6489 #define RTC_CR_COE_Pos               (23U)
6490 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
6491 #define RTC_CR_COE                   RTC_CR_COE_Msk
6492 #define RTC_CR_OSEL_Pos              (21U)
6493 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
6494 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
6495 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
6496 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
6497 #define RTC_CR_POL_Pos               (20U)
6498 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
6499 #define RTC_CR_POL                   RTC_CR_POL_Msk
6500 #define RTC_CR_COSEL_Pos             (19U)
6501 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
6502 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
6503 #define RTC_CR_BKP_Pos               (18U)
6504 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
6505 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
6506 #define RTC_CR_SUB1H_Pos             (17U)
6507 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
6508 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
6509 #define RTC_CR_ADD1H_Pos             (16U)
6510 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
6511 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
6512 #define RTC_CR_TSIE_Pos              (15U)
6513 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
6514 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
6515 #define RTC_CR_WUTIE_Pos             (14U)
6516 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
6517 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
6518 #define RTC_CR_ALRBIE_Pos            (13U)
6519 #define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
6520 #define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
6521 #define RTC_CR_ALRAIE_Pos            (12U)
6522 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
6523 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
6524 #define RTC_CR_TSE_Pos               (11U)
6525 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
6526 #define RTC_CR_TSE                   RTC_CR_TSE_Msk
6527 #define RTC_CR_WUTE_Pos              (10U)
6528 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
6529 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
6530 #define RTC_CR_ALRBE_Pos             (9U)
6531 #define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
6532 #define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
6533 #define RTC_CR_ALRAE_Pos             (8U)
6534 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
6535 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
6536 #define RTC_CR_FMT_Pos               (6U)
6537 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
6538 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
6539 #define RTC_CR_BYPSHAD_Pos           (5U)
6540 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
6541 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
6542 #define RTC_CR_REFCKON_Pos           (4U)
6543 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
6544 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
6545 #define RTC_CR_TSEDGE_Pos            (3U)
6546 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
6547 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
6548 #define RTC_CR_WUCKSEL_Pos           (0U)
6549 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
6550 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
6551 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
6552 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
6553 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
6554 
6555 /********************  Bits definition for RTC_WPR register  ******************/
6556 #define RTC_WPR_KEY_Pos              (0U)
6557 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
6558 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
6559 
6560 /********************  Bits definition for RTC_CALR register  *****************/
6561 #define RTC_CALR_CALP_Pos            (15U)
6562 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
6563 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
6564 #define RTC_CALR_CALW8_Pos           (14U)
6565 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
6566 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
6567 #define RTC_CALR_CALW16_Pos          (13U)
6568 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
6569 #define RTC_CALR_LPCAL               RTC_CALR_LPCAL_Msk
6570 #define RTC_CALR_LPCAL_Pos           (12U)
6571 #define RTC_CALR_LPCAL_Msk           (0x1UL << RTC_CALR_LPCAL_Pos)             /*!< 0x00001000 */
6572 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
6573 #define RTC_CALR_CALM_Pos            (0U)
6574 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
6575 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
6576 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
6577 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
6578 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
6579 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
6580 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
6581 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
6582 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
6583 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
6584 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
6585 
6586 /********************  Bits definition for RTC_SHIFTR register  ***************/
6587 #define RTC_SHIFTR_ADD1S_Pos         (31U)
6588 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
6589 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
6590 #define RTC_SHIFTR_SUBFS_Pos         (0U)
6591 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
6592 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
6593 
6594 /********************  Bits definition for RTC_TSTR register  *****************/
6595 #define RTC_TSTR_PM_Pos              (22U)
6596 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
6597 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk
6598 #define RTC_TSTR_HT_Pos              (20U)
6599 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
6600 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
6601 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
6602 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
6603 #define RTC_TSTR_HU_Pos              (16U)
6604 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
6605 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
6606 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
6607 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
6608 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
6609 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
6610 #define RTC_TSTR_MNT_Pos             (12U)
6611 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
6612 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
6613 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
6614 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
6615 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
6616 #define RTC_TSTR_MNU_Pos             (8U)
6617 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
6618 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
6619 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
6620 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
6621 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
6622 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
6623 #define RTC_TSTR_ST_Pos              (4U)
6624 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
6625 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
6626 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
6627 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
6628 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
6629 #define RTC_TSTR_SU_Pos              (0U)
6630 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
6631 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
6632 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
6633 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
6634 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
6635 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
6636 
6637 /********************  Bits definition for RTC_TSDR register  *****************/
6638 #define RTC_TSDR_WDU_Pos             (13U)
6639 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
6640 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk
6641 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
6642 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
6643 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
6644 #define RTC_TSDR_MT_Pos              (12U)
6645 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
6646 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
6647 #define RTC_TSDR_MU_Pos              (8U)
6648 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
6649 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
6650 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
6651 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
6652 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
6653 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
6654 #define RTC_TSDR_DT_Pos              (4U)
6655 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
6656 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
6657 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
6658 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
6659 #define RTC_TSDR_DU_Pos              (0U)
6660 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
6661 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
6662 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
6663 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
6664 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
6665 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
6666 
6667 /********************  Bits definition for RTC_TSSSR register  ****************/
6668 #define RTC_TSSSR_SS_Pos             (0U)
6669 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)             /*!< 0x0000FFFF */
6670 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk
6671 
6672 /********************  Bits definition for RTC_ALRMAR register  ***************/
6673 #define RTC_ALRMAR_MSK4_Pos          (31U)
6674 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
6675 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
6676 #define RTC_ALRMAR_WDSEL_Pos         (30U)
6677 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
6678 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
6679 #define RTC_ALRMAR_DT_Pos            (28U)
6680 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
6681 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
6682 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
6683 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
6684 #define RTC_ALRMAR_DU_Pos            (24U)
6685 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
6686 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
6687 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
6688 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
6689 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
6690 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
6691 #define RTC_ALRMAR_MSK3_Pos          (23U)
6692 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
6693 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
6694 #define RTC_ALRMAR_PM_Pos            (22U)
6695 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
6696 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
6697 #define RTC_ALRMAR_HT_Pos            (20U)
6698 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
6699 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
6700 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
6701 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
6702 #define RTC_ALRMAR_HU_Pos            (16U)
6703 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
6704 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
6705 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
6706 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
6707 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
6708 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
6709 #define RTC_ALRMAR_MSK2_Pos          (15U)
6710 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
6711 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
6712 #define RTC_ALRMAR_MNT_Pos           (12U)
6713 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
6714 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
6715 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
6716 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
6717 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
6718 #define RTC_ALRMAR_MNU_Pos           (8U)
6719 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
6720 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
6721 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
6722 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
6723 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
6724 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
6725 #define RTC_ALRMAR_MSK1_Pos          (7U)
6726 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
6727 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
6728 #define RTC_ALRMAR_ST_Pos            (4U)
6729 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
6730 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
6731 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
6732 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
6733 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
6734 #define RTC_ALRMAR_SU_Pos            (0U)
6735 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
6736 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
6737 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
6738 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
6739 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
6740 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
6741 
6742 /********************  Bits definition for RTC_ALRMASSR register  *************/
6743 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
6744 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)         /*!< 0x0F000000 */
6745 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
6746 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
6747 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
6748 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
6749 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
6750 #define RTC_ALRMASSR_SS_Pos          (0U)
6751 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
6752 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
6753 
6754 /********************  Bits definition for RTC_ALRMBR register  ***************/
6755 #define RTC_ALRMBR_MSK4_Pos          (31U)
6756 #define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
6757 #define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
6758 #define RTC_ALRMBR_WDSEL_Pos         (30U)
6759 #define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
6760 #define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
6761 #define RTC_ALRMBR_DT_Pos            (28U)
6762 #define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
6763 #define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
6764 #define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
6765 #define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
6766 #define RTC_ALRMBR_DU_Pos            (24U)
6767 #define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
6768 #define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
6769 #define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
6770 #define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
6771 #define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
6772 #define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
6773 #define RTC_ALRMBR_MSK3_Pos          (23U)
6774 #define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
6775 #define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
6776 #define RTC_ALRMBR_PM_Pos            (22U)
6777 #define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
6778 #define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
6779 #define RTC_ALRMBR_HT_Pos            (20U)
6780 #define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
6781 #define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
6782 #define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
6783 #define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
6784 #define RTC_ALRMBR_HU_Pos            (16U)
6785 #define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
6786 #define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
6787 #define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
6788 #define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
6789 #define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
6790 #define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
6791 #define RTC_ALRMBR_MSK2_Pos          (15U)
6792 #define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
6793 #define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
6794 #define RTC_ALRMBR_MNT_Pos           (12U)
6795 #define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
6796 #define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
6797 #define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
6798 #define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
6799 #define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
6800 #define RTC_ALRMBR_MNU_Pos           (8U)
6801 #define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
6802 #define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
6803 #define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
6804 #define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
6805 #define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
6806 #define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
6807 #define RTC_ALRMBR_MSK1_Pos          (7U)
6808 #define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
6809 #define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
6810 #define RTC_ALRMBR_ST_Pos            (4U)
6811 #define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
6812 #define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
6813 #define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
6814 #define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
6815 #define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
6816 #define RTC_ALRMBR_SU_Pos            (0U)
6817 #define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
6818 #define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
6819 #define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
6820 #define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
6821 #define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
6822 #define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
6823 
6824 /********************  Bits definition for RTC_ALRMBSSR register  *************/
6825 #define RTC_ALRMBSSR_MASKSS_Pos      (24U)
6826 #define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)         /*!< 0x0F000000 */
6827 #define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
6828 #define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
6829 #define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
6830 #define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
6831 #define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
6832 #define RTC_ALRMBSSR_SS_Pos          (0U)
6833 #define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
6834 #define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
6835 
6836 /********************  Bits definition for RTC_SR register  *******************/
6837 #define RTC_SR_ITSF_Pos              (5U)
6838 #define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
6839 #define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
6840 #define RTC_SR_TSOVF_Pos             (4U)
6841 #define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
6842 #define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
6843 #define RTC_SR_TSF_Pos               (3U)
6844 #define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
6845 #define RTC_SR_TSF                   RTC_SR_TSF_Msk
6846 #define RTC_SR_WUTF_Pos              (2U)
6847 #define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
6848 #define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
6849 #define RTC_SR_ALRBF_Pos             (1U)
6850 #define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
6851 #define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
6852 #define RTC_SR_ALRAF_Pos             (0U)
6853 #define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
6854 #define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
6855 
6856 /********************  Bits definition for RTC_MISR register  *****************/
6857 #define RTC_MISR_ITSMF_Pos           (5U)
6858 #define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
6859 #define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
6860 #define RTC_MISR_TSOVMF_Pos          (4U)
6861 #define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
6862 #define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
6863 #define RTC_MISR_TSMF_Pos            (3U)
6864 #define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
6865 #define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
6866 #define RTC_MISR_WUTMF_Pos           (2U)
6867 #define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
6868 #define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
6869 #define RTC_MISR_ALRBMF_Pos          (1U)
6870 #define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
6871 #define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
6872 #define RTC_MISR_ALRAMF_Pos          (0U)
6873 #define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
6874 #define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
6875 
6876 /********************  Bits definition for RTC_SCR register  ******************/
6877 #define RTC_SCR_CITSF_Pos            (5U)
6878 #define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
6879 #define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
6880 #define RTC_SCR_CTSOVF_Pos           (4U)
6881 #define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
6882 #define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
6883 #define RTC_SCR_CTSF_Pos             (3U)
6884 #define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
6885 #define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
6886 #define RTC_SCR_CWUTF_Pos            (2U)
6887 #define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
6888 #define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
6889 #define RTC_SCR_CALRBF_Pos           (1U)
6890 #define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
6891 #define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
6892 #define RTC_SCR_CALRAF_Pos           (0U)
6893 #define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
6894 #define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
6895 
6896 /******************************************************************************/
6897 /*                                                                            */
6898 /*                     Tamper and backup register (TAMP)                      */
6899 /*                                                                            */
6900 /******************************************************************************/
6901 /********************  Bits definition for TAMP_CR1 register  *****************/
6902 #define TAMP_CR1_TAMP1E_Pos          (0U)
6903 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)             /*!< 0x00000001 */
6904 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
6905 #define TAMP_CR1_TAMP2E_Pos          (1U)
6906 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)             /*!< 0x00000002 */
6907 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
6908 
6909 /********************  Bits definition for TAMP_CR2 register  *****************/
6910 #define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
6911 #define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)       /*!< 0x00000001 */
6912 #define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
6913 #define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
6914 #define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)       /*!< 0x00000002 */
6915 #define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
6916 #define TAMP_CR2_TAMP1MSK_Pos        (16U)
6917 #define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)           /*!< 0x00010000 */
6918 #define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
6919 #define TAMP_CR2_TAMP2MSK_Pos        (17U)
6920 #define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)           /*!< 0x00020000 */
6921 #define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
6922 #define TAMP_CR2_BKERASE_Pos         (23U)
6923 #define TAMP_CR2_BKERASE_Msk         (0x1UL << TAMP_CR2_BKERASE_Pos)            /*!< 0x00800000 */
6924 #define TAMP_CR2_BKERASE             TAMP_CR2_BKERASE_Msk
6925 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
6926 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)           /*!< 0x01000000 */
6927 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
6928 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
6929 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)           /*!< 0x02000000 */
6930 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
6931 
6932 /********************  Bits definition for TAMP_FLTCR register  ***************/
6933 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
6934 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */
6935 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
6936 #define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000001 */
6937 #define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000002 */
6938 #define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000004 */
6939 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
6940 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */
6941 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
6942 #define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000008 */
6943 #define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000010 */
6944 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
6945 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */
6946 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
6947 #define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000020 */
6948 #define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000040 */
6949 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
6950 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */
6951 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
6952 
6953 /********************  Bits definition for TAMP_IER register  *****************/
6954 #define TAMP_IER_TAMP1IE_Pos         (0U)
6955 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)            /*!< 0x00000001 */
6956 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
6957 #define TAMP_IER_TAMP2IE_Pos         (1U)
6958 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)            /*!< 0x00000002 */
6959 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
6960 
6961 /********************  Bits definition for TAMP_SR register  *****************/
6962 #define TAMP_SR_TAMP1F_Pos           (0U)
6963 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)              /*!< 0x00000001 */
6964 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
6965 #define TAMP_SR_TAMP2F_Pos           (1U)
6966 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)              /*!< 0x00000002 */
6967 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
6968 
6969 /********************  Bits definition for TAMP_MISR register  ************ *****/
6970 #define TAMP_MISR_TAMP1MF_Pos        (0U)
6971 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */
6972 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
6973 #define TAMP_MISR_TAMP2MF_Pos        (1U)
6974 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */
6975 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
6976 
6977 
6978 /********************  Bits definition for TAMP_SCR register  *****************/
6979 #define TAMP_SCR_CTAMP1F_Pos         (0U)
6980 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */
6981 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
6982 #define TAMP_SCR_CTAMP2F_Pos         (1U)
6983 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */
6984 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
6985 
6986 
6987 /********************  Bits definition for TAMP_COUNTR register  ***************/
6988 #define TAMP_COUNTR_Pos               (16U)
6989 #define TAMP_COUNTR_Msk               (0xFFFFUL << TAMP_COUNTR_Pos)             /*!< 0xFFFF0000 */
6990 #define TAMP_COUNTR                   TAMP_COUNTR_Msk
6991 
6992 /********************  Bits definition for TAMP_BKP0R register  ***************/
6993 #define TAMP_BKP0R_Pos               (0U)
6994 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */
6995 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
6996 
6997 /********************  Bits definition for TAMP_BKP1R register  ****************/
6998 #define TAMP_BKP1R_Pos               (0U)
6999 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */
7000 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
7001 
7002 /********************  Bits definition for TAMP_BKP2R register  ****************/
7003 #define TAMP_BKP2R_Pos               (0U)
7004 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */
7005 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
7006 
7007 /********************  Bits definition for TAMP_BKP3R register  ****************/
7008 #define TAMP_BKP3R_Pos               (0U)
7009 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */
7010 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
7011 
7012 /********************  Bits definition for TAMP_BKP4R register  ****************/
7013 #define TAMP_BKP4R_Pos               (0U)
7014 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */
7015 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
7016 
7017 /********************  Bits definition for TAMP_BKP5R register  ****************/
7018 #define TAMP_BKP5R_Pos               (0U)
7019 #define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)           /*!< 0xFFFFFFFF */
7020 #define TAMP_BKP5R                   TAMP_BKP5R_Msk
7021 
7022 /********************  Bits definition for TAMP_BKP6R register  ****************/
7023 #define TAMP_BKP6R_Pos               (0U)
7024 #define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)           /*!< 0xFFFFFFFF */
7025 #define TAMP_BKP6R                   TAMP_BKP6R_Msk
7026 
7027 /********************  Bits definition for TAMP_BKP7R register  ****************/
7028 #define TAMP_BKP7R_Pos               (0U)
7029 #define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)           /*!< 0xFFFFFFFF */
7030 #define TAMP_BKP7R                   TAMP_BKP7R_Msk
7031 
7032 /********************  Bits definition for TAMP_BKP8R register  ****************/
7033 #define TAMP_BKP8R_Pos               (0U)
7034 #define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)           /*!< 0xFFFFFFFF */
7035 #define TAMP_BKP8R                   TAMP_BKP8R_Msk
7036 
7037 /********************  Bits definition for TAMP_BKP9R register  ****************/
7038 #define TAMP_BKP9R_Pos               (0U)
7039 #define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)           /*!< 0xFFFFFFFF */
7040 #define TAMP_BKP9R                   TAMP_BKP9R_Msk
7041 
7042 /********************  Bits definition for TAMP_BKP10R register  ***************/
7043 #define TAMP_BKP10R_Pos              (0U)
7044 #define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)          /*!< 0xFFFFFFFF */
7045 #define TAMP_BKP10R                  TAMP_BKP10R_Msk
7046 
7047 /********************  Bits definition for TAMP_BKP11R register  ***************/
7048 #define TAMP_BKP11R_Pos              (0U)
7049 #define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)          /*!< 0xFFFFFFFF */
7050 #define TAMP_BKP11R                  TAMP_BKP11R_Msk
7051 
7052 /********************  Bits definition for TAMP_BKP12R register  ***************/
7053 #define TAMP_BKP12R_Pos              (0U)
7054 #define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)          /*!< 0xFFFFFFFF */
7055 #define TAMP_BKP12R                  TAMP_BKP12R_Msk
7056 
7057 /********************  Bits definition for TAMP_BKP13R register  ***************/
7058 #define TAMP_BKP13R_Pos              (0U)
7059 #define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)          /*!< 0xFFFFFFFF */
7060 #define TAMP_BKP13R                  TAMP_BKP13R_Msk
7061 
7062 /********************  Bits definition for TAMP_BKP14R register  ***************/
7063 #define TAMP_BKP14R_Pos              (0U)
7064 #define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */
7065 #define TAMP_BKP14R                  TAMP_BKP14R_Msk
7066 
7067 /********************  Bits definition for TAMP_BKP15R register  ***************/
7068 #define TAMP_BKP15R_Pos              (0U)
7069 #define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */
7070 #define TAMP_BKP15R                  TAMP_BKP15R_Msk
7071 
7072 /********************  Bits definition for TAMP_BKP16R register  ***************/
7073 #define TAMP_BKP16R_Pos              (0U)
7074 #define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */
7075 #define TAMP_BKP16R                  TAMP_BKP16R_Msk
7076 
7077 /********************  Bits definition for TAMP_BKP17R register  ***************/
7078 #define TAMP_BKP17R_Pos              (0U)
7079 #define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */
7080 #define TAMP_BKP17R                  TAMP_BKP17R_Msk
7081 
7082 /********************  Bits definition for TAMP_BKP18R register  ***************/
7083 #define TAMP_BKP18R_Pos              (0U)
7084 #define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */
7085 #define TAMP_BKP18R                  TAMP_BKP18R_Msk
7086 
7087 /********************  Bits definition for TAMP_BKP19R register  ***************/
7088 #define TAMP_BKP19R_Pos              (0U)
7089 #define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */
7090 #define TAMP_BKP19R                  TAMP_BKP19R_Msk
7091 
7092 /********************  Bits definition for TAMP_BKP20R register  ***************/
7093 #define TAMP_BKP20R_Pos              (0U)
7094 #define TAMP_BKP20R_Msk              (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */
7095 #define TAMP_BKP20R                  TAMP_BKP20R_Msk
7096 
7097 /********************  Bits definition for TAMP_BKP21R register  ***************/
7098 #define TAMP_BKP21R_Pos              (0U)
7099 #define TAMP_BKP21R_Msk              (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */
7100 #define TAMP_BKP21R                  TAMP_BKP21R_Msk
7101 
7102 /********************  Bits definition for TAMP_BKP22R register  ***************/
7103 #define TAMP_BKP22R_Pos              (0U)
7104 #define TAMP_BKP22R_Msk              (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */
7105 #define TAMP_BKP22R                  TAMP_BKP22R_Msk
7106 
7107 /********************  Bits definition for TAMP_BKP23R register  ***************/
7108 #define TAMP_BKP23R_Pos              (0U)
7109 #define TAMP_BKP23R_Msk              (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */
7110 #define TAMP_BKP23R                  TAMP_BKP23R_Msk
7111 
7112 /********************  Bits definition for TAMP_BKP24R register  ***************/
7113 #define TAMP_BKP24R_Pos              (0U)
7114 #define TAMP_BKP24R_Msk              (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */
7115 #define TAMP_BKP24R                  TAMP_BKP24R_Msk
7116 
7117 /********************  Bits definition for TAMP_BKP25R register  ***************/
7118 #define TAMP_BKP25R_Pos              (0U)
7119 #define TAMP_BKP25R_Msk              (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */
7120 #define TAMP_BKP25R                  TAMP_BKP25R_Msk
7121 
7122 /********************  Bits definition for TAMP_BKP26R register  ***************/
7123 #define TAMP_BKP26R_Pos              (0U)
7124 #define TAMP_BKP26R_Msk              (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */
7125 #define TAMP_BKP26R                  TAMP_BKP26R_Msk
7126 
7127 /********************  Bits definition for TAMP_BKP27R register  ***************/
7128 #define TAMP_BKP27R_Pos              (0U)
7129 #define TAMP_BKP27R_Msk              (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */
7130 #define TAMP_BKP27R                  TAMP_BKP27R_Msk
7131 
7132 /********************  Bits definition for TAMP_BKP28R register  ***************/
7133 #define TAMP_BKP28R_Pos              (0U)
7134 #define TAMP_BKP28R_Msk              (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */
7135 #define TAMP_BKP28R                  TAMP_BKP28R_Msk
7136 
7137 /********************  Bits definition for TAMP_BKP29R register  ***************/
7138 #define TAMP_BKP29R_Pos              (0U)
7139 #define TAMP_BKP29R_Msk              (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */
7140 #define TAMP_BKP29R                  TAMP_BKP29R_Msk
7141 
7142 /********************  Bits definition for TAMP_BKP30R register  ***************/
7143 #define TAMP_BKP30R_Pos              (0U)
7144 #define TAMP_BKP30R_Msk              (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */
7145 #define TAMP_BKP30R                  TAMP_BKP30R_Msk
7146 
7147 /********************  Bits definition for TAMP_BKP31R register  ***************/
7148 #define TAMP_BKP31R_Pos              (0U)
7149 #define TAMP_BKP31R_Msk              (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */
7150 #define TAMP_BKP31R                  TAMP_BKP31R_Msk
7151 
7152 
7153 /******************************************************************************/
7154 /*                                                                            */
7155 /*                        Serial Peripheral Interface (SPI)                   */
7156 /*                                                                            */
7157 /******************************************************************************/
7158 /*******************  Bit definition for SPI_CR1 register  ********************/
7159 #define SPI_CR1_CPHA_Pos         (0U)
7160 #define SPI_CR1_CPHA_Msk         (0x1UL << SPI_CR1_CPHA_Pos)                   /*!< 0x00000001 */
7161 #define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */
7162 #define SPI_CR1_CPOL_Pos         (1U)
7163 #define SPI_CR1_CPOL_Msk         (0x1UL << SPI_CR1_CPOL_Pos)                   /*!< 0x00000002 */
7164 #define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */
7165 #define SPI_CR1_MSTR_Pos         (2U)
7166 #define SPI_CR1_MSTR_Msk         (0x1UL << SPI_CR1_MSTR_Pos)                   /*!< 0x00000004 */
7167 #define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */
7168 
7169 #define SPI_CR1_BR_Pos           (3U)
7170 #define SPI_CR1_BR_Msk           (0x7UL << SPI_CR1_BR_Pos)                     /*!< 0x00000038 */
7171 #define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */
7172 #define SPI_CR1_BR_0             (0x1UL << SPI_CR1_BR_Pos)                     /*!< 0x00000008 */
7173 #define SPI_CR1_BR_1             (0x2UL << SPI_CR1_BR_Pos)                     /*!< 0x00000010 */
7174 #define SPI_CR1_BR_2             (0x4UL << SPI_CR1_BR_Pos)                     /*!< 0x00000020 */
7175 
7176 #define SPI_CR1_SPE_Pos          (6U)
7177 #define SPI_CR1_SPE_Msk          (0x1UL << SPI_CR1_SPE_Pos)                    /*!< 0x00000040 */
7178 #define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */
7179 #define SPI_CR1_LSBFIRST_Pos     (7U)
7180 #define SPI_CR1_LSBFIRST_Msk     (0x1UL << SPI_CR1_LSBFIRST_Pos)               /*!< 0x00000080 */
7181 #define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */
7182 #define SPI_CR1_SSI_Pos          (8U)
7183 #define SPI_CR1_SSI_Msk          (0x1UL << SPI_CR1_SSI_Pos)                    /*!< 0x00000100 */
7184 #define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */
7185 #define SPI_CR1_SSM_Pos          (9U)
7186 #define SPI_CR1_SSM_Msk          (0x1UL << SPI_CR1_SSM_Pos)                    /*!< 0x00000200 */
7187 #define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */
7188 #define SPI_CR1_RXONLY_Pos       (10U)
7189 #define SPI_CR1_RXONLY_Msk       (0x1UL << SPI_CR1_RXONLY_Pos)                 /*!< 0x00000400 */
7190 #define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */
7191 #define SPI_CR1_CRCL_Pos         (11U)
7192 #define SPI_CR1_CRCL_Msk         (0x1UL << SPI_CR1_CRCL_Pos)                   /*!< 0x00000800 */
7193 #define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */
7194 #define SPI_CR1_CRCNEXT_Pos      (12U)
7195 #define SPI_CR1_CRCNEXT_Msk      (0x1UL << SPI_CR1_CRCNEXT_Pos)                /*!< 0x00001000 */
7196 #define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */
7197 #define SPI_CR1_CRCEN_Pos        (13U)
7198 #define SPI_CR1_CRCEN_Msk        (0x1UL << SPI_CR1_CRCEN_Pos)                  /*!< 0x00002000 */
7199 #define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */
7200 #define SPI_CR1_BIDIOE_Pos       (14U)
7201 #define SPI_CR1_BIDIOE_Msk       (0x1UL << SPI_CR1_BIDIOE_Pos)                 /*!< 0x00004000 */
7202 #define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */
7203 #define SPI_CR1_BIDIMODE_Pos     (15U)
7204 #define SPI_CR1_BIDIMODE_Msk     (0x1UL << SPI_CR1_BIDIMODE_Pos)               /*!< 0x00008000 */
7205 #define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */
7206 
7207 /*******************  Bit definition for SPI_CR2 register  ********************/
7208 #define SPI_CR2_RXDMAEN_Pos      (0U)
7209 #define SPI_CR2_RXDMAEN_Msk      (0x1UL << SPI_CR2_RXDMAEN_Pos)                /*!< 0x00000001 */
7210 #define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */
7211 #define SPI_CR2_TXDMAEN_Pos      (1U)
7212 #define SPI_CR2_TXDMAEN_Msk      (0x1UL << SPI_CR2_TXDMAEN_Pos)                /*!< 0x00000002 */
7213 #define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */
7214 #define SPI_CR2_SSOE_Pos         (2U)
7215 #define SPI_CR2_SSOE_Msk         (0x1UL << SPI_CR2_SSOE_Pos)                   /*!< 0x00000004 */
7216 #define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */
7217 #define SPI_CR2_NSSP_Pos         (3U)
7218 #define SPI_CR2_NSSP_Msk         (0x1UL << SPI_CR2_NSSP_Pos)                   /*!< 0x00000008 */
7219 #define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */
7220 #define SPI_CR2_FRF_Pos          (4U)
7221 #define SPI_CR2_FRF_Msk          (0x1UL << SPI_CR2_FRF_Pos)                    /*!< 0x00000010 */
7222 #define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */
7223 #define SPI_CR2_ERRIE_Pos        (5U)
7224 #define SPI_CR2_ERRIE_Msk        (0x1UL << SPI_CR2_ERRIE_Pos)                  /*!< 0x00000020 */
7225 #define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */
7226 #define SPI_CR2_RXNEIE_Pos       (6U)
7227 #define SPI_CR2_RXNEIE_Msk       (0x1UL << SPI_CR2_RXNEIE_Pos)                 /*!< 0x00000040 */
7228 #define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */
7229 #define SPI_CR2_TXEIE_Pos        (7U)
7230 #define SPI_CR2_TXEIE_Msk        (0x1UL << SPI_CR2_TXEIE_Pos)                  /*!< 0x00000080 */
7231 #define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */
7232 #define SPI_CR2_DS_Pos           (8U)
7233 #define SPI_CR2_DS_Msk           (0xFUL << SPI_CR2_DS_Pos)                     /*!< 0x00000F00 */
7234 #define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */
7235 #define SPI_CR2_DS_0             (0x1UL << SPI_CR2_DS_Pos)                     /*!< 0x00000100 */
7236 #define SPI_CR2_DS_1             (0x2UL << SPI_CR2_DS_Pos)                     /*!< 0x00000200 */
7237 #define SPI_CR2_DS_2             (0x4UL << SPI_CR2_DS_Pos)                     /*!< 0x00000400 */
7238 #define SPI_CR2_DS_3             (0x8UL << SPI_CR2_DS_Pos)                     /*!< 0x00000800 */
7239 #define SPI_CR2_FRXTH_Pos        (12U)
7240 #define SPI_CR2_FRXTH_Msk        (0x1UL << SPI_CR2_FRXTH_Pos)                  /*!< 0x00001000 */
7241 #define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */
7242 #define SPI_CR2_LDMARX_Pos       (13U)
7243 #define SPI_CR2_LDMARX_Msk       (0x1UL << SPI_CR2_LDMARX_Pos)                 /*!< 0x00002000 */
7244 #define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */
7245 #define SPI_CR2_LDMATX_Pos       (14U)
7246 #define SPI_CR2_LDMATX_Msk       (0x1UL << SPI_CR2_LDMATX_Pos)                 /*!< 0x00004000 */
7247 #define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */
7248 
7249 /********************  Bit definition for SPI_SR register  ********************/
7250 #define SPI_SR_RXNE_Pos          (0U)
7251 #define SPI_SR_RXNE_Msk          (0x1UL << SPI_SR_RXNE_Pos)                    /*!< 0x00000001 */
7252 #define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */
7253 #define SPI_SR_TXE_Pos           (1U)
7254 #define SPI_SR_TXE_Msk           (0x1UL << SPI_SR_TXE_Pos)                     /*!< 0x00000002 */
7255 #define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */
7256 #define SPI_SR_CHSIDE_Pos        (2U)
7257 #define SPI_SR_CHSIDE_Msk        (0x1UL << SPI_SR_CHSIDE_Pos)                  /*!< 0x00000004 */
7258 #define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */
7259 #define SPI_SR_UDR_Pos           (3U)
7260 #define SPI_SR_UDR_Msk           (0x1UL << SPI_SR_UDR_Pos)                     /*!< 0x00000008 */
7261 #define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */
7262 #define SPI_SR_CRCERR_Pos        (4U)
7263 #define SPI_SR_CRCERR_Msk        (0x1UL << SPI_SR_CRCERR_Pos)                  /*!< 0x00000010 */
7264 #define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */
7265 #define SPI_SR_MODF_Pos          (5U)
7266 #define SPI_SR_MODF_Msk          (0x1UL << SPI_SR_MODF_Pos)                    /*!< 0x00000020 */
7267 #define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */
7268 #define SPI_SR_OVR_Pos           (6U)
7269 #define SPI_SR_OVR_Msk           (0x1UL << SPI_SR_OVR_Pos)                     /*!< 0x00000040 */
7270 #define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */
7271 #define SPI_SR_BSY_Pos           (7U)
7272 #define SPI_SR_BSY_Msk           (0x1UL << SPI_SR_BSY_Pos)                     /*!< 0x00000080 */
7273 #define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */
7274 #define SPI_SR_FRE_Pos           (8U)
7275 #define SPI_SR_FRE_Msk           (0x1UL << SPI_SR_FRE_Pos)                     /*!< 0x00000100 */
7276 #define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */
7277 #define SPI_SR_FRLVL_Pos         (9U)
7278 #define SPI_SR_FRLVL_Msk         (0x3UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000600 */
7279 #define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */
7280 #define SPI_SR_FRLVL_0           (0x1UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000200 */
7281 #define SPI_SR_FRLVL_1           (0x2UL << SPI_SR_FRLVL_Pos)                   /*!< 0x00000400 */
7282 #define SPI_SR_FTLVL_Pos         (11U)
7283 #define SPI_SR_FTLVL_Msk         (0x3UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00001800 */
7284 #define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */
7285 #define SPI_SR_FTLVL_0           (0x1UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00000800 */
7286 #define SPI_SR_FTLVL_1           (0x2UL << SPI_SR_FTLVL_Pos)                   /*!< 0x00001000 */
7287 
7288 /********************  Bit definition for SPI_DR register  ********************/
7289 #define SPI_DR_DR_Pos            (0U)
7290 #define SPI_DR_DR_Msk            (0xFFFFUL << SPI_DR_DR_Pos)                   /*!< 0x0000FFFF */
7291 #define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */
7292 
7293 /*******************  Bit definition for SPI_CRCPR register  ******************/
7294 #define SPI_CRCPR_CRCPOLY_Pos    (0U)
7295 #define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)           /*!< 0x0000FFFF */
7296 #define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */
7297 
7298 /******************  Bit definition for SPI_RXCRCR register  ******************/
7299 #define SPI_RXCRCR_RXCRC_Pos     (0U)
7300 #define SPI_RXCRCR_RXCRC_Msk     (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)            /*!< 0x0000FFFF */
7301 #define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */
7302 
7303 /******************  Bit definition for SPI_TXCRCR register  ******************/
7304 #define SPI_TXCRCR_TXCRC_Pos     (0U)
7305 #define SPI_TXCRCR_TXCRC_Msk     (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)            /*!< 0x0000FFFF */
7306 #define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */
7307 
7308 /******************************************************************************/
7309 /*                                                                            */
7310 /*                                    QUADSPI                                 */
7311 /*                                                                            */
7312 /******************************************************************************/
7313 /*****************  Bit definition for QUADSPI_CR register  *******************/
7314 #define QUADSPI_CR_EN_Pos              (0U)
7315 #define QUADSPI_CR_EN_Msk              (0x1UL << QUADSPI_CR_EN_Pos)            /*!< 0x00000001 */
7316 #define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
7317 #define QUADSPI_CR_ABORT_Pos           (1U)
7318 #define QUADSPI_CR_ABORT_Msk           (0x1UL << QUADSPI_CR_ABORT_Pos)         /*!< 0x00000002 */
7319 #define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
7320 #define QUADSPI_CR_DMAEN_Pos           (2U)
7321 #define QUADSPI_CR_DMAEN_Msk           (0x1UL << QUADSPI_CR_DMAEN_Pos)         /*!< 0x00000004 */
7322 #define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
7323 #define QUADSPI_CR_TCEN_Pos            (3U)
7324 #define QUADSPI_CR_TCEN_Msk            (0x1UL << QUADSPI_CR_TCEN_Pos)          /*!< 0x00000008 */
7325 #define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
7326 #define QUADSPI_CR_SSHIFT_Pos          (4U)
7327 #define QUADSPI_CR_SSHIFT_Msk          (0x1UL << QUADSPI_CR_SSHIFT_Pos)        /*!< 0x00000010 */
7328 #define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
7329 #define QUADSPI_CR_DFM_Pos             (6U)
7330 #define QUADSPI_CR_DFM_Msk             (0x1UL << QUADSPI_CR_DFM_Pos)           /*!< 0x00000040 */
7331 #define QUADSPI_CR_DFM                 QUADSPI_CR_DFM_Msk                      /*!< Dual-flash mode */
7332 #define QUADSPI_CR_FSEL_Pos            (7U)
7333 #define QUADSPI_CR_FSEL_Msk            (0x1UL << QUADSPI_CR_FSEL_Pos)          /*!< 0x00000080 */
7334 #define QUADSPI_CR_FSEL                QUADSPI_CR_FSEL_Msk                     /*!< Flash memory selection */
7335 #define QUADSPI_CR_FTHRES_Pos          (8U)
7336 #define QUADSPI_CR_FTHRES_Msk          (0xFUL << QUADSPI_CR_FTHRES_Pos)        /*!< 0x00000F00 */
7337 #define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
7338 #define QUADSPI_CR_TEIE_Pos            (16U)
7339 #define QUADSPI_CR_TEIE_Msk            (0x1UL << QUADSPI_CR_TEIE_Pos)          /*!< 0x00010000 */
7340 #define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
7341 #define QUADSPI_CR_TCIE_Pos            (17U)
7342 #define QUADSPI_CR_TCIE_Msk            (0x1UL << QUADSPI_CR_TCIE_Pos)          /*!< 0x00020000 */
7343 #define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
7344 #define QUADSPI_CR_FTIE_Pos            (18U)
7345 #define QUADSPI_CR_FTIE_Msk            (0x1UL << QUADSPI_CR_FTIE_Pos)          /*!< 0x00040000 */
7346 #define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
7347 #define QUADSPI_CR_SMIE_Pos            (19U)
7348 #define QUADSPI_CR_SMIE_Msk            (0x1UL << QUADSPI_CR_SMIE_Pos)          /*!< 0x00080000 */
7349 #define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
7350 #define QUADSPI_CR_TOIE_Pos            (20U)
7351 #define QUADSPI_CR_TOIE_Msk            (0x1UL << QUADSPI_CR_TOIE_Pos)          /*!< 0x00100000 */
7352 #define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
7353 #define QUADSPI_CR_APMS_Pos            (22U)
7354 #define QUADSPI_CR_APMS_Msk            (0x1UL << QUADSPI_CR_APMS_Pos)          /*!< 0x00400000 */
7355 #define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
7356 #define QUADSPI_CR_PMM_Pos             (23U)
7357 #define QUADSPI_CR_PMM_Msk             (0x1UL << QUADSPI_CR_PMM_Pos)           /*!< 0x00800000 */
7358 #define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
7359 #define QUADSPI_CR_PRESCALER_Pos       (24U)
7360 #define QUADSPI_CR_PRESCALER_Msk       (0xFFUL << QUADSPI_CR_PRESCALER_Pos)    /*!< 0xFF000000 */
7361 #define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
7362 
7363 /*****************  Bit definition for QUADSPI_DCR register  ******************/
7364 #define QUADSPI_DCR_CKMODE_Pos         (0U)
7365 #define QUADSPI_DCR_CKMODE_Msk         (0x1UL << QUADSPI_DCR_CKMODE_Pos)       /*!< 0x00000001 */
7366 #define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
7367 #define QUADSPI_DCR_CSHT_Pos           (8U)
7368 #define QUADSPI_DCR_CSHT_Msk           (0x7UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000700 */
7369 #define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
7370 #define QUADSPI_DCR_CSHT_0             (0x1UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000100 */
7371 #define QUADSPI_DCR_CSHT_1             (0x2UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000200 */
7372 #define QUADSPI_DCR_CSHT_2             (0x4UL << QUADSPI_DCR_CSHT_Pos)         /*!< 0x00000400 */
7373 #define QUADSPI_DCR_FSIZE_Pos          (16U)
7374 #define QUADSPI_DCR_FSIZE_Msk          (0x1FUL << QUADSPI_DCR_FSIZE_Pos)       /*!< 0x001F0000 */
7375 #define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
7376 
7377 /******************  Bit definition for QUADSPI_SR register  *******************/
7378 #define QUADSPI_SR_TEF_Pos             (0U)
7379 #define QUADSPI_SR_TEF_Msk             (0x1UL << QUADSPI_SR_TEF_Pos)           /*!< 0x00000001 */
7380 #define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
7381 #define QUADSPI_SR_TCF_Pos             (1U)
7382 #define QUADSPI_SR_TCF_Msk             (0x1UL << QUADSPI_SR_TCF_Pos)           /*!< 0x00000002 */
7383 #define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
7384 #define QUADSPI_SR_FTF_Pos             (2U)
7385 #define QUADSPI_SR_FTF_Msk             (0x1UL << QUADSPI_SR_FTF_Pos)           /*!< 0x00000004 */
7386 #define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
7387 #define QUADSPI_SR_SMF_Pos             (3U)
7388 #define QUADSPI_SR_SMF_Msk             (0x1UL << QUADSPI_SR_SMF_Pos)           /*!< 0x00000008 */
7389 #define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
7390 #define QUADSPI_SR_TOF_Pos             (4U)
7391 #define QUADSPI_SR_TOF_Msk             (0x1UL << QUADSPI_SR_TOF_Pos)           /*!< 0x00000010 */
7392 #define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
7393 #define QUADSPI_SR_BUSY_Pos            (5U)
7394 #define QUADSPI_SR_BUSY_Msk            (0x1UL << QUADSPI_SR_BUSY_Pos)          /*!< 0x00000020 */
7395 #define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
7396 #define QUADSPI_SR_FLEVEL_Pos          (8U)
7397 #define QUADSPI_SR_FLEVEL_Msk          (0x1FUL << QUADSPI_SR_FLEVEL_Pos)       /*!< 0x00001F00 */
7398 #define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
7399 
7400 /******************  Bit definition for QUADSPI_FCR register  ******************/
7401 #define QUADSPI_FCR_CTEF_Pos           (0U)
7402 #define QUADSPI_FCR_CTEF_Msk           (0x1UL << QUADSPI_FCR_CTEF_Pos)         /*!< 0x00000001 */
7403 #define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
7404 #define QUADSPI_FCR_CTCF_Pos           (1U)
7405 #define QUADSPI_FCR_CTCF_Msk           (0x1UL << QUADSPI_FCR_CTCF_Pos)         /*!< 0x00000002 */
7406 #define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
7407 #define QUADSPI_FCR_CSMF_Pos           (3U)
7408 #define QUADSPI_FCR_CSMF_Msk           (0x1UL << QUADSPI_FCR_CSMF_Pos)         /*!< 0x00000008 */
7409 #define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
7410 #define QUADSPI_FCR_CTOF_Pos           (4U)
7411 #define QUADSPI_FCR_CTOF_Msk           (0x1UL << QUADSPI_FCR_CTOF_Pos)         /*!< 0x00000010 */
7412 #define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
7413 
7414 /******************  Bit definition for QUADSPI_DLR register  ******************/
7415 #define QUADSPI_DLR_DL_Pos             (0U)
7416 #define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)    /*!< 0xFFFFFFFF */
7417 #define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
7418 
7419 /******************  Bit definition for QUADSPI_CCR register  ******************/
7420 #define QUADSPI_CCR_INSTRUCTION_Pos    (0U)
7421 #define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
7422 #define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
7423 #define QUADSPI_CCR_IMODE_Pos          (8U)
7424 #define QUADSPI_CCR_IMODE_Msk          (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
7425 #define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
7426 #define QUADSPI_CCR_IMODE_0            (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
7427 #define QUADSPI_CCR_IMODE_1            (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
7428 #define QUADSPI_CCR_ADMODE_Pos         (10U)
7429 #define QUADSPI_CCR_ADMODE_Msk         (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
7430 #define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
7431 #define QUADSPI_CCR_ADMODE_0           (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
7432 #define QUADSPI_CCR_ADMODE_1           (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
7433 #define QUADSPI_CCR_ADSIZE_Pos         (12U)
7434 #define QUADSPI_CCR_ADSIZE_Msk         (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
7435 #define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
7436 #define QUADSPI_CCR_ADSIZE_0           (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
7437 #define QUADSPI_CCR_ADSIZE_1           (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
7438 #define QUADSPI_CCR_ABMODE_Pos         (14U)
7439 #define QUADSPI_CCR_ABMODE_Msk         (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
7440 #define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
7441 #define QUADSPI_CCR_ABMODE_0           (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
7442 #define QUADSPI_CCR_ABMODE_1           (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
7443 #define QUADSPI_CCR_ABSIZE_Pos         (16U)
7444 #define QUADSPI_CCR_ABSIZE_Msk         (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
7445 #define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
7446 #define QUADSPI_CCR_ABSIZE_0           (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
7447 #define QUADSPI_CCR_ABSIZE_1           (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
7448 #define QUADSPI_CCR_DCYC_Pos           (18U)
7449 #define QUADSPI_CCR_DCYC_Msk           (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
7450 #define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
7451 #define QUADSPI_CCR_DMODE_Pos          (24U)
7452 #define QUADSPI_CCR_DMODE_Msk          (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
7453 #define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
7454 #define QUADSPI_CCR_DMODE_0            (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
7455 #define QUADSPI_CCR_DMODE_1            (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
7456 #define QUADSPI_CCR_FMODE_Pos          (26U)
7457 #define QUADSPI_CCR_FMODE_Msk          (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
7458 #define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
7459 #define QUADSPI_CCR_FMODE_0            (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
7460 #define QUADSPI_CCR_FMODE_1            (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
7461 #define QUADSPI_CCR_SIOO_Pos           (28U)
7462 #define QUADSPI_CCR_SIOO_Msk           (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
7463 #define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
7464 #define QUADSPI_CCR_DHHC_Pos           (30U)
7465 #define QUADSPI_CCR_DHHC_Msk           (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
7466 #define QUADSPI_CCR_DHHC               QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold */
7467 #define QUADSPI_CCR_DDRM_Pos           (31U)
7468 #define QUADSPI_CCR_DDRM_Msk           (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
7469 #define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
7470 
7471 /******************  Bit definition for QUADSPI_AR register  *******************/
7472 #define QUADSPI_AR_ADDRESS_Pos         (0U)
7473 #define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
7474 #define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
7475 
7476 /******************  Bit definition for QUADSPI_ABR register  ******************/
7477 #define QUADSPI_ABR_ALTERNATE_Pos      (0U)
7478 #define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
7479 #define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
7480 
7481 /******************  Bit definition for QUADSPI_DR register  *******************/
7482 #define QUADSPI_DR_DATA_Pos            (0U)
7483 #define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)   /*!< 0xFFFFFFFF */
7484 #define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
7485 
7486 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
7487 #define QUADSPI_PSMKR_MASK_Pos         (0U)
7488 #define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
7489 #define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
7490 
7491 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
7492 #define QUADSPI_PSMAR_MATCH_Pos        (0U)
7493 #define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
7494 #define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
7495 
7496 /******************  Bit definition for QUADSPI_PIR register  *****************/
7497 #define QUADSPI_PIR_INTERVAL_Pos       (0U)
7498 #define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)  /*!< 0x0000FFFF */
7499 #define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
7500 
7501 /******************  Bit definition for QUADSPI_LPTR register  *****************/
7502 #define QUADSPI_LPTR_TIMEOUT_Pos       (0U)
7503 #define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)  /*!< 0x0000FFFF */
7504 #define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
7505 
7506 /******************************************************************************/
7507 /*                                                                            */
7508 /*                                 SYSCFG                                     */
7509 /*                                                                            */
7510 /******************************************************************************/
7511 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
7512 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
7513 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000007 */
7514 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
7515 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000001 */
7516 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000002 */
7517 #define SYSCFG_MEMRMP_MEM_MODE_2        (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)  /*!< 0x00000004 */
7518 
7519 /******************  Bit definition for SYSCFG_CFGR1 register  ******************/
7520 #define SYSCFG_CFGR1_FWDIS_Pos          (0U)
7521 #define SYSCFG_CFGR1_FWDIS_Msk          (0x1UL << SYSCFG_CFGR1_FWDIS_Pos)      /*!< 0x00000001 */
7522 #define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/
7523 #define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
7524 #define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)    /*!< 0x00000100 */
7525 #define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
7526 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
7527 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
7528 #define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
7529 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
7530 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
7531 #define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
7532 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
7533 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
7534 #define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
7535 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
7536 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
7537 #define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
7538 #define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)
7539 #define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)   /*!< 0x00100000 */
7540 #define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
7541 #define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)
7542 #define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)   /*!< 0x00200000 */
7543 #define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
7544 #define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)
7545 #define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)   /*!< 0x00400000 */
7546 #define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
7547 #define SYSCFG_CFGR1_FPU_IE_0           (0x04000000UL)                         /*!<  Invalid operation Interrupt enable */
7548 #define SYSCFG_CFGR1_FPU_IE_1           (0x08000000UL)                         /*!<  Divide-by-zero Interrupt enable */
7549 #define SYSCFG_CFGR1_FPU_IE_2           (0x10000000UL)                         /*!<  Underflow Interrupt enable */
7550 #define SYSCFG_CFGR1_FPU_IE_3           (0x20000000UL)                         /*!<  Overflow Interrupt enable */
7551 #define SYSCFG_CFGR1_FPU_IE_4           (0x40000000UL)                         /*!<  Input denormal Interrupt enable */
7552 #define SYSCFG_CFGR1_FPU_IE_5           (0x80000000UL)                         /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
7553 
7554 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
7555 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
7556 #define SYSCFG_EXTICR1_EXTI0_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x00000007 */
7557 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
7558 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
7559 #define SYSCFG_EXTICR1_EXTI1_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x00000070 */
7560 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
7561 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
7562 #define SYSCFG_EXTICR1_EXTI2_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000700 */
7563 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
7564 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
7565 #define SYSCFG_EXTICR1_EXTI3_Msk        (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x00007000 */
7566 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
7567 
7568 /**
7569   * @brief   EXTI0 configuration
7570   */
7571 #define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000UL)                     /*!<PA[0] pin */
7572 #define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001UL)                     /*!<PB[0] pin */
7573 #define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002UL)                     /*!<PC[0] pin */
7574 #define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003UL)                     /*!<PD[0] pin */
7575 #define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007UL)                     /*!<PH[0] pin */
7576 
7577 /**
7578   * @brief   EXTI1 configuration
7579   */
7580 #define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000UL)                     /*!<PA[1] pin */
7581 #define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010UL)                     /*!<PB[1] pin */
7582 #define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020UL)                     /*!<PC[1] pin */
7583 #define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030UL)                     /*!<PD[1] pin */
7584 #define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070UL)                     /*!<PH[1] pin */
7585 
7586 /**
7587   * @brief   EXTI2 configuration
7588   */
7589 #define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000UL)                     /*!<PA[2] pin */
7590 #define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100UL)                     /*!<PB[2] pin */
7591 #define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200UL)                     /*!<PC[2] pin */
7592 #define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300UL)                     /*!<PD[2] pin */
7593 
7594 /**
7595   * @brief   EXTI3 configuration
7596   */
7597 #define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000UL)                     /*!<PA[3] pin */
7598 #define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000UL)                     /*!<PB[3] pin */
7599 #define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000UL)                     /*!<PC[3] pin */
7600 #define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000UL)                     /*!<PD[3] pin */
7601 #define SYSCFG_EXTICR1_EXTI3_PH             (0x00007000UL)                     /*!<PH[3] pin */
7602 
7603 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
7604 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
7605 #define SYSCFG_EXTICR2_EXTI4_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x00000007 */
7606 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
7607 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
7608 #define SYSCFG_EXTICR2_EXTI5_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x00000070 */
7609 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
7610 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
7611 #define SYSCFG_EXTICR2_EXTI6_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000700 */
7612 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
7613 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
7614 #define SYSCFG_EXTICR2_EXTI7_Msk        (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x00007000 */
7615 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
7616 /**
7617   * @brief   EXTI4 configuration
7618   */
7619 #define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000UL)                     /*!<PA[4] pin */
7620 #define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001UL)                     /*!<PB[4] pin */
7621 #define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002UL)                     /*!<PC[4] pin */
7622 #define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003UL)                     /*!<PD[4] pin */
7623 
7624 /**
7625   * @brief   EXTI5 configuration
7626   */
7627 #define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000UL)                     /*!<PA[5] pin */
7628 #define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010UL)                     /*!<PB[5] pin */
7629 #define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020UL)                     /*!<PC[5] pin */
7630 #define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030UL)                     /*!<PD[5] pin */
7631 
7632 /**
7633   * @brief   EXTI6 configuration
7634   */
7635 #define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000UL)                     /*!<PA[6] pin */
7636 #define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100UL)                     /*!<PB[6] pin */
7637 #define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200UL)                     /*!<PC[6] pin */
7638 #define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300UL)                     /*!<PD[6] pin */
7639 
7640 /**
7641   * @brief   EXTI7 configuration
7642   */
7643 #define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000UL)                     /*!<PA[7] pin */
7644 #define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000UL)                     /*!<PB[7] pin */
7645 #define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000UL)                     /*!<PC[7] pin */
7646 #define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000UL)                     /*!<PD[7] pin */
7647 
7648 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
7649 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
7650 #define SYSCFG_EXTICR3_EXTI8_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x00000007 */
7651 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
7652 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
7653 #define SYSCFG_EXTICR3_EXTI9_Msk        (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x00000070 */
7654 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
7655 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
7656 #define SYSCFG_EXTICR3_EXTI10_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000700 */
7657 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
7658 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
7659 #define SYSCFG_EXTICR3_EXTI11_Msk       (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x00007000 */
7660 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
7661 
7662 /**
7663   * @brief   EXTI8 configuration
7664   */
7665 #define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000UL)                     /*!<PA[8] pin */
7666 #define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001UL)                     /*!<PB[8] pin */
7667 #define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002UL)                     /*!<PC[8] pin */
7668 #define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003UL)                     /*!<PD[8] pin */
7669 
7670 /**
7671   * @brief   EXTI9 configuration
7672   */
7673 #define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000UL)                     /*!<PA[9] pin */
7674 #define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010UL)                     /*!<PB[9] pin */
7675 #define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020UL)                     /*!<PC[9] pin */
7676 #define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030UL)                     /*!<PD[9] pin */
7677 
7678 /**
7679   * @brief   EXTI10 configuration
7680   */
7681 #define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000UL)                     /*!<PA[10] pin */
7682 #define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100UL)                     /*!<PB[10] pin */
7683 #define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200UL)                     /*!<PC[10] pin */
7684 #define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300UL)                     /*!<PD[10] pin */
7685 
7686 /**
7687   * @brief   EXTI11 configuration
7688   */
7689 #define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000UL)                     /*!<PA[11] pin */
7690 #define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000UL)                     /*!<PB[11] pin */
7691 #define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000UL)                     /*!<PC[11] pin */
7692 #define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000UL)                     /*!<PD[11] pin */
7693 
7694 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
7695 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
7696 #define SYSCFG_EXTICR4_EXTI12_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x00000007 */
7697 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
7698 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
7699 #define SYSCFG_EXTICR4_EXTI13_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x00000070 */
7700 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
7701 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
7702 #define SYSCFG_EXTICR4_EXTI14_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000700 */
7703 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
7704 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
7705 #define SYSCFG_EXTICR4_EXTI15_Msk       (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x00007000 */
7706 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
7707 
7708 /**
7709   * @brief   EXTI12 configuration
7710   */
7711 #define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000UL)                     /*!<PA[12] pin */
7712 #define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001UL)                     /*!<PB[12] pin */
7713 #define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002UL)                     /*!<PC[12] pin */
7714 #define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003UL)                     /*!<PD[12] pin */
7715 
7716 /**
7717   * @brief   EXTI13 configuration
7718   */
7719 #define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000UL)                     /*!<PA[13] pin */
7720 #define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010UL)                     /*!<PB[13] pin */
7721 #define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020UL)                     /*!<PC[13] pin */
7722 #define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030UL)                     /*!<PD[13] pin */
7723 
7724 /**
7725   * @brief   EXTI14 configuration
7726   */
7727 #define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000UL)                     /*!<PA[14] pin */
7728 #define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100UL)                     /*!<PB[14] pin */
7729 #define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200UL)                     /*!<PC[14] pin */
7730 #define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300UL)                     /*!<PD[14] pin */
7731 
7732 /**
7733   * @brief   EXTI15 configuration
7734   */
7735 #define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000UL)                     /*!<PA[15] pin */
7736 #define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000UL)                     /*!<PB[15] pin */
7737 #define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000UL)                     /*!<PC[15] pin */
7738 #define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000UL)                     /*!<PD[15] pin */
7739 
7740 /******************  Bit definition for SYSCFG_SCSR register  ****************/
7741 #define SYSCFG_SCSR_SRAM2ER_Pos         (0U)
7742 #define SYSCFG_SCSR_SRAM2ER_Msk         (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)     /*!< 0x00000001 */
7743 #define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */
7744 #define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)
7745 #define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)    /*!< 0x00000002 */
7746 #define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */
7747 
7748 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
7749 #define SYSCFG_CFGR2_CLL_Pos            (0U)
7750 #define SYSCFG_CFGR2_CLL_Msk            (0x1UL << SYSCFG_CFGR2_CLL_Pos)        /*!< 0x00000001 */
7751 #define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
7752 #define SYSCFG_CFGR2_SPL_Pos            (1U)
7753 #define SYSCFG_CFGR2_SPL_Msk            (0x1UL << SYSCFG_CFGR2_SPL_Pos)        /*!< 0x00000002 */
7754 #define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
7755 #define SYSCFG_CFGR2_PVDL_Pos           (2U)
7756 #define SYSCFG_CFGR2_PVDL_Msk           (0x1UL << SYSCFG_CFGR2_PVDL_Pos)       /*!< 0x00000004 */
7757 #define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
7758 #define SYSCFG_CFGR2_ECCL_Pos           (3U)
7759 #define SYSCFG_CFGR2_ECCL_Msk           (0x1UL << SYSCFG_CFGR2_ECCL_Pos)       /*!< 0x00000008 */
7760 #define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
7761 #define SYSCFG_CFGR2_SPF_Pos            (8U)
7762 #define SYSCFG_CFGR2_SPF_Msk            (0x1UL << SYSCFG_CFGR2_SPF_Pos)        /*!< 0x00000100 */
7763 #define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
7764 
7765 /******************  Bit definition for SYSCFG_SWPR register  ****************/
7766 #define SYSCFG_SWPR_PAGE0_Pos           (0U)
7767 #define SYSCFG_SWPR_PAGE0_Msk           (0x1UL << SYSCFG_SWPR_PAGE0_Pos)       /*!< 0x00000001 */
7768 #define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */
7769 #define SYSCFG_SWPR_PAGE1_Pos           (1U)
7770 #define SYSCFG_SWPR_PAGE1_Msk           (0x1UL << SYSCFG_SWPR_PAGE1_Pos)       /*!< 0x00000002 */
7771 #define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */
7772 #define SYSCFG_SWPR_PAGE2_Pos           (2U)
7773 #define SYSCFG_SWPR_PAGE2_Msk           (0x1UL << SYSCFG_SWPR_PAGE2_Pos)       /*!< 0x00000004 */
7774 #define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */
7775 #define SYSCFG_SWPR_PAGE3_Pos           (3U)
7776 #define SYSCFG_SWPR_PAGE3_Msk           (0x1UL << SYSCFG_SWPR_PAGE3_Pos)       /*!< 0x00000008 */
7777 #define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */
7778 #define SYSCFG_SWPR_PAGE4_Pos           (4U)
7779 #define SYSCFG_SWPR_PAGE4_Msk           (0x1UL << SYSCFG_SWPR_PAGE4_Pos)       /*!< 0x00000010 */
7780 #define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */
7781 #define SYSCFG_SWPR_PAGE5_Pos           (5U)
7782 #define SYSCFG_SWPR_PAGE5_Msk           (0x1UL << SYSCFG_SWPR_PAGE5_Pos)       /*!< 0x00000020 */
7783 #define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */
7784 #define SYSCFG_SWPR_PAGE6_Pos           (6U)
7785 #define SYSCFG_SWPR_PAGE6_Msk           (0x1UL << SYSCFG_SWPR_PAGE6_Pos)       /*!< 0x00000040 */
7786 #define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */
7787 #define SYSCFG_SWPR_PAGE7_Pos           (7U)
7788 #define SYSCFG_SWPR_PAGE7_Msk           (0x1UL << SYSCFG_SWPR_PAGE7_Pos)       /*!< 0x00000080 */
7789 #define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */
7790 #define SYSCFG_SWPR_PAGE8_Pos           (8U)
7791 #define SYSCFG_SWPR_PAGE8_Msk           (0x1UL << SYSCFG_SWPR_PAGE8_Pos)       /*!< 0x00000100 */
7792 #define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */
7793 #define SYSCFG_SWPR_PAGE9_Pos           (9U)
7794 #define SYSCFG_SWPR_PAGE9_Msk           (0x1UL << SYSCFG_SWPR_PAGE9_Pos)       /*!< 0x00000200 */
7795 #define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */
7796 #define SYSCFG_SWPR_PAGE10_Pos          (10U)
7797 #define SYSCFG_SWPR_PAGE10_Msk          (0x1UL << SYSCFG_SWPR_PAGE10_Pos)      /*!< 0x00000400 */
7798 #define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/
7799 #define SYSCFG_SWPR_PAGE11_Pos          (11U)
7800 #define SYSCFG_SWPR_PAGE11_Msk          (0x1UL << SYSCFG_SWPR_PAGE11_Pos)      /*!< 0x00000800 */
7801 #define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/
7802 #define SYSCFG_SWPR_PAGE12_Pos          (12U)
7803 #define SYSCFG_SWPR_PAGE12_Msk          (0x1UL << SYSCFG_SWPR_PAGE12_Pos)      /*!< 0x00001000 */
7804 #define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/
7805 #define SYSCFG_SWPR_PAGE13_Pos          (13U)
7806 #define SYSCFG_SWPR_PAGE13_Msk          (0x1UL << SYSCFG_SWPR_PAGE13_Pos)      /*!< 0x00002000 */
7807 #define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/
7808 #define SYSCFG_SWPR_PAGE14_Pos          (14U)
7809 #define SYSCFG_SWPR_PAGE14_Msk          (0x1UL << SYSCFG_SWPR_PAGE14_Pos)      /*!< 0x00004000 */
7810 #define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/
7811 #define SYSCFG_SWPR_PAGE15_Pos          (15U)
7812 #define SYSCFG_SWPR_PAGE15_Msk          (0x1UL << SYSCFG_SWPR_PAGE15_Pos)      /*!< 0x00008000 */
7813 #define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/
7814 
7815 /******************  Bit definition for SYSCFG_SKR register  ****************/
7816 #define SYSCFG_SKR_KEY_Pos              (0U)
7817 #define SYSCFG_SKR_KEY_Msk              (0xFFUL << SYSCFG_SKR_KEY_Pos)         /*!< 0x000000FF */
7818 #define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */
7819 
7820 
7821 
7822 
7823 /******************************************************************************/
7824 /*                                                                            */
7825 /*                                    TIM                                     */
7826 /*                                                                            */
7827 /******************************************************************************/
7828 /*******************  Bit definition for TIM_CR1 register  ********************/
7829 #define TIM_CR1_CEN_Pos           (0U)
7830 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
7831 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
7832 #define TIM_CR1_UDIS_Pos          (1U)
7833 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
7834 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
7835 #define TIM_CR1_URS_Pos           (2U)
7836 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
7837 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
7838 #define TIM_CR1_OPM_Pos           (3U)
7839 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
7840 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
7841 #define TIM_CR1_DIR_Pos           (4U)
7842 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
7843 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
7844 
7845 #define TIM_CR1_CMS_Pos           (5U)
7846 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
7847 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
7848 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
7849 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
7850 
7851 #define TIM_CR1_ARPE_Pos          (7U)
7852 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
7853 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
7854 
7855 #define TIM_CR1_CKD_Pos           (8U)
7856 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
7857 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
7858 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
7859 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
7860 
7861 #define TIM_CR1_UIFREMAP_Pos      (11U)
7862 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
7863 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
7864 
7865 /*******************  Bit definition for TIM_CR2 register  ********************/
7866 #define TIM_CR2_CCPC_Pos          (0U)
7867 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
7868 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
7869 #define TIM_CR2_CCUS_Pos          (2U)
7870 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
7871 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
7872 #define TIM_CR2_CCDS_Pos          (3U)
7873 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
7874 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
7875 
7876 #define TIM_CR2_MMS_Pos           (4U)
7877 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
7878 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
7879 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */
7880 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */
7881 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */
7882 
7883 #define TIM_CR2_TI1S_Pos          (7U)
7884 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
7885 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
7886 #define TIM_CR2_OIS1_Pos          (8U)
7887 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
7888 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
7889 #define TIM_CR2_OIS1N_Pos         (9U)
7890 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
7891 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
7892 #define TIM_CR2_OIS2_Pos          (10U)
7893 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
7894 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
7895 #define TIM_CR2_OIS2N_Pos         (11U)
7896 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
7897 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
7898 #define TIM_CR2_OIS3_Pos          (12U)
7899 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
7900 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
7901 #define TIM_CR2_OIS3N_Pos         (13U)
7902 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
7903 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
7904 #define TIM_CR2_OIS4_Pos          (14U)
7905 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
7906 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
7907 #define TIM_CR2_OIS5_Pos          (16U)
7908 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
7909 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
7910 #define TIM_CR2_OIS6_Pos          (18U)
7911 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
7912 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
7913 
7914 #define TIM_CR2_MMS2_Pos          (20U)
7915 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
7916 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
7917 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
7918 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
7919 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
7920 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
7921 
7922 /*******************  Bit definition for TIM_SMCR register  *******************/
7923 #define TIM_SMCR_SMS_Pos          (0U)
7924 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
7925 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
7926 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
7927 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
7928 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
7929 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
7930 
7931 #define TIM_SMCR_OCCS_Pos         (3U)
7932 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
7933 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
7934 
7935 #define TIM_SMCR_TS_Pos           (4U)
7936 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000070 */
7937 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
7938 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000010 */
7939 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000020 */
7940 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                   /*!< 0x00000040 */
7941 
7942 #define TIM_SMCR_MSM_Pos          (7U)
7943 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
7944 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
7945 
7946 #define TIM_SMCR_ETF_Pos          (8U)
7947 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
7948 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
7949 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
7950 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
7951 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
7952 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
7953 
7954 #define TIM_SMCR_ETPS_Pos         (12U)
7955 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
7956 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
7957 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
7958 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
7959 
7960 #define TIM_SMCR_ECE_Pos          (14U)
7961 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
7962 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
7963 #define TIM_SMCR_ETP_Pos          (15U)
7964 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
7965 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
7966 
7967 /*******************  Bit definition for TIM_DIER register  *******************/
7968 #define TIM_DIER_UIE_Pos          (0U)
7969 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
7970 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
7971 #define TIM_DIER_CC1IE_Pos        (1U)
7972 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
7973 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
7974 #define TIM_DIER_CC2IE_Pos        (2U)
7975 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
7976 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
7977 #define TIM_DIER_CC3IE_Pos        (3U)
7978 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
7979 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
7980 #define TIM_DIER_CC4IE_Pos        (4U)
7981 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
7982 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
7983 #define TIM_DIER_COMIE_Pos        (5U)
7984 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
7985 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
7986 #define TIM_DIER_TIE_Pos          (6U)
7987 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
7988 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
7989 #define TIM_DIER_BIE_Pos          (7U)
7990 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
7991 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
7992 #define TIM_DIER_UDE_Pos          (8U)
7993 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
7994 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
7995 #define TIM_DIER_CC1DE_Pos        (9U)
7996 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
7997 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
7998 #define TIM_DIER_CC2DE_Pos        (10U)
7999 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
8000 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
8001 #define TIM_DIER_CC3DE_Pos        (11U)
8002 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
8003 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
8004 #define TIM_DIER_CC4DE_Pos        (12U)
8005 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
8006 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
8007 #define TIM_DIER_COMDE_Pos        (13U)
8008 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
8009 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
8010 #define TIM_DIER_TDE_Pos          (14U)
8011 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
8012 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
8013 
8014 /********************  Bit definition for TIM_SR register  ********************/
8015 #define TIM_SR_UIF_Pos            (0U)
8016 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
8017 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
8018 #define TIM_SR_CC1IF_Pos          (1U)
8019 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
8020 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
8021 #define TIM_SR_CC2IF_Pos          (2U)
8022 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
8023 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
8024 #define TIM_SR_CC3IF_Pos          (3U)
8025 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
8026 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
8027 #define TIM_SR_CC4IF_Pos          (4U)
8028 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
8029 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
8030 #define TIM_SR_COMIF_Pos          (5U)
8031 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
8032 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
8033 #define TIM_SR_TIF_Pos            (6U)
8034 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
8035 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
8036 #define TIM_SR_BIF_Pos            (7U)
8037 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
8038 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
8039 #define TIM_SR_B2IF_Pos           (8U)
8040 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
8041 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
8042 #define TIM_SR_CC1OF_Pos          (9U)
8043 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
8044 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
8045 #define TIM_SR_CC2OF_Pos          (10U)
8046 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
8047 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
8048 #define TIM_SR_CC3OF_Pos          (11U)
8049 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
8050 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
8051 #define TIM_SR_CC4OF_Pos          (12U)
8052 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
8053 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
8054 #define TIM_SR_SBIF_Pos           (13U)
8055 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
8056 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
8057 #define TIM_SR_CC5IF_Pos          (16U)
8058 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
8059 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
8060 #define TIM_SR_CC6IF_Pos          (17U)
8061 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
8062 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
8063 
8064 
8065 /*******************  Bit definition for TIM_EGR register  ********************/
8066 #define TIM_EGR_UG_Pos            (0U)
8067 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
8068 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
8069 #define TIM_EGR_CC1G_Pos          (1U)
8070 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
8071 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
8072 #define TIM_EGR_CC2G_Pos          (2U)
8073 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
8074 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
8075 #define TIM_EGR_CC3G_Pos          (3U)
8076 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
8077 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
8078 #define TIM_EGR_CC4G_Pos          (4U)
8079 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
8080 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
8081 #define TIM_EGR_COMG_Pos          (5U)
8082 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
8083 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
8084 #define TIM_EGR_TG_Pos            (6U)
8085 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
8086 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
8087 #define TIM_EGR_BG_Pos            (7U)
8088 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
8089 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
8090 #define TIM_EGR_B2G_Pos           (8U)
8091 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
8092 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
8093 
8094 
8095 /******************  Bit definition for TIM_CCMR1 register  *******************/
8096 #define TIM_CCMR1_CC1S_Pos        (0U)
8097 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
8098 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
8099 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
8100 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
8101 
8102 #define TIM_CCMR1_OC1FE_Pos       (2U)
8103 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
8104 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
8105 #define TIM_CCMR1_OC1PE_Pos       (3U)
8106 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
8107 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
8108 
8109 #define TIM_CCMR1_OC1M_Pos        (4U)
8110 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
8111 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
8112 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
8113 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
8114 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
8115 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
8116 
8117 #define TIM_CCMR1_OC1CE_Pos       (7U)
8118 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
8119 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
8120 
8121 #define TIM_CCMR1_CC2S_Pos        (8U)
8122 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
8123 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
8124 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
8125 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
8126 
8127 #define TIM_CCMR1_OC2FE_Pos       (10U)
8128 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
8129 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
8130 #define TIM_CCMR1_OC2PE_Pos       (11U)
8131 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
8132 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
8133 
8134 #define TIM_CCMR1_OC2M_Pos        (12U)
8135 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
8136 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
8137 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
8138 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
8139 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
8140 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
8141 
8142 #define TIM_CCMR1_OC2CE_Pos       (15U)
8143 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
8144 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
8145 
8146 /*----------------------------------------------------------------------------*/
8147 #define TIM_CCMR1_IC1PSC_Pos      (2U)
8148 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
8149 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
8150 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
8151 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
8152 
8153 #define TIM_CCMR1_IC1F_Pos        (4U)
8154 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
8155 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
8156 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
8157 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
8158 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
8159 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
8160 
8161 #define TIM_CCMR1_IC2PSC_Pos      (10U)
8162 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
8163 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
8164 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
8165 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
8166 
8167 #define TIM_CCMR1_IC2F_Pos        (12U)
8168 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
8169 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
8170 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
8171 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
8172 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
8173 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
8174 
8175 /******************  Bit definition for TIM_CCMR2 register  *******************/
8176 #define TIM_CCMR2_CC3S_Pos        (0U)
8177 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
8178 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
8179 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
8180 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
8181 
8182 #define TIM_CCMR2_OC3FE_Pos       (2U)
8183 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
8184 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
8185 #define TIM_CCMR2_OC3PE_Pos       (3U)
8186 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
8187 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
8188 
8189 #define TIM_CCMR2_OC3M_Pos        (4U)
8190 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
8191 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
8192 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
8193 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
8194 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
8195 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
8196 
8197 #define TIM_CCMR2_OC3CE_Pos       (7U)
8198 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
8199 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
8200 
8201 #define TIM_CCMR2_CC4S_Pos        (8U)
8202 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
8203 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
8204 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
8205 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
8206 
8207 #define TIM_CCMR2_OC4FE_Pos       (10U)
8208 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
8209 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
8210 #define TIM_CCMR2_OC4PE_Pos       (11U)
8211 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
8212 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
8213 
8214 #define TIM_CCMR2_OC4M_Pos        (12U)
8215 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
8216 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
8217 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
8218 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
8219 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
8220 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
8221 
8222 #define TIM_CCMR2_OC4CE_Pos       (15U)
8223 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
8224 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
8225 
8226 /*----------------------------------------------------------------------------*/
8227 #define TIM_CCMR2_IC3PSC_Pos      (2U)
8228 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
8229 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
8230 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
8231 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
8232 
8233 #define TIM_CCMR2_IC3F_Pos        (4U)
8234 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
8235 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
8236 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
8237 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
8238 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
8239 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
8240 
8241 #define TIM_CCMR2_IC4PSC_Pos      (10U)
8242 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
8243 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
8244 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
8245 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
8246 
8247 #define TIM_CCMR2_IC4F_Pos        (12U)
8248 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
8249 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
8250 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
8251 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
8252 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
8253 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
8254 
8255 /******************  Bit definition for TIM_CCMR3 register  *******************/
8256 #define TIM_CCMR3_OC5FE_Pos       (2U)
8257 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
8258 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
8259 #define TIM_CCMR3_OC5PE_Pos       (3U)
8260 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
8261 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
8262 
8263 #define TIM_CCMR3_OC5M_Pos        (4U)
8264 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
8265 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
8266 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
8267 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
8268 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
8269 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
8270 
8271 #define TIM_CCMR3_OC5CE_Pos       (7U)
8272 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
8273 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
8274 
8275 #define TIM_CCMR3_OC6FE_Pos       (10U)
8276 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
8277 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
8278 #define TIM_CCMR3_OC6PE_Pos       (11U)
8279 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
8280 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
8281 
8282 #define TIM_CCMR3_OC6M_Pos        (12U)
8283 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
8284 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
8285 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
8286 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
8287 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
8288 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
8289 
8290 #define TIM_CCMR3_OC6CE_Pos       (15U)
8291 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
8292 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
8293 
8294 /*******************  Bit definition for TIM_CCER register  *******************/
8295 #define TIM_CCER_CC1E_Pos         (0U)
8296 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
8297 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
8298 #define TIM_CCER_CC1P_Pos         (1U)
8299 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
8300 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
8301 #define TIM_CCER_CC1NE_Pos        (2U)
8302 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
8303 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
8304 #define TIM_CCER_CC1NP_Pos        (3U)
8305 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
8306 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
8307 #define TIM_CCER_CC2E_Pos         (4U)
8308 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
8309 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
8310 #define TIM_CCER_CC2P_Pos         (5U)
8311 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
8312 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
8313 #define TIM_CCER_CC2NE_Pos        (6U)
8314 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
8315 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
8316 #define TIM_CCER_CC2NP_Pos        (7U)
8317 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
8318 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
8319 #define TIM_CCER_CC3E_Pos         (8U)
8320 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
8321 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
8322 #define TIM_CCER_CC3P_Pos         (9U)
8323 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
8324 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
8325 #define TIM_CCER_CC3NE_Pos        (10U)
8326 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
8327 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
8328 #define TIM_CCER_CC3NP_Pos        (11U)
8329 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
8330 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
8331 #define TIM_CCER_CC4E_Pos         (12U)
8332 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
8333 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
8334 #define TIM_CCER_CC4P_Pos         (13U)
8335 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
8336 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
8337 #define TIM_CCER_CC4NP_Pos        (15U)
8338 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
8339 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
8340 #define TIM_CCER_CC5E_Pos         (16U)
8341 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
8342 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
8343 #define TIM_CCER_CC5P_Pos         (17U)
8344 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
8345 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
8346 #define TIM_CCER_CC6E_Pos         (20U)
8347 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
8348 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
8349 #define TIM_CCER_CC6P_Pos         (21U)
8350 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
8351 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
8352 
8353 /*******************  Bit definition for TIM_CNT register  ********************/
8354 #define TIM_CNT_CNT_Pos           (0U)
8355 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
8356 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
8357 #define TIM_CNT_UIFCPY_Pos        (31U)
8358 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
8359 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
8360 
8361 /*******************  Bit definition for TIM_PSC register  ********************/
8362 #define TIM_PSC_PSC_Pos           (0U)
8363 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
8364 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
8365 
8366 /*******************  Bit definition for TIM_ARR register  ********************/
8367 #define TIM_ARR_ARR_Pos           (0U)
8368 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
8369 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
8370 
8371 /*******************  Bit definition for TIM_RCR register  ********************/
8372 #define TIM_RCR_REP_Pos           (0U)
8373 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
8374 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
8375 
8376 /*******************  Bit definition for TIM_CCR1 register  *******************/
8377 #define TIM_CCR1_CCR1_Pos         (0U)
8378 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
8379 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
8380 
8381 /*******************  Bit definition for TIM_CCR2 register  *******************/
8382 #define TIM_CCR2_CCR2_Pos         (0U)
8383 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
8384 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
8385 
8386 /*******************  Bit definition for TIM_CCR3 register  *******************/
8387 #define TIM_CCR3_CCR3_Pos         (0U)
8388 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
8389 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
8390 
8391 /*******************  Bit definition for TIM_CCR4 register  *******************/
8392 #define TIM_CCR4_CCR4_Pos         (0U)
8393 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
8394 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
8395 
8396 /*******************  Bit definition for TIM_CCR5 register  *******************/
8397 #define TIM_CCR5_CCR5_Pos         (0U)
8398 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
8399 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
8400 #define TIM_CCR5_GC5C1_Pos        (29U)
8401 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
8402 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
8403 #define TIM_CCR5_GC5C2_Pos        (30U)
8404 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
8405 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
8406 #define TIM_CCR5_GC5C3_Pos        (31U)
8407 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
8408 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
8409 
8410 /*******************  Bit definition for TIM_CCR6 register  *******************/
8411 #define TIM_CCR6_CCR6_Pos         (0U)
8412 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
8413 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
8414 
8415 /*******************  Bit definition for TIM_BDTR register  *******************/
8416 #define TIM_BDTR_DTG_Pos          (0U)
8417 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
8418 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
8419 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
8420 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
8421 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
8422 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
8423 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
8424 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
8425 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
8426 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
8427 
8428 #define TIM_BDTR_LOCK_Pos         (8U)
8429 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
8430 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
8431 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
8432 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
8433 
8434 #define TIM_BDTR_OSSI_Pos         (10U)
8435 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
8436 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
8437 #define TIM_BDTR_OSSR_Pos         (11U)
8438 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
8439 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
8440 #define TIM_BDTR_BKE_Pos          (12U)
8441 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
8442 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
8443 #define TIM_BDTR_BKP_Pos          (13U)
8444 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
8445 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
8446 #define TIM_BDTR_AOE_Pos          (14U)
8447 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
8448 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
8449 #define TIM_BDTR_MOE_Pos          (15U)
8450 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
8451 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
8452 
8453 #define TIM_BDTR_BKF_Pos          (16U)
8454 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
8455 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
8456 #define TIM_BDTR_BK2F_Pos         (20U)
8457 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
8458 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
8459 
8460 #define TIM_BDTR_BK2E_Pos         (24U)
8461 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
8462 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
8463 #define TIM_BDTR_BK2P_Pos         (25U)
8464 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
8465 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
8466 
8467 /*******************  Bit definition for TIM_DCR register  ********************/
8468 #define TIM_DCR_DBA_Pos           (0U)
8469 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
8470 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
8471 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
8472 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
8473 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
8474 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
8475 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
8476 
8477 #define TIM_DCR_DBL_Pos           (8U)
8478 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
8479 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
8480 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
8481 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
8482 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
8483 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
8484 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
8485 
8486 /*******************  Bit definition for TIM_DMAR register  *******************/
8487 #define TIM_DMAR_DMAB_Pos         (0U)
8488 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
8489 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
8490 
8491 /*******************  Bit definition for TIM1_OR1 register  *******************/
8492 #define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)
8493 #define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000003 */
8494 #define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
8495 #define TIM1_OR1_ETR_ADC1_RMP_0        (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000001 */
8496 #define TIM1_OR1_ETR_ADC1_RMP_1        (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos)    /*!< 0x00000002 */
8497 
8498 #define TIM1_OR1_TI1_RMP_Pos           (4U)
8499 #define TIM1_OR1_TI1_RMP_Msk           (0x1UL << TIM1_OR1_TI1_RMP_Pos)         /*!< 0x00000010 */
8500 #define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */
8501 
8502 /*******************  Bit definition for TIM1_OR2 register  *******************/
8503 #define TIM1_OR2_BKINE_Pos             (0U)
8504 #define TIM1_OR2_BKINE_Msk             (0x1UL << TIM1_OR2_BKINE_Pos)           /*!< 0x00000001 */
8505 #define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
8506 #define TIM1_OR2_BKCMP1E_Pos           (1U)
8507 #define TIM1_OR2_BKCMP1E_Msk           (0x1UL << TIM1_OR2_BKCMP1E_Pos)         /*!< 0x00000002 */
8508 #define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
8509 #define TIM1_OR2_BKCMP2E_Pos           (2U)
8510 #define TIM1_OR2_BKCMP2E_Msk           (0x1UL << TIM1_OR2_BKCMP2E_Pos)         /*!< 0x00000004 */
8511 #define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
8512 #define TIM1_OR2_BKINP_Pos             (9U)
8513 #define TIM1_OR2_BKINP_Msk             (0x1UL << TIM1_OR2_BKINP_Pos)           /*!< 0x00000200 */
8514 #define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
8515 #define TIM1_OR2_BKCMP1P_Pos           (10U)
8516 #define TIM1_OR2_BKCMP1P_Msk           (0x1UL << TIM1_OR2_BKCMP1P_Pos)         /*!< 0x00000400 */
8517 #define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
8518 #define TIM1_OR2_BKCMP2P_Pos           (11U)
8519 #define TIM1_OR2_BKCMP2P_Msk           (0x1UL << TIM1_OR2_BKCMP2P_Pos)         /*!< 0x00000800 */
8520 #define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
8521 
8522 #define TIM1_OR2_ETRSEL_Pos            (14U)
8523 #define TIM1_OR2_ETRSEL_Msk            (0x7UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x0001C000 */
8524 #define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
8525 #define TIM1_OR2_ETRSEL_0              (0x1UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00004000 */
8526 #define TIM1_OR2_ETRSEL_1              (0x2UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00008000 */
8527 #define TIM1_OR2_ETRSEL_2              (0x4UL << TIM1_OR2_ETRSEL_Pos)          /*!< 0x00010000 */
8528 
8529 /*******************  Bit definition for TIM1_OR3 register  *******************/
8530 #define TIM1_OR3_BK2INE_Pos            (0U)
8531 #define TIM1_OR3_BK2INE_Msk            (0x1UL << TIM1_OR3_BK2INE_Pos)          /*!< 0x00000001 */
8532 #define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
8533 #define TIM1_OR3_BK2CMP1E_Pos          (1U)
8534 #define TIM1_OR3_BK2CMP1E_Msk          (0x1UL << TIM1_OR3_BK2CMP1E_Pos)        /*!< 0x00000002 */
8535 #define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
8536 #define TIM1_OR3_BK2CMP2E_Pos          (2U)
8537 #define TIM1_OR3_BK2CMP2E_Msk          (0x1UL << TIM1_OR3_BK2CMP2E_Pos)        /*!< 0x00000004 */
8538 #define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
8539 #define TIM1_OR3_BK2INP_Pos            (9U)
8540 #define TIM1_OR3_BK2INP_Msk            (0x1UL << TIM1_OR3_BK2INP_Pos)          /*!< 0x00000200 */
8541 #define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
8542 #define TIM1_OR3_BK2CMP1P_Pos          (10U)
8543 #define TIM1_OR3_BK2CMP1P_Msk          (0x1UL << TIM1_OR3_BK2CMP1P_Pos)        /*!< 0x00000400 */
8544 #define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
8545 #define TIM1_OR3_BK2CMP2P_Pos          (11U)
8546 #define TIM1_OR3_BK2CMP2P_Msk          (0x1UL << TIM1_OR3_BK2CMP2P_Pos)        /*!< 0x00000800 */
8547 #define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
8548 
8549 
8550 /*******************  Bit definition for TIM2_OR1 register  *******************/
8551 #define TIM2_OR1_ITR1_RMP_Pos     (0U)
8552 #define TIM2_OR1_ITR1_RMP_Msk     (0x1UL << TIM2_OR1_ITR1_RMP_Pos)             /*!< 0x00000001 */
8553 #define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */
8554 #define TIM2_OR1_ETR1_RMP_Pos     (1U)
8555 #define TIM2_OR1_ETR1_RMP_Msk     (0x1UL << TIM2_OR1_ETR1_RMP_Pos)             /*!< 0x00000002 */
8556 #define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */
8557 
8558 #define TIM2_OR1_TI4_RMP_Pos      (2U)
8559 #define TIM2_OR1_TI4_RMP_Msk      (0x3UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x0000000C */
8560 #define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
8561 #define TIM2_OR1_TI4_RMP_0        (0x1UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000004 */
8562 #define TIM2_OR1_TI4_RMP_1        (0x2UL << TIM2_OR1_TI4_RMP_Pos)              /*!< 0x00000008 */
8563 
8564 /*******************  Bit definition for TIM2_OR2 register  *******************/
8565 #define TIM2_OR2_ETRSEL_Pos       (14U)
8566 #define TIM2_OR2_ETRSEL_Msk       (0x7UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x0001C000 */
8567 #define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
8568 #define TIM2_OR2_ETRSEL_0         (0x1UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00004000 */
8569 #define TIM2_OR2_ETRSEL_1         (0x2UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00008000 */
8570 #define TIM2_OR2_ETRSEL_2         (0x4UL << TIM2_OR2_ETRSEL_Pos)               /*!< 0x00010000 */
8571 
8572 
8573 /*******************  Bit definition for TIM15_OR1 register  ******************/
8574 #define TIM15_OR1_TI1_RMP_Pos           (0U)
8575 #define TIM15_OR1_TI1_RMP_Msk           (0x1UL << TIM15_OR1_TI1_RMP_Pos)       /*!< 0x00000001 */
8576 #define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */
8577 
8578 #define TIM15_OR1_ENCODER_MODE_Pos      (1U)
8579 #define TIM15_OR1_ENCODER_MODE_Msk      (0x3UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000006 */
8580 #define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
8581 #define TIM15_OR1_ENCODER_MODE_0        (0x1UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000002 */
8582 #define TIM15_OR1_ENCODER_MODE_1        (0x2UL << TIM15_OR1_ENCODER_MODE_Pos)  /*!< 0x00000004 */
8583 
8584 /*******************  Bit definition for TIM15_OR2 register  ******************/
8585 #define TIM15_OR2_BKINE_Pos             (0U)
8586 #define TIM15_OR2_BKINE_Msk             (0x1UL << TIM15_OR2_BKINE_Pos)         /*!< 0x00000001 */
8587 #define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */
8588 #define TIM15_OR2_BKCMP1E_Pos           (1U)
8589 #define TIM15_OR2_BKCMP1E_Msk           (0x1UL << TIM15_OR2_BKCMP1E_Pos)       /*!< 0x00000002 */
8590 #define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */
8591 #define TIM15_OR2_BKINP_Pos             (9U)
8592 #define TIM15_OR2_BKINP_Msk             (0x1UL << TIM15_OR2_BKINP_Pos)         /*!< 0x00000200 */
8593 #define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */
8594 #define TIM15_OR2_BKCMP1P_Pos           (10U)
8595 #define TIM15_OR2_BKCMP1P_Msk           (0x1UL << TIM15_OR2_BKCMP1P_Pos)       /*!< 0x00000400 */
8596 #define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */
8597 
8598 /*******************  Bit definition for TIM16_OR1 register  ******************/
8599 #define TIM16_OR1_TI1_RMP_Pos      (0U)
8600 #define TIM16_OR1_TI1_RMP_Msk      (0x7UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000007 */
8601 #define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */
8602 #define TIM16_OR1_TI1_RMP_0        (0x1UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */
8603 #define TIM16_OR1_TI1_RMP_1        (0x2UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */
8604 #define TIM16_OR1_TI1_RMP_2        (0x4UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000004 */
8605 
8606 /*******************  Bit definition for TIM16_OR2 register  ******************/
8607 #define TIM16_OR2_BKINE_Pos        (0U)
8608 #define TIM16_OR2_BKINE_Msk        (0x1UL << TIM16_OR2_BKINE_Pos)              /*!< 0x00000001 */
8609 #define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
8610 #define TIM16_OR2_BKCMP1E_Pos      (1U)
8611 #define TIM16_OR2_BKCMP1E_Msk      (0x1UL << TIM16_OR2_BKCMP1E_Pos)            /*!< 0x00000002 */
8612 #define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
8613 #define TIM16_OR2_BKINP_Pos        (9U)
8614 #define TIM16_OR2_BKINP_Msk        (0x1UL << TIM16_OR2_BKINP_Pos)              /*!< 0x00000200 */
8615 #define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
8616 #define TIM16_OR2_BKCMP1P_Pos      (10U)
8617 #define TIM16_OR2_BKCMP1P_Msk      (0x1UL << TIM16_OR2_BKCMP1P_Pos)            /*!< 0x00000400 */
8618 #define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
8619 
8620 
8621 /******************************************************************************/
8622 /*                                                                            */
8623 /*                         Low Power Timer (LPTIM)                            */
8624 /*                                                                            */
8625 /******************************************************************************/
8626 /******************  Bit definition for LPTIM_ISR register  *******************/
8627 #define LPTIM_ISR_CMPM_Pos          (0U)
8628 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
8629 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
8630 #define LPTIM_ISR_ARRM_Pos          (1U)
8631 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
8632 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
8633 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
8634 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
8635 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
8636 #define LPTIM_ISR_CMPOK_Pos         (3U)
8637 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
8638 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
8639 #define LPTIM_ISR_ARROK_Pos         (4U)
8640 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
8641 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
8642 #define LPTIM_ISR_UP_Pos            (5U)
8643 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
8644 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
8645 #define LPTIM_ISR_DOWN_Pos          (6U)
8646 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
8647 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
8648 #define LPTIM_ISR_UE_Pos            (7U)
8649 #define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
8650 #define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event occurrence */
8651 #define LPTIM_ISR_REPOK_Pos         (8U)
8652 #define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)             /*!< 0x00000100 */
8653 #define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                        /*!< Repetition register update OK */
8654 
8655 /******************  Bit definition for LPTIM_ICR register  *******************/
8656 #define LPTIM_ICR_CMPMCF_Pos        (0U)
8657 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
8658 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
8659 #define LPTIM_ICR_ARRMCF_Pos        (1U)
8660 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
8661 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
8662 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
8663 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
8664 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
8665 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
8666 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
8667 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
8668 #define LPTIM_ICR_ARROKCF_Pos       (4U)
8669 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
8670 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
8671 #define LPTIM_ICR_UPCF_Pos          (5U)
8672 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
8673 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
8674 #define LPTIM_ICR_DOWNCF_Pos        (6U)
8675 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
8676 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
8677 #define LPTIM_ICR_UECF_Pos          (7U)
8678 #define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)               /*!< 0x00000080 */
8679 #define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event Clear Flag */
8680 #define LPTIM_ICR_REPOKCF_Pos       (8U)
8681 #define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)            /*!< 0x00000100 */
8682 #define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK Clear Flag */
8683 
8684 /******************  Bit definition for LPTIM_IER register ********************/
8685 #define LPTIM_IER_CMPMIE_Pos        (0U)
8686 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
8687 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
8688 #define LPTIM_IER_ARRMIE_Pos        (1U)
8689 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
8690 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
8691 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
8692 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
8693 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
8694 #define LPTIM_IER_CMPOKIE_Pos       (3U)
8695 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
8696 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
8697 #define LPTIM_IER_ARROKIE_Pos       (4U)
8698 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
8699 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
8700 #define LPTIM_IER_UPIE_Pos          (5U)
8701 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
8702 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
8703 #define LPTIM_IER_DOWNIE_Pos        (6U)
8704 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
8705 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
8706 #define LPTIM_IER_UEIE_Pos          (7U)
8707 #define LPTIM_IER_UEIE_Msk          (0x1UL << LPTIM_IER_UEIE_Pos)              /*!< 0x00000080 */
8708 #define LPTIM_IER_UEIE              LPTIM_IER_UEIE_Msk                         /*!< Update event Interrupt Enable */
8709 #define LPTIM_IER_REPOKIE_Pos       (8U)
8710 #define LPTIM_IER_REPOKIE_Msk       (0x1UL << LPTIM_IER_REPOKIE_Pos)           /*!< 0x00000100 */
8711 #define LPTIM_IER_REPOKIE           LPTIM_IER_REPOKIE_Msk                      /*!< Repetition register update OK Interrupt Enable */
8712 
8713 /******************  Bit definition for LPTIM_CFGR register *******************/
8714 #define LPTIM_CFGR_CKSEL_Pos        (0U)
8715 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
8716 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
8717 
8718 #define LPTIM_CFGR_CKPOL_Pos        (1U)
8719 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
8720 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
8721 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
8722 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
8723 
8724 #define LPTIM_CFGR_CKFLT_Pos        (3U)
8725 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
8726 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
8727 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
8728 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
8729 
8730 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
8731 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
8732 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
8733 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
8734 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
8735 
8736 #define LPTIM_CFGR_PRESC_Pos        (9U)
8737 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
8738 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
8739 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
8740 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
8741 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
8742 
8743 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
8744 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
8745 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
8746 #define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
8747 #define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
8748 #define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
8749 
8750 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
8751 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
8752 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
8753 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
8754 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
8755 
8756 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
8757 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
8758 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
8759 #define LPTIM_CFGR_WAVE_Pos         (20U)
8760 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
8761 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
8762 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
8763 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
8764 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
8765 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
8766 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
8767 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
8768 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
8769 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
8770 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
8771 #define LPTIM_CFGR_ENC_Pos          (24U)
8772 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
8773 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
8774 
8775 /******************  Bit definition for LPTIM_CR register  ********************/
8776 #define LPTIM_CR_ENABLE_Pos         (0U)
8777 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
8778 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
8779 #define LPTIM_CR_SNGSTRT_Pos        (1U)
8780 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
8781 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
8782 #define LPTIM_CR_CNTSTRT_Pos        (2U)
8783 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
8784 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
8785 #define LPTIM_CR_COUNTRST_Pos       (3U)
8786 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
8787 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
8788 #define LPTIM_CR_RSTARE_Pos         (4U)
8789 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
8790 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
8791 
8792 /******************  Bit definition for LPTIM_CMP register  *******************/
8793 #define LPTIM_CMP_CMP_Pos           (0U)
8794 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
8795 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
8796 
8797 /******************  Bit definition for LPTIM_ARR register  *******************/
8798 #define LPTIM_ARR_ARR_Pos           (0U)
8799 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
8800 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
8801 
8802 /******************  Bit definition for LPTIM_CNT register  *******************/
8803 #define LPTIM_CNT_CNT_Pos           (0U)
8804 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
8805 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
8806 
8807 /******************  Bit definition for LPTIM_OR register  ********************/
8808 #define LPTIM_OR_OR_Pos             (0U)
8809 #define LPTIM_OR_OR_Msk             (0x3UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000003 */
8810 #define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
8811 #define LPTIM_OR_OR_0               (0x1UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000001 */
8812 #define LPTIM_OR_OR_1               (0x2UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000002 */
8813 
8814 /******************  Bit definition for LPTIM_RCR register  *******************/
8815 #define LPTIM_RCR_REP_Pos           (0U)
8816 #define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
8817 #define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!<Repetition Counter Value */
8818 
8819 /******************************************************************************/
8820 /*                                                                            */
8821 /*                      Analog Comparators (COMP)                             */
8822 /*                                                                            */
8823 /******************************************************************************/
8824 /**********************  Bit definition for COMP_CSR register  ****************/
8825 #define COMP_CSR_EN_Pos            (0U)
8826 #define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
8827 #define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
8828 
8829 #define COMP_CSR_PWRMODE_Pos       (2U)
8830 #define COMP_CSR_PWRMODE_Msk       (0x3UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x0000000C */
8831 #define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
8832 #define COMP_CSR_PWRMODE_0         (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000004 */
8833 #define COMP_CSR_PWRMODE_1         (0x2UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000008 */
8834 
8835 #define COMP_CSR_INMSEL_Pos        (4U)
8836 #define COMP_CSR_INMSEL_Msk        (0x7UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
8837 #define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
8838 #define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
8839 #define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
8840 #define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
8841 
8842 #define COMP_CSR_INPSEL_Pos        (7U)
8843 #define COMP_CSR_INPSEL_Msk        (0x3UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000180 */
8844 #define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
8845 #define COMP_CSR_INPSEL_0          (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */
8846 #define COMP_CSR_INPSEL_1          (0x2UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
8847 
8848 #define COMP_CSR_POLARITY_Pos      (15U)
8849 #define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
8850 #define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
8851 
8852 #define COMP_CSR_HYST_Pos          (16U)
8853 #define COMP_CSR_HYST_Msk          (0x3UL << COMP_CSR_HYST_Pos)                /*!< 0x00030000 */
8854 #define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
8855 #define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
8856 #define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
8857 
8858 #define COMP_CSR_BLANKING_Pos      (18U)
8859 #define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x001C0000 */
8860 #define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
8861 #define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00040000 */
8862 #define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
8863 #define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
8864 
8865 #define COMP_CSR_BRGEN_Pos         (22U)
8866 #define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
8867 #define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
8868 #define COMP_CSR_SCALEN_Pos        (23U)
8869 #define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
8870 #define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
8871 
8872 #define COMP_CSR_INMESEL_Pos       (25U)
8873 #define COMP_CSR_INMESEL_Msk       (0x3UL << COMP_CSR_INMESEL_Pos)             /*!< 0x06000000 */
8874 #define COMP_CSR_INMESEL           COMP_CSR_INMESEL_Msk                        /*!< Comparator input minus extended selection */
8875 #define COMP_CSR_INMESEL_0         (0x1UL << COMP_CSR_INMESEL_Pos)             /*!< 0x02000000 */
8876 #define COMP_CSR_INMESEL_1         (0x2UL << COMP_CSR_INMESEL_Pos)             /*!< 0x04000000 */
8877 
8878 #define COMP_CSR_VALUE_Pos         (30U)
8879 #define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
8880 #define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
8881 
8882 #define COMP_CSR_LOCK_Pos          (31U)
8883 #define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
8884 #define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
8885 
8886 /******************************************************************************/
8887 /*                                                                            */
8888 /*                         Operational Amplifier (OPAMP)                      */
8889 /*                                                                            */
8890 /******************************************************************************/
8891 /*********************  Bit definition for OPAMPx_CSR register  ***************/
8892 #define OPAMP_CSR_OPAMPxEN_Pos           (0U)
8893 #define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */
8894 #define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
8895 #define OPAMP_CSR_OPALPM_Pos             (1U)
8896 #define OPAMP_CSR_OPALPM_Msk             (0x1UL << OPAMP_CSR_OPALPM_Pos)       /*!< 0x00000002 */
8897 #define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */
8898 
8899 #define OPAMP_CSR_OPAMODE_Pos            (2U)
8900 #define OPAMP_CSR_OPAMODE_Msk            (0x3UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x0000000C */
8901 #define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */
8902 #define OPAMP_CSR_OPAMODE_0              (0x1UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x00000004 */
8903 #define OPAMP_CSR_OPAMODE_1              (0x2UL << OPAMP_CSR_OPAMODE_Pos)      /*!< 0x00000008 */
8904 
8905 #define OPAMP_CSR_PGGAIN_Pos             (4U)
8906 #define OPAMP_CSR_PGGAIN_Msk             (0x3UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000030 */
8907 #define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
8908 #define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000010 */
8909 #define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x00000020 */
8910 
8911 #define OPAMP_CSR_VMSEL_Pos              (8U)
8912 #define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000300 */
8913 #define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
8914 #define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000100 */
8915 #define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000200 */
8916 
8917 #define OPAMP_CSR_VPSEL_Pos              (10U)
8918 #define OPAMP_CSR_VPSEL_Msk              (0x1UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x00000400 */
8919 #define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
8920 #define OPAMP_CSR_CALON_Pos              (12U)
8921 #define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00001000 */
8922 #define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
8923 #define OPAMP_CSR_CALSEL_Pos             (13U)
8924 #define OPAMP_CSR_CALSEL_Msk             (0x1UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00002000 */
8925 #define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
8926 #define OPAMP_CSR_USERTRIM_Pos           (14U)
8927 #define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00004000 */
8928 #define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
8929 #define OPAMP_CSR_CALOUT_Pos             (15U)
8930 #define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x00008000 */
8931 #define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */
8932 
8933 /*********************  Bit definition for OPAMP1_CSR register  ***************/
8934 #define OPAMP1_CSR_OPAEN_Pos              (0U)
8935 #define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */
8936 #define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
8937 #define OPAMP1_CSR_OPALPM_Pos             (1U)
8938 #define OPAMP1_CSR_OPALPM_Msk             (0x1UL << OPAMP1_CSR_OPALPM_Pos)     /*!< 0x00000002 */
8939 #define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */
8940 
8941 #define OPAMP1_CSR_OPAMODE_Pos            (2U)
8942 #define OPAMP1_CSR_OPAMODE_Msk            (0x3UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x0000000C */
8943 #define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */
8944 #define OPAMP1_CSR_OPAMODE_0              (0x1UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x00000004 */
8945 #define OPAMP1_CSR_OPAMODE_1              (0x2UL << OPAMP1_CSR_OPAMODE_Pos)    /*!< 0x00000008 */
8946 
8947 #define OPAMP1_CSR_PGAGAIN_Pos            (4U)
8948 #define OPAMP1_CSR_PGAGAIN_Msk            (0x3UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000030 */
8949 #define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */
8950 #define OPAMP1_CSR_PGAGAIN_0              (0x1UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000010 */
8951 #define OPAMP1_CSR_PGAGAIN_1              (0x2UL << OPAMP1_CSR_PGAGAIN_Pos)    /*!< 0x00000020 */
8952 
8953 #define OPAMP1_CSR_VMSEL_Pos              (8U)
8954 #define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000300 */
8955 #define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
8956 #define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000100 */
8957 #define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000200 */
8958 
8959 #define OPAMP1_CSR_VPSEL_Pos              (10U)
8960 #define OPAMP1_CSR_VPSEL_Msk              (0x1UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x00000400 */
8961 #define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
8962 #define OPAMP1_CSR_CALON_Pos              (12U)
8963 #define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00001000 */
8964 #define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
8965 #define OPAMP1_CSR_CALSEL_Pos             (13U)
8966 #define OPAMP1_CSR_CALSEL_Msk             (0x1UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00002000 */
8967 #define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
8968 #define OPAMP1_CSR_USERTRIM_Pos           (14U)
8969 #define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00004000 */
8970 #define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
8971 #define OPAMP1_CSR_CALOUT_Pos             (15U)
8972 #define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x00008000 */
8973 #define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
8974 
8975 #define OPAMP1_CSR_OPARANGE_Pos           (31U)
8976 #define OPAMP1_CSR_OPARANGE_Msk           (0x1UL << OPAMP1_CSR_OPARANGE_Pos)   /*!< 0x80000000 */
8977 #define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
8978 
8979 /*******************  Bit definition for OPAMP_OTR register  ******************/
8980 #define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
8981 #define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
8982 #define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
8983 #define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
8984 #define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
8985 #define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
8986 
8987 /*******************  Bit definition for OPAMP1_OTR register  ******************/
8988 #define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
8989 #define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
8990 #define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
8991 #define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
8992 #define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
8993 #define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
8994 
8995 /*******************  Bit definition for OPAMP_LPOTR register  ****************/
8996 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)
8997 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
8998 #define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
8999 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)
9000 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
9001 #define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
9002 
9003 /*******************  Bit definition for OPAMP1_LPOTR register  ****************/
9004 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)
9005 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
9006 #define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
9007 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)
9008 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
9009 #define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
9010 
9011 /******************************************************************************/
9012 /*                                                                            */
9013 /*                          Touch Sensing Controller (TSC)                    */
9014 /*                                                                            */
9015 /******************************************************************************/
9016 /*******************  Bit definition for TSC_CR register  *********************/
9017 #define TSC_CR_TSCE_Pos          (0U)
9018 #define TSC_CR_TSCE_Msk          (0x1UL << TSC_CR_TSCE_Pos)                    /*!< 0x00000001 */
9019 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
9020 #define TSC_CR_START_Pos         (1U)
9021 #define TSC_CR_START_Msk         (0x1UL << TSC_CR_START_Pos)                   /*!< 0x00000002 */
9022 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
9023 #define TSC_CR_AM_Pos            (2U)
9024 #define TSC_CR_AM_Msk            (0x1UL << TSC_CR_AM_Pos)                      /*!< 0x00000004 */
9025 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
9026 #define TSC_CR_SYNCPOL_Pos       (3U)
9027 #define TSC_CR_SYNCPOL_Msk       (0x1UL << TSC_CR_SYNCPOL_Pos)                 /*!< 0x00000008 */
9028 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
9029 #define TSC_CR_IODEF_Pos         (4U)
9030 #define TSC_CR_IODEF_Msk         (0x1UL << TSC_CR_IODEF_Pos)                   /*!< 0x00000010 */
9031 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
9032 
9033 #define TSC_CR_MCV_Pos           (5U)
9034 #define TSC_CR_MCV_Msk           (0x7UL << TSC_CR_MCV_Pos)                     /*!< 0x000000E0 */
9035 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
9036 #define TSC_CR_MCV_0             (0x1UL << TSC_CR_MCV_Pos)                     /*!< 0x00000020 */
9037 #define TSC_CR_MCV_1             (0x2UL << TSC_CR_MCV_Pos)                     /*!< 0x00000040 */
9038 #define TSC_CR_MCV_2             (0x4UL << TSC_CR_MCV_Pos)                     /*!< 0x00000080 */
9039 
9040 #define TSC_CR_PGPSC_Pos         (12U)
9041 #define TSC_CR_PGPSC_Msk         (0x7UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00007000 */
9042 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
9043 #define TSC_CR_PGPSC_0           (0x1UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00001000 */
9044 #define TSC_CR_PGPSC_1           (0x2UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00002000 */
9045 #define TSC_CR_PGPSC_2           (0x4UL << TSC_CR_PGPSC_Pos)                   /*!< 0x00004000 */
9046 
9047 #define TSC_CR_SSPSC_Pos         (15U)
9048 #define TSC_CR_SSPSC_Msk         (0x1UL << TSC_CR_SSPSC_Pos)                   /*!< 0x00008000 */
9049 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
9050 #define TSC_CR_SSE_Pos           (16U)
9051 #define TSC_CR_SSE_Msk           (0x1UL << TSC_CR_SSE_Pos)                     /*!< 0x00010000 */
9052 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
9053 
9054 #define TSC_CR_SSD_Pos           (17U)
9055 #define TSC_CR_SSD_Msk           (0x7FUL << TSC_CR_SSD_Pos)                    /*!< 0x00FE0000 */
9056 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
9057 #define TSC_CR_SSD_0             (0x01UL << TSC_CR_SSD_Pos)                    /*!< 0x00020000 */
9058 #define TSC_CR_SSD_1             (0x02UL << TSC_CR_SSD_Pos)                    /*!< 0x00040000 */
9059 #define TSC_CR_SSD_2             (0x04UL << TSC_CR_SSD_Pos)                    /*!< 0x00080000 */
9060 #define TSC_CR_SSD_3             (0x08UL << TSC_CR_SSD_Pos)                    /*!< 0x00100000 */
9061 #define TSC_CR_SSD_4             (0x10UL << TSC_CR_SSD_Pos)                    /*!< 0x00200000 */
9062 #define TSC_CR_SSD_5             (0x20UL << TSC_CR_SSD_Pos)                    /*!< 0x00400000 */
9063 #define TSC_CR_SSD_6             (0x40UL << TSC_CR_SSD_Pos)                    /*!< 0x00800000 */
9064 
9065 #define TSC_CR_CTPL_Pos          (24U)
9066 #define TSC_CR_CTPL_Msk          (0xFUL << TSC_CR_CTPL_Pos)                    /*!< 0x0F000000 */
9067 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
9068 #define TSC_CR_CTPL_0            (0x1UL << TSC_CR_CTPL_Pos)                    /*!< 0x01000000 */
9069 #define TSC_CR_CTPL_1            (0x2UL << TSC_CR_CTPL_Pos)                    /*!< 0x02000000 */
9070 #define TSC_CR_CTPL_2            (0x4UL << TSC_CR_CTPL_Pos)                    /*!< 0x04000000 */
9071 #define TSC_CR_CTPL_3            (0x8UL << TSC_CR_CTPL_Pos)                    /*!< 0x08000000 */
9072 
9073 #define TSC_CR_CTPH_Pos          (28U)
9074 #define TSC_CR_CTPH_Msk          (0xFUL << TSC_CR_CTPH_Pos)                    /*!< 0xF0000000 */
9075 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
9076 #define TSC_CR_CTPH_0            (0x1UL << TSC_CR_CTPH_Pos)                    /*!< 0x10000000 */
9077 #define TSC_CR_CTPH_1            (0x2UL << TSC_CR_CTPH_Pos)                    /*!< 0x20000000 */
9078 #define TSC_CR_CTPH_2            (0x4UL << TSC_CR_CTPH_Pos)                    /*!< 0x40000000 */
9079 #define TSC_CR_CTPH_3            (0x8UL << TSC_CR_CTPH_Pos)                    /*!< 0x80000000 */
9080 
9081 /*******************  Bit definition for TSC_IER register  ********************/
9082 #define TSC_IER_EOAIE_Pos        (0U)
9083 #define TSC_IER_EOAIE_Msk        (0x1UL << TSC_IER_EOAIE_Pos)                  /*!< 0x00000001 */
9084 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
9085 #define TSC_IER_MCEIE_Pos        (1U)
9086 #define TSC_IER_MCEIE_Msk        (0x1UL << TSC_IER_MCEIE_Pos)                  /*!< 0x00000002 */
9087 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
9088 
9089 /*******************  Bit definition for TSC_ICR register  ********************/
9090 #define TSC_ICR_EOAIC_Pos        (0U)
9091 #define TSC_ICR_EOAIC_Msk        (0x1UL << TSC_ICR_EOAIC_Pos)                  /*!< 0x00000001 */
9092 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
9093 #define TSC_ICR_MCEIC_Pos        (1U)
9094 #define TSC_ICR_MCEIC_Msk        (0x1UL << TSC_ICR_MCEIC_Pos)                  /*!< 0x00000002 */
9095 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
9096 
9097 /*******************  Bit definition for TSC_ISR register  ********************/
9098 #define TSC_ISR_EOAF_Pos         (0U)
9099 #define TSC_ISR_EOAF_Msk         (0x1UL << TSC_ISR_EOAF_Pos)                   /*!< 0x00000001 */
9100 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
9101 #define TSC_ISR_MCEF_Pos         (1U)
9102 #define TSC_ISR_MCEF_Msk         (0x1UL << TSC_ISR_MCEF_Pos)                   /*!< 0x00000002 */
9103 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
9104 
9105 /*******************  Bit definition for TSC_IOHCR register  ******************/
9106 #define TSC_IOHCR_G1_IO1_Pos     (0U)
9107 #define TSC_IOHCR_G1_IO1_Msk     (0x1UL << TSC_IOHCR_G1_IO1_Pos)               /*!< 0x00000001 */
9108 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
9109 #define TSC_IOHCR_G1_IO2_Pos     (1U)
9110 #define TSC_IOHCR_G1_IO2_Msk     (0x1UL << TSC_IOHCR_G1_IO2_Pos)               /*!< 0x00000002 */
9111 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
9112 #define TSC_IOHCR_G1_IO3_Pos     (2U)
9113 #define TSC_IOHCR_G1_IO3_Msk     (0x1UL << TSC_IOHCR_G1_IO3_Pos)               /*!< 0x00000004 */
9114 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
9115 #define TSC_IOHCR_G1_IO4_Pos     (3U)
9116 #define TSC_IOHCR_G1_IO4_Msk     (0x1UL << TSC_IOHCR_G1_IO4_Pos)               /*!< 0x00000008 */
9117 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
9118 #define TSC_IOHCR_G2_IO1_Pos     (4U)
9119 #define TSC_IOHCR_G2_IO1_Msk     (0x1UL << TSC_IOHCR_G2_IO1_Pos)               /*!< 0x00000010 */
9120 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
9121 #define TSC_IOHCR_G2_IO2_Pos     (5U)
9122 #define TSC_IOHCR_G2_IO2_Msk     (0x1UL << TSC_IOHCR_G2_IO2_Pos)               /*!< 0x00000020 */
9123 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
9124 #define TSC_IOHCR_G2_IO3_Pos     (6U)
9125 #define TSC_IOHCR_G2_IO3_Msk     (0x1UL << TSC_IOHCR_G2_IO3_Pos)               /*!< 0x00000040 */
9126 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
9127 #define TSC_IOHCR_G2_IO4_Pos     (7U)
9128 #define TSC_IOHCR_G2_IO4_Msk     (0x1UL << TSC_IOHCR_G2_IO4_Pos)               /*!< 0x00000080 */
9129 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
9130 #define TSC_IOHCR_G3_IO1_Pos     (8U)
9131 #define TSC_IOHCR_G3_IO1_Msk     (0x1UL << TSC_IOHCR_G3_IO1_Pos)               /*!< 0x00000100 */
9132 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
9133 #define TSC_IOHCR_G3_IO2_Pos     (9U)
9134 #define TSC_IOHCR_G3_IO2_Msk     (0x1UL << TSC_IOHCR_G3_IO2_Pos)               /*!< 0x00000200 */
9135 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
9136 #define TSC_IOHCR_G3_IO3_Pos     (10U)
9137 #define TSC_IOHCR_G3_IO3_Msk     (0x1UL << TSC_IOHCR_G3_IO3_Pos)               /*!< 0x00000400 */
9138 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
9139 #define TSC_IOHCR_G3_IO4_Pos     (11U)
9140 #define TSC_IOHCR_G3_IO4_Msk     (0x1UL << TSC_IOHCR_G3_IO4_Pos)               /*!< 0x00000800 */
9141 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
9142 #define TSC_IOHCR_G4_IO1_Pos     (12U)
9143 #define TSC_IOHCR_G4_IO1_Msk     (0x1UL << TSC_IOHCR_G4_IO1_Pos)               /*!< 0x00001000 */
9144 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
9145 #define TSC_IOHCR_G4_IO2_Pos     (13U)
9146 #define TSC_IOHCR_G4_IO2_Msk     (0x1UL << TSC_IOHCR_G4_IO2_Pos)               /*!< 0x00002000 */
9147 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
9148 #define TSC_IOHCR_G4_IO3_Pos     (14U)
9149 #define TSC_IOHCR_G4_IO3_Msk     (0x1UL << TSC_IOHCR_G4_IO3_Pos)               /*!< 0x00004000 */
9150 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
9151 #define TSC_IOHCR_G4_IO4_Pos     (15U)
9152 #define TSC_IOHCR_G4_IO4_Msk     (0x1UL << TSC_IOHCR_G4_IO4_Pos)               /*!< 0x00008000 */
9153 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
9154 
9155 /*******************  Bit definition for TSC_IOASCR register  *****************/
9156 #define TSC_IOASCR_G1_IO1_Pos    (0U)
9157 #define TSC_IOASCR_G1_IO1_Msk    (0x1UL << TSC_IOASCR_G1_IO1_Pos)              /*!< 0x00000001 */
9158 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
9159 #define TSC_IOASCR_G1_IO2_Pos    (1U)
9160 #define TSC_IOASCR_G1_IO2_Msk    (0x1UL << TSC_IOASCR_G1_IO2_Pos)              /*!< 0x00000002 */
9161 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
9162 #define TSC_IOASCR_G1_IO3_Pos    (2U)
9163 #define TSC_IOASCR_G1_IO3_Msk    (0x1UL << TSC_IOASCR_G1_IO3_Pos)              /*!< 0x00000004 */
9164 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
9165 #define TSC_IOASCR_G1_IO4_Pos    (3U)
9166 #define TSC_IOASCR_G1_IO4_Msk    (0x1UL << TSC_IOASCR_G1_IO4_Pos)              /*!< 0x00000008 */
9167 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
9168 #define TSC_IOASCR_G2_IO1_Pos    (4U)
9169 #define TSC_IOASCR_G2_IO1_Msk    (0x1UL << TSC_IOASCR_G2_IO1_Pos)              /*!< 0x00000010 */
9170 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
9171 #define TSC_IOASCR_G2_IO2_Pos    (5U)
9172 #define TSC_IOASCR_G2_IO2_Msk    (0x1UL << TSC_IOASCR_G2_IO2_Pos)              /*!< 0x00000020 */
9173 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
9174 #define TSC_IOASCR_G2_IO3_Pos    (6U)
9175 #define TSC_IOASCR_G2_IO3_Msk    (0x1UL << TSC_IOASCR_G2_IO3_Pos)              /*!< 0x00000040 */
9176 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
9177 #define TSC_IOASCR_G2_IO4_Pos    (7U)
9178 #define TSC_IOASCR_G2_IO4_Msk    (0x1UL << TSC_IOASCR_G2_IO4_Pos)              /*!< 0x00000080 */
9179 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
9180 #define TSC_IOASCR_G3_IO1_Pos    (8U)
9181 #define TSC_IOASCR_G3_IO1_Msk    (0x1UL << TSC_IOASCR_G3_IO1_Pos)              /*!< 0x00000100 */
9182 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
9183 #define TSC_IOASCR_G3_IO2_Pos    (9U)
9184 #define TSC_IOASCR_G3_IO2_Msk    (0x1UL << TSC_IOASCR_G3_IO2_Pos)              /*!< 0x00000200 */
9185 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
9186 #define TSC_IOASCR_G3_IO3_Pos    (10U)
9187 #define TSC_IOASCR_G3_IO3_Msk    (0x1UL << TSC_IOASCR_G3_IO3_Pos)              /*!< 0x00000400 */
9188 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
9189 #define TSC_IOASCR_G3_IO4_Pos    (11U)
9190 #define TSC_IOASCR_G3_IO4_Msk    (0x1UL << TSC_IOASCR_G3_IO4_Pos)              /*!< 0x00000800 */
9191 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
9192 #define TSC_IOASCR_G4_IO1_Pos    (12U)
9193 #define TSC_IOASCR_G4_IO1_Msk    (0x1UL << TSC_IOASCR_G4_IO1_Pos)              /*!< 0x00001000 */
9194 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
9195 #define TSC_IOASCR_G4_IO2_Pos    (13U)
9196 #define TSC_IOASCR_G4_IO2_Msk    (0x1UL << TSC_IOASCR_G4_IO2_Pos)              /*!< 0x00002000 */
9197 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
9198 #define TSC_IOASCR_G4_IO3_Pos    (14U)
9199 #define TSC_IOASCR_G4_IO3_Msk    (0x1UL << TSC_IOASCR_G4_IO3_Pos)              /*!< 0x00004000 */
9200 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
9201 #define TSC_IOASCR_G4_IO4_Pos    (15U)
9202 #define TSC_IOASCR_G4_IO4_Msk    (0x1UL << TSC_IOASCR_G4_IO4_Pos)              /*!< 0x00008000 */
9203 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
9204 
9205 /*******************  Bit definition for TSC_IOSCR register  ******************/
9206 #define TSC_IOSCR_G1_IO1_Pos     (0U)
9207 #define TSC_IOSCR_G1_IO1_Msk     (0x1UL << TSC_IOSCR_G1_IO1_Pos)               /*!< 0x00000001 */
9208 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
9209 #define TSC_IOSCR_G1_IO2_Pos     (1U)
9210 #define TSC_IOSCR_G1_IO2_Msk     (0x1UL << TSC_IOSCR_G1_IO2_Pos)               /*!< 0x00000002 */
9211 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
9212 #define TSC_IOSCR_G1_IO3_Pos     (2U)
9213 #define TSC_IOSCR_G1_IO3_Msk     (0x1UL << TSC_IOSCR_G1_IO3_Pos)               /*!< 0x00000004 */
9214 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
9215 #define TSC_IOSCR_G1_IO4_Pos     (3U)
9216 #define TSC_IOSCR_G1_IO4_Msk     (0x1UL << TSC_IOSCR_G1_IO4_Pos)               /*!< 0x00000008 */
9217 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
9218 #define TSC_IOSCR_G2_IO1_Pos     (4U)
9219 #define TSC_IOSCR_G2_IO1_Msk     (0x1UL << TSC_IOSCR_G2_IO1_Pos)               /*!< 0x00000010 */
9220 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
9221 #define TSC_IOSCR_G2_IO2_Pos     (5U)
9222 #define TSC_IOSCR_G2_IO2_Msk     (0x1UL << TSC_IOSCR_G2_IO2_Pos)               /*!< 0x00000020 */
9223 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
9224 #define TSC_IOSCR_G2_IO3_Pos     (6U)
9225 #define TSC_IOSCR_G2_IO3_Msk     (0x1UL << TSC_IOSCR_G2_IO3_Pos)               /*!< 0x00000040 */
9226 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
9227 #define TSC_IOSCR_G2_IO4_Pos     (7U)
9228 #define TSC_IOSCR_G2_IO4_Msk     (0x1UL << TSC_IOSCR_G2_IO4_Pos)               /*!< 0x00000080 */
9229 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
9230 #define TSC_IOSCR_G3_IO1_Pos     (8U)
9231 #define TSC_IOSCR_G3_IO1_Msk     (0x1UL << TSC_IOSCR_G3_IO1_Pos)               /*!< 0x00000100 */
9232 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
9233 #define TSC_IOSCR_G3_IO2_Pos     (9U)
9234 #define TSC_IOSCR_G3_IO2_Msk     (0x1UL << TSC_IOSCR_G3_IO2_Pos)               /*!< 0x00000200 */
9235 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
9236 #define TSC_IOSCR_G3_IO3_Pos     (10U)
9237 #define TSC_IOSCR_G3_IO3_Msk     (0x1UL << TSC_IOSCR_G3_IO3_Pos)               /*!< 0x00000400 */
9238 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
9239 #define TSC_IOSCR_G3_IO4_Pos     (11U)
9240 #define TSC_IOSCR_G3_IO4_Msk     (0x1UL << TSC_IOSCR_G3_IO4_Pos)               /*!< 0x00000800 */
9241 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
9242 #define TSC_IOSCR_G4_IO1_Pos     (12U)
9243 #define TSC_IOSCR_G4_IO1_Msk     (0x1UL << TSC_IOSCR_G4_IO1_Pos)               /*!< 0x00001000 */
9244 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
9245 #define TSC_IOSCR_G4_IO2_Pos     (13U)
9246 #define TSC_IOSCR_G4_IO2_Msk     (0x1UL << TSC_IOSCR_G4_IO2_Pos)               /*!< 0x00002000 */
9247 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
9248 #define TSC_IOSCR_G4_IO3_Pos     (14U)
9249 #define TSC_IOSCR_G4_IO3_Msk     (0x1UL << TSC_IOSCR_G4_IO3_Pos)               /*!< 0x00004000 */
9250 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
9251 #define TSC_IOSCR_G4_IO4_Pos     (15U)
9252 #define TSC_IOSCR_G4_IO4_Msk     (0x1UL << TSC_IOSCR_G4_IO4_Pos)               /*!< 0x00008000 */
9253 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
9254 
9255 /*******************  Bit definition for TSC_IOCCR register  ******************/
9256 #define TSC_IOCCR_G1_IO1_Pos     (0U)
9257 #define TSC_IOCCR_G1_IO1_Msk     (0x1UL << TSC_IOCCR_G1_IO1_Pos)               /*!< 0x00000001 */
9258 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
9259 #define TSC_IOCCR_G1_IO2_Pos     (1U)
9260 #define TSC_IOCCR_G1_IO2_Msk     (0x1UL << TSC_IOCCR_G1_IO2_Pos)               /*!< 0x00000002 */
9261 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
9262 #define TSC_IOCCR_G1_IO3_Pos     (2U)
9263 #define TSC_IOCCR_G1_IO3_Msk     (0x1UL << TSC_IOCCR_G1_IO3_Pos)               /*!< 0x00000004 */
9264 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
9265 #define TSC_IOCCR_G1_IO4_Pos     (3U)
9266 #define TSC_IOCCR_G1_IO4_Msk     (0x1UL << TSC_IOCCR_G1_IO4_Pos)               /*!< 0x00000008 */
9267 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
9268 #define TSC_IOCCR_G2_IO1_Pos     (4U)
9269 #define TSC_IOCCR_G2_IO1_Msk     (0x1UL << TSC_IOCCR_G2_IO1_Pos)               /*!< 0x00000010 */
9270 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
9271 #define TSC_IOCCR_G2_IO2_Pos     (5U)
9272 #define TSC_IOCCR_G2_IO2_Msk     (0x1UL << TSC_IOCCR_G2_IO2_Pos)               /*!< 0x00000020 */
9273 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
9274 #define TSC_IOCCR_G2_IO3_Pos     (6U)
9275 #define TSC_IOCCR_G2_IO3_Msk     (0x1UL << TSC_IOCCR_G2_IO3_Pos)               /*!< 0x00000040 */
9276 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
9277 #define TSC_IOCCR_G2_IO4_Pos     (7U)
9278 #define TSC_IOCCR_G2_IO4_Msk     (0x1UL << TSC_IOCCR_G2_IO4_Pos)               /*!< 0x00000080 */
9279 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
9280 #define TSC_IOCCR_G3_IO1_Pos     (8U)
9281 #define TSC_IOCCR_G3_IO1_Msk     (0x1UL << TSC_IOCCR_G3_IO1_Pos)               /*!< 0x00000100 */
9282 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
9283 #define TSC_IOCCR_G3_IO2_Pos     (9U)
9284 #define TSC_IOCCR_G3_IO2_Msk     (0x1UL << TSC_IOCCR_G3_IO2_Pos)               /*!< 0x00000200 */
9285 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
9286 #define TSC_IOCCR_G3_IO3_Pos     (10U)
9287 #define TSC_IOCCR_G3_IO3_Msk     (0x1UL << TSC_IOCCR_G3_IO3_Pos)               /*!< 0x00000400 */
9288 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
9289 #define TSC_IOCCR_G3_IO4_Pos     (11U)
9290 #define TSC_IOCCR_G3_IO4_Msk     (0x1UL << TSC_IOCCR_G3_IO4_Pos)               /*!< 0x00000800 */
9291 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
9292 #define TSC_IOCCR_G4_IO1_Pos     (12U)
9293 #define TSC_IOCCR_G4_IO1_Msk     (0x1UL << TSC_IOCCR_G4_IO1_Pos)               /*!< 0x00001000 */
9294 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
9295 #define TSC_IOCCR_G4_IO2_Pos     (13U)
9296 #define TSC_IOCCR_G4_IO2_Msk     (0x1UL << TSC_IOCCR_G4_IO2_Pos)               /*!< 0x00002000 */
9297 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
9298 #define TSC_IOCCR_G4_IO3_Pos     (14U)
9299 #define TSC_IOCCR_G4_IO3_Msk     (0x1UL << TSC_IOCCR_G4_IO3_Pos)               /*!< 0x00004000 */
9300 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
9301 #define TSC_IOCCR_G4_IO4_Pos     (15U)
9302 #define TSC_IOCCR_G4_IO4_Msk     (0x1UL << TSC_IOCCR_G4_IO4_Pos)               /*!< 0x00008000 */
9303 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
9304 
9305 /*******************  Bit definition for TSC_IOGCSR register  *****************/
9306 #define TSC_IOGCSR_G1E_Pos       (0U)
9307 #define TSC_IOGCSR_G1E_Msk       (0x1UL << TSC_IOGCSR_G1E_Pos)                 /*!< 0x00000001 */
9308 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
9309 #define TSC_IOGCSR_G2E_Pos       (1U)
9310 #define TSC_IOGCSR_G2E_Msk       (0x1UL << TSC_IOGCSR_G2E_Pos)                 /*!< 0x00000002 */
9311 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
9312 #define TSC_IOGCSR_G3E_Pos       (2U)
9313 #define TSC_IOGCSR_G3E_Msk       (0x1UL << TSC_IOGCSR_G3E_Pos)                 /*!< 0x00000004 */
9314 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
9315 #define TSC_IOGCSR_G4E_Pos       (3U)
9316 #define TSC_IOGCSR_G4E_Msk       (0x1UL << TSC_IOGCSR_G4E_Pos)                 /*!< 0x00000008 */
9317 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
9318 #define TSC_IOGCSR_G1S_Pos       (16U)
9319 #define TSC_IOGCSR_G1S_Msk       (0x1UL << TSC_IOGCSR_G1S_Pos)                 /*!< 0x00010000 */
9320 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
9321 #define TSC_IOGCSR_G2S_Pos       (17U)
9322 #define TSC_IOGCSR_G2S_Msk       (0x1UL << TSC_IOGCSR_G2S_Pos)                 /*!< 0x00020000 */
9323 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
9324 #define TSC_IOGCSR_G3S_Pos       (18U)
9325 #define TSC_IOGCSR_G3S_Msk       (0x1UL << TSC_IOGCSR_G3S_Pos)                 /*!< 0x00040000 */
9326 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
9327 #define TSC_IOGCSR_G4S_Pos       (19U)
9328 #define TSC_IOGCSR_G4S_Msk       (0x1UL << TSC_IOGCSR_G4S_Pos)                 /*!< 0x00080000 */
9329 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
9330 
9331 /*******************  Bit definition for TSC_IOGXCR register  *****************/
9332 #define TSC_IOGXCR_CNT_Pos       (0U)
9333 #define TSC_IOGXCR_CNT_Msk       (0x3FFFUL << TSC_IOGXCR_CNT_Pos)              /*!< 0x00003FFF */
9334 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
9335 
9336 /******************************************************************************/
9337 /*                                                                            */
9338 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
9339 /*                                                                            */
9340 /******************************************************************************/
9341 
9342 /*
9343 * @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
9344 */
9345 #define USART_TCBGT_SUPPORT
9346 
9347 /******************  Bit definition for USART_CR1 register  *******************/
9348 #define USART_CR1_UE_Pos              (0U)
9349 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)              /*!< 0x00000001 */
9350 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
9351 #define USART_CR1_UESM_Pos            (1U)
9352 #define USART_CR1_UESM_Msk            (0x1UL << USART_CR1_UESM_Pos)            /*!< 0x00000002 */
9353 #define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
9354 #define USART_CR1_RE_Pos              (2U)
9355 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)              /*!< 0x00000004 */
9356 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
9357 #define USART_CR1_TE_Pos              (3U)
9358 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)              /*!< 0x00000008 */
9359 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
9360 #define USART_CR1_IDLEIE_Pos          (4U)
9361 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)          /*!< 0x00000010 */
9362 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
9363 #define USART_CR1_RXNEIE_Pos          (5U)
9364 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)          /*!< 0x00000020 */
9365 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
9366 #define USART_CR1_TCIE_Pos            (6U)
9367 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)            /*!< 0x00000040 */
9368 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
9369 #define USART_CR1_TXEIE_Pos           (7U)
9370 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)           /*!< 0x00000080 */
9371 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
9372 #define USART_CR1_PEIE_Pos            (8U)
9373 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)            /*!< 0x00000100 */
9374 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
9375 #define USART_CR1_PS_Pos              (9U)
9376 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)              /*!< 0x00000200 */
9377 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
9378 #define USART_CR1_PCE_Pos             (10U)
9379 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)             /*!< 0x00000400 */
9380 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
9381 #define USART_CR1_WAKE_Pos            (11U)
9382 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)            /*!< 0x00000800 */
9383 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
9384 #define USART_CR1_M_Pos               (12U)
9385 #define USART_CR1_M_Msk               (0x10001UL << USART_CR1_M_Pos)           /*!< 0x10001000 */
9386 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
9387 #define USART_CR1_M0_Pos              (12U)
9388 #define USART_CR1_M0_Msk              (0x1UL << USART_CR1_M0_Pos)              /*!< 0x00001000 */
9389 #define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
9390 #define USART_CR1_MME_Pos             (13U)
9391 #define USART_CR1_MME_Msk             (0x1UL << USART_CR1_MME_Pos)             /*!< 0x00002000 */
9392 #define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
9393 #define USART_CR1_CMIE_Pos            (14U)
9394 #define USART_CR1_CMIE_Msk            (0x1UL << USART_CR1_CMIE_Pos)            /*!< 0x00004000 */
9395 #define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
9396 #define USART_CR1_OVER8_Pos           (15U)
9397 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)           /*!< 0x00008000 */
9398 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
9399 #define USART_CR1_DEDT_Pos            (16U)
9400 #define USART_CR1_DEDT_Msk            (0x1FUL << USART_CR1_DEDT_Pos)           /*!< 0x001F0000 */
9401 #define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
9402 #define USART_CR1_DEDT_0              (0x01UL << USART_CR1_DEDT_Pos)           /*!< 0x00010000 */
9403 #define USART_CR1_DEDT_1              (0x02UL << USART_CR1_DEDT_Pos)           /*!< 0x00020000 */
9404 #define USART_CR1_DEDT_2              (0x04UL << USART_CR1_DEDT_Pos)           /*!< 0x00040000 */
9405 #define USART_CR1_DEDT_3              (0x08UL << USART_CR1_DEDT_Pos)           /*!< 0x00080000 */
9406 #define USART_CR1_DEDT_4              (0x10UL << USART_CR1_DEDT_Pos)           /*!< 0x00100000 */
9407 #define USART_CR1_DEAT_Pos            (21U)
9408 #define USART_CR1_DEAT_Msk            (0x1FUL << USART_CR1_DEAT_Pos)           /*!< 0x03E00000 */
9409 #define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
9410 #define USART_CR1_DEAT_0              (0x01UL << USART_CR1_DEAT_Pos)           /*!< 0x00200000 */
9411 #define USART_CR1_DEAT_1              (0x02UL << USART_CR1_DEAT_Pos)           /*!< 0x00400000 */
9412 #define USART_CR1_DEAT_2              (0x04UL << USART_CR1_DEAT_Pos)           /*!< 0x00800000 */
9413 #define USART_CR1_DEAT_3              (0x08UL << USART_CR1_DEAT_Pos)           /*!< 0x01000000 */
9414 #define USART_CR1_DEAT_4              (0x10UL << USART_CR1_DEAT_Pos)           /*!< 0x02000000 */
9415 #define USART_CR1_RTOIE_Pos           (26U)
9416 #define USART_CR1_RTOIE_Msk           (0x1UL << USART_CR1_RTOIE_Pos)           /*!< 0x04000000 */
9417 #define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
9418 #define USART_CR1_EOBIE_Pos           (27U)
9419 #define USART_CR1_EOBIE_Msk           (0x1UL << USART_CR1_EOBIE_Pos)           /*!< 0x08000000 */
9420 #define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
9421 #define USART_CR1_M1_Pos              (28U)
9422 #define USART_CR1_M1_Msk              (0x1UL << USART_CR1_M1_Pos)              /*!< 0x10000000 */
9423 #define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
9424 
9425 /******************  Bit definition for USART_CR2 register  *******************/
9426 #define USART_CR2_ADDM7_Pos           (4U)
9427 #define USART_CR2_ADDM7_Msk           (0x1UL << USART_CR2_ADDM7_Pos)           /*!< 0x00000010 */
9428 #define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
9429 #define USART_CR2_LBDL_Pos            (5U)
9430 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)            /*!< 0x00000020 */
9431 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
9432 #define USART_CR2_LBDIE_Pos           (6U)
9433 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)           /*!< 0x00000040 */
9434 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
9435 #define USART_CR2_LBCL_Pos            (8U)
9436 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)            /*!< 0x00000100 */
9437 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
9438 #define USART_CR2_CPHA_Pos            (9U)
9439 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)            /*!< 0x00000200 */
9440 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
9441 #define USART_CR2_CPOL_Pos            (10U)
9442 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)            /*!< 0x00000400 */
9443 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
9444 #define USART_CR2_CLKEN_Pos           (11U)
9445 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)           /*!< 0x00000800 */
9446 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
9447 #define USART_CR2_STOP_Pos            (12U)
9448 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)            /*!< 0x00003000 */
9449 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
9450 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)            /*!< 0x00001000 */
9451 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)            /*!< 0x00002000 */
9452 #define USART_CR2_LINEN_Pos           (14U)
9453 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)           /*!< 0x00004000 */
9454 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
9455 #define USART_CR2_SWAP_Pos            (15U)
9456 #define USART_CR2_SWAP_Msk            (0x1UL << USART_CR2_SWAP_Pos)            /*!< 0x00008000 */
9457 #define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
9458 #define USART_CR2_RXINV_Pos           (16U)
9459 #define USART_CR2_RXINV_Msk           (0x1UL << USART_CR2_RXINV_Pos)           /*!< 0x00010000 */
9460 #define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
9461 #define USART_CR2_TXINV_Pos           (17U)
9462 #define USART_CR2_TXINV_Msk           (0x1UL << USART_CR2_TXINV_Pos)           /*!< 0x00020000 */
9463 #define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
9464 #define USART_CR2_DATAINV_Pos         (18U)
9465 #define USART_CR2_DATAINV_Msk         (0x1UL << USART_CR2_DATAINV_Pos)         /*!< 0x00040000 */
9466 #define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
9467 #define USART_CR2_MSBFIRST_Pos        (19U)
9468 #define USART_CR2_MSBFIRST_Msk        (0x1UL << USART_CR2_MSBFIRST_Pos)        /*!< 0x00080000 */
9469 #define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
9470 #define USART_CR2_ABREN_Pos           (20U)
9471 #define USART_CR2_ABREN_Msk           (0x1UL << USART_CR2_ABREN_Pos)           /*!< 0x00100000 */
9472 #define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
9473 #define USART_CR2_ABRMODE_Pos         (21U)
9474 #define USART_CR2_ABRMODE_Msk         (0x3UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00600000 */
9475 #define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
9476 #define USART_CR2_ABRMODE_0           (0x1UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00200000 */
9477 #define USART_CR2_ABRMODE_1           (0x2UL << USART_CR2_ABRMODE_Pos)         /*!< 0x00400000 */
9478 #define USART_CR2_RTOEN_Pos           (23U)
9479 #define USART_CR2_RTOEN_Msk           (0x1UL << USART_CR2_RTOEN_Pos)           /*!< 0x00800000 */
9480 #define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
9481 #define USART_CR2_ADD_Pos             (24U)
9482 #define USART_CR2_ADD_Msk             (0xFFUL << USART_CR2_ADD_Pos)            /*!< 0xFF000000 */
9483 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
9484 
9485 /******************  Bit definition for USART_CR3 register  *******************/
9486 #define USART_CR3_EIE_Pos             (0U)
9487 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)             /*!< 0x00000001 */
9488 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
9489 #define USART_CR3_IREN_Pos            (1U)
9490 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)            /*!< 0x00000002 */
9491 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
9492 #define USART_CR3_IRLP_Pos            (2U)
9493 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)            /*!< 0x00000004 */
9494 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
9495 #define USART_CR3_HDSEL_Pos           (3U)
9496 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)           /*!< 0x00000008 */
9497 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
9498 #define USART_CR3_NACK_Pos            (4U)
9499 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)            /*!< 0x00000010 */
9500 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
9501 #define USART_CR3_SCEN_Pos            (5U)
9502 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)            /*!< 0x00000020 */
9503 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
9504 #define USART_CR3_DMAR_Pos            (6U)
9505 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)            /*!< 0x00000040 */
9506 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
9507 #define USART_CR3_DMAT_Pos            (7U)
9508 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)            /*!< 0x00000080 */
9509 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
9510 #define USART_CR3_RTSE_Pos            (8U)
9511 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)            /*!< 0x00000100 */
9512 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
9513 #define USART_CR3_CTSE_Pos            (9U)
9514 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)            /*!< 0x00000200 */
9515 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
9516 #define USART_CR3_CTSIE_Pos           (10U)
9517 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)           /*!< 0x00000400 */
9518 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
9519 #define USART_CR3_ONEBIT_Pos          (11U)
9520 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)          /*!< 0x00000800 */
9521 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
9522 #define USART_CR3_OVRDIS_Pos          (12U)
9523 #define USART_CR3_OVRDIS_Msk          (0x1UL << USART_CR3_OVRDIS_Pos)          /*!< 0x00001000 */
9524 #define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
9525 #define USART_CR3_DDRE_Pos            (13U)
9526 #define USART_CR3_DDRE_Msk            (0x1UL << USART_CR3_DDRE_Pos)            /*!< 0x00002000 */
9527 #define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
9528 #define USART_CR3_DEM_Pos             (14U)
9529 #define USART_CR3_DEM_Msk             (0x1UL << USART_CR3_DEM_Pos)             /*!< 0x00004000 */
9530 #define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
9531 #define USART_CR3_DEP_Pos             (15U)
9532 #define USART_CR3_DEP_Msk             (0x1UL << USART_CR3_DEP_Pos)             /*!< 0x00008000 */
9533 #define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
9534 #define USART_CR3_SCARCNT_Pos         (17U)
9535 #define USART_CR3_SCARCNT_Msk         (0x7UL << USART_CR3_SCARCNT_Pos)         /*!< 0x000E0000 */
9536 #define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
9537 #define USART_CR3_SCARCNT_0           (0x1UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00020000 */
9538 #define USART_CR3_SCARCNT_1           (0x2UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00040000 */
9539 #define USART_CR3_SCARCNT_2           (0x4UL << USART_CR3_SCARCNT_Pos)         /*!< 0x00080000 */
9540 #define USART_CR3_WUS_Pos             (20U)
9541 #define USART_CR3_WUS_Msk             (0x3UL << USART_CR3_WUS_Pos)             /*!< 0x00300000 */
9542 #define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
9543 #define USART_CR3_WUS_0               (0x1UL << USART_CR3_WUS_Pos)             /*!< 0x00100000 */
9544 #define USART_CR3_WUS_1               (0x2UL << USART_CR3_WUS_Pos)             /*!< 0x00200000 */
9545 #define USART_CR3_WUFIE_Pos           (22U)
9546 #define USART_CR3_WUFIE_Msk           (0x1UL << USART_CR3_WUFIE_Pos)           /*!< 0x00400000 */
9547 #define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
9548 #define USART_CR3_UCESM_Pos           (23U)
9549 #define USART_CR3_UCESM_Msk           (0x1UL << USART_CR3_UCESM_Pos)           /*!< 0x02000000 */
9550 #define USART_CR3_UCESM               USART_CR3_UCESM_Msk                      /*!< USART Clock enable in Stop mode */
9551 #define USART_CR3_TCBGTIE_Pos         (24U)
9552 #define USART_CR3_TCBGTIE_Msk         (0x1UL << USART_CR3_TCBGTIE_Pos)         /*!< 0x01000000 */
9553 #define USART_CR3_TCBGTIE             USART_CR3_TCBGTIE_Msk                    /*!< Transmission Complete Before Guard Time Interrupt Enable */
9554 
9555 /******************  Bit definition for USART_BRR register  *******************/
9556 #define USART_BRR_DIV_FRACTION_Pos    (0U)
9557 #define USART_BRR_DIV_FRACTION_Msk    (0xFUL << USART_BRR_DIV_FRACTION_Pos)    /*!< 0x0000000F */
9558 #define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
9559 #define USART_BRR_DIV_MANTISSA_Pos    (4U)
9560 #define USART_BRR_DIV_MANTISSA_Msk    (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)  /*!< 0x0000FFF0 */
9561 #define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
9562 
9563 /******************  Bit definition for USART_GTPR register  ******************/
9564 #define USART_GTPR_PSC_Pos            (0U)
9565 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)           /*!< 0x000000FF */
9566 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
9567 #define USART_GTPR_GT_Pos             (8U)
9568 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)            /*!< 0x0000FF00 */
9569 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
9570 
9571 /*******************  Bit definition for USART_RTOR register  *****************/
9572 #define USART_RTOR_RTO_Pos            (0U)
9573 #define USART_RTOR_RTO_Msk            (0xFFFFFFUL << USART_RTOR_RTO_Pos)       /*!< 0x00FFFFFF */
9574 #define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
9575 #define USART_RTOR_BLEN_Pos           (24U)
9576 #define USART_RTOR_BLEN_Msk           (0xFFUL << USART_RTOR_BLEN_Pos)          /*!< 0xFF000000 */
9577 #define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
9578 
9579 /*******************  Bit definition for USART_RQR register  ******************/
9580 #define USART_RQR_ABRRQ_Pos           (0U)
9581 #define USART_RQR_ABRRQ_Msk           (0x1UL << USART_RQR_ABRRQ_Pos)           /*!< 0x00000001 */
9582 #define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
9583 #define USART_RQR_SBKRQ_Pos           (1U)
9584 #define USART_RQR_SBKRQ_Msk           (0x1UL << USART_RQR_SBKRQ_Pos)           /*!< 0x00000002 */
9585 #define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
9586 #define USART_RQR_MMRQ_Pos            (2U)
9587 #define USART_RQR_MMRQ_Msk            (0x1UL << USART_RQR_MMRQ_Pos)            /*!< 0x00000004 */
9588 #define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
9589 #define USART_RQR_RXFRQ_Pos           (3U)
9590 #define USART_RQR_RXFRQ_Msk           (0x1UL << USART_RQR_RXFRQ_Pos)           /*!< 0x00000008 */
9591 #define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
9592 #define USART_RQR_TXFRQ_Pos           (4U)
9593 #define USART_RQR_TXFRQ_Msk           (0x1UL << USART_RQR_TXFRQ_Pos)           /*!< 0x00000010 */
9594 #define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
9595 
9596 /*******************  Bit definition for USART_ISR register  ******************/
9597 #define USART_ISR_PE_Pos              (0U)
9598 #define USART_ISR_PE_Msk              (0x1UL << USART_ISR_PE_Pos)              /*!< 0x00000001 */
9599 #define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
9600 #define USART_ISR_FE_Pos              (1U)
9601 #define USART_ISR_FE_Msk              (0x1UL << USART_ISR_FE_Pos)              /*!< 0x00000002 */
9602 #define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
9603 #define USART_ISR_NE_Pos              (2U)
9604 #define USART_ISR_NE_Msk              (0x1UL << USART_ISR_NE_Pos)              /*!< 0x00000004 */
9605 #define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise Error detected Flag */
9606 #define USART_ISR_ORE_Pos             (3U)
9607 #define USART_ISR_ORE_Msk             (0x1UL << USART_ISR_ORE_Pos)             /*!< 0x00000008 */
9608 #define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
9609 #define USART_ISR_IDLE_Pos            (4U)
9610 #define USART_ISR_IDLE_Msk            (0x1UL << USART_ISR_IDLE_Pos)            /*!< 0x00000010 */
9611 #define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
9612 #define USART_ISR_RXNE_Pos            (5U)
9613 #define USART_ISR_RXNE_Msk            (0x1UL << USART_ISR_RXNE_Pos)            /*!< 0x00000020 */
9614 #define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
9615 #define USART_ISR_TC_Pos              (6U)
9616 #define USART_ISR_TC_Msk              (0x1UL << USART_ISR_TC_Pos)              /*!< 0x00000040 */
9617 #define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
9618 #define USART_ISR_TXE_Pos             (7U)
9619 #define USART_ISR_TXE_Msk             (0x1UL << USART_ISR_TXE_Pos)             /*!< 0x00000080 */
9620 #define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
9621 #define USART_ISR_LBDF_Pos            (8U)
9622 #define USART_ISR_LBDF_Msk            (0x1UL << USART_ISR_LBDF_Pos)            /*!< 0x00000100 */
9623 #define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
9624 #define USART_ISR_CTSIF_Pos           (9U)
9625 #define USART_ISR_CTSIF_Msk           (0x1UL << USART_ISR_CTSIF_Pos)           /*!< 0x00000200 */
9626 #define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
9627 #define USART_ISR_CTS_Pos             (10U)
9628 #define USART_ISR_CTS_Msk             (0x1UL << USART_ISR_CTS_Pos)             /*!< 0x00000400 */
9629 #define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
9630 #define USART_ISR_RTOF_Pos            (11U)
9631 #define USART_ISR_RTOF_Msk            (0x1UL << USART_ISR_RTOF_Pos)            /*!< 0x00000800 */
9632 #define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
9633 #define USART_ISR_EOBF_Pos            (12U)
9634 #define USART_ISR_EOBF_Msk            (0x1UL << USART_ISR_EOBF_Pos)            /*!< 0x00001000 */
9635 #define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
9636 #define USART_ISR_ABRE_Pos            (14U)
9637 #define USART_ISR_ABRE_Msk            (0x1UL << USART_ISR_ABRE_Pos)            /*!< 0x00004000 */
9638 #define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
9639 #define USART_ISR_ABRF_Pos            (15U)
9640 #define USART_ISR_ABRF_Msk            (0x1UL << USART_ISR_ABRF_Pos)            /*!< 0x00008000 */
9641 #define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
9642 #define USART_ISR_BUSY_Pos            (16U)
9643 #define USART_ISR_BUSY_Msk            (0x1UL << USART_ISR_BUSY_Pos)            /*!< 0x00010000 */
9644 #define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
9645 #define USART_ISR_CMF_Pos             (17U)
9646 #define USART_ISR_CMF_Msk             (0x1UL << USART_ISR_CMF_Pos)             /*!< 0x00020000 */
9647 #define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
9648 #define USART_ISR_SBKF_Pos            (18U)
9649 #define USART_ISR_SBKF_Msk            (0x1UL << USART_ISR_SBKF_Pos)            /*!< 0x00040000 */
9650 #define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
9651 #define USART_ISR_RWU_Pos             (19U)
9652 #define USART_ISR_RWU_Msk             (0x1UL << USART_ISR_RWU_Pos)             /*!< 0x00080000 */
9653 #define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
9654 #define USART_ISR_WUF_Pos             (20U)
9655 #define USART_ISR_WUF_Msk             (0x1UL << USART_ISR_WUF_Pos)             /*!< 0x00100000 */
9656 #define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
9657 #define USART_ISR_TEACK_Pos           (21U)
9658 #define USART_ISR_TEACK_Msk           (0x1UL << USART_ISR_TEACK_Pos)           /*!< 0x00200000 */
9659 #define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
9660 #define USART_ISR_REACK_Pos           (22U)
9661 #define USART_ISR_REACK_Msk           (0x1UL << USART_ISR_REACK_Pos)           /*!< 0x00400000 */
9662 #define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
9663 #define USART_ISR_TCBGT_Pos           (25U)
9664 #define USART_ISR_TCBGT_Msk           (0x1UL << USART_ISR_TCBGT_Pos)           /*!< 0x02000000 */
9665 #define USART_ISR_TCBGT               USART_ISR_TCBGT_Msk                      /*!< Transmission Complete Before Guard Time Completion Flag */
9666 
9667 /*******************  Bit definition for USART_ICR register  ******************/
9668 #define USART_ICR_PECF_Pos            (0U)
9669 #define USART_ICR_PECF_Msk            (0x1UL << USART_ICR_PECF_Pos)            /*!< 0x00000001 */
9670 #define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
9671 #define USART_ICR_FECF_Pos            (1U)
9672 #define USART_ICR_FECF_Msk            (0x1UL << USART_ICR_FECF_Pos)            /*!< 0x00000002 */
9673 #define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
9674 #define USART_ICR_NECF_Pos            (2U)
9675 #define USART_ICR_NECF_Msk            (0x1UL << USART_ICR_NECF_Pos)            /*!< 0x00000004 */
9676 #define USART_ICR_NECF                USART_ICR_NECF_Msk                       /*!< Noise Error detected Clear Flag */
9677 #define USART_ICR_ORECF_Pos           (3U)
9678 #define USART_ICR_ORECF_Msk           (0x1UL << USART_ICR_ORECF_Pos)           /*!< 0x00000008 */
9679 #define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
9680 #define USART_ICR_IDLECF_Pos          (4U)
9681 #define USART_ICR_IDLECF_Msk          (0x1UL << USART_ICR_IDLECF_Pos)          /*!< 0x00000010 */
9682 #define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
9683 #define USART_ICR_TCCF_Pos            (6U)
9684 #define USART_ICR_TCCF_Msk            (0x1UL << USART_ICR_TCCF_Pos)            /*!< 0x00000040 */
9685 #define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
9686 #define USART_ICR_TCBGTCF_Pos         (7U)
9687 #define USART_ICR_TCBGTCF_Msk         (0x1UL << USART_ICR_TCBGTCF_Pos)         /*!< 0x00000080 */
9688 #define USART_ICR_TCBGTCF             USART_ICR_TCBGTCF_Msk                    /*!< Transmission Complete Before Guard Time Clear Flag */
9689 #define USART_ICR_LBDCF_Pos           (8U)
9690 #define USART_ICR_LBDCF_Msk           (0x1UL << USART_ICR_LBDCF_Pos)           /*!< 0x00000100 */
9691 #define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
9692 #define USART_ICR_CTSCF_Pos           (9U)
9693 #define USART_ICR_CTSCF_Msk           (0x1UL << USART_ICR_CTSCF_Pos)           /*!< 0x00000200 */
9694 #define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
9695 #define USART_ICR_RTOCF_Pos           (11U)
9696 #define USART_ICR_RTOCF_Msk           (0x1UL << USART_ICR_RTOCF_Pos)           /*!< 0x00000800 */
9697 #define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
9698 #define USART_ICR_EOBCF_Pos           (12U)
9699 #define USART_ICR_EOBCF_Msk           (0x1UL << USART_ICR_EOBCF_Pos)           /*!< 0x00001000 */
9700 #define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
9701 #define USART_ICR_CMCF_Pos            (17U)
9702 #define USART_ICR_CMCF_Msk            (0x1UL << USART_ICR_CMCF_Pos)            /*!< 0x00020000 */
9703 #define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
9704 #define USART_ICR_WUCF_Pos            (20U)
9705 #define USART_ICR_WUCF_Msk            (0x1UL << USART_ICR_WUCF_Pos)            /*!< 0x00100000 */
9706 #define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
9707 
9708 /* Legacy defines */
9709 #define USART_ICR_NCF_Pos             USART_ICR_NECF_Pos
9710 #define USART_ICR_NCF_Msk             USART_ICR_NECF_Msk
9711 #define USART_ICR_NCF                 USART_ICR_NECF
9712 
9713 /*******************  Bit definition for USART_RDR register  ******************/
9714 #define USART_RDR_RDR_Pos             (0U)
9715 #define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */
9716 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
9717 
9718 /*******************  Bit definition for USART_TDR register  ******************/
9719 #define USART_TDR_TDR_Pos             (0U)
9720 #define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */
9721 #define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
9722 
9723 
9724 /******************************************************************************/
9725 /*                                                                            */
9726 /*                            Window WATCHDOG                                 */
9727 /*                                                                            */
9728 /******************************************************************************/
9729 /*******************  Bit definition for WWDG_CR register  ********************/
9730 #define WWDG_CR_T_Pos           (0U)
9731 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
9732 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
9733 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
9734 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
9735 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
9736 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
9737 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
9738 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
9739 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
9740 
9741 #define WWDG_CR_WDGA_Pos        (7U)
9742 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
9743 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
9744 
9745 /*******************  Bit definition for WWDG_CFR register  *******************/
9746 #define WWDG_CFR_W_Pos          (0U)
9747 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
9748 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
9749 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
9750 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
9751 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
9752 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
9753 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
9754 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
9755 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
9756 
9757 #define WWDG_CFR_WDGTB_Pos      (7U)
9758 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000180 */
9759 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
9760 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000080 */
9761 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000100 */
9762 
9763 #define WWDG_CFR_EWI_Pos        (9U)
9764 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
9765 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
9766 
9767 /*******************  Bit definition for WWDG_SR register  ********************/
9768 #define WWDG_SR_EWIF_Pos        (0U)
9769 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
9770 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
9771 
9772 
9773 /******************************************************************************/
9774 /*                                                                            */
9775 /*                                 Debug MCU                                  */
9776 /*                                                                            */
9777 /******************************************************************************/
9778 /********************  Bit definition for DBGMCU_IDCODE register  *************/
9779 #define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
9780 #define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
9781 #define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk
9782 #define DBGMCU_IDCODE_REV_ID_Pos               (16U)
9783 #define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
9784 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
9785 
9786 /********************  Bit definition for DBGMCU_CR register  *****************/
9787 #define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
9788 #define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
9789 #define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
9790 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
9791 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
9792 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
9793 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
9794 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
9795 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
9796 #define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
9797 #define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
9798 #define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
9799 
9800 #define DBGMCU_CR_TRACE_MODE_Pos               (6U)
9801 #define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
9802 #define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk
9803 #define DBGMCU_CR_TRACE_MODE_0                 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
9804 #define DBGMCU_CR_TRACE_MODE_1                 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
9805 
9806 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
9807 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)
9808 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
9809 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
9810 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)
9811 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
9812 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
9813 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)
9814 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
9815 #define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
9816 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)
9817 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
9818 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
9819 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)
9820 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
9821 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
9822 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)
9823 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
9824 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
9825 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)
9826 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
9827 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
9828 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)
9829 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
9830 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
9831 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)
9832 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
9833 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
9834 
9835 /********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
9836 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)
9837 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
9838 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
9839 
9840 /********************  Bit definition for DBGMCU_APB2FZ register  ************/
9841 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)
9842 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
9843 #define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
9844 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)
9845 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
9846 #define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
9847 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)
9848 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
9849 #define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
9850 
9851 /******************************************************************************/
9852 /*                                                                            */
9853 /*                         USB Device FS Endpoint registers                   */
9854 /*                                                                            */
9855 /******************************************************************************/
9856 #define USB_EP0R                                 USB_BASE                  /*!< endpoint 0 register address */
9857 #define USB_EP1R                                 (USB_BASE + 0x00000004UL)   /*!< endpoint 1 register address */
9858 #define USB_EP2R                                 (USB_BASE + 0x00000008UL)   /*!< endpoint 2 register address */
9859 #define USB_EP3R                                 (USB_BASE + 0x0000000CUL)   /*!< endpoint 3 register address */
9860 #define USB_EP4R                                 (USB_BASE + 0x00000010UL)   /*!< endpoint 4 register address */
9861 #define USB_EP5R                                 (USB_BASE + 0x00000014UL)   /*!< endpoint 5 register address */
9862 #define USB_EP6R                                 (USB_BASE + 0x00000018UL)   /*!< endpoint 6 register address */
9863 #define USB_EP7R                                 (USB_BASE + 0x0000001CUL)   /*!< endpoint 7 register address */
9864 
9865 /* bit positions */
9866 #define USB_EP_CTR_RX                            ((uint16_t)0x8000U)           /*!<  EndPoint Correct TRansfer RX */
9867 #define USB_EP_DTOG_RX                           ((uint16_t)0x4000U)           /*!<  EndPoint Data TOGGLE RX */
9868 #define USB_EPRX_STAT                            ((uint16_t)0x3000U)           /*!<  EndPoint RX STATus bit field */
9869 #define USB_EP_SETUP                             ((uint16_t)0x0800U)           /*!<  EndPoint SETUP */
9870 #define USB_EP_T_FIELD                           ((uint16_t)0x0600U)           /*!<  EndPoint TYPE */
9871 #define USB_EP_KIND                              ((uint16_t)0x0100U)           /*!<  EndPoint KIND */
9872 #define USB_EP_CTR_TX                            ((uint16_t)0x0080U)           /*!<  EndPoint Correct TRansfer TX */
9873 #define USB_EP_DTOG_TX                           ((uint16_t)0x0040U)           /*!<  EndPoint Data TOGGLE TX */
9874 #define USB_EPTX_STAT                            ((uint16_t)0x0030U)           /*!<  EndPoint TX STATus bit field */
9875 #define USB_EPADDR_FIELD                         ((uint16_t)0x000FU)           /*!<  EndPoint ADDRess FIELD */
9876 
9877 /* EndPoint REGister MASK (no toggle fields) */
9878 #define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
9879                                                                          /*!< EP_TYPE[1:0] EndPoint TYPE */
9880 #define USB_EP_TYPE_MASK                         ((uint16_t)0x0600U)           /*!< EndPoint TYPE Mask */
9881 #define USB_EP_BULK                              ((uint16_t)0x0000U)           /*!< EndPoint BULK */
9882 #define USB_EP_CONTROL                           ((uint16_t)0x0200U)           /*!< EndPoint CONTROL */
9883 #define USB_EP_ISOCHRONOUS                       ((uint16_t)0x0400U)           /*!< EndPoint ISOCHRONOUS */
9884 #define USB_EP_INTERRUPT                         ((uint16_t)0x0600U)           /*!< EndPoint INTERRUPT */
9885 #define USB_EP_T_MASK                        ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
9886 
9887 #define USB_EPKIND_MASK                      ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
9888                                                                          /*!< STAT_TX[1:0] STATus for TX transfer */
9889 #define USB_EP_TX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint TX DISabled */
9890 #define USB_EP_TX_STALL                          ((uint16_t)0x0010U)           /*!< EndPoint TX STALLed */
9891 #define USB_EP_TX_NAK                            ((uint16_t)0x0020U)           /*!< EndPoint TX NAKed */
9892 #define USB_EP_TX_VALID                          ((uint16_t)0x0030U)           /*!< EndPoint TX VALID */
9893 #define USB_EPTX_DTOG1                           ((uint16_t)0x0010U)           /*!< EndPoint TX Data TOGgle bit1 */
9894 #define USB_EPTX_DTOG2                           ((uint16_t)0x0020U)           /*!< EndPoint TX Data TOGgle bit2 */
9895 #define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
9896                                                                          /*!< STAT_RX[1:0] STATus for RX transfer */
9897 #define USB_EP_RX_DIS                            ((uint16_t)0x0000U)           /*!< EndPoint RX DISabled */
9898 #define USB_EP_RX_STALL                          ((uint16_t)0x1000U)           /*!< EndPoint RX STALLed */
9899 #define USB_EP_RX_NAK                            ((uint16_t)0x2000U)           /*!< EndPoint RX NAKed */
9900 #define USB_EP_RX_VALID                          ((uint16_t)0x3000U)           /*!< EndPoint RX VALID */
9901 #define USB_EPRX_DTOG1                           ((uint16_t)0x1000U)           /*!< EndPoint RX Data TOGgle bit1 */
9902 #define USB_EPRX_DTOG2                           ((uint16_t)0x2000U)           /*!< EndPoint RX Data TOGgle bit1 */
9903 #define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
9904 
9905 /******************************************************************************/
9906 /*                                                                            */
9907 /*                         USB Device FS General registers                    */
9908 /*                                                                            */
9909 /******************************************************************************/
9910 #define USB_CNTR                             (USB_BASE + 0x00000040UL)     /*!< Control register */
9911 #define USB_ISTR                             (USB_BASE + 0x00000044UL)     /*!< Interrupt status register */
9912 #define USB_FNR                              (USB_BASE + 0x00000048UL)     /*!< Frame number register */
9913 #define USB_DADDR                            (USB_BASE + 0x0000004CUL)     /*!< Device address register */
9914 #define USB_BTABLE                           (USB_BASE + 0x00000050UL)     /*!< Buffer Table address register */
9915 #define USB_LPMCSR                           (USB_BASE + 0x00000054UL)     /*!< LPM Control and Status register */
9916 #define USB_BCDR                             (USB_BASE + 0x00000058UL)     /*!< Battery Charging detector register*/
9917 
9918 /******************  Bits definition for USB_CNTR register  *******************/
9919 #define USB_CNTR_CTRM                            ((uint16_t)0x8000U)           /*!< Correct TRansfer Mask */
9920 #define USB_CNTR_PMAOVRM                         ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun Mask */
9921 #define USB_CNTR_ERRM                            ((uint16_t)0x2000U)           /*!< ERRor Mask */
9922 #define USB_CNTR_WKUPM                           ((uint16_t)0x1000U)           /*!< WaKe UP Mask */
9923 #define USB_CNTR_SUSPM                           ((uint16_t)0x0800U)           /*!< SUSPend Mask */
9924 #define USB_CNTR_RESETM                          ((uint16_t)0x0400U)           /*!< RESET Mask   */
9925 #define USB_CNTR_SOFM                            ((uint16_t)0x0200U)           /*!< Start Of Frame Mask */
9926 #define USB_CNTR_ESOFM                           ((uint16_t)0x0100U)           /*!< Expected Start Of Frame Mask */
9927 #define USB_CNTR_L1REQM                          ((uint16_t)0x0080U)           /*!< LPM L1 state request interrupt mask */
9928 #define USB_CNTR_L1RESUME                        ((uint16_t)0x0020U)           /*!< LPM L1 Resume request */
9929 #define USB_CNTR_RESUME                          ((uint16_t)0x0010U)           /*!< RESUME request */
9930 #define USB_CNTR_FSUSP                           ((uint16_t)0x0008U)           /*!< Force SUSPend */
9931 #define USB_CNTR_LPMODE                          ((uint16_t)0x0004U)           /*!< Low-power MODE */
9932 #define USB_CNTR_PDWN                            ((uint16_t)0x0002U)           /*!< Power DoWN */
9933 #define USB_CNTR_FRES                            ((uint16_t)0x0001U)           /*!< Force USB RESet */
9934 
9935 /******************  Bits definition for USB_ISTR register  *******************/
9936 #define USB_ISTR_EP_ID                           ((uint16_t)0x000FU)           /*!< EndPoint IDentifier (read-only bit)  */
9937 #define USB_ISTR_DIR                             ((uint16_t)0x0010U)           /*!< DIRection of transaction (read-only bit)  */
9938 #define USB_ISTR_L1REQ                           ((uint16_t)0x0080U)           /*!< LPM L1 state request  */
9939 #define USB_ISTR_ESOF                            ((uint16_t)0x0100U)           /*!< Expected Start Of Frame (clear-only bit) */
9940 #define USB_ISTR_SOF                             ((uint16_t)0x0200U)           /*!< Start Of Frame (clear-only bit) */
9941 #define USB_ISTR_RESET                           ((uint16_t)0x0400U)           /*!< RESET (clear-only bit) */
9942 #define USB_ISTR_SUSP                            ((uint16_t)0x0800U)           /*!< SUSPend (clear-only bit) */
9943 #define USB_ISTR_WKUP                            ((uint16_t)0x1000U)           /*!< WaKe UP (clear-only bit) */
9944 #define USB_ISTR_ERR                             ((uint16_t)0x2000U)           /*!< ERRor (clear-only bit) */
9945 #define USB_ISTR_PMAOVR                          ((uint16_t)0x4000U)           /*!< DMA OVeR/underrun (clear-only bit) */
9946 #define USB_ISTR_CTR                             ((uint16_t)0x8000U)           /*!< Correct TRansfer (clear-only bit) */
9947 
9948 #define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
9949 #define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
9950 #define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
9951 #define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
9952 #define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
9953 #define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
9954 #define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
9955 #define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
9956 #define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
9957 
9958 /******************  Bits definition for USB_FNR register  ********************/
9959 #define USB_FNR_FN                               ((uint16_t)0x07FFU)           /*!< Frame Number */
9960 #define USB_FNR_LSOF                             ((uint16_t)0x1800U)           /*!< Lost SOF */
9961 #define USB_FNR_LCK                              ((uint16_t)0x2000U)           /*!< LoCKed */
9962 #define USB_FNR_RXDM                             ((uint16_t)0x4000U)           /*!< status of D- data line */
9963 #define USB_FNR_RXDP                             ((uint16_t)0x8000U)           /*!< status of D+ data line */
9964 
9965 /******************  Bits definition for USB_DADDR register    ****************/
9966 #define USB_DADDR_ADD                            ((uint8_t)0x7FU)              /*!< ADD[6:0] bits (Device Address) */
9967 #define USB_DADDR_ADD0                           ((uint8_t)0x01U)              /*!< Bit 0 */
9968 #define USB_DADDR_ADD1                           ((uint8_t)0x02U)              /*!< Bit 1 */
9969 #define USB_DADDR_ADD2                           ((uint8_t)0x04U)              /*!< Bit 2 */
9970 #define USB_DADDR_ADD3                           ((uint8_t)0x08U)              /*!< Bit 3 */
9971 #define USB_DADDR_ADD4                           ((uint8_t)0x10U)              /*!< Bit 4 */
9972 #define USB_DADDR_ADD5                           ((uint8_t)0x20U)              /*!< Bit 5 */
9973 #define USB_DADDR_ADD6                           ((uint8_t)0x40U)              /*!< Bit 6 */
9974 
9975 #define USB_DADDR_EF                             ((uint8_t)0x80U)              /*!< Enable Function */
9976 
9977 /******************  Bit definition for USB_BTABLE register  ******************/
9978 #define USB_BTABLE_BTABLE                        ((uint16_t)0xFFF8U)           /*!< Buffer Table */
9979 
9980 /******************  Bits definition for USB_BCDR register  *******************/
9981 #define USB_BCDR_BCDEN                           ((uint16_t)0x0001U)           /*!< Battery charging detector (BCD) enable */
9982 #define USB_BCDR_DCDEN                           ((uint16_t)0x0002U)           /*!< Data contact detection (DCD) mode enable */
9983 #define USB_BCDR_PDEN                            ((uint16_t)0x0004U)           /*!< Primary detection (PD) mode enable */
9984 #define USB_BCDR_SDEN                            ((uint16_t)0x0008U)           /*!< Secondary detection (SD) mode enable */
9985 #define USB_BCDR_DCDET                           ((uint16_t)0x0010U)           /*!< Data contact detection (DCD) status */
9986 #define USB_BCDR_PDET                            ((uint16_t)0x0020U)           /*!< Primary detection (PD) status */
9987 #define USB_BCDR_SDET                            ((uint16_t)0x0040U)           /*!< Secondary detection (SD) status */
9988 #define USB_BCDR_PS2DET                          ((uint16_t)0x0080U)           /*!< PS2 port or proprietary charger detected */
9989 #define USB_BCDR_DPPU                            ((uint16_t)0x8000U)           /*!< DP Pull-up Enable */
9990 
9991 /*******************  Bit definition for LPMCSR register  *********************/
9992 #define USB_LPMCSR_LMPEN                         ((uint16_t)0x0001U)           /*!< LPM support enable  */
9993 #define USB_LPMCSR_LPMACK                        ((uint16_t)0x0002U)           /*!< LPM Token acknowledge enable*/
9994 #define USB_LPMCSR_REMWAKE                       ((uint16_t)0x0008U)           /*!< bRemoteWake value received with last ACKed LPM Token */
9995 #define USB_LPMCSR_BESL                          ((uint16_t)0x00F0U)           /*!< BESL value received with last ACKed LPM Token  */
9996 
9997 /*!< Buffer descriptor table */
9998 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
9999 #define USB_ADDR0_TX_ADDR0_TX_Pos                (1U)
10000 #define USB_ADDR0_TX_ADDR0_TX_Msk                (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
10001 #define USB_ADDR0_TX_ADDR0_TX                    USB_ADDR0_TX_ADDR0_TX_Msk     /*!< Transmission Buffer Address 0 */
10002 
10003 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
10004 #define USB_ADDR1_TX_ADDR1_TX_Pos                (1U)
10005 #define USB_ADDR1_TX_ADDR1_TX_Msk                (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
10006 #define USB_ADDR1_TX_ADDR1_TX                    USB_ADDR1_TX_ADDR1_TX_Msk     /*!< Transmission Buffer Address 1 */
10007 
10008 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
10009 #define USB_ADDR2_TX_ADDR2_TX_Pos                (1U)
10010 #define USB_ADDR2_TX_ADDR2_TX_Msk                (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
10011 #define USB_ADDR2_TX_ADDR2_TX                    USB_ADDR2_TX_ADDR2_TX_Msk     /*!< Transmission Buffer Address 2 */
10012 
10013 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
10014 #define USB_ADDR3_TX_ADDR3_TX_Pos                (1U)
10015 #define USB_ADDR3_TX_ADDR3_TX_Msk                (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
10016 #define USB_ADDR3_TX_ADDR3_TX                    USB_ADDR3_TX_ADDR3_TX_Msk     /*!< Transmission Buffer Address 3 */
10017 
10018 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
10019 #define USB_ADDR4_TX_ADDR4_TX_Pos                (1U)
10020 #define USB_ADDR4_TX_ADDR4_TX_Msk                (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
10021 #define USB_ADDR4_TX_ADDR4_TX                    USB_ADDR4_TX_ADDR4_TX_Msk     /*!< Transmission Buffer Address 4 */
10022 
10023 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
10024 #define USB_ADDR5_TX_ADDR5_TX_Pos                (1U)
10025 #define USB_ADDR5_TX_ADDR5_TX_Msk                (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
10026 #define USB_ADDR5_TX_ADDR5_TX                    USB_ADDR5_TX_ADDR5_TX_Msk     /*!< Transmission Buffer Address 5 */
10027 
10028 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
10029 #define USB_ADDR6_TX_ADDR6_TX_Pos                (1U)
10030 #define USB_ADDR6_TX_ADDR6_TX_Msk                (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
10031 #define USB_ADDR6_TX_ADDR6_TX                    USB_ADDR6_TX_ADDR6_TX_Msk     /*!< Transmission Buffer Address 6 */
10032 
10033 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
10034 #define USB_ADDR7_TX_ADDR7_TX_Pos                (1U)
10035 #define USB_ADDR7_TX_ADDR7_TX_Msk                (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
10036 #define USB_ADDR7_TX_ADDR7_TX                    USB_ADDR7_TX_ADDR7_TX_Msk     /*!< Transmission Buffer Address 7 */
10037 
10038 /*----------------------------------------------------------------------------*/
10039 
10040 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
10041 #define USB_COUNT0_TX_COUNT0_TX_Pos              (0U)
10042 #define USB_COUNT0_TX_COUNT0_TX_Msk              (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
10043 #define USB_COUNT0_TX_COUNT0_TX                  USB_COUNT0_TX_COUNT0_TX_Msk   /*!< Transmission Byte Count 0 */
10044 
10045 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
10046 #define USB_COUNT1_TX_COUNT1_TX_Pos              (0U)
10047 #define USB_COUNT1_TX_COUNT1_TX_Msk              (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
10048 #define USB_COUNT1_TX_COUNT1_TX                  USB_COUNT1_TX_COUNT1_TX_Msk   /*!< Transmission Byte Count 1 */
10049 
10050 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
10051 #define USB_COUNT2_TX_COUNT2_TX_Pos              (0U)
10052 #define USB_COUNT2_TX_COUNT2_TX_Msk              (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
10053 #define USB_COUNT2_TX_COUNT2_TX                  USB_COUNT2_TX_COUNT2_TX_Msk   /*!< Transmission Byte Count 2 */
10054 
10055 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
10056 #define USB_COUNT3_TX_COUNT3_TX_Pos              (0U)
10057 #define USB_COUNT3_TX_COUNT3_TX_Msk              (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
10058 #define USB_COUNT3_TX_COUNT3_TX                  USB_COUNT3_TX_COUNT3_TX_Msk   /*!< Transmission Byte Count 3 */
10059 
10060 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
10061 #define USB_COUNT4_TX_COUNT4_TX_Pos              (0U)
10062 #define USB_COUNT4_TX_COUNT4_TX_Msk              (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
10063 #define USB_COUNT4_TX_COUNT4_TX                  USB_COUNT4_TX_COUNT4_TX_Msk   /*!< Transmission Byte Count 4 */
10064 
10065 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
10066 #define USB_COUNT5_TX_COUNT5_TX_Pos              (0U)
10067 #define USB_COUNT5_TX_COUNT5_TX_Msk              (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
10068 #define USB_COUNT5_TX_COUNT5_TX                  USB_COUNT5_TX_COUNT5_TX_Msk   /*!< Transmission Byte Count 5 */
10069 
10070 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
10071 #define USB_COUNT6_TX_COUNT6_TX_Pos              (0U)
10072 #define USB_COUNT6_TX_COUNT6_TX_Msk              (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
10073 #define USB_COUNT6_TX_COUNT6_TX                  USB_COUNT6_TX_COUNT6_TX_Msk   /*!< Transmission Byte Count 6 */
10074 
10075 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
10076 #define USB_COUNT7_TX_COUNT7_TX_Pos              (0U)
10077 #define USB_COUNT7_TX_COUNT7_TX_Msk              (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
10078 #define USB_COUNT7_TX_COUNT7_TX                  USB_COUNT7_TX_COUNT7_TX_Msk   /*!< Transmission Byte Count 7 */
10079 
10080 /*----------------------------------------------------------------------------*/
10081 
10082 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
10083 #define USB_COUNT0_TX_0_COUNT0_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 0 (low) */
10084 
10085 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
10086 #define USB_COUNT0_TX_1_COUNT0_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 0 (high) */
10087 
10088 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
10089 #define USB_COUNT1_TX_0_COUNT1_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 1 (low) */
10090 
10091 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
10092 #define USB_COUNT1_TX_1_COUNT1_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 1 (high) */
10093 
10094 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
10095 #define USB_COUNT2_TX_0_COUNT2_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 2 (low) */
10096 
10097 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
10098 #define USB_COUNT2_TX_1_COUNT2_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 2 (high) */
10099 
10100 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
10101 #define USB_COUNT3_TX_0_COUNT3_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 3 (low) */
10102 
10103 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
10104 #define USB_COUNT3_TX_1_COUNT3_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 3 (high) */
10105 
10106 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
10107 #define USB_COUNT4_TX_0_COUNT4_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 4 (low) */
10108 
10109 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
10110 #define USB_COUNT4_TX_1_COUNT4_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 4 (high) */
10111 
10112 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
10113 #define USB_COUNT5_TX_0_COUNT5_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 5 (low) */
10114 
10115 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
10116 #define USB_COUNT5_TX_1_COUNT5_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 5 (high) */
10117 
10118 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
10119 #define USB_COUNT6_TX_0_COUNT6_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 6 (low) */
10120 
10121 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
10122 #define USB_COUNT6_TX_1_COUNT6_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 6 (high) */
10123 
10124 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
10125 #define USB_COUNT7_TX_0_COUNT7_TX_0         (0x000003FFUL)       /*!< Transmission Byte Count 7 (low) */
10126 
10127 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
10128 #define USB_COUNT7_TX_1_COUNT7_TX_1         (0x03FF0000UL)       /*!< Transmission Byte Count 7 (high) */
10129 
10130 /*----------------------------------------------------------------------------*/
10131 
10132 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
10133 #define USB_ADDR0_RX_ADDR0_RX_Pos                (1U)
10134 #define USB_ADDR0_RX_ADDR0_RX_Msk                (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
10135 #define USB_ADDR0_RX_ADDR0_RX                    USB_ADDR0_RX_ADDR0_RX_Msk     /*!< Reception Buffer Address 0 */
10136 
10137 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
10138 #define USB_ADDR1_RX_ADDR1_RX_Pos                (1U)
10139 #define USB_ADDR1_RX_ADDR1_RX_Msk                (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
10140 #define USB_ADDR1_RX_ADDR1_RX                    USB_ADDR1_RX_ADDR1_RX_Msk     /*!< Reception Buffer Address 1 */
10141 
10142 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
10143 #define USB_ADDR2_RX_ADDR2_RX_Pos                (1U)
10144 #define USB_ADDR2_RX_ADDR2_RX_Msk                (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
10145 #define USB_ADDR2_RX_ADDR2_RX                    USB_ADDR2_RX_ADDR2_RX_Msk     /*!< Reception Buffer Address 2 */
10146 
10147 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
10148 #define USB_ADDR3_RX_ADDR3_RX_Pos                (1U)
10149 #define USB_ADDR3_RX_ADDR3_RX_Msk                (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
10150 #define USB_ADDR3_RX_ADDR3_RX                    USB_ADDR3_RX_ADDR3_RX_Msk     /*!< Reception Buffer Address 3 */
10151 
10152 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
10153 #define USB_ADDR4_RX_ADDR4_RX_Pos                (1U)
10154 #define USB_ADDR4_RX_ADDR4_RX_Msk                (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
10155 #define USB_ADDR4_RX_ADDR4_RX                    USB_ADDR4_RX_ADDR4_RX_Msk     /*!< Reception Buffer Address 4 */
10156 
10157 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
10158 #define USB_ADDR5_RX_ADDR5_RX_Pos                (1U)
10159 #define USB_ADDR5_RX_ADDR5_RX_Msk                (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
10160 #define USB_ADDR5_RX_ADDR5_RX                    USB_ADDR5_RX_ADDR5_RX_Msk     /*!< Reception Buffer Address 5 */
10161 
10162 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
10163 #define USB_ADDR6_RX_ADDR6_RX_Pos                (1U)
10164 #define USB_ADDR6_RX_ADDR6_RX_Msk                (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
10165 #define USB_ADDR6_RX_ADDR6_RX                    USB_ADDR6_RX_ADDR6_RX_Msk     /*!< Reception Buffer Address 6 */
10166 
10167 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
10168 #define USB_ADDR7_RX_ADDR7_RX_Pos                (1U)
10169 #define USB_ADDR7_RX_ADDR7_RX_Msk                (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
10170 #define USB_ADDR7_RX_ADDR7_RX                    USB_ADDR7_RX_ADDR7_RX_Msk     /*!< Reception Buffer Address 7 */
10171 
10172 /*----------------------------------------------------------------------------*/
10173 
10174 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
10175 #define USB_COUNT0_RX_COUNT0_RX_Pos              (0U)
10176 #define USB_COUNT0_RX_COUNT0_RX_Msk              (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
10177 #define USB_COUNT0_RX_COUNT0_RX                  USB_COUNT0_RX_COUNT0_RX_Msk   /*!< Reception Byte Count */
10178 
10179 #define USB_COUNT0_RX_NUM_BLOCK_Pos              (10U)
10180 #define USB_COUNT0_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10181 #define USB_COUNT0_RX_NUM_BLOCK                  USB_COUNT0_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10182 #define USB_COUNT0_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10183 #define USB_COUNT0_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10184 #define USB_COUNT0_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10185 #define USB_COUNT0_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10186 #define USB_COUNT0_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10187 
10188 #define USB_COUNT0_RX_BLSIZE_Pos                 (15U)
10189 #define USB_COUNT0_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
10190 #define USB_COUNT0_RX_BLSIZE                     USB_COUNT0_RX_BLSIZE_Msk      /*!< BLock SIZE */
10191 
10192 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
10193 #define USB_COUNT1_RX_COUNT1_RX_Pos              (0U)
10194 #define USB_COUNT1_RX_COUNT1_RX_Msk              (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
10195 #define USB_COUNT1_RX_COUNT1_RX                  USB_COUNT1_RX_COUNT1_RX_Msk   /*!< Reception Byte Count */
10196 
10197 #define USB_COUNT1_RX_NUM_BLOCK_Pos              (10U)
10198 #define USB_COUNT1_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10199 #define USB_COUNT1_RX_NUM_BLOCK                  USB_COUNT1_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10200 #define USB_COUNT1_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10201 #define USB_COUNT1_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10202 #define USB_COUNT1_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10203 #define USB_COUNT1_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10204 #define USB_COUNT1_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10205 
10206 #define USB_COUNT1_RX_BLSIZE_Pos                 (15U)
10207 #define USB_COUNT1_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
10208 #define USB_COUNT1_RX_BLSIZE                     USB_COUNT1_RX_BLSIZE_Msk      /*!< BLock SIZE */
10209 
10210 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
10211 #define USB_COUNT2_RX_COUNT2_RX_Pos              (0U)
10212 #define USB_COUNT2_RX_COUNT2_RX_Msk              (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
10213 #define USB_COUNT2_RX_COUNT2_RX                  USB_COUNT2_RX_COUNT2_RX_Msk   /*!< Reception Byte Count */
10214 
10215 #define USB_COUNT2_RX_NUM_BLOCK_Pos              (10U)
10216 #define USB_COUNT2_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10217 #define USB_COUNT2_RX_NUM_BLOCK                  USB_COUNT2_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10218 #define USB_COUNT2_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10219 #define USB_COUNT2_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10220 #define USB_COUNT2_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10221 #define USB_COUNT2_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10222 #define USB_COUNT2_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10223 
10224 #define USB_COUNT2_RX_BLSIZE_Pos                 (15U)
10225 #define USB_COUNT2_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
10226 #define USB_COUNT2_RX_BLSIZE                     USB_COUNT2_RX_BLSIZE_Msk      /*!< BLock SIZE */
10227 
10228 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
10229 #define USB_COUNT3_RX_COUNT3_RX_Pos              (0U)
10230 #define USB_COUNT3_RX_COUNT3_RX_Msk              (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
10231 #define USB_COUNT3_RX_COUNT3_RX                  USB_COUNT3_RX_COUNT3_RX_Msk   /*!< Reception Byte Count */
10232 
10233 #define USB_COUNT3_RX_NUM_BLOCK_Pos              (10U)
10234 #define USB_COUNT3_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10235 #define USB_COUNT3_RX_NUM_BLOCK                  USB_COUNT3_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10236 #define USB_COUNT3_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10237 #define USB_COUNT3_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10238 #define USB_COUNT3_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10239 #define USB_COUNT3_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10240 #define USB_COUNT3_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10241 
10242 #define USB_COUNT3_RX_BLSIZE_Pos                 (15U)
10243 #define USB_COUNT3_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
10244 #define USB_COUNT3_RX_BLSIZE                     USB_COUNT3_RX_BLSIZE_Msk      /*!< BLock SIZE */
10245 
10246 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
10247 #define USB_COUNT4_RX_COUNT4_RX_Pos              (0U)
10248 #define USB_COUNT4_RX_COUNT4_RX_Msk              (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
10249 #define USB_COUNT4_RX_COUNT4_RX                  USB_COUNT4_RX_COUNT4_RX_Msk   /*!< Reception Byte Count */
10250 
10251 #define USB_COUNT4_RX_NUM_BLOCK_Pos              (10U)
10252 #define USB_COUNT4_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10253 #define USB_COUNT4_RX_NUM_BLOCK                  USB_COUNT4_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10254 #define USB_COUNT4_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10255 #define USB_COUNT4_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10256 #define USB_COUNT4_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10257 #define USB_COUNT4_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10258 #define USB_COUNT4_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10259 
10260 #define USB_COUNT4_RX_BLSIZE_Pos                 (15U)
10261 #define USB_COUNT4_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
10262 #define USB_COUNT4_RX_BLSIZE                     USB_COUNT4_RX_BLSIZE_Msk      /*!< BLock SIZE */
10263 
10264 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
10265 #define USB_COUNT5_RX_COUNT5_RX_Pos              (0U)
10266 #define USB_COUNT5_RX_COUNT5_RX_Msk              (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
10267 #define USB_COUNT5_RX_COUNT5_RX                  USB_COUNT5_RX_COUNT5_RX_Msk   /*!< Reception Byte Count */
10268 
10269 #define USB_COUNT5_RX_NUM_BLOCK_Pos              (10U)
10270 #define USB_COUNT5_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10271 #define USB_COUNT5_RX_NUM_BLOCK                  USB_COUNT5_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10272 #define USB_COUNT5_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10273 #define USB_COUNT5_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10274 #define USB_COUNT5_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10275 #define USB_COUNT5_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10276 #define USB_COUNT5_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10277 
10278 #define USB_COUNT5_RX_BLSIZE_Pos                 (15U)
10279 #define USB_COUNT5_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
10280 #define USB_COUNT5_RX_BLSIZE                     USB_COUNT5_RX_BLSIZE_Msk      /*!< BLock SIZE */
10281 
10282 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
10283 #define USB_COUNT6_RX_COUNT6_RX_Pos              (0U)
10284 #define USB_COUNT6_RX_COUNT6_RX_Msk              (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
10285 #define USB_COUNT6_RX_COUNT6_RX                  USB_COUNT6_RX_COUNT6_RX_Msk   /*!< Reception Byte Count */
10286 
10287 #define USB_COUNT6_RX_NUM_BLOCK_Pos              (10U)
10288 #define USB_COUNT6_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10289 #define USB_COUNT6_RX_NUM_BLOCK                  USB_COUNT6_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10290 #define USB_COUNT6_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10291 #define USB_COUNT6_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10292 #define USB_COUNT6_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10293 #define USB_COUNT6_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10294 #define USB_COUNT6_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10295 
10296 #define USB_COUNT6_RX_BLSIZE_Pos                 (15U)
10297 #define USB_COUNT6_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
10298 #define USB_COUNT6_RX_BLSIZE                     USB_COUNT6_RX_BLSIZE_Msk      /*!< BLock SIZE */
10299 
10300 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
10301 #define USB_COUNT7_RX_COUNT7_RX_Pos              (0U)
10302 #define USB_COUNT7_RX_COUNT7_RX_Msk              (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
10303 #define USB_COUNT7_RX_COUNT7_RX                  USB_COUNT7_RX_COUNT7_RX_Msk   /*!< Reception Byte Count */
10304 
10305 #define USB_COUNT7_RX_NUM_BLOCK_Pos              (10U)
10306 #define USB_COUNT7_RX_NUM_BLOCK_Msk              (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
10307 #define USB_COUNT7_RX_NUM_BLOCK                  USB_COUNT7_RX_NUM_BLOCK_Msk   /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
10308 #define USB_COUNT7_RX_NUM_BLOCK_0                (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
10309 #define USB_COUNT7_RX_NUM_BLOCK_1                (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
10310 #define USB_COUNT7_RX_NUM_BLOCK_2                (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
10311 #define USB_COUNT7_RX_NUM_BLOCK_3                (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
10312 #define USB_COUNT7_RX_NUM_BLOCK_4                (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
10313 
10314 #define USB_COUNT7_RX_BLSIZE_Pos                 (15U)
10315 #define USB_COUNT7_RX_BLSIZE_Msk                 (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
10316 #define USB_COUNT7_RX_BLSIZE                     USB_COUNT7_RX_BLSIZE_Msk      /*!< BLock SIZE */
10317 
10318 /*----------------------------------------------------------------------------*/
10319 
10320 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
10321 #define USB_COUNT0_RX_0_COUNT0_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10322 
10323 #define USB_COUNT0_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10324 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10325 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10326 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10327 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10328 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10329 
10330 #define USB_COUNT0_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10331 
10332 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
10333 #define USB_COUNT0_RX_1_COUNT0_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10334 
10335 #define USB_COUNT0_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10336 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 1 */
10337 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10338 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10339 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10340 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10341 
10342 #define USB_COUNT0_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10343 
10344 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
10345 #define USB_COUNT1_RX_0_COUNT1_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10346 
10347 #define USB_COUNT1_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10348 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10349 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10350 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10351 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10352 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10353 
10354 #define USB_COUNT1_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10355 
10356 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
10357 #define USB_COUNT1_RX_1_COUNT1_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10358 
10359 #define USB_COUNT1_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10360 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10361 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10362 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10363 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10364 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10365 
10366 #define USB_COUNT1_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10367 
10368 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
10369 #define USB_COUNT2_RX_0_COUNT2_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10370 
10371 #define USB_COUNT2_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10372 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10373 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10374 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10375 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10376 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10377 
10378 #define USB_COUNT2_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10379 
10380 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
10381 #define USB_COUNT2_RX_1_COUNT2_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10382 
10383 #define USB_COUNT2_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10384 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10385 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10386 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10387 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10388 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10389 
10390 #define USB_COUNT2_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10391 
10392 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
10393 #define USB_COUNT3_RX_0_COUNT3_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10394 
10395 #define USB_COUNT3_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10396 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10397 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10398 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10399 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10400 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10401 
10402 #define USB_COUNT3_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10403 
10404 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
10405 #define USB_COUNT3_RX_1_COUNT3_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10406 
10407 #define USB_COUNT3_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10408 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10409 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10410 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10411 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10412 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10413 
10414 #define USB_COUNT3_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10415 
10416 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
10417 #define USB_COUNT4_RX_0_COUNT4_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10418 
10419 #define USB_COUNT4_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10420 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10421 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10422 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10423 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10424 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10425 
10426 #define USB_COUNT4_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10427 
10428 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
10429 #define USB_COUNT4_RX_1_COUNT4_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10430 
10431 #define USB_COUNT4_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10432 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10433 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10434 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10435 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10436 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10437 
10438 #define USB_COUNT4_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10439 
10440 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
10441 #define USB_COUNT5_RX_0_COUNT5_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10442 
10443 #define USB_COUNT5_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10444 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10445 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10446 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10447 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10448 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10449 
10450 #define USB_COUNT5_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10451 
10452 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
10453 #define USB_COUNT5_RX_1_COUNT5_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10454 
10455 #define USB_COUNT5_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10456 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10457 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10458 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10459 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10460 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10461 
10462 #define USB_COUNT5_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10463 
10464 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
10465 #define USB_COUNT6_RX_0_COUNT6_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10466 
10467 #define USB_COUNT6_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10468 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10469 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10470 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10471 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10472 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10473 
10474 #define USB_COUNT6_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10475 
10476 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
10477 #define USB_COUNT6_RX_1_COUNT6_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10478 
10479 #define USB_COUNT6_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10480 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10481 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10482 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10483 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10484 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10485 
10486 #define USB_COUNT6_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10487 
10488 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
10489 #define USB_COUNT7_RX_0_COUNT7_RX_0              (0x000003FFUL)          /*!< Reception Byte Count (low) */
10490 
10491 #define USB_COUNT7_RX_0_NUM_BLOCK_0              (0x00007C00UL)          /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
10492 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0            (0x00000400UL)          /*!< Bit 0 */
10493 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1            (0x00000800UL)          /*!< Bit 1 */
10494 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2            (0x00001000UL)          /*!< Bit 2 */
10495 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3            (0x00002000UL)          /*!< Bit 3 */
10496 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4            (0x00004000UL)          /*!< Bit 4 */
10497 
10498 #define USB_COUNT7_RX_0_BLSIZE_0                 (0x00008000UL)          /*!< BLock SIZE (low) */
10499 
10500 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
10501 #define USB_COUNT7_RX_1_COUNT7_RX_1              (0x03FF0000UL)          /*!< Reception Byte Count (high) */
10502 
10503 #define USB_COUNT7_RX_1_NUM_BLOCK_1              (0x7C000000UL)          /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
10504 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0            (0x04000000UL)          /*!< Bit 0 */
10505 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1            (0x08000000UL)          /*!< Bit 1 */
10506 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2            (0x10000000UL)          /*!< Bit 2 */
10507 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3            (0x20000000UL)          /*!< Bit 3 */
10508 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4            (0x40000000UL)          /*!< Bit 4 */
10509 
10510 #define USB_COUNT7_RX_1_BLSIZE_1                 (0x80000000UL)          /*!< BLock SIZE (high) */
10511 
10512 
10513 /**
10514   * @}
10515   */
10516 
10517 /**
10518   * @}
10519   */
10520 
10521 /** @addtogroup Exported_macros
10522   * @{
10523   */
10524 
10525 /******************************* ADC Instances ********************************/
10526 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
10527                                        ((INSTANCE) == ADC2))
10528 
10529 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
10530 
10531 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
10532 
10533 /******************************** CAN Instances ******************************/
10534 
10535 /******************************** COMP Instances ******************************/
10536 #define IS_COMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
10537 
10538 /******************************* CRC Instances ********************************/
10539 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
10540 
10541 
10542 /******************************** DMA Instances *******************************/
10543 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
10544                                        ((INSTANCE) == DMA1_Channel2) || \
10545                                        ((INSTANCE) == DMA1_Channel3) || \
10546                                        ((INSTANCE) == DMA1_Channel4) || \
10547                                        ((INSTANCE) == DMA1_Channel5) || \
10548                                        ((INSTANCE) == DMA1_Channel6) || \
10549                                        ((INSTANCE) == DMA1_Channel7) || \
10550                                        ((INSTANCE) == DMA2_Channel1) || \
10551                                        ((INSTANCE) == DMA2_Channel2) || \
10552                                        ((INSTANCE) == DMA2_Channel3) || \
10553                                        ((INSTANCE) == DMA2_Channel4) || \
10554                                        ((INSTANCE) == DMA2_Channel5) || \
10555                                        ((INSTANCE) == DMA2_Channel6) || \
10556                                        ((INSTANCE) == DMA2_Channel7))
10557 
10558 /******************************* GPIO Instances *******************************/
10559 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
10560                                         ((INSTANCE) == GPIOB) || \
10561                                         ((INSTANCE) == GPIOC) || \
10562                                         ((INSTANCE) == GPIOD) || \
10563                                         ((INSTANCE) == GPIOH))
10564 
10565 /******************************* GPIO AF Instances ****************************/
10566 /* On L4, all GPIO Bank support AF */
10567 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
10568 
10569 /**************************** GPIO Lock Instances *****************************/
10570 /* On L4, all GPIO Bank support the Lock mechanism */
10571 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
10572 
10573 /******************************** I2C Instances *******************************/
10574 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
10575                                        ((INSTANCE) == I2C2) || \
10576                                        ((INSTANCE) == I2C3))
10577 
10578 /****************** I2C Instances : wakeup capability from stop modes *********/
10579 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
10580 
10581 /****************************** OPAMP Instances *******************************/
10582 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP1)
10583 
10584 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP1_COMMON)
10585 
10586 /******************************* QSPI Instances *******************************/
10587 #define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
10588 
10589 /******************************* RNG Instances ********************************/
10590 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
10591 
10592 /****************************** RTC Instances *********************************/
10593 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
10594 
10595 /******************************** SAI Instances *******************************/
10596 
10597 /****************************** SMBUS Instances *******************************/
10598 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
10599                                          ((INSTANCE) == I2C2) || \
10600                                          ((INSTANCE) == I2C3))
10601 
10602 /******************************** SPI Instances *******************************/
10603 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
10604                                        ((INSTANCE) == SPI2))
10605 
10606 /****************** LPTIM Instances : All supported instances *****************/
10607 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
10608                                          ((INSTANCE) == LPTIM2))
10609 
10610 /****************** LPTIM Instances : supporting the encoder mode *************/
10611 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
10612 
10613 /****************** TIM Instances : All supported instances *******************/
10614 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
10615                                          ((INSTANCE) == TIM2)   || \
10616                                          ((INSTANCE) == TIM6)   || \
10617                                          ((INSTANCE) == TIM15)  || \
10618                                          ((INSTANCE) == TIM16))
10619 
10620 /****************** TIM Instances : supporting 32 bits counter ****************/
10621 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
10622 
10623 /****************** TIM Instances : supporting the break function *************/
10624 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
10625                                             ((INSTANCE) == TIM15)   || \
10626                                             ((INSTANCE) == TIM16))
10627 
10628 /************** TIM Instances : supporting Break source selection *************/
10629 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
10630                                                ((INSTANCE) == TIM15)  || \
10631                                                ((INSTANCE) == TIM16))
10632 
10633 /****************** TIM Instances : supporting 2 break inputs *****************/
10634 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
10635 
10636 /************* TIM Instances : at least 1 capture/compare channel *************/
10637 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10638                                          ((INSTANCE) == TIM2)   || \
10639                                          ((INSTANCE) == TIM15)  || \
10640                                          ((INSTANCE) == TIM16))
10641 
10642 /************ TIM Instances : at least 2 capture/compare channels *************/
10643 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10644                                          ((INSTANCE) == TIM2)   || \
10645                                          ((INSTANCE) == TIM15))
10646 
10647 /************ TIM Instances : at least 3 capture/compare channels *************/
10648 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10649                                          ((INSTANCE) == TIM2))
10650 
10651 /************ TIM Instances : at least 4 capture/compare channels *************/
10652 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10653                                          ((INSTANCE) == TIM2))
10654 
10655 /****************** TIM Instances : at least 5 capture/compare channels *******/
10656 #define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
10657 
10658 /****************** TIM Instances : at least 6 capture/compare channels *******/
10659 #define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
10660 
10661 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
10662 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
10663                                             ((INSTANCE) == TIM15)  || \
10664                                             ((INSTANCE) == TIM16))
10665 
10666 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
10667 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
10668                                             ((INSTANCE) == TIM2)   || \
10669                                             ((INSTANCE) == TIM6)   || \
10670                                             ((INSTANCE) == TIM15)  || \
10671                                             ((INSTANCE) == TIM16))
10672 
10673 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
10674 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
10675                                             ((INSTANCE) == TIM2)   || \
10676                                             ((INSTANCE) == TIM15)  || \
10677                                             ((INSTANCE) == TIM16))
10678 
10679 /******************** TIM Instances : DMA burst feature ***********************/
10680 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
10681                                             ((INSTANCE) == TIM2)   || \
10682                                             ((INSTANCE) == TIM15)  || \
10683                                             ((INSTANCE) == TIM16))
10684 
10685 /******************* TIM Instances : output(s) available **********************/
10686 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
10687     ((((INSTANCE) == TIM1) &&                  \
10688      (((CHANNEL) == TIM_CHANNEL_1) ||          \
10689       ((CHANNEL) == TIM_CHANNEL_2) ||          \
10690       ((CHANNEL) == TIM_CHANNEL_3) ||          \
10691       ((CHANNEL) == TIM_CHANNEL_4) ||          \
10692       ((CHANNEL) == TIM_CHANNEL_5) ||          \
10693       ((CHANNEL) == TIM_CHANNEL_6)))           \
10694      ||                                        \
10695      (((INSTANCE) == TIM2) &&                  \
10696      (((CHANNEL) == TIM_CHANNEL_1) ||          \
10697       ((CHANNEL) == TIM_CHANNEL_2) ||          \
10698       ((CHANNEL) == TIM_CHANNEL_3) ||          \
10699       ((CHANNEL) == TIM_CHANNEL_4)))           \
10700      ||                                        \
10701      (((INSTANCE) == TIM15) &&                 \
10702      (((CHANNEL) == TIM_CHANNEL_1) ||          \
10703       ((CHANNEL) == TIM_CHANNEL_2)))           \
10704      ||                                        \
10705      (((INSTANCE) == TIM16) &&                 \
10706      (((CHANNEL) == TIM_CHANNEL_1))))
10707 
10708 /****************** TIM Instances : supporting complementary output(s) ********/
10709 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
10710    ((((INSTANCE) == TIM1) &&                    \
10711      (((CHANNEL) == TIM_CHANNEL_1) ||           \
10712       ((CHANNEL) == TIM_CHANNEL_2) ||           \
10713       ((CHANNEL) == TIM_CHANNEL_3)))            \
10714     ||                                          \
10715     (((INSTANCE) == TIM15) &&                   \
10716      ((CHANNEL) == TIM_CHANNEL_1))              \
10717     ||                                          \
10718     (((INSTANCE) == TIM16) &&                   \
10719      ((CHANNEL) == TIM_CHANNEL_1)))
10720 
10721 /****************** TIM Instances : supporting clock division *****************/
10722 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
10723                                                     ((INSTANCE) == TIM2)    || \
10724                                                     ((INSTANCE) == TIM15)   || \
10725                                                     ((INSTANCE) == TIM16))
10726 
10727 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
10728 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10729                                                         ((INSTANCE) == TIM2) || \
10730                                                         ((INSTANCE) == TIM15))
10731 
10732 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
10733 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10734                                                         ((INSTANCE) == TIM2))
10735 
10736 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
10737 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
10738                                                         ((INSTANCE) == TIM2) || \
10739                                                         ((INSTANCE) == TIM15))
10740 
10741 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
10742 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
10743                                                         ((INSTANCE) == TIM2) || \
10744                                                         ((INSTANCE) == TIM15))
10745 
10746 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
10747 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
10748 
10749 /****************** TIM Instances : supporting commutation event generation ***/
10750 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
10751                                                      ((INSTANCE) == TIM15)  || \
10752                                                      ((INSTANCE) == TIM16))
10753 
10754 /****************** TIM Instances : supporting counting mode selection ********/
10755 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
10756                                                         ((INSTANCE) == TIM2))
10757 
10758 /****************** TIM Instances : supporting encoder interface **************/
10759 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
10760                                                       ((INSTANCE) == TIM2))
10761 
10762 /****************** TIM Instances : supporting Hall sensor interface **********/
10763 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
10764                                                           ((INSTANCE) == TIM2))
10765 
10766 /**************** TIM Instances : external trigger input available ************/
10767 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
10768                                             ((INSTANCE) == TIM2))
10769 
10770 /************* TIM Instances : supporting ETR source selection ***************/
10771 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
10772                                              ((INSTANCE) == TIM2))
10773 
10774 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
10775 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
10776                                             ((INSTANCE) == TIM2)  || \
10777                                             ((INSTANCE) == TIM6)  || \
10778                                             ((INSTANCE) == TIM15))
10779 
10780 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
10781 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
10782                                             ((INSTANCE) == TIM2)  || \
10783                                             ((INSTANCE) == TIM15))
10784 
10785 /****************** TIM Instances : supporting OCxREF clear *******************/
10786 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
10787                                                        ((INSTANCE) == TIM2))
10788 
10789 /****************** TIM Instances : remapping capability **********************/
10790 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
10791                                             ((INSTANCE) == TIM2)  || \
10792                                             ((INSTANCE) == TIM15) || \
10793                                             ((INSTANCE) == TIM16))
10794 
10795 /****************** TIM Instances : supporting repetition counter *************/
10796 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
10797                                                        ((INSTANCE) == TIM15) || \
10798                                                        ((INSTANCE) == TIM16))
10799 
10800 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
10801 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
10802 
10803 /******************* TIM Instances : Timer input XOR function *****************/
10804 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
10805                                             ((INSTANCE) == TIM2)   || \
10806                                             ((INSTANCE) == TIM15))
10807 
10808 /****************** TIM Instances : Advanced timer instances *******************/
10809 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
10810 
10811 /****************************** TSC Instances *********************************/
10812 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
10813 
10814 /******************** USART Instances : Synchronous mode **********************/
10815 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10816                                      ((INSTANCE) == USART2) || \
10817                                      ((INSTANCE) == USART3))
10818 
10819 /******************** UART Instances : Asynchronous mode **********************/
10820 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10821                                     ((INSTANCE) == USART2) || \
10822                                     ((INSTANCE) == USART3))
10823 
10824 /****************** UART Instances : Auto Baud Rate detection ****************/
10825 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10826                                                             ((INSTANCE) == USART2) || \
10827                                                             ((INSTANCE) == USART3))
10828 
10829 /****************** UART Instances : Driver Enable *****************/
10830 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
10831                                                       ((INSTANCE) == USART2) || \
10832                                                       ((INSTANCE) == USART3) || \
10833                                                       ((INSTANCE) == LPUART1))
10834 
10835 /******************** UART Instances : Half-Duplex mode **********************/
10836 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
10837                                                  ((INSTANCE) == USART2) || \
10838                                                  ((INSTANCE) == USART3) || \
10839                                                  ((INSTANCE) == LPUART1))
10840 
10841 /****************** UART Instances : Hardware Flow control ********************/
10842 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10843                                            ((INSTANCE) == USART2) || \
10844                                            ((INSTANCE) == USART3) || \
10845                                            ((INSTANCE) == LPUART1))
10846 
10847 /******************** UART Instances : LIN mode **********************/
10848 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
10849                                           ((INSTANCE) == USART2) || \
10850                                           ((INSTANCE) == USART3))
10851 
10852 /******************** UART Instances : Wake-up from Stop mode **********************/
10853 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
10854                                                       ((INSTANCE) == USART2) || \
10855                                                       ((INSTANCE) == USART3) || \
10856                                                       ((INSTANCE) == LPUART1))
10857 
10858 /*********************** UART Instances : IRDA mode ***************************/
10859 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10860                                     ((INSTANCE) == USART2) || \
10861                                     ((INSTANCE) == USART3))
10862 
10863 /********************* USART Instances : Smard card mode ***********************/
10864 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10865                                          ((INSTANCE) == USART2) || \
10866                                          ((INSTANCE) == USART3))
10867 
10868 /******************** LPUART Instance *****************************************/
10869 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
10870 
10871 /****************************** IWDG Instances ********************************/
10872 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
10873 
10874 /****************************** WWDG Instances ********************************/
10875 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
10876 
10877 /******************************* USB Instances *******************************/
10878 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
10879 #define IS_PCD_ALL_INSTANCE           IS_USB_ALL_INSTANCE
10880 /**
10881   * @}
10882   */
10883 
10884 
10885 /******************************************************************************/
10886 /*  For a painless codes migration between the STM32L4xx device product       */
10887 /*  lines, the aliases defined below are put in place to overcome the         */
10888 /*  differences in the interrupt handlers and IRQn definitions.               */
10889 /*  No need to update developed interrupt code when moving across             */
10890 /*  product lines within the same STM32L4 Family                              */
10891 /******************************************************************************/
10892 
10893 /* Aliases for __IRQn */
10894 #define ADC1_IRQn                      ADC1_2_IRQn
10895 #define HASH_RNG_IRQn                  RNG_IRQn
10896 #define HASH_CRS_IRQn                  CRS_IRQn
10897 #define TIM1_TRG_COM_TIM17_IRQn        TIM1_TRG_COM_IRQn
10898 #define TIM6_DAC_IRQn                  TIM6_IRQn
10899 
10900 /* Aliases for __IRQHandler */
10901 #define ADC1_IRQHandler                ADC1_2_IRQHandler
10902 #define HASH_RNG_IRQHandler            RNG_IRQHandler
10903 #define HASH_CRS_IRQHandler            CRS_IRQHandler
10904 #define TIM1_TRG_COM_TIM17_IRQHandler  TIM1_TRG_COM_IRQHandler
10905 #define TIM6_DAC_IRQHandler            TIM6_IRQHandler
10906 
10907 #ifdef __cplusplus
10908 }
10909 #endif /* __cplusplus */
10910 
10911 #endif /* __STM32L412xx_H */
10912 
10913 /**
10914   * @}
10915   */
10916 
10917   /**
10918   * @}
10919   */
10920 
10921