/hal_stm32-3.6.0/stm32cube/stm32f0xx/soc/ |
D | stm32f051x8.h | 5836 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 5837 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32f058xx.h | 5805 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 5806 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32f071xb.h | 6389 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 6390 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32f042x6.h | 9611 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 9612 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32f048xx.h | 9575 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 9576 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32f072xb.h | 10186 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 10187 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32f078xx.h | 10156 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 10157 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32f098xx.h | 10810 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 10811 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32f091xc.h | 10843 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 10844 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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/hal_stm32-3.6.0/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6362 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 6363 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32l053xx.h | 6521 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 6522 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32l062xx.h | 6499 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 6500 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32l063xx.h | 6656 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 6657 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32l072xx.h | 6658 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 6659 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32l073xx.h | 6817 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 6818 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32l082xx.h | 6795 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 6796 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32l083xx.h | 6954 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 6955 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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/hal_stm32-3.6.0/stm32cube/stm32f3xx/soc/ |
D | stm32f318xx.h | 7610 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 7611 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32f301x8.h | 7623 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 7624 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32f373xc.h | 10797 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 10798 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32f378xx.h | 10695 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 10696 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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/hal_stm32-3.6.0/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9443 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 9444 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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/hal_stm32-3.6.0/stm32cube/stm32l4xx/soc/ |
D | stm32l412xx.h | 9292 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 9293 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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D | stm32l422xx.h | 9517 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 9518 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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/hal_stm32-3.6.0/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb15xx.h | 8252 #define TSC_IOCCR_G4_IO1_Pos (12U) macro 8253 #define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
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