/hal_stm32-3.6.0/stm32cube/stm32f0xx/soc/ |
D | stm32f051x8.h | 5824 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 5825 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32f058xx.h | 5793 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 5794 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32f071xb.h | 6377 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 6378 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32f042x6.h | 9599 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 9600 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32f048xx.h | 9563 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 9564 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32f072xb.h | 10174 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 10175 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32f078xx.h | 10144 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 10145 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32f098xx.h | 10798 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 10799 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32f091xc.h | 10831 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 10832 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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/hal_stm32-3.6.0/stm32cube/stm32l0xx/soc/ |
D | stm32l052xx.h | 6350 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 6351 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32l053xx.h | 6509 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 6510 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32l062xx.h | 6487 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 6488 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32l063xx.h | 6644 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 6645 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32l072xx.h | 6646 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 6647 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32l073xx.h | 6805 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 6806 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32l082xx.h | 6783 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 6784 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32l083xx.h | 6942 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 6943 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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/hal_stm32-3.6.0/stm32cube/stm32f3xx/soc/ |
D | stm32f318xx.h | 7598 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 7599 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32f301x8.h | 7611 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 7612 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32f373xc.h | 10785 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 10786 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32f378xx.h | 10683 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 10684 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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/hal_stm32-3.6.0/stm32cube/stm32wbaxx/soc/ |
D | stm32wba50xx.h | 9431 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 9432 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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/hal_stm32-3.6.0/stm32cube/stm32l4xx/soc/ |
D | stm32l412xx.h | 9280 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 9281 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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D | stm32l422xx.h | 9505 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 9506 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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/hal_stm32-3.6.0/stm32cube/stm32wbxx/soc/Include/ |
D | stm32wb15xx.h | 8240 #define TSC_IOCCR_G3_IO1_Pos (8U) macro 8241 #define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
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