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Searched refs:pll1 (Results 1 – 25 of 28) sorted by relevance

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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/
Dpll_hsi_160.overlay16 &pll1 {
26 clocks = <&pll1>;
Dpll_hsi_40.overlay16 &pll1 {
26 clocks = <&pll1>;
Dpll_msis_160.overlay22 &pll1 {
32 clocks = <&pll1>;
Dpll_msis_ahb_2_40.overlay22 &pll1 {
32 clocks = <&pll1>;
Dpll_hsi_fracn_160.overlay16 &pll1 {
Dpll_hse_160.overlay23 &pll1 {
Dpll_hse_fracn_160.overlay22 &pll1 {
Dclear_clocks.overlay32 &pll1 {
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay43 &pll1 {
82 &pll1 {
92 clocks = <&pll1>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/
Dpll_hse_100_ahb_50.overlay17 &pll1 {
Dpll_hse_100.overlay17 &pll1 {
Dclear_clocks.overlay21 &pll1 {
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dpll_hse25_240.overlay24 &pll1 {
/Zephyr-latest/boards/st/nucleo_wba52cg/
Dnucleo_wba52cg.dts67 &pll1 {
77 clocks = <&pll1>;
/Zephyr-latest/boards/st/nucleo_u575zi_q/
Dnucleo_u575zi_q-common.dtsi69 &pll1 {
79 clocks = <&pll1>;
/Zephyr-latest/boards/st/nucleo_u5a5zj_q/
Dnucleo_u5a5zj_q-common.dtsi68 &pll1 {
79 clocks = <&pll1>;
/Zephyr-latest/drivers/clock_control/
Dclock_control_ifx_cat1.c121 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1))
245 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1))
246 [INFINEON_CAT1_CLOCK_PLL1] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(pll1)) },
486 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1)) in clock_control_infineon_cat1_init()
488 frequency = DT_PROP(DT_NODELABEL(pll1), clock_frequency); in clock_control_infineon_cat1_init()
/Zephyr-latest/boards/st/b_u585i_iot02a/
Db_u585i_iot02a-common.dtsi59 &pll1 {
69 clocks = <&pll1>;
/Zephyr-latest/boards/st/stm32u5a9j_dk/
Dstm32u5a9j_dk.dts96 &pll1 {
107 clocks = <&pll1>;
/Zephyr-latest/boards/st/steval_stwinbx1/
Dsteval_stwinbx1.dts87 &pll1 {
117 clocks = <&pll1>;
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h261 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll1), st_stm32n6_pll_clock, okay)
263 #define STM32_PLL1_M_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_m)
264 #define STM32_PLL1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll1), mul_n)
265 #define STM32_PLL1_P1_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p1)
266 #define STM32_PLL1_P2_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p2)
/Zephyr-latest/boards/st/stm32n6570_dk/
Dstm32n6570_dk_common.dtsi44 &pll1 {
/Zephyr-latest/boards/st/sensortile_box_pro/
Dsensortile_box_pro.dts104 &pll1 {
114 clocks = <&pll1>;
/Zephyr-latest/boards/st/nucleo_n657x0_q/
Dnucleo_n657x0_q_common.dtsi62 &pll1 {
/Zephyr-latest/dts/arm/st/wba/
Dstm32wba.dtsi114 pll1: pll: pll { label

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