Searched refs:pll1 (Results 1 – 25 of 28) sorted by relevance
12
16 &pll1 {26 clocks = <&pll1>;
22 &pll1 {32 clocks = <&pll1>;
16 &pll1 {
23 &pll1 {
22 &pll1 {
32 &pll1 {
43 &pll1 {82 &pll1 {92 clocks = <&pll1>;
17 &pll1 {
21 &pll1 {
24 &pll1 {
67 &pll1 {77 clocks = <&pll1>;
69 &pll1 {79 clocks = <&pll1>;
68 &pll1 {79 clocks = <&pll1>;
121 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1))245 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1))246 [INFINEON_CAT1_CLOCK_PLL1] = { .dt_ord = DT_DEP_ORD(DT_NODELABEL(pll1)) },486 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll1)) in clock_control_infineon_cat1_init()488 frequency = DT_PROP(DT_NODELABEL(pll1), clock_frequency); in clock_control_infineon_cat1_init()
59 &pll1 {69 clocks = <&pll1>;
96 &pll1 {107 clocks = <&pll1>;
87 &pll1 {117 clocks = <&pll1>;
261 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll1), st_stm32n6_pll_clock, okay)263 #define STM32_PLL1_M_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_m)264 #define STM32_PLL1_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll1), mul_n)265 #define STM32_PLL1_P1_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p1)266 #define STM32_PLL1_P2_DIVISOR DT_PROP(DT_NODELABEL(pll1), div_p2)
44 &pll1 {
104 &pll1 {114 clocks = <&pll1>;
62 &pll1 {
114 pll1: pll: pll { label