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Searched refs:RCC_CFGR4_HDIV5 (Results 1 – 7 of 7) sorted by relevance

/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/src/
Dstm32wbaxx_hal_rcc.c1009 MODIFY_REG(RCC->CFGR4, (RCC_CFGR4_HDIV5 | RCC_CFGR4_HPRE5), in HAL_RCC_ClockConfig()
1371 tmp = (RCC->CFGR4 & RCC_CFGR4_HDIV5) >> RCC_CFGR4_HDIV5_Pos; in HAL_RCC_GetHCLK5Freq()
1550 RCC_ClkInitStruct->AHB5_HSEHSI_CLKDivider = (tmpreg1 & RCC_CFGR4_HDIV5); in HAL_RCC_GetClockConfig()
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/drivers/include/
Dstm32wbaxx_ll_rcc.h333 #define LL_RCC_AHB5_DIVIDER_2 RCC_CFGR4_HDIV5
1554 MODIFY_REG(RCC->CFGR4, RCC_CFGR4_HDIV5, Divider); in LL_RCC_SetAHB5Divider()
1654 return (uint32_t)(READ_BIT(RCC->CFGR4, RCC_CFGR4_HDIV5)); in LL_RCC_GetAHB5Divider()
Dstm32wbaxx_hal_rcc.h352 #define RCC_SYSCLK_HSEHSI_DIV2 RCC_CFGR4_HDIV5 /*!< SYSCLK when HSE or HSI is source d…
/hal_stm32-3.5.0/stm32cube/stm32wbaxx/soc/
Dstm32wba50xx.h6582 #define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk macro
Dstm32wba52xx.h10479 #define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk macro
Dstm32wba54xx.h10872 #define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk macro
Dstm32wba55xx.h10890 #define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk macro