Searched refs:dr (Results 1 – 18 of 18) sorted by relevance
192 uint8_t dr : 2; member196 uint8_t dr : 2;
273 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4; in h3lis100dl_data_rate_set()298 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) in h3lis100dl_data_rate_get()
191 uint8_t dr : 2; member195 uint8_t dr : 2;
283 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4; in h3lis331dl_data_rate_set()308 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) in h3lis331dl_data_rate_get()
189 uint8_t dr : 2; member191 uint8_t dr : 2;
138 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4; in i3g4250d_data_rate_set()163 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pd) in i3g4250d_data_rate_get()
188 uint8_t dr : 2; member190 uint8_t dr : 2;
138 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4; in a3g4250d_data_rate_set()163 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pd) in a3g4250d_data_rate_get()
288 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4; in lis331dlh_data_rate_set()313 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) in lis331dlh_data_rate_get()
282 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4; in iis328dq_data_rate_set()306 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) in iis328dq_data_rate_get()
215 uint8_t dr : 2; member219 uint8_t dr : 2;
282 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4; in ais328dq_data_rate_set()306 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) in ais328dq_data_rate_get()
282 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4; in ais3624dq_data_rate_set()307 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm) in ais3624dq_data_rate_get()
193 uint8_t dr : 2; member195 uint8_t dr : 2;
198 ctrl1.dr = (uint8_t)val & 0x07U; in l3gd20h_gy_data_rate_set()237 switch ((ctrl1.pd << 7) + (low_odr.low_odr << 4) + ctrl1.dr) in l3gd20h_gy_data_rate_get()697 switch ((low_odr.low_odr << 7) + (ctrl1.dr << 4) + ctrl1.bw) in l3gd20h_gy_filter_lp_bandwidth_get()
