1 /**
2 ******************************************************************************
3 * @file ais3624dq_reg.c
4 * @author Sensors Software Solution Team
5 * @brief AIS3624DQ driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ais3624dq_reg.h"
21
22 /**
23 * @defgroup AIS3624DQ
24 * @brief This file provides a set of functions needed to drive the
25 * ais3624dq enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup AIS3624DQ_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ais3624dq_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ais3624dq_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL) return -1;
56
57 ret = ctx->read_reg(ctx->handle, reg, data, len);
58
59 return ret;
60 }
61
62 /**
63 * @brief Write generic device register
64 *
65 * @param ctx read / write interface definitions(ptr)
66 * @param reg register to write
67 * @param data pointer to data to write in register reg(ptr)
68 * @param len number of consecutive register to write
69 * @retval interface status (MANDATORY: return 0 -> no Error)
70 *
71 */
ais3624dq_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)72 int32_t __weak ais3624dq_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
73 uint8_t *data,
74 uint16_t len)
75 {
76 int32_t ret;
77
78 if (ctx == NULL) return -1;
79
80 ret = ctx->write_reg(ctx->handle, reg, data, len);
81
82 return ret;
83 }
84
85 /**
86 * @}
87 *
88 */
89
90 /**
91 * @defgroup AIS3624DQ_Sensitivity
92 * @brief These functions convert raw-data into engineering units.
93 * @{
94 *
95 */
96
ais3624dq_from_fs6_to_mg(int16_t lsb)97 float_t ais3624dq_from_fs6_to_mg(int16_t lsb)
98 {
99 return ((float_t)lsb * 2.9f / 16.0f);
100 }
101
ais3624dq_from_fs12_to_mg(int16_t lsb)102 float_t ais3624dq_from_fs12_to_mg(int16_t lsb)
103 {
104 return ((float_t)lsb * 5.9f / 16.0f);
105 }
106
ais3624dq_from_fs24_to_mg(int16_t lsb)107 float_t ais3624dq_from_fs24_to_mg(int16_t lsb)
108 {
109 return ((float_t)lsb * 11.7f / 16.0f);
110 }
111
112 /**
113 * @}
114 *
115 */
116
117 /**
118 * @defgroup AIS3624DQ_Data_Generation
119 * @brief This section group all the functions concerning
120 * data generation
121 * @{
122 *
123 */
124
125 /**
126 * @brief X axis enable/disable.[set]
127 *
128 * @param ctx read / write interface definitions(ptr)
129 * @param val change the values of xen in reg CTRL_REG1
130 * @retval interface status (MANDATORY: return 0 -> no Error)
131 *
132 */
ais3624dq_axis_x_data_set(const stmdev_ctx_t * ctx,uint8_t val)133 int32_t ais3624dq_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val)
134 {
135 ais3624dq_ctrl_reg1_t ctrl_reg1;
136 int32_t ret;
137
138 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
139 (uint8_t *)&ctrl_reg1, 1);
140
141 if (ret == 0)
142 {
143 ctrl_reg1.xen = val;
144 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG1,
145 (uint8_t *)&ctrl_reg1, 1);
146 }
147
148 return ret;
149 }
150
151 /**
152 * @brief X axis enable/disable.[get]
153 *
154 * @param ctx read / write interface definitions(ptr)
155 * @param val change the values of xen in reg CTRL_REG1
156 * @retval interface status (MANDATORY: return 0 -> no Error)
157 *
158 */
ais3624dq_axis_x_data_get(const stmdev_ctx_t * ctx,uint8_t * val)159 int32_t ais3624dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
160 {
161 ais3624dq_ctrl_reg1_t ctrl_reg1;
162 int32_t ret;
163
164 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
165 (uint8_t *)&ctrl_reg1, 1);
166 *val = ctrl_reg1.xen;
167
168 return ret;
169 }
170
171 /**
172 * @brief Y axis enable/disable.[set]
173 *
174 * @param ctx read / write interface definitions(ptr)
175 * @param val change the values of yen in reg CTRL_REG1
176 * @retval interface status (MANDATORY: return 0 -> no Error)
177 *
178 */
ais3624dq_axis_y_data_set(const stmdev_ctx_t * ctx,uint8_t val)179 int32_t ais3624dq_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val)
180 {
181 ais3624dq_ctrl_reg1_t ctrl_reg1;
182 int32_t ret;
183
184 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
185 (uint8_t *)&ctrl_reg1, 1);
186
187 if (ret == 0)
188 {
189 ctrl_reg1.yen = val;
190 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG1,
191 (uint8_t *)&ctrl_reg1, 1);
192 }
193
194 return ret;
195 }
196
197 /**
198 * @brief Y axis enable/disable.[get]
199 *
200 * @param ctx read / write interface definitions(ptr)
201 * @param val change the values of yen in reg CTRL_REG1
202 * @retval interface status (MANDATORY: return 0 -> no Error)
203 *
204 */
ais3624dq_axis_y_data_get(const stmdev_ctx_t * ctx,uint8_t * val)205 int32_t ais3624dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
206 {
207 ais3624dq_ctrl_reg1_t ctrl_reg1;
208 int32_t ret;
209
210 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
211 (uint8_t *)&ctrl_reg1, 1);
212 *val = ctrl_reg1.yen;
213
214 return ret;
215 }
216
217 /**
218 * @brief Z axis enable/disable.[set]
219 *
220 * @param ctx read / write interface definitions(ptr)
221 * @param val change the values of zen in reg CTRL_REG1
222 * @retval interface status (MANDATORY: return 0 -> no Error)
223 *
224 */
ais3624dq_axis_z_data_set(const stmdev_ctx_t * ctx,uint8_t val)225 int32_t ais3624dq_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val)
226 {
227 ais3624dq_ctrl_reg1_t ctrl_reg1;
228 int32_t ret;
229
230 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
231 (uint8_t *)&ctrl_reg1, 1);
232
233 if (ret == 0)
234 {
235 ctrl_reg1.zen = val;
236 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG1,
237 (uint8_t *)&ctrl_reg1, 1);
238 }
239
240 return ret;
241 }
242
243 /**
244 * @brief Z axis enable/disable.[get]
245 *
246 * @param ctx read / write interface definitions(ptr)
247 * @param val change the values of zen in reg CTRL_REG1
248 * @retval interface status (MANDATORY: return 0 -> no Error)
249 *
250 */
ais3624dq_axis_z_data_get(const stmdev_ctx_t * ctx,uint8_t * val)251 int32_t ais3624dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
252 {
253 ais3624dq_ctrl_reg1_t ctrl_reg1;
254 int32_t ret;
255
256 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
257 (uint8_t *)&ctrl_reg1, 1);
258 *val = ctrl_reg1.zen;
259
260 return ret;
261 }
262
263 /**
264 * @brief Accelerometer data rate selection.[set]
265 *
266 * @param ctx read / write interface definitions(ptr)
267 * @param val change the values of dr in reg CTRL_REG1
268 * @retval interface status (MANDATORY: return 0 -> no Error)
269 *
270 */
ais3624dq_data_rate_set(const stmdev_ctx_t * ctx,ais3624dq_dr_t val)271 int32_t ais3624dq_data_rate_set(const stmdev_ctx_t *ctx, ais3624dq_dr_t val)
272 {
273 ais3624dq_ctrl_reg1_t ctrl_reg1;
274 int32_t ret;
275
276 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
277 (uint8_t *)&ctrl_reg1, 1);
278
279 if (ret == 0)
280 {
281 ctrl_reg1.pm = (uint8_t)val & 0x07U;
282 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
283 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG1,
284 (uint8_t *)&ctrl_reg1, 1);
285 }
286
287 return ret;
288 }
289
290 /**
291 * @brief Accelerometer data rate selection.[get]
292 *
293 * @param ctx read / write interface definitions(ptr)
294 * @param val Get the values of dr in reg CTRL_REG1
295 * @retval interface status (MANDATORY: return 0 -> no Error)
296 *
297 */
ais3624dq_data_rate_get(const stmdev_ctx_t * ctx,ais3624dq_dr_t * val)298 int32_t ais3624dq_data_rate_get(const stmdev_ctx_t *ctx,
299 ais3624dq_dr_t *val)
300 {
301 ais3624dq_ctrl_reg1_t ctrl_reg1;
302 int32_t ret;
303
304 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG1,
305 (uint8_t *)&ctrl_reg1, 1);
306
307 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
308 {
309 case AIS3624DQ_ODR_OFF:
310 *val = AIS3624DQ_ODR_OFF;
311 break;
312
313 case AIS3624DQ_ODR_Hz5:
314 *val = AIS3624DQ_ODR_Hz5;
315 break;
316
317 case AIS3624DQ_ODR_1Hz:
318 *val = AIS3624DQ_ODR_1Hz;
319 break;
320
321 case AIS3624DQ_ODR_2Hz:
322 *val = AIS3624DQ_ODR_2Hz;
323 break;
324
325 case AIS3624DQ_ODR_5Hz:
326 *val = AIS3624DQ_ODR_5Hz;
327 break;
328
329 case AIS3624DQ_ODR_10Hz:
330 *val = AIS3624DQ_ODR_10Hz;
331 break;
332
333 case AIS3624DQ_ODR_50Hz:
334 *val = AIS3624DQ_ODR_50Hz;
335 break;
336
337 case AIS3624DQ_ODR_100Hz:
338 *val = AIS3624DQ_ODR_100Hz;
339 break;
340
341 case AIS3624DQ_ODR_400Hz:
342 *val = AIS3624DQ_ODR_400Hz;
343 break;
344
345 case AIS3624DQ_ODR_1kHz:
346 *val = AIS3624DQ_ODR_1kHz;
347 break;
348
349 default:
350 *val = AIS3624DQ_ODR_OFF;
351 break;
352 }
353
354 return ret;
355 }
356
357 /**
358 * @brief High pass filter mode selection.[set]
359 *
360 * @param ctx read / write interface definitions(ptr)
361 * @param val change the values of hpm in reg CTRL_REG2
362 * @retval interface status (MANDATORY: return 0 -> no Error)
363 *
364 */
ais3624dq_reference_mode_set(const stmdev_ctx_t * ctx,ais3624dq_hpm_t val)365 int32_t ais3624dq_reference_mode_set(const stmdev_ctx_t *ctx,
366 ais3624dq_hpm_t val)
367 {
368 ais3624dq_ctrl_reg2_t ctrl_reg2;
369 int32_t ret;
370
371 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
372 (uint8_t *)&ctrl_reg2, 1);
373
374 if (ret == 0)
375 {
376 ctrl_reg2.hpm = (uint8_t)val;
377 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG2,
378 (uint8_t *)&ctrl_reg2, 1);
379 }
380
381 return ret;
382 }
383
384 /**
385 * @brief High pass filter mode selection.[get]
386 *
387 * @param ctx read / write interface definitions(ptr)
388 * @param val Get the values of hpm in reg CTRL_REG2
389 * @retval interface status (MANDATORY: return 0 -> no Error)
390 *
391 */
ais3624dq_reference_mode_get(const stmdev_ctx_t * ctx,ais3624dq_hpm_t * val)392 int32_t ais3624dq_reference_mode_get(const stmdev_ctx_t *ctx,
393 ais3624dq_hpm_t *val)
394 {
395 ais3624dq_ctrl_reg2_t ctrl_reg2;
396 int32_t ret;
397
398 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
399 (uint8_t *)&ctrl_reg2, 1);
400
401 switch (ctrl_reg2.hpm)
402 {
403 case AIS3624DQ_NORMAL_MODE:
404 *val = AIS3624DQ_NORMAL_MODE;
405 break;
406
407 case AIS3624DQ_REF_MODE_ENABLE:
408 *val = AIS3624DQ_REF_MODE_ENABLE;
409 break;
410
411 default:
412 *val = AIS3624DQ_NORMAL_MODE;
413 break;
414 }
415
416 return ret;
417 }
418
419 /**
420 * @brief Accelerometer full-scale selection.[set]
421 *
422 * @param ctx read / write interface definitions(ptr)
423 * @param val change the values of fs in reg CTRL_REG4
424 * @retval interface status (MANDATORY: return 0 -> no Error)
425 *
426 */
ais3624dq_full_scale_set(const stmdev_ctx_t * ctx,ais3624dq_fs_t val)427 int32_t ais3624dq_full_scale_set(const stmdev_ctx_t *ctx,
428 ais3624dq_fs_t val)
429 {
430 ais3624dq_ctrl_reg4_t ctrl_reg4;
431 int32_t ret;
432
433 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
434 (uint8_t *)&ctrl_reg4, 1);
435
436 if (ret == 0)
437 {
438 ctrl_reg4.fs = (uint8_t)val;
439 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG4,
440 (uint8_t *)&ctrl_reg4, 1);
441 }
442
443 return ret;
444 }
445
446 /**
447 * @brief Accelerometer full-scale selection.[get]
448 *
449 * @param ctx read / write interface definitions(ptr)
450 * @param val Get the values of fs in reg CTRL_REG4
451 * @retval interface status (MANDATORY: return 0 -> no Error)
452 *
453 */
ais3624dq_full_scale_get(const stmdev_ctx_t * ctx,ais3624dq_fs_t * val)454 int32_t ais3624dq_full_scale_get(const stmdev_ctx_t *ctx,
455 ais3624dq_fs_t *val)
456 {
457 ais3624dq_ctrl_reg4_t ctrl_reg4;
458 int32_t ret;
459
460 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
461 (uint8_t *)&ctrl_reg4, 1);
462
463 switch (ctrl_reg4.fs)
464 {
465 case AIS3624DQ_6g:
466 *val = AIS3624DQ_6g;
467 break;
468
469 case AIS3624DQ_12g:
470 *val = AIS3624DQ_12g;
471 break;
472
473 case AIS3624DQ_24g:
474 *val = AIS3624DQ_24g;
475 break;
476
477 default:
478 *val = AIS3624DQ_6g;
479 break;
480 }
481
482 return ret;
483 }
484
485 /**
486 * @brief Block data update.[set]
487 *
488 * @param ctx read / write interface definitions(ptr)
489 * @param val change the values of bdu in reg CTRL_REG4
490 * @retval interface status (MANDATORY: return 0 -> no Error)
491 *
492 */
ais3624dq_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)493 int32_t ais3624dq_block_data_update_set(const stmdev_ctx_t *ctx,
494 uint8_t val)
495 {
496 ais3624dq_ctrl_reg4_t ctrl_reg4;
497 int32_t ret;
498
499 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
500 (uint8_t *)&ctrl_reg4, 1);
501
502 if (ret == 0)
503 {
504 ctrl_reg4.bdu = val;
505 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG4,
506 (uint8_t *)&ctrl_reg4, 1);
507 }
508
509 return ret;
510 }
511
512 /**
513 * @brief Block data update.[get]
514 *
515 * @param ctx read / write interface definitions(ptr)
516 * @param val change the values of bdu in reg CTRL_REG4
517 * @retval interface status (MANDATORY: return 0 -> no Error)
518 *
519 */
ais3624dq_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)520 int32_t ais3624dq_block_data_update_get(const stmdev_ctx_t *ctx,
521 uint8_t *val)
522 {
523 ais3624dq_ctrl_reg4_t ctrl_reg4;
524 int32_t ret;
525
526 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
527 (uint8_t *)&ctrl_reg4, 1);
528 *val = ctrl_reg4.bdu;
529
530 return ret;
531 }
532
533 /**
534 * @brief The STATUS_REG register is read by the interface.[get]
535 *
536 * @param ctx read / write interface definitions(ptr)
537 * @param val registers STATUS_REG
538 * @retval interface status (MANDATORY: return 0 -> no Error)
539 *
540 */
ais3624dq_status_reg_get(const stmdev_ctx_t * ctx,ais3624dq_status_reg_t * val)541 int32_t ais3624dq_status_reg_get(const stmdev_ctx_t *ctx,
542 ais3624dq_status_reg_t *val)
543 {
544 int32_t ret;
545
546 ret = ais3624dq_read_reg(ctx, AIS3624DQ_STATUS_REG, (uint8_t *) val, 1);
547
548 return ret;
549 }
550
551 /**
552 * @brief Accelerometer new data available.[get]
553 *
554 * @param ctx read / write interface definitions(ptr)
555 * @param val change the values of zyxda in reg STATUS_REG
556 * @retval interface status (MANDATORY: return 0 -> no Error)
557 *
558 */
ais3624dq_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)559 int32_t ais3624dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
560 {
561 ais3624dq_status_reg_t status_reg;
562 int32_t ret;
563
564 ret = ais3624dq_read_reg(ctx, AIS3624DQ_STATUS_REG,
565 (uint8_t *)&status_reg, 1);
566 *val = status_reg.zyxda;
567
568 return ret;
569 }
570
571 /**
572 * @}
573 *
574 */
575
576 /**
577 * @defgroup AIS3624DQ_Data_Output
578 * @brief This section groups all the data output functions.
579 * @{
580 *
581 */
582
583 /**
584 * @brief Linear acceleration output register. The value is expressed
585 * as a 16-bit word in two’s complement.[get]
586 *
587 * @param ctx read / write interface definitions(ptr)
588 * @param buff buffer that stores data read
589 * @retval interface status (MANDATORY: return 0 -> no Error)
590 *
591 */
ais3624dq_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)592 int32_t ais3624dq_acceleration_raw_get(const stmdev_ctx_t *ctx,
593 int16_t *val)
594 {
595 uint8_t buff[6];
596 int32_t ret;
597
598 ret = ais3624dq_read_reg(ctx, AIS3624DQ_OUT_X_L, buff, 6);
599 val[0] = (int16_t)buff[1];
600 val[0] = (val[0] * 256) + (int16_t)buff[0];
601 val[1] = (int16_t)buff[3];
602 val[1] = (val[1] * 256) + (int16_t)buff[2];
603 val[2] = (int16_t)buff[5];
604 val[2] = (val[2] * 256) + (int16_t)buff[4];
605
606 return ret;
607 }
608
609 /**
610 * @}
611 *
612 */
613
614 /**
615 * @defgroup AIS3624DQ_Common
616 * @brief This section groups common useful functions.
617 * @{
618 *
619 */
620
621 /**
622 * @brief Device Who am I.[get]
623 *
624 * @param ctx read / write interface definitions(ptr)
625 * @param buff buffer that stores data read
626 * @retval interface status (MANDATORY: return 0 -> no Error)
627 *
628 */
ais3624dq_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)629 int32_t ais3624dq_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
630 {
631 int32_t ret;
632
633 ret = ais3624dq_read_reg(ctx, AIS3624DQ_WHO_AM_I, buff, 1);
634
635 return ret;
636 }
637
638 /**
639 * @brief Reboot memory content. Reload the calibration parameters.[set]
640 *
641 * @param ctx read / write interface definitions(ptr)
642 * @param val change the values of boot in reg CTRL_REG2
643 * @retval interface status (MANDATORY: return 0 -> no Error)
644 *
645 */
ais3624dq_boot_set(const stmdev_ctx_t * ctx,uint8_t val)646 int32_t ais3624dq_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
647 {
648 ais3624dq_ctrl_reg2_t ctrl_reg2;
649 int32_t ret;
650
651 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
652 (uint8_t *)&ctrl_reg2, 1);
653
654 if (ret == 0)
655 {
656 ctrl_reg2.boot = val;
657 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG2,
658 (uint8_t *)&ctrl_reg2, 1);
659 }
660
661 return ret;
662 }
663
664 /**
665 * @brief Reboot memory content. Reload the calibration parameters.[get]
666 *
667 * @param ctx read / write interface definitions(ptr)
668 * @param val change the values of boot in reg CTRL_REG2
669 * @retval interface status (MANDATORY: return 0 -> no Error)
670 *
671 */
ais3624dq_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)672 int32_t ais3624dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
673 {
674 ais3624dq_ctrl_reg2_t ctrl_reg2;
675 int32_t ret;
676
677 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
678 (uint8_t *)&ctrl_reg2, 1);
679 *val = ctrl_reg2.boot;
680
681 return ret;
682 }
683
684 /**
685 * @brief Linear acceleration sensor self-test enable.[set]
686 *
687 * @param ctx read / write interface definitions(ptr)
688 * @param val change the values of st in reg CTRL_REG4
689 * @retval interface status (MANDATORY: return 0 -> no Error)
690 *
691 */
ais3624dq_self_test_set(const stmdev_ctx_t * ctx,ais3624dq_st_t val)692 int32_t ais3624dq_self_test_set(const stmdev_ctx_t *ctx, ais3624dq_st_t val)
693 {
694 ais3624dq_ctrl_reg4_t ctrl_reg4;
695 int32_t ret;
696
697 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
698 (uint8_t *)&ctrl_reg4, 1);
699
700 if (ret == 0)
701 {
702 ctrl_reg4.st = (uint8_t)val;
703 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG4,
704 (uint8_t *)&ctrl_reg4, 1);
705 }
706
707 return ret;
708 }
709
710 /**
711 * @brief Linear acceleration sensor self-test enable.[get]
712 *
713 * @param ctx read / write interface definitions(ptr)
714 * @param val Get the values of st in reg CTRL_REG4
715 * @retval interface status (MANDATORY: return 0 -> no Error)
716 *
717 */
ais3624dq_self_test_get(const stmdev_ctx_t * ctx,ais3624dq_st_t * val)718 int32_t ais3624dq_self_test_get(const stmdev_ctx_t *ctx,
719 ais3624dq_st_t *val)
720 {
721 ais3624dq_ctrl_reg4_t ctrl_reg4;
722 int32_t ret;
723
724 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
725 (uint8_t *)&ctrl_reg4, 1);
726
727 switch (ctrl_reg4.st)
728 {
729 case AIS3624DQ_ST_DISABLE:
730 *val = AIS3624DQ_ST_DISABLE;
731 break;
732
733 case AIS3624DQ_ST_POSITIVE:
734 *val = AIS3624DQ_ST_POSITIVE;
735 break;
736
737 case AIS3624DQ_ST_NEGATIVE:
738 *val = AIS3624DQ_ST_NEGATIVE;
739 break;
740
741 default:
742 *val = AIS3624DQ_ST_DISABLE;
743 break;
744 }
745
746 return ret;
747 }
748
749 /**
750 * @brief Big/Little Endian Data selection.[set]
751 *
752 * @param ctx read / write interface definitions(ptr)
753 * @param val change the values of ble in reg CTRL_REG4
754 * @retval interface status (MANDATORY: return 0 -> no Error)
755 *
756 */
ais3624dq_data_format_set(const stmdev_ctx_t * ctx,ais3624dq_ble_t val)757 int32_t ais3624dq_data_format_set(const stmdev_ctx_t *ctx,
758 ais3624dq_ble_t val)
759 {
760 ais3624dq_ctrl_reg4_t ctrl_reg4;
761 int32_t ret;
762
763 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
764 (uint8_t *)&ctrl_reg4, 1);
765
766 if (ret == 0)
767 {
768 ctrl_reg4.ble = (uint8_t)val;
769 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG4,
770 (uint8_t *)&ctrl_reg4, 1);
771 }
772
773 return ret;
774 }
775
776 /**
777 * @brief Big/Little Endian Data selection.[get]
778 *
779 * @param ctx read / write interface definitions(ptr)
780 * @param val Get the values of ble in reg CTRL_REG4
781 * @retval interface status (MANDATORY: return 0 -> no Error)
782 *
783 */
ais3624dq_data_format_get(const stmdev_ctx_t * ctx,ais3624dq_ble_t * val)784 int32_t ais3624dq_data_format_get(const stmdev_ctx_t *ctx,
785 ais3624dq_ble_t *val)
786 {
787 ais3624dq_ctrl_reg4_t ctrl_reg4;
788 int32_t ret;
789
790 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
791 (uint8_t *)&ctrl_reg4, 1);
792
793 switch (ctrl_reg4.ble)
794 {
795 case AIS3624DQ_LSB_AT_LOW_ADD:
796 *val = AIS3624DQ_LSB_AT_LOW_ADD;
797 break;
798
799 case AIS3624DQ_MSB_AT_LOW_ADD:
800 *val = AIS3624DQ_MSB_AT_LOW_ADD;
801 break;
802
803 default:
804 *val = AIS3624DQ_LSB_AT_LOW_ADD;
805 break;
806 }
807
808 return ret;
809 }
810
811 /**
812 * @}
813 *
814 */
815
816 /**
817 * @defgroup AIS3624DQ_Filters
818 * @brief This section group all the functions concerning the
819 * filters configuration.
820 * @{
821 *
822 */
823
824 /**
825 * @brief High pass filter cut-off frequency configuration.[set]
826 *
827 * @param ctx read / write interface definitions(ptr)
828 * @param val change the values of hpcf in reg CTRL_REG2
829 * @retval interface status (MANDATORY: return 0 -> no Error)
830 *
831 */
ais3624dq_hp_bandwidth_set(const stmdev_ctx_t * ctx,ais3624dq_hpcf_t val)832 int32_t ais3624dq_hp_bandwidth_set(const stmdev_ctx_t *ctx,
833 ais3624dq_hpcf_t val)
834 {
835 ais3624dq_ctrl_reg2_t ctrl_reg2;
836 int32_t ret;
837
838 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
839 (uint8_t *)&ctrl_reg2, 1);
840
841 if (ret == 0)
842 {
843 ctrl_reg2.hpcf = (uint8_t)val;
844 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG2,
845 (uint8_t *)&ctrl_reg2, 1);
846 }
847
848 return ret;
849 }
850
851 /**
852 * @brief High pass filter cut-off frequency configuration.[get]
853 *
854 * @param ctx read / write interface definitions(ptr)
855 * @param val Get the values of hpcf in reg CTRL_REG2
856 * @retval interface status (MANDATORY: return 0 -> no Error)
857 *
858 */
ais3624dq_hp_bandwidth_get(const stmdev_ctx_t * ctx,ais3624dq_hpcf_t * val)859 int32_t ais3624dq_hp_bandwidth_get(const stmdev_ctx_t *ctx,
860 ais3624dq_hpcf_t *val)
861 {
862 ais3624dq_ctrl_reg2_t ctrl_reg2;
863 int32_t ret;
864
865 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
866 (uint8_t *)&ctrl_reg2, 1);
867
868 switch (ctrl_reg2.hpcf)
869 {
870 case AIS3624DQ_CUT_OFF_8Hz:
871 *val = AIS3624DQ_CUT_OFF_8Hz;
872 break;
873
874 case AIS3624DQ_CUT_OFF_16Hz:
875 *val = AIS3624DQ_CUT_OFF_16Hz;
876 break;
877
878 case AIS3624DQ_CUT_OFF_32Hz:
879 *val = AIS3624DQ_CUT_OFF_32Hz;
880 break;
881
882 case AIS3624DQ_CUT_OFF_64Hz:
883 *val = AIS3624DQ_CUT_OFF_64Hz;
884 break;
885
886 default:
887 *val = AIS3624DQ_CUT_OFF_8Hz;
888 break;
889 }
890
891 return ret;
892 }
893
894 /**
895 * @brief Select High Pass filter path.[set]
896 *
897 * @param ctx read / write interface definitions(ptr)
898 * @param val change the values of hpen in reg CTRL_REG2
899 * @retval interface status (MANDATORY: return 0 -> no Error)
900 *
901 */
ais3624dq_hp_path_set(const stmdev_ctx_t * ctx,ais3624dq_hpen_t val)902 int32_t ais3624dq_hp_path_set(const stmdev_ctx_t *ctx, ais3624dq_hpen_t val)
903 {
904 ais3624dq_ctrl_reg2_t ctrl_reg2;
905 int32_t ret;
906
907 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
908 (uint8_t *)&ctrl_reg2, 1);
909
910 if (ret == 0)
911 {
912 ctrl_reg2.hpen = (uint8_t)val & 0x03U;
913 ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
914 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG2,
915 (uint8_t *)&ctrl_reg2, 1);
916 }
917
918 return ret;
919 }
920
921 /**
922 * @brief Select High Pass filter path.[get]
923 *
924 * @param ctx read / write interface definitions(ptr)
925 * @param val Get the values of hpen in reg CTRL_REG2
926 * @retval interface status (MANDATORY: return 0 -> no Error)
927 *
928 */
ais3624dq_hp_path_get(const stmdev_ctx_t * ctx,ais3624dq_hpen_t * val)929 int32_t ais3624dq_hp_path_get(const stmdev_ctx_t *ctx,
930 ais3624dq_hpen_t *val)
931 {
932 ais3624dq_ctrl_reg2_t ctrl_reg2;
933 int32_t ret;
934
935 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG2,
936 (uint8_t *)&ctrl_reg2, 1);
937
938 switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
939 {
940 case AIS3624DQ_HP_DISABLE:
941 *val = AIS3624DQ_HP_DISABLE;
942 break;
943
944 case AIS3624DQ_HP_ON_OUT:
945 *val = AIS3624DQ_HP_ON_OUT;
946 break;
947
948 case AIS3624DQ_HP_ON_INT1:
949 *val = AIS3624DQ_HP_ON_INT1;
950 break;
951
952 case AIS3624DQ_HP_ON_INT2:
953 *val = AIS3624DQ_HP_ON_INT2;
954 break;
955
956 case AIS3624DQ_HP_ON_INT1_INT2:
957 *val = AIS3624DQ_HP_ON_INT1_INT2;
958 break;
959
960 case AIS3624DQ_HP_ON_INT1_INT2_OUT:
961 *val = AIS3624DQ_HP_ON_INT1_INT2_OUT;
962 break;
963
964 case AIS3624DQ_HP_ON_INT2_OUT:
965 *val = AIS3624DQ_HP_ON_INT2_OUT;
966 break;
967
968 case AIS3624DQ_HP_ON_INT1_OUT:
969 *val = AIS3624DQ_HP_ON_INT1_OUT;
970 break;
971
972 default:
973 *val = AIS3624DQ_HP_DISABLE;
974 break;
975 }
976
977 return ret;
978 }
979
980 /**
981 * @brief Reading at this address zeroes instantaneously
982 * the content of the internal high pass-filter.
983 * If the high pass filter is enabled all three axes
984 * are instantaneously set to 0g. This allows to
985 * overcome the settling time of the high pass
986 * filter.[get]
987 *
988 * @param ctx read / write interface definitions(ptr)
989 * @retval interface status (MANDATORY: return 0 -> no Error)
990 *
991 */
ais3624dq_hp_reset_get(const stmdev_ctx_t * ctx)992 int32_t ais3624dq_hp_reset_get(const stmdev_ctx_t *ctx)
993 {
994 uint8_t dummy;
995 int32_t ret;
996
997 ret = ais3624dq_read_reg(ctx, AIS3624DQ_HP_FILTER_RESET,
998 (uint8_t *)&dummy, 1);
999
1000 return ret;
1001 }
1002
1003 /**
1004 * @brief Reference value for high-pass filter.[set]
1005 *
1006 * @param ctx read / write interface definitions(ptr)
1007 * @param val change the values of ref in reg REFERENCE
1008 * @retval interface status (MANDATORY: return 0 -> no Error)
1009 *
1010 */
ais3624dq_hp_reference_value_set(const stmdev_ctx_t * ctx,uint8_t val)1011 int32_t ais3624dq_hp_reference_value_set(const stmdev_ctx_t *ctx,
1012 uint8_t val)
1013 {
1014 int32_t ret;
1015
1016 ret = ais3624dq_write_reg(ctx, AIS3624DQ_REFERENCE, (uint8_t *)&val, 1);
1017
1018 return ret;
1019 }
1020
1021 /**
1022 * @brief Reference value for high-pass filter.[get]
1023 *
1024 * @param ctx read / write interface definitions(ptr)
1025 * @param val change the values of ref in reg REFERENCE
1026 * @retval interface status (MANDATORY: return 0 -> no Error)
1027 *
1028 */
ais3624dq_hp_reference_value_get(const stmdev_ctx_t * ctx,uint8_t * val)1029 int32_t ais3624dq_hp_reference_value_get(const stmdev_ctx_t *ctx,
1030 uint8_t *val)
1031 {
1032 int32_t ret;
1033
1034 ret = ais3624dq_read_reg(ctx, AIS3624DQ_REFERENCE, val, 1);
1035
1036 return ret;
1037 }
1038
1039 /**
1040 * @}
1041 *
1042 */
1043
1044 /**
1045 * @defgroup AIS3624DQ_Serial_Interface
1046 * @brief This section groups all the functions concerning serial
1047 * interface management.
1048 * @{
1049 *
1050 */
1051
1052 /**
1053 * @brief SPI 3- or 4-wire interface.[set]
1054 *
1055 * @param ctx read / write interface definitions(ptr)
1056 * @param val change the values of sim in reg CTRL_REG4
1057 * @retval interface status (MANDATORY: return 0 -> no Error)
1058 *
1059 */
ais3624dq_spi_mode_set(const stmdev_ctx_t * ctx,ais3624dq_sim_t val)1060 int32_t ais3624dq_spi_mode_set(const stmdev_ctx_t *ctx, ais3624dq_sim_t val)
1061 {
1062 ais3624dq_ctrl_reg4_t ctrl_reg4;
1063 int32_t ret;
1064
1065 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
1066 (uint8_t *)&ctrl_reg4, 1);
1067
1068 if (ret == 0)
1069 {
1070 ctrl_reg4.sim = (uint8_t)val;
1071 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG4,
1072 (uint8_t *)&ctrl_reg4, 1);
1073 }
1074
1075 return ret;
1076 }
1077
1078 /**
1079 * @brief SPI 3- or 4-wire interface.[get]
1080 *
1081 * @param ctx read / write interface definitions(ptr)
1082 * @param val Get the values of sim in reg CTRL_REG4
1083 * @retval interface status (MANDATORY: return 0 -> no Error)
1084 *
1085 */
ais3624dq_spi_mode_get(const stmdev_ctx_t * ctx,ais3624dq_sim_t * val)1086 int32_t ais3624dq_spi_mode_get(const stmdev_ctx_t *ctx,
1087 ais3624dq_sim_t *val)
1088 {
1089 ais3624dq_ctrl_reg4_t ctrl_reg4;
1090 int32_t ret;
1091
1092 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG4,
1093 (uint8_t *)&ctrl_reg4, 1);
1094
1095 switch (ctrl_reg4.sim)
1096 {
1097 case AIS3624DQ_SPI_4_WIRE:
1098 *val = AIS3624DQ_SPI_4_WIRE;
1099 break;
1100
1101 case AIS3624DQ_SPI_3_WIRE:
1102 *val = AIS3624DQ_SPI_3_WIRE;
1103 break;
1104
1105 default:
1106 *val = AIS3624DQ_SPI_4_WIRE;
1107 break;
1108 }
1109
1110 return ret;
1111 }
1112
1113 /**
1114 * @}
1115 *
1116 */
1117
1118 /**
1119 * @defgroup AIS3624DQ_Interrupt_Pins
1120 * @brief This section groups all the functions that manage
1121 * interrupt pins.
1122 * @{
1123 *
1124 */
1125
1126 /**
1127 * @brief Data signal on INT 1 pad control bits.[set]
1128 *
1129 * @param ctx read / write interface definitions(ptr)
1130 * @param val change the values of i1_cfg in reg CTRL_REG3
1131 * @retval interface status (MANDATORY: return 0 -> no Error)
1132 *
1133 */
ais3624dq_pin_int1_route_set(const stmdev_ctx_t * ctx,ais3624dq_i1_cfg_t val)1134 int32_t ais3624dq_pin_int1_route_set(const stmdev_ctx_t *ctx,
1135 ais3624dq_i1_cfg_t val)
1136 {
1137 ais3624dq_ctrl_reg3_t ctrl_reg3;
1138 int32_t ret;
1139
1140 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1141 (uint8_t *)&ctrl_reg3, 1);
1142
1143 if (ret == 0)
1144 {
1145 ctrl_reg3.i1_cfg = (uint8_t)val;
1146 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
1147 (uint8_t *)&ctrl_reg3, 1);
1148 }
1149
1150 return ret;
1151 }
1152
1153 /**
1154 * @brief Data signal on INT 1 pad control bits.[get]
1155 *
1156 * @param ctx read / write interface definitions(ptr)
1157 * @param val Get the values of i1_cfg in reg CTRL_REG3
1158 * @retval interface status (MANDATORY: return 0 -> no Error)
1159 *
1160 */
ais3624dq_pin_int1_route_get(const stmdev_ctx_t * ctx,ais3624dq_i1_cfg_t * val)1161 int32_t ais3624dq_pin_int1_route_get(const stmdev_ctx_t *ctx,
1162 ais3624dq_i1_cfg_t *val)
1163 {
1164 ais3624dq_ctrl_reg3_t ctrl_reg3;
1165 int32_t ret;
1166
1167 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1168 (uint8_t *)&ctrl_reg3, 1);
1169
1170 switch (ctrl_reg3.i1_cfg)
1171 {
1172 case AIS3624DQ_PAD1_INT1_SRC:
1173 *val = AIS3624DQ_PAD1_INT1_SRC;
1174 break;
1175
1176 case AIS3624DQ_PAD1_INT1_OR_INT2_SRC:
1177 *val = AIS3624DQ_PAD1_INT1_OR_INT2_SRC;
1178 break;
1179
1180 case AIS3624DQ_PAD1_DRDY:
1181 *val = AIS3624DQ_PAD1_DRDY;
1182 break;
1183
1184 case AIS3624DQ_PAD1_BOOT:
1185 *val = AIS3624DQ_PAD1_BOOT;
1186 break;
1187
1188 default:
1189 *val = AIS3624DQ_PAD1_INT1_SRC;
1190 break;
1191 }
1192
1193 return ret;
1194 }
1195
1196 /**
1197 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1198 * register cleared by reading INT1_SRC register.[set]
1199 *
1200 * @param ctx read / write interface definitions(ptr)
1201 * @param val change the values of lir1 in reg CTRL_REG3
1202 * @retval interface status (MANDATORY: return 0 -> no Error)
1203 *
1204 */
ais3624dq_int1_notification_set(const stmdev_ctx_t * ctx,ais3624dq_lir1_t val)1205 int32_t ais3624dq_int1_notification_set(const stmdev_ctx_t *ctx,
1206 ais3624dq_lir1_t val)
1207 {
1208 ais3624dq_ctrl_reg3_t ctrl_reg3;
1209 int32_t ret;
1210
1211 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1212 (uint8_t *)&ctrl_reg3, 1);
1213
1214 if (ret == 0)
1215 {
1216 ctrl_reg3.lir1 = (uint8_t)val;
1217 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
1218 (uint8_t *)&ctrl_reg3, 1);
1219 }
1220
1221 return ret;
1222 }
1223
1224 /**
1225 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1226 * register cleared by reading INT1_SRC register.[get]
1227 *
1228 * @param ctx read / write interface definitions(ptr)
1229 * @param val Get the values of lir1 in reg CTRL_REG3
1230 * @retval interface status (MANDATORY: return 0 -> no Error)
1231 *
1232 */
ais3624dq_int1_notification_get(const stmdev_ctx_t * ctx,ais3624dq_lir1_t * val)1233 int32_t ais3624dq_int1_notification_get(const stmdev_ctx_t *ctx,
1234 ais3624dq_lir1_t *val)
1235 {
1236 ais3624dq_ctrl_reg3_t ctrl_reg3;
1237 int32_t ret;
1238
1239 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1240 (uint8_t *)&ctrl_reg3, 1);
1241
1242 switch (ctrl_reg3.lir1)
1243 {
1244 case AIS3624DQ_INT1_PULSED:
1245 *val = AIS3624DQ_INT1_PULSED;
1246 break;
1247
1248 case AIS3624DQ_INT1_LATCHED:
1249 *val = AIS3624DQ_INT1_LATCHED;
1250 break;
1251
1252 default:
1253 *val = AIS3624DQ_INT1_PULSED;
1254 break;
1255 }
1256
1257 return ret;
1258 }
1259
1260 /**
1261 * @brief Data signal on INT 2 pad control bits.[set]
1262 *
1263 * @param ctx read / write interface definitions(ptr)
1264 * @param val change the values of i2_cfg in reg CTRL_REG3
1265 * @retval interface status (MANDATORY: return 0 -> no Error)
1266 *
1267 */
ais3624dq_pin_int2_route_set(const stmdev_ctx_t * ctx,ais3624dq_i2_cfg_t val)1268 int32_t ais3624dq_pin_int2_route_set(const stmdev_ctx_t *ctx,
1269 ais3624dq_i2_cfg_t val)
1270 {
1271 ais3624dq_ctrl_reg3_t ctrl_reg3;
1272 int32_t ret;
1273
1274 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1275 (uint8_t *)&ctrl_reg3, 1);
1276
1277 if (ret == 0)
1278 {
1279 ctrl_reg3.i2_cfg = (uint8_t)val;
1280 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
1281 (uint8_t *)&ctrl_reg3, 1);
1282 }
1283
1284 return ret;
1285 }
1286
1287 /**
1288 * @brief Data signal on INT 2 pad control bits.[get]
1289 *
1290 * @param ctx read / write interface definitions(ptr)
1291 * @param val Get the values of i2_cfg in reg CTRL_REG3
1292 * @retval interface status (MANDATORY: return 0 -> no Error)
1293 *
1294 */
ais3624dq_pin_int2_route_get(const stmdev_ctx_t * ctx,ais3624dq_i2_cfg_t * val)1295 int32_t ais3624dq_pin_int2_route_get(const stmdev_ctx_t *ctx,
1296 ais3624dq_i2_cfg_t *val)
1297 {
1298 ais3624dq_ctrl_reg3_t ctrl_reg3;
1299 int32_t ret;
1300
1301 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1302 (uint8_t *)&ctrl_reg3, 1);
1303
1304 switch (ctrl_reg3.i2_cfg)
1305 {
1306 case AIS3624DQ_PAD2_INT2_SRC:
1307 *val = AIS3624DQ_PAD2_INT2_SRC;
1308 break;
1309
1310 case AIS3624DQ_PAD2_INT1_OR_INT2_SRC:
1311 *val = AIS3624DQ_PAD2_INT1_OR_INT2_SRC;
1312 break;
1313
1314 case AIS3624DQ_PAD2_DRDY:
1315 *val = AIS3624DQ_PAD2_DRDY;
1316 break;
1317
1318 case AIS3624DQ_PAD2_BOOT:
1319 *val = AIS3624DQ_PAD2_BOOT;
1320 break;
1321
1322 default:
1323 *val = AIS3624DQ_PAD2_INT2_SRC;
1324 break;
1325 }
1326
1327 return ret;
1328 }
1329
1330 /**
1331 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1332 * register cleared by reading INT2_SRC itself.[set]
1333 *
1334 * @param ctx read / write interface definitions(ptr)
1335 * @param val change the values of lir2 in reg CTRL_REG3
1336 * @retval interface status (MANDATORY: return 0 -> no Error)
1337 *
1338 */
ais3624dq_int2_notification_set(const stmdev_ctx_t * ctx,ais3624dq_lir2_t val)1339 int32_t ais3624dq_int2_notification_set(const stmdev_ctx_t *ctx,
1340 ais3624dq_lir2_t val)
1341 {
1342 ais3624dq_ctrl_reg3_t ctrl_reg3;
1343 int32_t ret;
1344
1345 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1346 (uint8_t *)&ctrl_reg3, 1);
1347
1348 if (ret == 0)
1349 {
1350 ctrl_reg3.lir2 = (uint8_t)val;
1351 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
1352 (uint8_t *)&ctrl_reg3, 1);
1353 }
1354
1355 return ret;
1356 }
1357
1358 /**
1359 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1360 * register cleared by reading INT2_SRC itself.[get]
1361 *
1362 * @param ctx read / write interface definitions(ptr)
1363 * @param val Get the values of lir2 in reg CTRL_REG3
1364 * @retval interface status (MANDATORY: return 0 -> no Error)
1365 *
1366 */
ais3624dq_int2_notification_get(const stmdev_ctx_t * ctx,ais3624dq_lir2_t * val)1367 int32_t ais3624dq_int2_notification_get(const stmdev_ctx_t *ctx,
1368 ais3624dq_lir2_t *val)
1369 {
1370 ais3624dq_ctrl_reg3_t ctrl_reg3;
1371 int32_t ret;
1372
1373 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1374 (uint8_t *)&ctrl_reg3, 1);
1375
1376 switch (ctrl_reg3.lir2)
1377 {
1378 case AIS3624DQ_INT2_PULSED:
1379 *val = AIS3624DQ_INT2_PULSED;
1380 break;
1381
1382 case AIS3624DQ_INT2_LATCHED:
1383 *val = AIS3624DQ_INT2_LATCHED;
1384 break;
1385
1386 default:
1387 *val = AIS3624DQ_INT2_PULSED;
1388 break;
1389 }
1390
1391 return ret;
1392 }
1393
1394 /**
1395 * @brief Push-pull/open drain selection on interrupt pads.[set]
1396 *
1397 * @param ctx read / write interface definitions(ptr)
1398 * @param val change the values of pp_od in reg CTRL_REG3
1399 * @retval interface status (MANDATORY: return 0 -> no Error)
1400 *
1401 */
ais3624dq_pin_mode_set(const stmdev_ctx_t * ctx,ais3624dq_pp_od_t val)1402 int32_t ais3624dq_pin_mode_set(const stmdev_ctx_t *ctx,
1403 ais3624dq_pp_od_t val)
1404 {
1405 ais3624dq_ctrl_reg3_t ctrl_reg3;
1406 int32_t ret;
1407
1408 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1409 (uint8_t *)&ctrl_reg3, 1);
1410
1411 if (ret == 0)
1412 {
1413 ctrl_reg3.pp_od = (uint8_t)val;
1414 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
1415 (uint8_t *)&ctrl_reg3, 1);
1416 }
1417
1418 return ret;
1419 }
1420
1421 /**
1422 * @brief Push-pull/open drain selection on interrupt pads.[get]
1423 *
1424 * @param ctx read / write interface definitions(ptr)
1425 * @param val Get the values of pp_od in reg CTRL_REG3
1426 * @retval interface status (MANDATORY: return 0 -> no Error)
1427 *
1428 */
ais3624dq_pin_mode_get(const stmdev_ctx_t * ctx,ais3624dq_pp_od_t * val)1429 int32_t ais3624dq_pin_mode_get(const stmdev_ctx_t *ctx,
1430 ais3624dq_pp_od_t *val)
1431 {
1432 ais3624dq_ctrl_reg3_t ctrl_reg3;
1433 int32_t ret;
1434
1435 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1436 (uint8_t *)&ctrl_reg3, 1);
1437
1438 switch (ctrl_reg3.pp_od)
1439 {
1440 case AIS3624DQ_PUSH_PULL:
1441 *val = AIS3624DQ_PUSH_PULL;
1442 break;
1443
1444 case AIS3624DQ_OPEN_DRAIN:
1445 *val = AIS3624DQ_OPEN_DRAIN;
1446 break;
1447
1448 default:
1449 *val = AIS3624DQ_PUSH_PULL;
1450 break;
1451 }
1452
1453 return ret;
1454 }
1455
1456 /**
1457 * @brief Interrupt active-high/low.[set]
1458 *
1459 * @param ctx read / write interface definitions(ptr)
1460 * @param val change the values of ihl in reg CTRL_REG3
1461 * @retval interface status (MANDATORY: return 0 -> no Error)
1462 *
1463 */
ais3624dq_pin_polarity_set(const stmdev_ctx_t * ctx,ais3624dq_ihl_t val)1464 int32_t ais3624dq_pin_polarity_set(const stmdev_ctx_t *ctx,
1465 ais3624dq_ihl_t val)
1466 {
1467 ais3624dq_ctrl_reg3_t ctrl_reg3;
1468 int32_t ret;
1469
1470 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1471 (uint8_t *)&ctrl_reg3, 1);
1472
1473 if (ret == 0)
1474 {
1475 ctrl_reg3.ihl = (uint8_t)val;
1476 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG3,
1477 (uint8_t *)&ctrl_reg3, 1);
1478 }
1479
1480 return ret;
1481 }
1482
1483 /**
1484 * @brief Interrupt active-high/low.[get]
1485 *
1486 * @param ctx read / write interface definitions(ptr)
1487 * @param val Get the values of ihl in reg CTRL_REG3
1488 * @retval interface status (MANDATORY: return 0 -> no Error)
1489 *
1490 */
ais3624dq_pin_polarity_get(const stmdev_ctx_t * ctx,ais3624dq_ihl_t * val)1491 int32_t ais3624dq_pin_polarity_get(const stmdev_ctx_t *ctx,
1492 ais3624dq_ihl_t *val)
1493 {
1494 ais3624dq_ctrl_reg3_t ctrl_reg3;
1495 int32_t ret;
1496
1497 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG3,
1498 (uint8_t *)&ctrl_reg3, 1);
1499
1500 switch (ctrl_reg3.ihl)
1501 {
1502 case AIS3624DQ_ACTIVE_HIGH:
1503 *val = AIS3624DQ_ACTIVE_HIGH;
1504 break;
1505
1506 case AIS3624DQ_ACTIVE_LOW:
1507 *val = AIS3624DQ_ACTIVE_LOW;
1508 break;
1509
1510 default:
1511 *val = AIS3624DQ_ACTIVE_HIGH;
1512 break;
1513 }
1514
1515 return ret;
1516 }
1517
1518 /**
1519 * @}
1520 *
1521 */
1522
1523 /**
1524 * @defgroup AIS3624DQ_interrupt_on_threshold
1525 * @brief This section groups all the functions that manage
1526 * the interrupt on threshold event generation.
1527 * @{
1528 *
1529 */
1530
1531 /**
1532 * @brief Configure the interrupt 1 threshold sign.[set]
1533 *
1534 * @param ctx read / write interface definitions(ptr)
1535 * @param val enable sign and axis for interrupt on threshold
1536 * @retval interface status (MANDATORY: return 0 -> no Error)
1537 *
1538 */
ais3624dq_int1_on_threshold_conf_set(const stmdev_ctx_t * ctx,ais3624dq_int1_on_th_conf_t val)1539 int32_t ais3624dq_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1540 ais3624dq_int1_on_th_conf_t val)
1541 {
1542 ais3624dq_int1_cfg_t int1_cfg;
1543 int32_t ret;
1544
1545 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
1546 (uint8_t *)&int1_cfg, 1);
1547
1548 if (ret == 0)
1549 {
1550 int1_cfg.xlie = val.int1_xlie;
1551 int1_cfg.xhie = val.int1_xhie;
1552 int1_cfg.ylie = val.int1_ylie;
1553 int1_cfg.yhie = val.int1_yhie;
1554 int1_cfg.zlie = val.int1_zlie;
1555 int1_cfg.zhie = val.int1_zhie;
1556 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_CFG,
1557 (uint8_t *)&int1_cfg, 1);
1558 }
1559
1560 return ret;
1561 }
1562
1563 /**
1564 * @brief Configure the interrupt 1 threshold sign.[get]
1565 *
1566 * @param ctx read / write interface definitions(ptr)
1567 * @param val enable sign and axis for interrupt on threshold
1568 * @retval interface status (MANDATORY: return 0 -> no Error)
1569 *
1570 */
ais3624dq_int1_on_threshold_conf_get(const stmdev_ctx_t * ctx,ais3624dq_int1_on_th_conf_t * val)1571 int32_t ais3624dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1572 ais3624dq_int1_on_th_conf_t *val)
1573 {
1574 ais3624dq_int1_cfg_t int1_cfg;
1575 int32_t ret;
1576
1577 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
1578 (uint8_t *)&int1_cfg, 1);
1579 val->int1_xlie = int1_cfg.xlie;
1580 val->int1_xhie = int1_cfg.xhie;
1581 val->int1_ylie = int1_cfg.ylie;
1582 val->int1_yhie = int1_cfg.yhie;
1583 val->int1_zlie = int1_cfg.zlie;
1584 val->int1_zhie = int1_cfg.zhie;
1585
1586 return ret;
1587 }
1588
1589 /**
1590 * @brief AND/OR combination of Interrupt 1 events.[set]
1591 *
1592 * @param ctx read / write interface definitions(ptr)
1593 * @param val change the values of aoi in reg INT1_CFG
1594 * @retval interface status (MANDATORY: return 0 -> no Error)
1595 *
1596 */
ais3624dq_int1_on_threshold_mode_set(const stmdev_ctx_t * ctx,ais3624dq_int1_aoi_t val)1597 int32_t ais3624dq_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1598 ais3624dq_int1_aoi_t val)
1599 {
1600 ais3624dq_int1_cfg_t int1_cfg;
1601 int32_t ret;
1602
1603 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
1604 (uint8_t *)&int1_cfg, 1);
1605
1606 if (ret == 0)
1607 {
1608 int1_cfg.aoi = (uint8_t) val;
1609 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_CFG,
1610 (uint8_t *)&int1_cfg, 1);
1611 }
1612
1613 return ret;
1614 }
1615
1616 /**
1617 * @brief AND/OR combination of Interrupt 1 events.[get]
1618 *
1619 * @param ctx read / write interface definitions(ptr)
1620 * @param val Get the values of aoi in reg INT1_CFG
1621 * @retval interface status (MANDATORY: return 0 -> no Error)
1622 *
1623 */
ais3624dq_int1_on_threshold_mode_get(const stmdev_ctx_t * ctx,ais3624dq_int1_aoi_t * val)1624 int32_t ais3624dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1625 ais3624dq_int1_aoi_t *val)
1626 {
1627 ais3624dq_int1_cfg_t int1_cfg;
1628 int32_t ret;
1629
1630 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
1631 (uint8_t *)&int1_cfg, 1);
1632
1633 switch (int1_cfg.aoi)
1634 {
1635 case AIS3624DQ_INT1_ON_THRESHOLD_OR:
1636 *val = AIS3624DQ_INT1_ON_THRESHOLD_OR;
1637 break;
1638
1639 case AIS3624DQ_INT1_ON_THRESHOLD_AND:
1640 *val = AIS3624DQ_INT1_ON_THRESHOLD_AND;
1641 break;
1642
1643 default:
1644 *val = AIS3624DQ_INT1_ON_THRESHOLD_OR;
1645 break;
1646 }
1647
1648 return ret;
1649 }
1650
1651 /**
1652 * @brief Interrupt generator 1 on threshold source register.[get]
1653 *
1654 * @param ctx read / write interface definitions(ptr)
1655 * @param val registers INT1_SRC
1656 * @retval interface status (MANDATORY: return 0 -> no Error)
1657 *
1658 */
ais3624dq_int1_src_get(const stmdev_ctx_t * ctx,ais3624dq_int1_src_t * val)1659 int32_t ais3624dq_int1_src_get(const stmdev_ctx_t *ctx,
1660 ais3624dq_int1_src_t *val)
1661 {
1662 int32_t ret;
1663
1664 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_SRC, (uint8_t *) val, 1);
1665
1666 return ret;
1667 }
1668
1669 /**
1670 * @brief Interrupt 1 threshold.[set]
1671 *
1672 * @param ctx read / write interface definitions(ptr)
1673 * @param val change the values of ths in reg INT1_THS
1674 * @retval interface status (MANDATORY: return 0 -> no Error)
1675 *
1676 */
ais3624dq_int1_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1677 int32_t ais3624dq_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1678 {
1679 ais3624dq_int1_ths_t int1_ths;
1680 int32_t ret;
1681
1682 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS,
1683 (uint8_t *)&int1_ths, 1);
1684
1685 if (ret == 0)
1686 {
1687 int1_ths.ths = val;
1688 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_THS,
1689 (uint8_t *)&int1_ths, 1);
1690 }
1691
1692 return ret;
1693 }
1694
1695 /**
1696 * @brief Interrupt 1 threshold.[get]
1697 *
1698 * @param ctx read / write interface definitions(ptr)
1699 * @param val change the values of ths in reg INT1_THS
1700 * @retval interface status (MANDATORY: return 0 -> no Error)
1701 *
1702 */
ais3624dq_int1_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1703 int32_t ais3624dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1704 {
1705 ais3624dq_int1_ths_t int1_ths;
1706 int32_t ret;
1707
1708 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS,
1709 (uint8_t *)&int1_ths, 1);
1710 *val = int1_ths.ths;
1711
1712 return ret;
1713 }
1714
1715 /**
1716 * @brief Duration value for interrupt 1 generator.[set]
1717 *
1718 * @param ctx read / write interface definitions(ptr)
1719 * @param val change the values of d in reg INT1_DURATION
1720 * @retval interface status (MANDATORY: return 0 -> no Error)
1721 *
1722 */
ais3624dq_int1_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1723 int32_t ais3624dq_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1724 {
1725 ais3624dq_int1_duration_t int1_duration;
1726 int32_t ret;
1727
1728 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_DURATION,
1729 (uint8_t *)&int1_duration, 1);
1730
1731 if (ret == 0)
1732 {
1733 int1_duration.d = val;
1734 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_DURATION,
1735 (uint8_t *)&int1_duration, 1);
1736 }
1737
1738 return ret;
1739 }
1740
1741 /**
1742 * @brief Duration value for interrupt 1 generator.[get]
1743 *
1744 * @param ctx read / write interface definitions(ptr)
1745 * @param val change the values of d in reg INT1_DURATION
1746 * @retval interface status (MANDATORY: return 0 -> no Error)
1747 *
1748 */
ais3624dq_int1_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1749 int32_t ais3624dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1750 {
1751 ais3624dq_int1_duration_t int1_duration;
1752 int32_t ret;
1753
1754 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_DURATION,
1755 (uint8_t *)&int1_duration, 1);
1756 *val = int1_duration.d;
1757
1758 return ret;
1759 }
1760
1761 /**
1762 * @brief Configure the interrupt 2 threshold sign.[set]
1763 *
1764 * @param ctx read / write interface definitions(ptr)
1765 * @param val enable sign and axis for interrupt on threshold
1766 * @retval interface status (MANDATORY: return 0 -> no Error)
1767 *
1768 */
ais3624dq_int2_on_threshold_conf_set(const stmdev_ctx_t * ctx,ais3624dq_int2_on_th_conf_t val)1769 int32_t ais3624dq_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1770 ais3624dq_int2_on_th_conf_t val)
1771 {
1772 ais3624dq_int2_cfg_t int2_cfg;
1773 int32_t ret;
1774
1775 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
1776 (uint8_t *)&int2_cfg, 1);
1777
1778 if (ret == 0)
1779 {
1780 int2_cfg.xlie = val.int2_xlie;
1781 int2_cfg.xhie = val.int2_xhie;
1782 int2_cfg.ylie = val.int2_ylie;
1783 int2_cfg.yhie = val.int2_yhie;
1784 int2_cfg.zlie = val.int2_zlie;
1785 int2_cfg.zhie = val.int2_zhie;
1786 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_CFG,
1787 (uint8_t *)&int2_cfg, 1);
1788 }
1789
1790 return ret;
1791 }
1792
1793 /**
1794 * @brief Configure the interrupt 2 threshold sign.[get]
1795 *
1796 * @param ctx read / write interface definitions(ptr)
1797 * @param val enable sign and axis for interrupt on threshold
1798 * @retval interface status (MANDATORY: return 0 -> no Error)
1799 *
1800 */
ais3624dq_int2_on_threshold_conf_get(const stmdev_ctx_t * ctx,ais3624dq_int2_on_th_conf_t * val)1801 int32_t ais3624dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1802 ais3624dq_int2_on_th_conf_t *val)
1803 {
1804 ais3624dq_int2_cfg_t int2_cfg;
1805 int32_t ret;
1806
1807 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
1808 (uint8_t *)&int2_cfg, 1);
1809 val->int2_xlie = int2_cfg.xlie;
1810 val->int2_xhie = int2_cfg.xhie;
1811 val->int2_ylie = int2_cfg.ylie;
1812 val->int2_yhie = int2_cfg.yhie;
1813 val->int2_zlie = int2_cfg.zlie;
1814 val->int2_zhie = int2_cfg.zhie;
1815
1816 return ret;
1817 }
1818
1819 /**
1820 * @brief AND/OR combination of Interrupt 2 events.[set]
1821 *
1822 * @param ctx read / write interface definitions(ptr)
1823 * @param val change the values of aoi in reg INT2_CFG
1824 * @retval interface status (MANDATORY: return 0 -> no Error)
1825 *
1826 */
ais3624dq_int2_on_threshold_mode_set(const stmdev_ctx_t * ctx,ais3624dq_int2_aoi_t val)1827 int32_t ais3624dq_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1828 ais3624dq_int2_aoi_t val)
1829 {
1830 ais3624dq_int2_cfg_t int2_cfg;
1831 int32_t ret;
1832
1833 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
1834 (uint8_t *)&int2_cfg, 1);
1835
1836 if (ret == 0)
1837 {
1838 int2_cfg.aoi = (uint8_t) val;
1839 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_CFG,
1840 (uint8_t *)&int2_cfg, 1);
1841 }
1842
1843 return ret;
1844 }
1845
1846 /**
1847 * @brief AND/OR combination of Interrupt 2 events.[get]
1848 *
1849 * @param ctx read / write interface definitions(ptr)
1850 * @param val Get the values of aoi in reg INT2_CFG
1851 * @retval interface status (MANDATORY: return 0 -> no Error)
1852 *
1853 */
ais3624dq_int2_on_threshold_mode_get(const stmdev_ctx_t * ctx,ais3624dq_int2_aoi_t * val)1854 int32_t ais3624dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1855 ais3624dq_int2_aoi_t *val)
1856 {
1857 ais3624dq_int2_cfg_t int2_cfg;
1858 int32_t ret;
1859
1860 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
1861 (uint8_t *)&int2_cfg, 1);
1862
1863 switch (int2_cfg.aoi)
1864 {
1865 case AIS3624DQ_INT2_ON_THRESHOLD_OR:
1866 *val = AIS3624DQ_INT2_ON_THRESHOLD_OR;
1867 break;
1868
1869 case AIS3624DQ_INT2_ON_THRESHOLD_AND:
1870 *val = AIS3624DQ_INT2_ON_THRESHOLD_AND;
1871 break;
1872
1873 default:
1874 *val = AIS3624DQ_INT2_ON_THRESHOLD_OR;
1875 break;
1876 }
1877
1878 return ret;
1879 }
1880
1881 /**
1882 * @brief Interrupt generator 1 on threshold source register.[get]
1883 *
1884 * @param ctx read / write interface definitions(ptr)
1885 * @param val registers INT2_SRC
1886 * @retval interface status (MANDATORY: return 0 -> no Error)
1887 *
1888 */
ais3624dq_int2_src_get(const stmdev_ctx_t * ctx,ais3624dq_int2_src_t * val)1889 int32_t ais3624dq_int2_src_get(const stmdev_ctx_t *ctx,
1890 ais3624dq_int2_src_t *val)
1891 {
1892 int32_t ret;
1893
1894 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_SRC, (uint8_t *) val, 1);
1895
1896 return ret;
1897 }
1898
1899 /**
1900 * @brief Interrupt 2 threshold.[set]
1901 *
1902 * @param ctx read / write interface definitions(ptr)
1903 * @param val change the values of ths in reg INT2_THS
1904 * @retval interface status (MANDATORY: return 0 -> no Error)
1905 *
1906 */
ais3624dq_int2_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1907 int32_t ais3624dq_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1908 {
1909 ais3624dq_int2_ths_t int2_ths;
1910 int32_t ret;
1911
1912 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS,
1913 (uint8_t *)&int2_ths, 1);
1914
1915 if (ret == 0)
1916 {
1917 int2_ths.ths = val;
1918 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_THS,
1919 (uint8_t *)&int2_ths, 1);
1920 }
1921
1922 return ret;
1923 }
1924
1925 /**
1926 * @brief Interrupt 2 threshold.[get]
1927 *
1928 * @param ctx read / write interface definitions(ptr)
1929 * @param val change the values of ths in reg INT2_THS
1930 * @retval interface status (MANDATORY: return 0 -> no Error)
1931 *
1932 */
ais3624dq_int2_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1933 int32_t ais3624dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1934 {
1935 ais3624dq_int2_ths_t int2_ths;
1936 int32_t ret;
1937
1938 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS,
1939 (uint8_t *)&int2_ths, 1);
1940 *val = int2_ths.ths;
1941
1942 return ret;
1943 }
1944
1945 /**
1946 * @brief Duration value for interrupt 2 generator.[set]
1947 *
1948 * @param ctx read / write interface definitions(ptr)
1949 * @param val change the values of d in reg INT2_DURATION
1950 * @retval interface status (MANDATORY: return 0 -> no Error)
1951 *
1952 */
ais3624dq_int2_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1953 int32_t ais3624dq_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1954 {
1955 ais3624dq_int2_duration_t int2_duration;
1956 int32_t ret;
1957
1958 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_DURATION,
1959 (uint8_t *)&int2_duration, 1);
1960
1961 if (ret == 0)
1962 {
1963 int2_duration.d = val;
1964 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_DURATION,
1965 (uint8_t *)&int2_duration, 1);
1966 }
1967
1968 return ret;
1969 }
1970
1971 /**
1972 * @brief Duration value for interrupt 2 generator.[get]
1973 *
1974 * @param ctx read / write interface definitions(ptr)
1975 * @param val change the values of d in reg INT2_DURATION
1976 * @retval interface status (MANDATORY: return 0 -> no Error)
1977 *
1978 */
ais3624dq_int2_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1979 int32_t ais3624dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1980 {
1981 ais3624dq_int2_duration_t int2_duration;
1982 int32_t ret;
1983
1984 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_DURATION,
1985 (uint8_t *)&int2_duration, 1);
1986 *val = int2_duration.d;
1987
1988 return ret;
1989 }
1990
1991 /**
1992 * @}
1993 *
1994 */
1995
1996 /**
1997 * @defgroup AIS3624DQ_Wake_Up_Event
1998 * @brief This section groups all the functions that manage the
1999 * Wake Up event generation.
2000 * @{
2001 *
2002 */
2003
2004 /**
2005 * @brief Turn-on mode selection for sleep to wake function.[set]
2006 *
2007 * @param ctx read / write interface definitions(ptr)
2008 * @param val change the values of turnon in reg CTRL_REG5
2009 * @retval interface status (MANDATORY: return 0 -> no Error)
2010 *
2011 */
ais3624dq_wkup_to_sleep_set(const stmdev_ctx_t * ctx,uint8_t val)2012 int32_t ais3624dq_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val)
2013 {
2014 ais3624dq_ctrl_reg5_t ctrl_reg5;
2015 int32_t ret;
2016
2017 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG5,
2018 (uint8_t *)&ctrl_reg5, 1);
2019
2020 if (ret == 0)
2021 {
2022 ctrl_reg5.turnon = val;
2023 ret = ais3624dq_write_reg(ctx, AIS3624DQ_CTRL_REG5,
2024 (uint8_t *)&ctrl_reg5, 1);
2025 }
2026
2027 return ret;
2028 }
2029
2030 /**
2031 * @brief Turn-on mode selection for sleep to wake function.[get]
2032 *
2033 * @param ctx read / write interface definitions(ptr)
2034 * @param val change the values of turnon in reg CTRL_REG5
2035 * @retval interface status (MANDATORY: return 0 -> no Error)
2036 *
2037 */
ais3624dq_wkup_to_sleep_get(const stmdev_ctx_t * ctx,uint8_t * val)2038 int32_t ais3624dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val)
2039 {
2040 ais3624dq_ctrl_reg5_t ctrl_reg5;
2041 int32_t ret;
2042
2043 ret = ais3624dq_read_reg(ctx, AIS3624DQ_CTRL_REG5,
2044 (uint8_t *)&ctrl_reg5, 1);
2045 *val = ctrl_reg5.turnon;
2046
2047 return ret;
2048 }
2049
2050 /**
2051 * @}
2052 *
2053 */
2054
2055 /**
2056 * @defgroup AIS3624DQ_Six_Position_Detection
2057 * @brief This section groups all the functions concerning six
2058 * position detection (6D).
2059 * @{
2060 *
2061 */
2062
2063 /**
2064 * @brief Configure the 6d on interrupt 1 generator.[set]
2065 *
2066 * @param ctx read / write interface definitions(ptr)
2067 * @param val change the values of 6d in reg INT1_CFG
2068 * @retval interface status (MANDATORY: return 0 -> no Error)
2069 *
2070 */
ais3624dq_int1_6d_mode_set(const stmdev_ctx_t * ctx,ais3624dq_int1_6d_t val)2071 int32_t ais3624dq_int1_6d_mode_set(const stmdev_ctx_t *ctx,
2072 ais3624dq_int1_6d_t val)
2073 {
2074 ais3624dq_int1_cfg_t int1_cfg;
2075 int32_t ret;
2076
2077 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
2078 (uint8_t *)&int1_cfg, 1);
2079
2080 if (ret == 0)
2081 {
2082 int1_cfg._6d = (uint8_t)val & 0x01U;
2083 int1_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
2084 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_CFG,
2085 (uint8_t *)&int1_cfg, 1);
2086 }
2087
2088 return ret;
2089 }
2090
2091 /**
2092 * @brief Configure the 6d on interrupt 1 generator.[get]
2093 *
2094 * @param ctx read / write interface definitions(ptr)
2095 * @param val Get the values of 6d in reg INT1_CFG
2096 * @retval interface status (MANDATORY: return 0 -> no Error)
2097 *
2098 */
ais3624dq_int1_6d_mode_get(const stmdev_ctx_t * ctx,ais3624dq_int1_6d_t * val)2099 int32_t ais3624dq_int1_6d_mode_get(const stmdev_ctx_t *ctx,
2100 ais3624dq_int1_6d_t *val)
2101 {
2102 ais3624dq_int1_cfg_t int1_cfg;
2103 int32_t ret;
2104
2105 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_CFG,
2106 (uint8_t *)&int1_cfg, 1);
2107
2108 switch ((int1_cfg.aoi << 1) + int1_cfg._6d)
2109 {
2110 case AIS3624DQ_6D_INT1_DISABLE:
2111 *val = AIS3624DQ_6D_INT1_DISABLE;
2112 break;
2113
2114 case AIS3624DQ_6D_INT1_MOVEMENT:
2115 *val = AIS3624DQ_6D_INT1_MOVEMENT;
2116 break;
2117
2118 case AIS3624DQ_6D_INT1_POSITION:
2119 *val = AIS3624DQ_6D_INT1_POSITION;
2120 break;
2121
2122 default:
2123 *val = AIS3624DQ_6D_INT1_DISABLE;
2124 break;
2125 }
2126
2127 return ret;
2128 }
2129
2130 /**
2131 * @brief 6D on interrupt generator 1 source register.[get]
2132 *
2133 * @param ctx read / write interface definitions(ptr)
2134 * @param val registers INT1_SRC
2135 * @retval interface status (MANDATORY: return 0 -> no Error)
2136 *
2137 */
ais3624dq_int1_6d_src_get(const stmdev_ctx_t * ctx,ais3624dq_int1_src_t * val)2138 int32_t ais3624dq_int1_6d_src_get(const stmdev_ctx_t *ctx,
2139 ais3624dq_int1_src_t *val)
2140 {
2141 int32_t ret;
2142
2143 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_SRC, (uint8_t *) val, 1);
2144
2145 return ret;
2146 }
2147
2148 /**
2149 * @brief Interrupt 1 threshold.[set]
2150 *
2151 * @param ctx read / write interface definitions(ptr)
2152 * @param val change the values of ths in reg INT1_THS
2153 * @retval interface status (MANDATORY: return 0 -> no Error)
2154 *
2155 */
ais3624dq_int1_6d_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2156 int32_t ais3624dq_int1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2157 {
2158 ais3624dq_int1_ths_t int1_ths;
2159 int32_t ret;
2160
2161 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS,
2162 (uint8_t *)&int1_ths, 1);
2163
2164 if (ret == 0)
2165 {
2166 int1_ths.ths = val;
2167 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT1_THS,
2168 (uint8_t *)&int1_ths, 1);
2169 }
2170
2171 return ret;
2172 }
2173
2174 /**
2175 * @brief Interrupt 1 threshold.[get]
2176 *
2177 * @param ctx read / write interface definitions(ptr)
2178 * @param val change the values of ths in reg INT1_THS
2179 * @retval interface status (MANDATORY: return 0 -> no Error)
2180 *
2181 */
ais3624dq_int1_6d_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2182 int32_t ais3624dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx,
2183 uint8_t *val)
2184 {
2185 ais3624dq_int1_ths_t int1_ths;
2186 int32_t ret;
2187
2188 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT1_THS,
2189 (uint8_t *)&int1_ths, 1);
2190 *val = int1_ths.ths;
2191
2192 return ret;
2193 }
2194
2195 /**
2196 * @brief Configure the 6d on interrupt 2 generator.[set]
2197 *
2198 * @param ctx read / write interface definitions(ptr)
2199 * @param val change the values of 6d in reg INT2_CFG
2200 * @retval interface status (MANDATORY: return 0 -> no Error)
2201 *
2202 */
ais3624dq_int2_6d_mode_set(const stmdev_ctx_t * ctx,ais3624dq_int2_6d_t val)2203 int32_t ais3624dq_int2_6d_mode_set(const stmdev_ctx_t *ctx,
2204 ais3624dq_int2_6d_t val)
2205 {
2206 ais3624dq_int2_cfg_t int2_cfg;
2207 int32_t ret;
2208
2209 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
2210 (uint8_t *)&int2_cfg, 1);
2211
2212 if (ret == 0)
2213 {
2214 int2_cfg._6d = (uint8_t)val & 0x01U;
2215 int2_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
2216 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_CFG,
2217 (uint8_t *)&int2_cfg, 1);
2218 }
2219
2220 return ret;
2221 }
2222
2223 /**
2224 * @brief Configure the 6d on interrupt 2 generator.[get]
2225 *
2226 * @param ctx read / write interface definitions(ptr)
2227 * @param val Get the values of 6d in reg INT2_CFG
2228 * @retval interface status (MANDATORY: return 0 -> no Error)
2229 *
2230 */
ais3624dq_int2_6d_mode_get(const stmdev_ctx_t * ctx,ais3624dq_int2_6d_t * val)2231 int32_t ais3624dq_int2_6d_mode_get(const stmdev_ctx_t *ctx,
2232 ais3624dq_int2_6d_t *val)
2233 {
2234 ais3624dq_int2_cfg_t int2_cfg;
2235 int32_t ret;
2236
2237 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_CFG,
2238 (uint8_t *)&int2_cfg, 1);
2239
2240 switch ((int2_cfg.aoi << 1) + int2_cfg._6d)
2241 {
2242 case AIS3624DQ_6D_INT2_DISABLE:
2243 *val = AIS3624DQ_6D_INT2_DISABLE;
2244 break;
2245
2246 case AIS3624DQ_6D_INT2_MOVEMENT:
2247 *val = AIS3624DQ_6D_INT2_MOVEMENT;
2248 break;
2249
2250 case AIS3624DQ_6D_INT2_POSITION:
2251 *val = AIS3624DQ_6D_INT2_POSITION;
2252 break;
2253
2254 default:
2255 *val = AIS3624DQ_6D_INT2_DISABLE;
2256 break;
2257 }
2258
2259 return ret;
2260 }
2261
2262 /**
2263 * @brief 6D on interrupt generator 2 source register.[get]
2264 *
2265 * @param ctx read / write interface definitions(ptr)
2266 * @param val registers INT2_SRC
2267 * @retval interface status (MANDATORY: return 0 -> no Error)
2268 *
2269 */
ais3624dq_int2_6d_src_get(const stmdev_ctx_t * ctx,ais3624dq_int2_src_t * val)2270 int32_t ais3624dq_int2_6d_src_get(const stmdev_ctx_t *ctx,
2271 ais3624dq_int2_src_t *val)
2272 {
2273 int32_t ret;
2274
2275 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_SRC, (uint8_t *) val, 1);
2276
2277 return ret;
2278 }
2279
2280 /**
2281 * @brief Interrupt 2 threshold.[set]
2282 *
2283 * @param ctx read / write interface definitions(ptr)
2284 * @param val change the values of ths in reg INT2_THS
2285 * @retval interface status (MANDATORY: return 0 -> no Error)
2286 *
2287 */
ais3624dq_int2_6d_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2288 int32_t ais3624dq_int2_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2289 {
2290 ais3624dq_int2_ths_t int2_ths;
2291 int32_t ret;
2292
2293 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS,
2294 (uint8_t *)&int2_ths, 1);
2295
2296 if (ret == 0)
2297 {
2298 int2_ths.ths = val;
2299 ret = ais3624dq_write_reg(ctx, AIS3624DQ_INT2_THS,
2300 (uint8_t *)&int2_ths, 1);
2301 }
2302
2303 return ret;
2304 }
2305
2306 /**
2307 * @brief Interrupt 2 threshold.[get]
2308 *
2309 * @param ctx read / write interface definitions(ptr)
2310 * @param val change the values of ths in reg INT2_THS
2311 * @retval interface status (MANDATORY: return 0 -> no Error)
2312 *
2313 */
ais3624dq_int2_6d_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2314 int32_t ais3624dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx,
2315 uint8_t *val)
2316 {
2317 ais3624dq_int2_ths_t int2_ths;
2318 int32_t ret;
2319
2320 ret = ais3624dq_read_reg(ctx, AIS3624DQ_INT2_THS,
2321 (uint8_t *)&int2_ths, 1);
2322 *val = int2_ths.ths;
2323
2324 return ret;
2325 }
2326
2327 /**
2328 * @}
2329 *
2330 */
2331
2332 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2333
