1 /**
2 ******************************************************************************
3 * @file i3g4250d_reg.c
4 * @author Sensors Software Solution Team
5 * @brief I3G4250D driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "i3g4250d_reg.h"
21
22 /**
23 * @defgroup I3G4250D
24 * @brief This file provides a set of functions needed to drive the
25 * i3g4250d enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup I3G4250D_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
i3g4250d_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak i3g4250d_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL) return -1;
56
57 ret = ctx->read_reg(ctx->handle, reg, data, len);
58
59 return ret;
60 }
61
62 /**
63 * @brief Write generic device register
64 *
65 * @param ctx read / write interface definitions(ptr)
66 * @param reg register to write
67 * @param data pointer to data to write in register reg(ptr)
68 * @param len number of consecutive register to write
69 * @retval interface status (MANDATORY: return 0 -> no Error)
70 *
71 */
i3g4250d_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)72 int32_t __weak i3g4250d_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
73 uint8_t *data,
74 uint16_t len)
75 {
76 int32_t ret;
77
78 if (ctx == NULL) return -1;
79
80 ret = ctx->write_reg(ctx->handle, reg, data, len);
81
82 return ret;
83 }
84
85 /**
86 * @}
87 *
88 */
89
90 /**
91 * @defgroup I3G4250D_Sensitivity
92 * @brief These functions convert raw-data into engineering units.
93 * @{
94 *
95 */
96
i3g4250d_from_fs245dps_to_mdps(int16_t lsb)97 float_t i3g4250d_from_fs245dps_to_mdps(int16_t lsb)
98 {
99 return ((float_t)lsb * 8.75f);
100 }
101
i3g4250d_from_lsb_to_celsius(int16_t lsb)102 float_t i3g4250d_from_lsb_to_celsius(int16_t lsb)
103 {
104 return ((float_t)lsb + 25.0f);
105 }
106
107 /**
108 * @}
109 *
110 */
111
112 /**
113 * @defgroup I3G4250D_data_generation
114 * @brief This section groups all the functions concerning
115 * data generation
116 * @{
117 *
118 */
119
120 /**
121 * @brief Accelerometer data rate selection.[set]
122 *
123 * @param ctx Read / write interface definitions.(ptr)
124 * @param val Change the values of dr in reg CTRL_REG1
125 * @retval Interface status (MANDATORY: return 0 -> no Error)
126 *
127 */
i3g4250d_data_rate_set(const stmdev_ctx_t * ctx,i3g4250d_dr_t val)128 int32_t i3g4250d_data_rate_set(const stmdev_ctx_t *ctx, i3g4250d_dr_t val)
129 {
130 i3g4250d_ctrl_reg1_t ctrl_reg1;
131 int32_t ret;
132
133 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1,
134 (uint8_t *)&ctrl_reg1, 1);
135
136 if (ret == 0)
137 {
138 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
139 ctrl_reg1.pd = ((uint8_t)val & 0x0FU);
140 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG1,
141 (uint8_t *)&ctrl_reg1, 1);
142 }
143
144 return ret;
145 }
146
147 /**
148 * @brief Accelerometer data rate selection.[get]
149 *
150 * @param ctx Read / write interface definitions.(ptr)
151 * @param val Get the values of dr in reg CTRL_REG1.(ptr)
152 * @retval Interface status (MANDATORY: return 0 -> no Error)
153 *
154 */
i3g4250d_data_rate_get(const stmdev_ctx_t * ctx,i3g4250d_dr_t * val)155 int32_t i3g4250d_data_rate_get(const stmdev_ctx_t *ctx, i3g4250d_dr_t *val)
156 {
157 i3g4250d_ctrl_reg1_t ctrl_reg1;
158 int32_t ret;
159
160 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1,
161 (uint8_t *)&ctrl_reg1, 1);
162
163 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pd)
164 {
165 case I3G4250D_ODR_OFF:
166 *val = I3G4250D_ODR_OFF;
167 break;
168
169 case I3G4250D_ODR_SLEEP:
170 *val = I3G4250D_ODR_SLEEP;
171 break;
172
173 case I3G4250D_ODR_100Hz:
174 *val = I3G4250D_ODR_100Hz;
175 break;
176
177 case I3G4250D_ODR_200Hz:
178 *val = I3G4250D_ODR_200Hz;
179 break;
180
181 case I3G4250D_ODR_400Hz:
182 *val = I3G4250D_ODR_400Hz;
183 break;
184
185 case I3G4250D_ODR_800Hz:
186 *val = I3G4250D_ODR_800Hz;
187 break;
188
189 default:
190 *val = I3G4250D_ODR_OFF;
191 break;
192 }
193
194 return ret;
195 }
196
197 /**
198 * @brief Gyroscope full-scale selection.[set]
199 *
200 * @param ctx read / write interface definitions(ptr)
201 * @param val change the values of fs in reg CTRL_REG4
202 * @retval Interface status (MANDATORY: return 0 -> no Error)
203 *
204 */
i3g4250d_full_scale_set(const stmdev_ctx_t * ctx,i3g4250d_fs_t val)205 int32_t i3g4250d_full_scale_set(const stmdev_ctx_t *ctx, i3g4250d_fs_t val)
206 {
207 i3g4250d_ctrl_reg4_t ctrl_reg4;
208 int32_t ret;
209
210 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
211 (uint8_t *)&ctrl_reg4, 1);
212
213 if (ret == 0)
214 {
215 ctrl_reg4.fs = (uint8_t)val;
216 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG4,
217 (uint8_t *)&ctrl_reg4, 1);
218 }
219
220 return ret;
221 }
222
223 /**
224 * @brief Gyroscope full-scale selection.[get]
225 *
226 * @param ctx read / write interface definitions(ptr)
227 * @param val Get the values of fs in reg CTRL_REG4
228 * @retval Interface status (MANDATORY: return 0 -> no Error)
229 *
230 */
i3g4250d_full_scale_get(const stmdev_ctx_t * ctx,i3g4250d_fs_t * val)231 int32_t i3g4250d_full_scale_get(const stmdev_ctx_t *ctx, i3g4250d_fs_t *val)
232 {
233 i3g4250d_ctrl_reg4_t ctrl_reg4;
234 int32_t ret;
235
236 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
237 (uint8_t *)&ctrl_reg4, 1);
238
239 switch (ctrl_reg4.fs)
240 {
241 case I3G4250D_245dps:
242 *val = I3G4250D_245dps;
243 break;
244
245 case I3G4250D_500dps:
246 *val = I3G4250D_500dps;
247 break;
248
249 case I3G4250D_2000dps:
250 *val = I3G4250D_2000dps;
251 break;
252
253 default:
254 *val = I3G4250D_245dps;
255 break;
256 }
257
258 return ret;
259 }
260
261 /**
262 * @brief The STATUS_REG register is read by the primary interface.[get]
263 *
264 * @param ctx Read / write interface definitions.(ptr)
265 * @param val registers STATUS_REG
266 * @retval Interface status (MANDATORY: return 0 -> no Error)
267 *
268 */
i3g4250d_status_reg_get(const stmdev_ctx_t * ctx,i3g4250d_status_reg_t * val)269 int32_t i3g4250d_status_reg_get(const stmdev_ctx_t *ctx,
270 i3g4250d_status_reg_t *val)
271 {
272 int32_t ret;
273
274 ret = i3g4250d_read_reg(ctx, I3G4250D_STATUS_REG, (uint8_t *) val, 1);
275
276 return ret;
277 }
278
279 /**
280 * @brief Accelerometer new data available.[get]
281 *
282 * @param ctx Read / write interface definitions.(ptr)
283 * @param val Change the values of "zyxda" in reg STATUS_REG.(ptr)
284 * @retval Interface status (MANDATORY: return 0 -> no Error)
285 *
286 */
i3g4250d_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)287 int32_t i3g4250d_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
288 {
289 i3g4250d_status_reg_t status_reg;
290 int32_t ret;
291
292 ret = i3g4250d_read_reg(ctx, I3G4250D_STATUS_REG,
293 (uint8_t *)&status_reg, 1);
294 *val = status_reg.zyxda;
295
296 return ret;
297 }
298 /**
299 * @}
300 *
301 */
302
303 /**
304 * @defgroup I3G4250D_Dataoutput
305 * @brief This section groups all the data output functions.
306 * @{
307 *
308 */
309
310 /**
311 * @brief Temperature data.[get]
312 *
313 * @param ctx Read / write interface definitions.(ptr)
314 * @param buff Buffer that stores the data read.(ptr)
315 * @retval Interface status (MANDATORY: return 0 -> no Error)
316 *
317 */
i3g4250d_temperature_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)318 int32_t i3g4250d_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
319 {
320 int32_t ret;
321
322 ret = i3g4250d_read_reg(ctx, I3G4250D_OUT_TEMP, buff, 1);
323
324 return ret;
325 }
326
327 /**
328 * @brief Angular rate sensor. The value is expressed as a 16-bit word in
329 * two’s complement.[get]
330 *
331 * @param ctx Read / write interface definitions.(ptr)
332 * @param buff Buffer that stores the data read.(ptr)
333 * @retval Interface status (MANDATORY: return 0 -> no Error)
334 *
335 */
i3g4250d_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)336 int32_t i3g4250d_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
337 {
338 uint8_t buff[6];
339 int32_t ret;
340
341 ret = i3g4250d_read_reg(ctx, I3G4250D_OUT_X_L, buff, 6);
342 val[0] = (int16_t)buff[1];
343 val[0] = (val[0] * 256) + (int16_t)buff[0];
344 val[1] = (int16_t)buff[3];
345 val[1] = (val[1] * 256) + (int16_t)buff[2];
346 val[2] = (int16_t)buff[5];
347 val[2] = (val[2] * 256) + (int16_t)buff[4];
348
349 return ret;
350 }
351
352 /**
353 * @}
354 *
355 */
356
357 /**
358 * @defgroup I3G4250D_common
359 * @brief This section groups common useful functions.
360 * @{
361 *
362 */
363
364 /**
365 * @brief Device Who amI.[get]
366 *
367 * @param ctx Read / write interface definitions.(ptr)
368 * @param buff Buffer that stores the data read.(ptr)
369 * @retval Interface status (MANDATORY: return 0 -> no Error)
370 *
371 */
i3g4250d_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)372 int32_t i3g4250d_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
373 {
374 int32_t ret;
375
376 ret = i3g4250d_read_reg(ctx, I3G4250D_WHO_AM_I, buff, 1);
377
378 return ret;
379 }
380
381 /**
382 * @brief Angular rate sensor self-test enable. [set]
383 *
384 * @param ctx Read / write interface definitions.(ptr)
385 * @param val change the values of st in reg CTRL_REG4.
386 * @retval Interface status (MANDATORY: return 0 -> no Error)
387 *
388 */
i3g4250d_self_test_set(const stmdev_ctx_t * ctx,i3g4250d_st_t val)389 int32_t i3g4250d_self_test_set(const stmdev_ctx_t *ctx, i3g4250d_st_t val)
390 {
391 i3g4250d_ctrl_reg4_t ctrl_reg4;
392 int32_t ret;
393
394 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
395 (uint8_t *)&ctrl_reg4, 1);
396
397 if (ret == 0)
398 {
399 ctrl_reg4.st = (uint8_t)val;
400 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG4,
401 (uint8_t *)&ctrl_reg4, 1);
402 }
403
404 return ret;
405 }
406
407 /**
408 * @brief Angular rate sensor self-test enable. [get]
409 *
410 * @param ctx Read / write interface definitions.(ptr)
411 * @param val Get the values of st in reg CTRL_REG4.(ptr)
412 * @retval Interface status (MANDATORY: return 0 -> no Error)
413 *
414 */
i3g4250d_self_test_get(const stmdev_ctx_t * ctx,i3g4250d_st_t * val)415 int32_t i3g4250d_self_test_get(const stmdev_ctx_t *ctx, i3g4250d_st_t *val)
416 {
417 i3g4250d_ctrl_reg4_t ctrl_reg4;
418 int32_t ret;
419
420 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
421 (uint8_t *)&ctrl_reg4, 1);
422
423 switch (ctrl_reg4.st)
424 {
425 case I3G4250D_GY_ST_DISABLE:
426 *val = I3G4250D_GY_ST_DISABLE;
427 break;
428
429 case I3G4250D_GY_ST_POSITIVE:
430 *val = I3G4250D_GY_ST_POSITIVE;
431 break;
432
433 case I3G4250D_GY_ST_NEGATIVE:
434 *val = I3G4250D_GY_ST_NEGATIVE;
435 break;
436
437 default:
438 *val = I3G4250D_GY_ST_DISABLE;
439 break;
440 }
441
442 return ret;
443 }
444
445 /**
446 * @brief Big/Little Endian data selection.[set]
447 *
448 * @param ctx Read / write interface definitions.(ptr)
449 * @param val Change the values of "ble" in reg CTRL_REG4.
450 * @retval Interface status (MANDATORY: return 0 -> no Error)
451 *
452 */
i3g4250d_data_format_set(const stmdev_ctx_t * ctx,i3g4250d_ble_t val)453 int32_t i3g4250d_data_format_set(const stmdev_ctx_t *ctx,
454 i3g4250d_ble_t val)
455 {
456 i3g4250d_ctrl_reg4_t ctrl_reg4;
457 int32_t ret;
458
459 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
460 (uint8_t *)&ctrl_reg4, 1);
461
462 if (ret == 0)
463 {
464 ctrl_reg4.ble = (uint8_t)val;
465 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG4,
466 (uint8_t *)&ctrl_reg4, 1);
467 }
468
469 return ret;
470 }
471
472 /**
473 * @brief Big/Little Endian data selection.[get]
474 *
475 * @param ctx Read / write interface definitions.(ptr)
476 * @param val Get the values of "ble" in reg CTRL_REG4.(ptr)
477 * @retval Interface status (MANDATORY: return 0 -> no Error)
478 *
479 */
i3g4250d_data_format_get(const stmdev_ctx_t * ctx,i3g4250d_ble_t * val)480 int32_t i3g4250d_data_format_get(const stmdev_ctx_t *ctx,
481 i3g4250d_ble_t *val)
482 {
483 i3g4250d_ctrl_reg4_t ctrl_reg4;
484 int32_t ret;
485
486 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
487 (uint8_t *)&ctrl_reg4, 1);
488
489 switch (ctrl_reg4.ble)
490 {
491 case I3G4250D_AUX_LSB_AT_LOW_ADD:
492 *val = I3G4250D_AUX_LSB_AT_LOW_ADD;
493 break;
494
495 case I3G4250D_AUX_MSB_AT_LOW_ADD:
496 *val = I3G4250D_AUX_MSB_AT_LOW_ADD;
497 break;
498
499 default:
500 *val = I3G4250D_AUX_LSB_AT_LOW_ADD;
501 break;
502 }
503
504 return ret;
505 }
506
507 /**
508 * @brief Reboot memory content. Reload the calibration parameters.[set]
509 *
510 * @param ctx Read / write interface definitions.(ptr)
511 * @param val Change the values of boot in reg CTRL_REG5.
512 * @retval Interface status (MANDATORY: return 0 -> no Error)
513 *
514 */
i3g4250d_boot_set(const stmdev_ctx_t * ctx,uint8_t val)515 int32_t i3g4250d_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
516 {
517 i3g4250d_ctrl_reg5_t ctrl_reg5;
518 int32_t ret;
519
520 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
521 (uint8_t *)&ctrl_reg5, 1);
522
523 if (ret == 0)
524 {
525 ctrl_reg5.boot = val;
526 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,
527 (uint8_t *)&ctrl_reg5, 1);
528 }
529
530 return ret;
531 }
532
533 /**
534 * @brief Reboot memory content. Reload the calibration parameters.[get]
535 *
536 * @param ctx Read / write interface definitions.(ptr)
537 * @param val Get the values of boot in reg CTRL_REG5.(ptr)
538 * @retval interface status (MANDATORY: return 0 -> no Error)
539 *
540 */
i3g4250d_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)541 int32_t i3g4250d_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
542 {
543 i3g4250d_ctrl_reg5_t ctrl_reg5;
544 int32_t ret;
545
546 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
547 (uint8_t *)&ctrl_reg5, 1);
548 *val = ctrl_reg5.boot;
549
550 return ret;
551 }
552
553 /**
554 * @}
555 *
556 */
557
558 /**
559 * @defgroup I3G4250D_filters
560 * @brief This section group all the functions concerning the
561 * filters configuration.
562 * @{
563 *
564 */
565
566 /**
567 * @brief Lowpass filter bandwidth selection.[set]
568 *
569 * @param ctx Read / write interface definitions.(ptr)
570 * @param val Change the values of "bw" in reg CTRL_REG1.
571 * @retval Interface status (MANDATORY: return 0 -> no Error)
572 *
573 */
i3g4250d_lp_bandwidth_set(const stmdev_ctx_t * ctx,i3g4250d_bw_t val)574 int32_t i3g4250d_lp_bandwidth_set(const stmdev_ctx_t *ctx,
575 i3g4250d_bw_t val)
576 {
577 i3g4250d_ctrl_reg1_t ctrl_reg1;
578 int32_t ret;
579
580 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1,
581 (uint8_t *)&ctrl_reg1, 1);
582
583 if (ret == 0)
584 {
585 ctrl_reg1.bw = (uint8_t)val;
586 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG1,
587 (uint8_t *)&ctrl_reg1, 1);
588 }
589
590 return ret;
591 }
592
593 /**
594 * @brief Lowpass filter bandwidth selection.[get]
595 *
596 * @param ctx Read / write interface definitions.(ptr)
597 * @param val Get the values of "bw" in reg CTRL_REG1.(ptr)
598 * @retval Interface status (MANDATORY: return 0 -> no Error)
599 *
600 */
i3g4250d_lp_bandwidth_get(const stmdev_ctx_t * ctx,i3g4250d_bw_t * val)601 int32_t i3g4250d_lp_bandwidth_get(const stmdev_ctx_t *ctx,
602 i3g4250d_bw_t *val)
603 {
604 i3g4250d_ctrl_reg1_t ctrl_reg1;
605 int32_t ret;
606
607 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG1,
608 (uint8_t *)&ctrl_reg1, 1);
609
610 switch (ctrl_reg1.bw)
611 {
612 case I3G4250D_CUT_OFF_LOW:
613 *val = I3G4250D_CUT_OFF_LOW;
614 break;
615
616 case I3G4250D_CUT_OFF_MEDIUM:
617 *val = I3G4250D_CUT_OFF_MEDIUM;
618 break;
619
620 case I3G4250D_CUT_OFF_HIGH:
621 *val = I3G4250D_CUT_OFF_HIGH;
622 break;
623
624 case I3G4250D_CUT_OFF_VERY_HIGH:
625 *val = I3G4250D_CUT_OFF_VERY_HIGH;
626 break;
627
628 default:
629 *val = I3G4250D_CUT_OFF_LOW;
630 break;
631 }
632
633 return ret;
634 }
635
636 /**
637 * @brief High-pass filter bandwidth selection.[set]
638 *
639 * @param ctx Read / write interface definitions.(ptr)
640 * @param val Change the values of "hpcf" in reg CTRL_REG2.
641 * @retval Interface status (MANDATORY: return 0 -> no Error)
642 *
643 */
i3g4250d_hp_bandwidth_set(const stmdev_ctx_t * ctx,i3g4250d_hpcf_t val)644 int32_t i3g4250d_hp_bandwidth_set(const stmdev_ctx_t *ctx,
645 i3g4250d_hpcf_t val)
646 {
647 i3g4250d_ctrl_reg2_t ctrl_reg2;
648 int32_t ret;
649
650 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,
651 (uint8_t *)&ctrl_reg2, 1);
652
653 if (ret == 0)
654 {
655 ctrl_reg2.hpcf = (uint8_t)val;
656 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG2,
657 (uint8_t *)&ctrl_reg2, 1);
658 }
659
660 return ret;
661 }
662
663 /**
664 * @brief High-pass filter bandwidth selection.[get]
665 *
666 * @param ctx Read / write interface definitions.(ptr)
667 * @param val Get the values of hpcf in reg CTRL_REG2.(ptr)
668 * @retval Interface status (MANDATORY: return 0 -> no Error)
669 *
670 */
i3g4250d_hp_bandwidth_get(const stmdev_ctx_t * ctx,i3g4250d_hpcf_t * val)671 int32_t i3g4250d_hp_bandwidth_get(const stmdev_ctx_t *ctx,
672 i3g4250d_hpcf_t *val)
673 {
674 i3g4250d_ctrl_reg2_t ctrl_reg2;
675 int32_t ret;
676
677 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,
678 (uint8_t *)&ctrl_reg2, 1);
679
680 switch (ctrl_reg2.hpcf)
681 {
682 case I3G4250D_HP_LEVEL_0:
683 *val = I3G4250D_HP_LEVEL_0;
684 break;
685
686 case I3G4250D_HP_LEVEL_1:
687 *val = I3G4250D_HP_LEVEL_1;
688 break;
689
690 case I3G4250D_HP_LEVEL_2:
691 *val = I3G4250D_HP_LEVEL_2;
692 break;
693
694 case I3G4250D_HP_LEVEL_3:
695 *val = I3G4250D_HP_LEVEL_3;
696 break;
697
698 case I3G4250D_HP_LEVEL_4:
699 *val = I3G4250D_HP_LEVEL_4;
700 break;
701
702 case I3G4250D_HP_LEVEL_5:
703 *val = I3G4250D_HP_LEVEL_5;
704 break;
705
706 case I3G4250D_HP_LEVEL_6:
707 *val = I3G4250D_HP_LEVEL_6;
708 break;
709
710 case I3G4250D_HP_LEVEL_7:
711 *val = I3G4250D_HP_LEVEL_7;
712 break;
713
714 case I3G4250D_HP_LEVEL_8:
715 *val = I3G4250D_HP_LEVEL_8;
716 break;
717
718 case I3G4250D_HP_LEVEL_9:
719 *val = I3G4250D_HP_LEVEL_9;
720 break;
721
722 default:
723 *val = I3G4250D_HP_LEVEL_0;
724 break;
725 }
726
727 return ret;
728 }
729
730 /**
731 * @brief High-pass filter mode selection. [set]
732 *
733 * @param ctx Read / write interface definitions.(ptr)
734 * @param val Change the values of "hpm" in reg CTRL_REG2.
735 * @retval Interface status (MANDATORY: return 0 -> no Error)
736 *
737 */
i3g4250d_hp_mode_set(const stmdev_ctx_t * ctx,i3g4250d_hpm_t val)738 int32_t i3g4250d_hp_mode_set(const stmdev_ctx_t *ctx, i3g4250d_hpm_t val)
739 {
740 i3g4250d_ctrl_reg2_t ctrl_reg2;
741 int32_t ret;
742
743 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,
744 (uint8_t *)&ctrl_reg2, 1);
745
746 if (ret == 0)
747 {
748 ctrl_reg2.hpm = (uint8_t)val;
749 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG2,
750 (uint8_t *)&ctrl_reg2, 1);
751 }
752
753 return ret;
754 }
755
756 /**
757 * @brief High-pass filter mode selection. [get]
758 *
759 * @param ctx Read / write interface definitions.(ptr)
760 * @param val Get the values of hpm in reg CTRL_REG2.(ptr)
761 * @retval Interface status (MANDATORY: return 0 -> no Error)
762 *
763 */
i3g4250d_hp_mode_get(const stmdev_ctx_t * ctx,i3g4250d_hpm_t * val)764 int32_t i3g4250d_hp_mode_get(const stmdev_ctx_t *ctx, i3g4250d_hpm_t *val)
765 {
766 i3g4250d_ctrl_reg2_t ctrl_reg2;
767 int32_t ret;
768
769 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG2,
770 (uint8_t *)&ctrl_reg2, 1);
771
772 switch (ctrl_reg2.hpm)
773 {
774 case I3G4250D_HP_NORMAL_MODE_WITH_RST:
775 *val = I3G4250D_HP_NORMAL_MODE_WITH_RST;
776 break;
777
778 case I3G4250D_HP_REFERENCE_SIGNAL:
779 *val = I3G4250D_HP_REFERENCE_SIGNAL;
780 break;
781
782 case I3G4250D_HP_NORMAL_MODE:
783 *val = I3G4250D_HP_NORMAL_MODE;
784 break;
785
786 case I3G4250D_HP_AUTO_RESET_ON_INT:
787 *val = I3G4250D_HP_AUTO_RESET_ON_INT;
788 break;
789
790 default:
791 *val = I3G4250D_HP_NORMAL_MODE_WITH_RST;
792 break;
793 }
794
795 return ret;
796 }
797
798 /**
799 * @brief Out/FIFO selection path. [set]
800 *
801 * @param ctx Read / write interface definitions.(ptr)
802 * @param val Change the values of "out_sel" in reg CTRL_REG5.
803 * @retval Interface status (MANDATORY: return 0 -> no Error)
804 *
805 */
i3g4250d_filter_path_set(const stmdev_ctx_t * ctx,i3g4250d_out_sel_t val)806 int32_t i3g4250d_filter_path_set(const stmdev_ctx_t *ctx,
807 i3g4250d_out_sel_t val)
808 {
809 i3g4250d_ctrl_reg5_t ctrl_reg5;
810 int32_t ret;
811
812 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
813 (uint8_t *)&ctrl_reg5, 1);
814
815 if (ret == 0)
816 {
817 ctrl_reg5.out_sel = (uint8_t)val & 0x03U;
818 ctrl_reg5.hpen = ((uint8_t)val & 0x04U) >> 2;
819 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,
820 (uint8_t *)&ctrl_reg5, 1);
821 }
822
823 return ret;
824 }
825
826 /**
827 * @brief Out/FIFO selection path. [get]
828 *
829 * @param ctx Read / write interface definitions.(ptr)
830 * @param val Get the values of out_sel in reg CTRL_REG5.(ptr)
831 * @retval Interface status (MANDATORY: return 0 -> no Error)
832 *
833 */
i3g4250d_filter_path_get(const stmdev_ctx_t * ctx,i3g4250d_out_sel_t * val)834 int32_t i3g4250d_filter_path_get(const stmdev_ctx_t *ctx,
835 i3g4250d_out_sel_t *val)
836 {
837 i3g4250d_ctrl_reg5_t ctrl_reg5;
838 int32_t ret;
839
840 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
841 (uint8_t *)&ctrl_reg5, 1);
842
843 switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.out_sel)
844 {
845 case I3G4250D_ONLY_LPF1_ON_OUT:
846 *val = I3G4250D_ONLY_LPF1_ON_OUT;
847 break;
848
849 case I3G4250D_LPF1_HP_ON_OUT:
850 *val = I3G4250D_LPF1_HP_ON_OUT;
851 break;
852
853 case I3G4250D_LPF1_LPF2_ON_OUT:
854 *val = I3G4250D_LPF1_LPF2_ON_OUT;
855 break;
856
857 case I3G4250D_LPF1_HP_LPF2_ON_OUT:
858 *val = I3G4250D_LPF1_HP_LPF2_ON_OUT;
859 break;
860
861 default:
862 *val = I3G4250D_ONLY_LPF1_ON_OUT;
863 break;
864 }
865
866 return ret;
867 }
868
869 /**
870 * @brief Interrupt generator selection path.[set]
871 *
872 * @param ctx Read / write interface definitions.(ptr)
873 * @param val Change the values of int1_sel in reg CTRL_REG5
874 * @retval Interface status (MANDATORY: return 0 -> no Error)
875 *
876 */
i3g4250d_filter_path_internal_set(const stmdev_ctx_t * ctx,i3g4250d_int1_sel_t val)877 int32_t i3g4250d_filter_path_internal_set(const stmdev_ctx_t *ctx,
878 i3g4250d_int1_sel_t val)
879 {
880 i3g4250d_ctrl_reg5_t ctrl_reg5;
881 int32_t ret;
882
883 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
884 (uint8_t *)&ctrl_reg5, 1);
885
886 if (ret == 0)
887 {
888 ctrl_reg5.int1_sel = (uint8_t)val & 0x03U;
889 ctrl_reg5.hpen = ((uint8_t)val & 0x04U) >> 2;
890 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,
891 (uint8_t *)&ctrl_reg5, 1);
892 }
893
894 return ret;
895 }
896
897 /**
898 * @brief Interrupt generator selection path.[get]
899 *
900 * @param ctx Read / write interface definitions.(ptr)
901 * @param val Get the values of int1_sel in reg CTRL_REG5.(ptr)
902 * @retval Interface status (MANDATORY: return 0 -> no Error)
903 *
904 */
i3g4250d_filter_path_internal_get(const stmdev_ctx_t * ctx,i3g4250d_int1_sel_t * val)905 int32_t i3g4250d_filter_path_internal_get(const stmdev_ctx_t *ctx,
906 i3g4250d_int1_sel_t *val)
907 {
908 i3g4250d_ctrl_reg5_t ctrl_reg5;
909 int32_t ret;
910
911 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
912 (uint8_t *)&ctrl_reg5, 1);
913
914 switch ((ctrl_reg5.hpen << 2) + ctrl_reg5.int1_sel)
915 {
916 case I3G4250D_ONLY_LPF1_ON_INT:
917 *val = I3G4250D_ONLY_LPF1_ON_INT;
918 break;
919
920 case I3G4250D_LPF1_HP_ON_INT:
921 *val = I3G4250D_LPF1_HP_ON_INT;
922 break;
923
924 case I3G4250D_LPF1_LPF2_ON_INT:
925 *val = I3G4250D_LPF1_LPF2_ON_INT;
926 break;
927
928 case I3G4250D_LPF1_HP_LPF2_ON_INT:
929 *val = I3G4250D_LPF1_HP_LPF2_ON_INT;
930 break;
931
932 default:
933 *val = I3G4250D_ONLY_LPF1_ON_INT;
934 break;
935 }
936
937 return ret;
938 }
939
940 /**
941 * @brief Reference value for high-pass filter.[set]
942 *
943 * @param ctx Read / write interface definitions.(ptr)
944 * @param val Change the values of ref in reg REFERENCE
945 * @retval Interface status (MANDATORY: return 0 -> no Error)
946 *
947 */
i3g4250d_hp_reference_value_set(const stmdev_ctx_t * ctx,uint8_t val)948 int32_t i3g4250d_hp_reference_value_set(const stmdev_ctx_t *ctx,
949 uint8_t val)
950 {
951 i3g4250d_reference_t reference;
952 int32_t ret;
953
954 ret = i3g4250d_read_reg(ctx, I3G4250D_REFERENCE,
955 (uint8_t *)&reference, 1);
956
957 if (ret == 0)
958 {
959 reference.ref = val;
960 ret = i3g4250d_write_reg(ctx, I3G4250D_REFERENCE,
961 (uint8_t *)&reference, 1);
962 }
963
964 return ret;
965 }
966
967 /**
968 * @brief Reference value for high-pass filter.[get]
969 *
970 * @param ctx Read / write interface definitions.(ptr)
971 * @param val Get the values of ref in reg REFERENCE.(ptr)
972 * @retval Interface status (MANDATORY: return 0 -> no Error)
973 *
974 */
i3g4250d_hp_reference_value_get(const stmdev_ctx_t * ctx,uint8_t * val)975 int32_t i3g4250d_hp_reference_value_get(const stmdev_ctx_t *ctx,
976 uint8_t *val)
977 {
978 i3g4250d_reference_t reference;
979 int32_t ret;
980
981 ret = i3g4250d_read_reg(ctx, I3G4250D_REFERENCE,
982 (uint8_t *)&reference, 1);
983 *val = reference.ref;
984
985 return ret;
986 }
987
988 /**
989 * @}
990 *
991 */
992
993 /**
994 * @defgroup I3G4250D_serial_interface
995 * @brief This section groups all the functions concerning main serial
996 * interface management.
997 * @{
998 *
999 */
1000
1001 /**
1002 * @brief SPI Serial Interface Mode selection.[set]
1003 *
1004 * @param ctx Read / write interface definitions.(ptr)
1005 * @param val Change the values of sim in reg CTRL_REG4
1006 * @retval Interface status (MANDATORY: return 0 -> no Error)
1007 *
1008 */
i3g4250d_spi_mode_set(const stmdev_ctx_t * ctx,i3g4250d_sim_t val)1009 int32_t i3g4250d_spi_mode_set(const stmdev_ctx_t *ctx, i3g4250d_sim_t val)
1010 {
1011 i3g4250d_ctrl_reg4_t ctrl_reg4;
1012 int32_t ret;
1013
1014 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
1015 (uint8_t *)&ctrl_reg4, 1);
1016
1017 if (ret == 0)
1018 {
1019 ctrl_reg4.sim = (uint8_t)val;
1020 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG4,
1021 (uint8_t *)&ctrl_reg4, 1);
1022 }
1023
1024 return ret;
1025 }
1026
1027 /**
1028 * @brief SPI Serial Interface Mode selection.[get]
1029 *
1030 * @param ctx Read / write interface definitions.(ptr)
1031 * @param val Get the values of sim in reg CTRL_REG4.(ptr)
1032 * @retval Interface status (MANDATORY: return 0 -> no Error)
1033 *
1034 */
i3g4250d_spi_mode_get(const stmdev_ctx_t * ctx,i3g4250d_sim_t * val)1035 int32_t i3g4250d_spi_mode_get(const stmdev_ctx_t *ctx, i3g4250d_sim_t *val)
1036 {
1037 i3g4250d_ctrl_reg4_t ctrl_reg4;
1038 int32_t ret;
1039
1040 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG4,
1041 (uint8_t *)&ctrl_reg4, 1);
1042
1043 switch (ctrl_reg4.sim)
1044 {
1045 case I3G4250D_SPI_4_WIRE:
1046 *val = I3G4250D_SPI_4_WIRE;
1047 break;
1048
1049 case I3G4250D_SPI_3_WIRE:
1050 *val = I3G4250D_SPI_3_WIRE;
1051 break;
1052
1053 default:
1054 *val = I3G4250D_SPI_4_WIRE;
1055 break;
1056 }
1057
1058 return ret;
1059 }
1060
1061 /**
1062 * @}
1063 *
1064 */
1065
1066 /**
1067 * @defgroup I3G4250D_interrupt_pins
1068 * @brief This section groups all the functions that manage interrupt pins
1069 * @{
1070 *
1071 */
1072
1073
1074 /**
1075 * @brief Select the signal that need to route on int1 pad.[set]
1076 *
1077 * @param ctx Read / write interface definitions.(ptr)
1078 * @param val Configure CTRL_REG3 int1 pad
1079 * @retval Interface status (MANDATORY: return 0 -> no Error)
1080 *
1081 */
i3g4250d_pin_int1_route_set(const stmdev_ctx_t * ctx,i3g4250d_int1_route_t val)1082 int32_t i3g4250d_pin_int1_route_set(const stmdev_ctx_t *ctx,
1083 i3g4250d_int1_route_t val)
1084 {
1085 i3g4250d_ctrl_reg3_t ctrl_reg3;
1086 int32_t ret;
1087
1088 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
1089 (uint8_t *)&ctrl_reg3, 1);
1090
1091 if (ret == 0)
1092 {
1093 ctrl_reg3.i1_int1 = val.i1_int1;
1094 ctrl_reg3.i1_boot = val.i1_boot;
1095 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,
1096 (uint8_t *)&ctrl_reg3, 1);
1097 }
1098
1099 return ret;
1100 }
1101
1102 /**
1103 * @brief Select the signal that need to route on int1 pad.[get]
1104 *
1105 * @param ctx Read / write interface definitions.(ptr)
1106 * @param val Read CTRL_REG3 int1 pad.(ptr)
1107 * @retval Interface status (MANDATORY: return 0 -> no Error)
1108 *
1109 */
1110
i3g4250d_pin_int1_route_get(const stmdev_ctx_t * ctx,i3g4250d_int1_route_t * val)1111 int32_t i3g4250d_pin_int1_route_get(const stmdev_ctx_t *ctx,
1112 i3g4250d_int1_route_t *val)
1113 {
1114 i3g4250d_ctrl_reg3_t ctrl_reg3;
1115 int32_t ret;
1116
1117 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
1118 (uint8_t *)&ctrl_reg3, 1);
1119 val->i1_int1 = ctrl_reg3.i1_int1;
1120 val->i1_boot = ctrl_reg3.i1_boot;
1121
1122 return ret;
1123 }
1124 /**
1125 * @brief Select the signal that need to route on int2 pad.[set]
1126 *
1127 * @param ctx Read / write interface definitions.(ptr)
1128 * @param val Configure CTRL_REG3 int2 pad
1129 * @retval Interface status (MANDATORY: return 0 -> no Error)
1130 *
1131 */
i3g4250d_pin_int2_route_set(const stmdev_ctx_t * ctx,i3g4250d_int2_route_t val)1132 int32_t i3g4250d_pin_int2_route_set(const stmdev_ctx_t *ctx,
1133 i3g4250d_int2_route_t val)
1134 {
1135 i3g4250d_ctrl_reg3_t ctrl_reg3;
1136 int32_t ret;
1137
1138 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
1139 (uint8_t *)&ctrl_reg3, 1);
1140
1141 if (ret == 0)
1142 {
1143 ctrl_reg3.i2_empty = val.i2_empty;
1144 ctrl_reg3.i2_orun = val.i2_orun;
1145 ctrl_reg3.i2_wtm = val.i2_wtm;
1146 ctrl_reg3.i2_drdy = val.i2_drdy;
1147 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,
1148 (uint8_t *)&ctrl_reg3, 1);
1149 }
1150
1151 return ret;
1152 }
1153
1154 /**
1155 * @brief Select the signal that need to route on int2 pad.[get]
1156 *
1157 * @param ctx Read / write interface definitions.(ptr)
1158 * @param val Read CTRL_REG3 int2 pad.(ptr)
1159 * @retval Interface status (MANDATORY: return 0 -> no Error)
1160 *
1161 */
i3g4250d_pin_int2_route_get(const stmdev_ctx_t * ctx,i3g4250d_int2_route_t * val)1162 int32_t i3g4250d_pin_int2_route_get(const stmdev_ctx_t *ctx,
1163 i3g4250d_int2_route_t *val)
1164 {
1165 i3g4250d_ctrl_reg3_t ctrl_reg3;
1166 int32_t ret;
1167
1168 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
1169 (uint8_t *)&ctrl_reg3, 1);
1170 val->i2_empty = ctrl_reg3.i2_empty;
1171 val->i2_orun = ctrl_reg3.i2_orun;
1172 val->i2_wtm = ctrl_reg3.i2_wtm;
1173 val->i2_drdy = ctrl_reg3.i2_drdy;
1174
1175 return ret;
1176 }
1177 /**
1178 * @brief Push-pull/open drain selection on interrupt pads.[set]
1179 *
1180 * @param ctx Read / write interface definitions.(ptr)
1181 * @param val Change the values of pp_od in reg CTRL_REG3
1182 * @retval Interface status (MANDATORY: return 0 -> no Error)
1183 *
1184 */
1185
i3g4250d_pin_mode_set(const stmdev_ctx_t * ctx,i3g4250d_pp_od_t val)1186 int32_t i3g4250d_pin_mode_set(const stmdev_ctx_t *ctx, i3g4250d_pp_od_t val)
1187 {
1188 i3g4250d_ctrl_reg3_t ctrl_reg3;
1189 int32_t ret;
1190
1191 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
1192 (uint8_t *)&ctrl_reg3, 1);
1193
1194 if (ret == 0)
1195 {
1196 ctrl_reg3.pp_od = (uint8_t)val;
1197 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,
1198 (uint8_t *)&ctrl_reg3, 1);
1199 }
1200
1201 return ret;
1202 }
1203
1204 /**
1205 * @brief Push-pull/open drain selection on interrupt pads.[get]
1206 *
1207 * @param ctx Read / write interface definitions.(ptr)
1208 * @param val Get the values of pp_od in reg CTRL_REG3.(ptr)
1209 * @retval Interface status (MANDATORY: return 0 -> no Error)
1210 *
1211 */
i3g4250d_pin_mode_get(const stmdev_ctx_t * ctx,i3g4250d_pp_od_t * val)1212 int32_t i3g4250d_pin_mode_get(const stmdev_ctx_t *ctx,
1213 i3g4250d_pp_od_t *val)
1214 {
1215 i3g4250d_ctrl_reg3_t ctrl_reg3;
1216 int32_t ret;
1217
1218 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
1219 (uint8_t *)&ctrl_reg3, 1);
1220
1221 switch (ctrl_reg3.pp_od)
1222 {
1223 case I3G4250D_PUSH_PULL:
1224 *val = I3G4250D_PUSH_PULL;
1225 break;
1226
1227 case I3G4250D_OPEN_DRAIN:
1228 *val = I3G4250D_OPEN_DRAIN;
1229 break;
1230
1231 default:
1232 *val = I3G4250D_PUSH_PULL;
1233 break;
1234 }
1235
1236 return ret;
1237 }
1238
1239 /**
1240 * @brief Pin active-high/low.[set]
1241 *
1242 * @param ctx Read / write interface definitions.(ptr)
1243 * @param val Change the values of h_lactive in reg CTRL_REG3.
1244 * @retval Interface status (MANDATORY: return 0 -> no Error)
1245 *
1246 */
i3g4250d_pin_polarity_set(const stmdev_ctx_t * ctx,i3g4250d_h_lactive_t val)1247 int32_t i3g4250d_pin_polarity_set(const stmdev_ctx_t *ctx,
1248 i3g4250d_h_lactive_t val)
1249 {
1250 i3g4250d_ctrl_reg3_t ctrl_reg3;
1251 int32_t ret;
1252
1253 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
1254 (uint8_t *)&ctrl_reg3, 1);
1255
1256 if (ret == 0)
1257 {
1258 ctrl_reg3.h_lactive = (uint8_t)val;
1259 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG3,
1260 (uint8_t *)&ctrl_reg3, 1);
1261 }
1262
1263 return ret;
1264 }
1265
1266 /**
1267 * @brief Pin active-high/low.[get]
1268 *
1269 * @param ctx Read / write interface definitions.(ptr)
1270 * @param val Get the values of h_lactive in reg CTRL_REG3.(ptr)
1271 * @retval Interface status (MANDATORY: return 0 -> no Error)
1272 *
1273 */
i3g4250d_pin_polarity_get(const stmdev_ctx_t * ctx,i3g4250d_h_lactive_t * val)1274 int32_t i3g4250d_pin_polarity_get(const stmdev_ctx_t *ctx,
1275 i3g4250d_h_lactive_t *val)
1276 {
1277 i3g4250d_ctrl_reg3_t ctrl_reg3;
1278 int32_t ret;
1279
1280 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG3,
1281 (uint8_t *)&ctrl_reg3, 1);
1282
1283 switch (ctrl_reg3.h_lactive)
1284 {
1285 case I3G4250D_ACTIVE_HIGH:
1286 *val = I3G4250D_ACTIVE_HIGH;
1287 break;
1288
1289 case I3G4250D_ACTIVE_LOW:
1290 *val = I3G4250D_ACTIVE_LOW;
1291 break;
1292
1293 default:
1294 *val = I3G4250D_ACTIVE_HIGH;
1295 break;
1296 }
1297
1298 return ret;
1299 }
1300
1301 /**
1302 * @brief Latched/pulsed interrupt.[set]
1303 *
1304 * @param ctx Read / write interface definitions.(ptr)
1305 * @param val Change the values of lir in reg INT1_CFG.
1306 * @retval Interface status (MANDATORY: return 0 -> no Error)
1307 *
1308 */
i3g4250d_int_notification_set(const stmdev_ctx_t * ctx,i3g4250d_lir_t val)1309 int32_t i3g4250d_int_notification_set(const stmdev_ctx_t *ctx,
1310 i3g4250d_lir_t val)
1311 {
1312 i3g4250d_int1_cfg_t int1_cfg;
1313 int32_t ret;
1314
1315 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1316
1317 if (ret == 0)
1318 {
1319 int1_cfg.lir = (uint8_t)val;
1320 ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1321 }
1322
1323 return ret;
1324 }
1325
1326 /**
1327 * @brief Latched/pulsed interrupt.[get]
1328 *
1329 * @param ctx Read / write interface definitions.(ptr)
1330 * @param val Get the values of lir in reg INT1_CFG.(ptr)
1331 * @retval Interface status (MANDATORY: return 0 -> no Error)
1332 *
1333 */
i3g4250d_int_notification_get(const stmdev_ctx_t * ctx,i3g4250d_lir_t * val)1334 int32_t i3g4250d_int_notification_get(const stmdev_ctx_t *ctx,
1335 i3g4250d_lir_t *val)
1336 {
1337 i3g4250d_int1_cfg_t int1_cfg;
1338 int32_t ret;
1339
1340 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1341
1342 switch (int1_cfg.lir)
1343 {
1344 case I3G4250D_INT_PULSED:
1345 *val = I3G4250D_INT_PULSED;
1346 break;
1347
1348 case I3G4250D_INT_LATCHED:
1349 *val = I3G4250D_INT_LATCHED;
1350 break;
1351
1352 default:
1353 *val = I3G4250D_INT_PULSED;
1354 break;
1355 }
1356
1357 return ret;
1358 }
1359
1360 /**
1361 * @}
1362 *
1363 */
1364
1365 /**
1366 * @defgroup I3G4250D_ interrupt_on_threshold
1367 * @brief This section groups all the functions that manage the event
1368 * generation on threshold.
1369 * @{
1370 *
1371 */
1372
1373 /**
1374 * @brief Configure the interrupt threshold sign.[set]
1375 *
1376 * @param ctx Read / write interface definitions.(ptr)
1377 * @param val Struct of registers INT1_CFG
1378 * @retval Interface status (MANDATORY: return 0 -> no Error)
1379 *
1380 */
i3g4250d_int_on_threshold_conf_set(const stmdev_ctx_t * ctx,i3g4250d_int1_cfg_t * val)1381 int32_t i3g4250d_int_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1382 i3g4250d_int1_cfg_t *val)
1383 {
1384 int32_t ret;
1385
1386 ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *) val, 1);
1387
1388 return ret;
1389 }
1390
1391 /**
1392 * @brief Configure the interrupt threshold sign.[get]
1393 *
1394 * @param ctx Read / write interface definitions.(ptr)
1395 * @param val Struct of registers from INT1_CFG to.(ptr)
1396 * @retval Interface status (MANDATORY: return 0 -> no Error)
1397 *
1398 */
i3g4250d_int_on_threshold_conf_get(const stmdev_ctx_t * ctx,i3g4250d_int1_cfg_t * val)1399 int32_t i3g4250d_int_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1400 i3g4250d_int1_cfg_t *val)
1401 {
1402 int32_t ret;
1403
1404 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *) val, 1);
1405
1406 return ret;
1407 }
1408 /**
1409 * @brief AND/OR combination of interrupt events.[set]
1410 *
1411 * @param ctx Read / write interface definitions.(ptr)
1412 * @param val Change the values of and_or in reg INT1_CFG
1413 * @retval Interface status (MANDATORY: return 0 -> no Error)
1414 *
1415 */
i3g4250d_int_on_threshold_mode_set(const stmdev_ctx_t * ctx,i3g4250d_and_or_t val)1416 int32_t i3g4250d_int_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1417 i3g4250d_and_or_t val)
1418 {
1419 i3g4250d_int1_cfg_t int1_cfg;
1420 int32_t ret;
1421
1422 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1423
1424 if (ret == 0)
1425 {
1426 int1_cfg.and_or = (uint8_t)val;
1427 ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1428 }
1429
1430 return ret;
1431 }
1432
1433 /**
1434 * @brief AND/OR combination of interrupt events.[get]
1435 *
1436 * @param ctx Read / write interface definitions.(ptr)
1437 * @param val Get the values of and_or in reg INT1_CFG.(ptr)
1438 * @retval Interface status (MANDATORY: return 0 -> no Error)
1439 *
1440 */
i3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t * ctx,i3g4250d_and_or_t * val)1441 int32_t i3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1442 i3g4250d_and_or_t *val)
1443 {
1444 i3g4250d_int1_cfg_t int1_cfg;
1445 int32_t ret;
1446
1447 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1448
1449 switch (int1_cfg.and_or)
1450 {
1451 case I3G4250D_INT1_ON_TH_OR:
1452 *val = I3G4250D_INT1_ON_TH_OR;
1453 break;
1454
1455 case I3G4250D_INT1_ON_TH_AND:
1456 *val = I3G4250D_INT1_ON_TH_AND;
1457 break;
1458
1459 default:
1460 *val = I3G4250D_INT1_ON_TH_OR;
1461 break;
1462 }
1463
1464 return ret;
1465 }
1466
1467 /**
1468 * @brief int_on_threshold_src: [get]
1469 *
1470 * @param ctx Read / write interface definitions.(ptr)
1471 * @param val Union of registers from INT1_SRC to.(ptr)
1472 * @retval Interface status (MANDATORY: return 0 -> no Error)
1473 *
1474 */
i3g4250d_int_on_threshold_src_get(const stmdev_ctx_t * ctx,i3g4250d_int1_src_t * val)1475 int32_t i3g4250d_int_on_threshold_src_get(const stmdev_ctx_t *ctx,
1476 i3g4250d_int1_src_t *val)
1477 {
1478 int32_t ret;
1479
1480 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_SRC, (uint8_t *) val, 1);
1481
1482 return ret;
1483 }
1484
1485 /**
1486 * @brief Interrupt threshold on X.[set]
1487 *
1488 * @param ctx Read / write interface definitions.(ptr)
1489 * @param val Change the values of thsx in reg INT1_TSH_XH
1490 * @retval Interface status (MANDATORY: return 0 -> no Error)
1491 *
1492 */
i3g4250d_int_x_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)1493 int32_t i3g4250d_int_x_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
1494 {
1495 i3g4250d_int1_tsh_xh_t int1_tsh_xh;
1496 i3g4250d_int1_tsh_xl_t int1_tsh_xl;
1497 int32_t ret;
1498
1499 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_XH,
1500 (uint8_t *)&int1_tsh_xh, 1);
1501
1502 if (ret == 0)
1503 {
1504 int1_tsh_xh.thsx = (uint8_t)(val / 256U) & 0x7FU;
1505 ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_XH,
1506 (uint8_t *)&int1_tsh_xh, 1);
1507 }
1508
1509 if (ret == 0)
1510 {
1511 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_XL,
1512 (uint8_t *)&int1_tsh_xl, 1);
1513 }
1514
1515 if (ret == 0)
1516 {
1517 int1_tsh_xl.thsx = (uint8_t)(val - (int1_tsh_xh.thsx * 256U));
1518 ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_XL,
1519 (uint8_t *)&int1_tsh_xl, 1);
1520 }
1521
1522 return ret;
1523 }
1524
1525 /**
1526 * @brief Interrupt threshold on X.[get]
1527 *
1528 * @param ctx Read / write interface definitions.(ptr)
1529 * @param val Get the values of thsx in reg INT1_TSH_XH.(ptr)
1530 * @retval Interface status (MANDATORY: return 0 -> no Error)
1531 *
1532 */
i3g4250d_int_x_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)1533 int32_t i3g4250d_int_x_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val)
1534 {
1535 i3g4250d_int1_tsh_xh_t int1_tsh_xh;
1536 i3g4250d_int1_tsh_xl_t int1_tsh_xl;
1537 int32_t ret;
1538
1539 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_XH,
1540 (uint8_t *)&int1_tsh_xh, 1);
1541
1542 if (ret == 0)
1543 {
1544 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_XL,
1545 (uint8_t *)&int1_tsh_xl, 1);
1546 *val = int1_tsh_xh.thsx;
1547 *val = *val * 256U;
1548 *val += int1_tsh_xl.thsx;
1549 }
1550
1551 return ret;
1552 }
1553
1554 /**
1555 * @brief Interrupt threshold on Y.[set]
1556 *
1557 * @param ctx Read / write interface definitions.(ptr)
1558 * @param val Change the values of thsy in reg INT1_TSH_YH
1559 * @retval Interface status (MANDATORY: return 0 -> no Error)
1560 *
1561 */
i3g4250d_int_y_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)1562 int32_t i3g4250d_int_y_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
1563 {
1564 i3g4250d_int1_tsh_yh_t int1_tsh_yh;
1565 i3g4250d_int1_tsh_yl_t int1_tsh_yl;
1566 int32_t ret;
1567
1568 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_YH,
1569 (uint8_t *)&int1_tsh_yh, 1);
1570 int1_tsh_yh.thsy = (uint8_t)(val / 256U) & 0x7FU;
1571
1572 if (ret == 0)
1573 {
1574 ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_YH,
1575 (uint8_t *)&int1_tsh_yh, 1);
1576 }
1577
1578 if (ret == 0)
1579 {
1580 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_YL,
1581 (uint8_t *)&int1_tsh_yl, 1);
1582 int1_tsh_yl.thsy = (uint8_t)(val - (int1_tsh_yh.thsy * 256U));
1583 }
1584
1585 if (ret == 0)
1586 {
1587 ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_YL,
1588 (uint8_t *)&int1_tsh_yl, 1);
1589 }
1590
1591 return ret;
1592 }
1593
1594 /**
1595 * @brief Interrupt threshold on Y.[get]
1596 *
1597 * @param ctx Read / write interface definitions.(ptr)
1598 * @param val Get the values of thsy in reg INT1_TSH_YH.(ptr)
1599 * @retval Interface status (MANDATORY: return 0 -> no Error)
1600 *
1601 */
i3g4250d_int_y_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)1602 int32_t i3g4250d_int_y_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val)
1603 {
1604 i3g4250d_int1_tsh_yh_t int1_tsh_yh;
1605 i3g4250d_int1_tsh_yl_t int1_tsh_yl;
1606 int32_t ret;
1607
1608 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_YH,
1609 (uint8_t *)&int1_tsh_yh, 1);
1610
1611 if (ret == 0)
1612 {
1613 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_YL,
1614 (uint8_t *)&int1_tsh_yl, 1);
1615 *val = int1_tsh_yh.thsy;
1616 *val = *val * 256U;
1617 *val += int1_tsh_yl.thsy;
1618 }
1619
1620 return ret;
1621 }
1622
1623 /**
1624 * @brief Interrupt threshold on Z.[set]
1625 *
1626 * @param ctx Read / write interface definitions.(ptr)
1627 * @param val Change the values of thsz in reg INT1_TSH_ZH.
1628 * @retval Interface status (MANDATORY: return 0 -> no Error)
1629 *
1630 */
i3g4250d_int_z_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)1631 int32_t i3g4250d_int_z_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
1632 {
1633 i3g4250d_int1_tsh_zh_t int1_tsh_zh;
1634 i3g4250d_int1_tsh_zl_t int1_tsh_zl;
1635 int32_t ret;
1636
1637 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_ZH,
1638 (uint8_t *)&int1_tsh_zh, 1);
1639 int1_tsh_zh.thsz = (uint8_t)(val / 256U) & 0x7FU;;
1640
1641 if (ret == 0)
1642 {
1643 ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_ZH,
1644 (uint8_t *)&int1_tsh_zh, 1);
1645 }
1646
1647 if (ret == 0)
1648 {
1649 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_ZL,
1650 (uint8_t *)&int1_tsh_zl, 1);
1651 int1_tsh_zl.thsz = (uint8_t)(val - (int1_tsh_zh.thsz * 256U));
1652 }
1653
1654 if (ret == 0)
1655 {
1656 ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_TSH_ZL,
1657 (uint8_t *)&int1_tsh_zl, 1);
1658 }
1659
1660 return ret;
1661 }
1662
1663 /**
1664 * @brief Interrupt threshold on Z.[get]
1665 *
1666 * @param ctx Read / write interface definitions.(ptr)
1667 * @param val Get the values of thsz in reg INT1_TSH_ZH.(ptr)
1668 * @retval Interface status (MANDATORY: return 0 -> no Error)
1669 *
1670 */
i3g4250d_int_z_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)1671 int32_t i3g4250d_int_z_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val)
1672 {
1673 i3g4250d_int1_tsh_zh_t int1_tsh_zh;
1674 i3g4250d_int1_tsh_zl_t int1_tsh_zl;
1675 int32_t ret;
1676
1677 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_ZH,
1678 (uint8_t *)&int1_tsh_zh, 1);
1679
1680 if (ret == 0)
1681 {
1682 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_TSH_ZL,
1683 (uint8_t *)&int1_tsh_zl, 1);
1684 *val = int1_tsh_zh.thsz;
1685 *val = *val * 256U;
1686 *val += int1_tsh_zl.thsz;
1687 }
1688
1689 return ret;
1690 }
1691
1692 /**
1693 * @brief Durationvalue.[set]
1694 *
1695 * @param ctx Read / write interface definitions.(ptr)
1696 * @param val Change the values of d in reg INT1_DURATION
1697 * @retval Interface status (MANDATORY: return 0 -> no Error)
1698 *
1699 */
i3g4250d_int_on_threshold_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1700 int32_t i3g4250d_int_on_threshold_dur_set(const stmdev_ctx_t *ctx,
1701 uint8_t val)
1702 {
1703 i3g4250d_int1_duration_t int1_duration;
1704 int32_t ret;
1705
1706 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_DURATION,
1707 (uint8_t *)&int1_duration, 1);
1708
1709 if (ret == 0)
1710 {
1711 int1_duration.d = val;
1712
1713 if (val != PROPERTY_DISABLE)
1714 {
1715 int1_duration.wait = PROPERTY_ENABLE;
1716 }
1717
1718 else
1719 {
1720 int1_duration.wait = PROPERTY_DISABLE;
1721 }
1722
1723 ret = i3g4250d_write_reg(ctx, I3G4250D_INT1_DURATION,
1724 (uint8_t *)&int1_duration, 1);
1725 }
1726
1727 return ret;
1728 }
1729
1730 /**
1731 * @brief Durationvalue.[get]
1732 *
1733 * @param ctx Read / write interface definitions.(ptr)
1734 * @param val Get the values of d in reg INT1_DURATION.(ptr)
1735 * @retval Interface status (MANDATORY: return 0 -> no Error)
1736 *
1737 */
i3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1738 int32_t i3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t *ctx,
1739 uint8_t *val)
1740 {
1741 i3g4250d_int1_duration_t int1_duration;
1742 int32_t ret;
1743
1744 ret = i3g4250d_read_reg(ctx, I3G4250D_INT1_DURATION,
1745 (uint8_t *)&int1_duration, 1);
1746 *val = int1_duration.d;
1747
1748 return ret;
1749 }
1750
1751 /**
1752 * @}
1753 *
1754 */
1755
1756 /**
1757 * @defgroup I3G4250D_fifo
1758 * @brief This section group all the functions concerning the fifo usage
1759 * @{
1760 *
1761 */
1762
1763 /**
1764 * @brief FIFOenable.[set]
1765 *
1766 * @param ctx Read / write interface definitions.(ptr)
1767 * @param val Change the values of fifo_en in reg CTRL_REG5
1768 * @retval Interface status (MANDATORY: return 0 -> no Error)
1769 *
1770 */
i3g4250d_fifo_enable_set(const stmdev_ctx_t * ctx,uint8_t val)1771 int32_t i3g4250d_fifo_enable_set(const stmdev_ctx_t *ctx, uint8_t val)
1772 {
1773 i3g4250d_ctrl_reg5_t ctrl_reg5;
1774 int32_t ret;
1775
1776 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
1777 (uint8_t *)&ctrl_reg5, 1);
1778
1779 if (ret == 0)
1780 {
1781 ctrl_reg5.fifo_en = val;
1782 ret = i3g4250d_write_reg(ctx, I3G4250D_CTRL_REG5,
1783 (uint8_t *)&ctrl_reg5, 1);
1784 }
1785
1786 return ret;
1787 }
1788
1789 /**
1790 * @brief FIFOenable.[get]
1791 *
1792 * @param ctx Read / write interface definitions.(ptr)
1793 * @param val Get the values of fifo_en in reg CTRL_REG5.(ptr)
1794 * @retval Interface status (MANDATORY: return 0 -> no Error)
1795 *
1796 */
i3g4250d_fifo_enable_get(const stmdev_ctx_t * ctx,uint8_t * val)1797 int32_t i3g4250d_fifo_enable_get(const stmdev_ctx_t *ctx, uint8_t *val)
1798 {
1799 i3g4250d_ctrl_reg5_t ctrl_reg5;
1800 int32_t ret;
1801
1802 ret = i3g4250d_read_reg(ctx, I3G4250D_CTRL_REG5,
1803 (uint8_t *)&ctrl_reg5, 1);
1804 *val = ctrl_reg5.fifo_en;
1805
1806 return ret;
1807 }
1808
1809 /**
1810 * @brief FIFO watermark level selection.[set]
1811 *
1812 * @param ctx Read / write interface definitions.(ptr)
1813 * @param val Change the values of wtm in reg FIFO_CTRL_REG
1814 * @retval Interface status (MANDATORY: return 0 -> no Error)
1815 *
1816 */
i3g4250d_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)1817 int32_t i3g4250d_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
1818 {
1819 i3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
1820 int32_t ret;
1821
1822 ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_CTRL_REG,
1823 (uint8_t *)&fifo_ctrl_reg, 1);
1824
1825 if (ret == 0)
1826 {
1827 fifo_ctrl_reg.wtm = val;
1828 ret = i3g4250d_write_reg(ctx, I3G4250D_FIFO_CTRL_REG,
1829 (uint8_t *)&fifo_ctrl_reg, 1);
1830 }
1831
1832 return ret;
1833 }
1834
1835 /**
1836 * @brief FIFO watermark level selection.[get]
1837 *
1838 * @param ctx Read / write interface definitions.(ptr)
1839 * @param val Get the values of wtm in reg FIFO_CTRL_REG.(ptr)
1840 * @retval Interface status (MANDATORY: return 0 -> no Error)
1841 *
1842 */
i3g4250d_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)1843 int32_t i3g4250d_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
1844 {
1845 i3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
1846 int32_t ret;
1847
1848 ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_CTRL_REG,
1849 (uint8_t *)&fifo_ctrl_reg, 1);
1850 *val = fifo_ctrl_reg.wtm;
1851
1852 return ret;
1853 }
1854
1855 /**
1856 * @brief FIFO mode selection.[set]
1857 *
1858 * @param ctx Read / write interface definitions.(ptr)
1859 * @param val Change the values of fm in reg FIFO_CTRL_REG
1860 * @retval Interface status (MANDATORY: return 0 -> no Error)
1861 *
1862 */
i3g4250d_fifo_mode_set(const stmdev_ctx_t * ctx,i3g4250d_fifo_mode_t val)1863 int32_t i3g4250d_fifo_mode_set(const stmdev_ctx_t *ctx,
1864 i3g4250d_fifo_mode_t val)
1865 {
1866 i3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
1867 int32_t ret;
1868
1869 ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_CTRL_REG,
1870 (uint8_t *)&fifo_ctrl_reg, 1);
1871
1872 if (ret == 0)
1873 {
1874 fifo_ctrl_reg.fm = (uint8_t)val;
1875 ret = i3g4250d_write_reg(ctx, I3G4250D_FIFO_CTRL_REG,
1876 (uint8_t *)&fifo_ctrl_reg, 1);
1877 }
1878
1879 return ret;
1880 }
1881
1882 /**
1883 * @brief FIFO mode selection.[get]
1884 *
1885 * @param ctx Read / write interface definitions.(ptr)
1886 * @param val Get the values of fm in reg FIFO_CTRL_REG.(ptr)
1887 * @retval Interface status (MANDATORY: return 0 -> no Error)
1888 *
1889 */
i3g4250d_fifo_mode_get(const stmdev_ctx_t * ctx,i3g4250d_fifo_mode_t * val)1890 int32_t i3g4250d_fifo_mode_get(const stmdev_ctx_t *ctx,
1891 i3g4250d_fifo_mode_t *val)
1892 {
1893 i3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg;
1894 int32_t ret;
1895
1896 ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_CTRL_REG,
1897 (uint8_t *)&fifo_ctrl_reg, 1);
1898
1899 switch (fifo_ctrl_reg.fm)
1900 {
1901 case I3G4250D_FIFO_BYPASS_MODE:
1902 *val = I3G4250D_FIFO_BYPASS_MODE;
1903 break;
1904
1905 case I3G4250D_FIFO_MODE:
1906 *val = I3G4250D_FIFO_MODE;
1907 break;
1908
1909 case I3G4250D_FIFO_STREAM_MODE:
1910 *val = I3G4250D_FIFO_STREAM_MODE;
1911 break;
1912
1913 default:
1914 *val = I3G4250D_FIFO_BYPASS_MODE;
1915 break;
1916 }
1917
1918 return ret;
1919 }
1920
1921 /**
1922 * @brief FIFO stored data level[get]
1923 *
1924 * @param ctx Read / write interface definitions.(ptr)
1925 * @param val Get the values of fss in reg FIFO_SRC_REG.(ptr)
1926 * @retval Interface status (MANDATORY: return 0 -> no Error)
1927 *
1928 */
i3g4250d_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)1929 int32_t i3g4250d_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
1930 {
1931 i3g4250d_fifo_src_reg_t fifo_src_reg;
1932 int32_t ret;
1933
1934 ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG,
1935 (uint8_t *)&fifo_src_reg, 1);
1936 *val = fifo_src_reg.fss;
1937
1938 return ret;
1939 }
1940
1941 /**
1942 * @brief FIFOemptybit.[get]
1943 *
1944 * @param ctx Read / write interface definitions.(ptr)
1945 * @param val Get the values of empty in reg FIFO_SRC_REG.(ptr)
1946 * @retval Interface status (MANDATORY: return 0 -> no Error)
1947 *
1948 */
i3g4250d_fifo_empty_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1949 int32_t i3g4250d_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1950 {
1951 i3g4250d_fifo_src_reg_t fifo_src_reg;
1952 int32_t ret;
1953
1954 ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG,
1955 (uint8_t *)&fifo_src_reg, 1);
1956 *val = fifo_src_reg.empty;
1957
1958 return ret;
1959 }
1960
1961 /**
1962 * @brief Overrun bit status.[get]
1963 *
1964 * @param ctx Read / write interface definitions.(ptr)
1965 * @param val Get the values of ovrn in reg FIFO_SRC_REG.(ptr)
1966 * @retval Interface status (MANDATORY: return 0 -> no Error)
1967 *
1968 */
i3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1969 int32_t i3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1970 {
1971 i3g4250d_fifo_src_reg_t fifo_src_reg;
1972 int32_t ret;
1973
1974 ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG,
1975 (uint8_t *)&fifo_src_reg, 1);
1976 *val = fifo_src_reg.ovrn;
1977
1978 return ret;
1979 }
1980
1981 /**
1982 * @brief Watermark status:[get]
1983 * 0: FIFO filling is lower than WTM level;
1984 * 1: FIFO filling is equal or higher than WTM level)
1985 *
1986 * @param ctx Read / write interface definitions.(ptr)
1987 * @param val Get the values of wtm in reg FIFO_SRC_REG.(ptr)
1988 * @retval Interface status (MANDATORY: return 0 -> no Error)
1989 *
1990 */
1991
i3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)1992 int32_t i3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
1993 {
1994 i3g4250d_fifo_src_reg_t fifo_src_reg;
1995 int32_t ret;
1996
1997 ret = i3g4250d_read_reg(ctx, I3G4250D_FIFO_SRC_REG,
1998 (uint8_t *)&fifo_src_reg, 1);
1999 *val = fifo_src_reg.wtm;
2000
2001 return ret;
2002 }
2003
2004 /**
2005 * @}
2006 *
2007 */
2008
2009 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2010
