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Searched refs:EMU (Results 1 – 25 of 429) sorted by relevance

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/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_emu.c423 vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) in emState()
438 EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); in emState()
471 if ((EMU->CTRL & _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK) != 0U) { in emState()
624 emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL; in dcdcFetCntSet()
625 tmp = EMU->DCDCMISCCTRL in dcdcFetCntSet()
629 EMU->DCDCMISCCTRL = tmp; in dcdcFetCntSet()
632 EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg; in dcdcFetCntSet()
644 if ((EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) { in dcdcHsFixLnBlock()
667 uint32_t em23vs = (EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) >> _EMU_CTRL_EM23VSCALE_SHIFT; in vScaleDownEM23Setup()
668 uint32_t em01vs = (EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT; in vScaleDownEM23Setup()
[all …]
Dem_rmu.c256 BUS_RegBitWrite(&EMU->RSTCTRL, (uint32_t)shift, mode ? 1 : 0); in RMU_ResetControl()
281 EMU->CMD_SET = EMU_CMD_RSTCAUSECLR; in RMU_ResetCauseClear()
292 locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED; in RMU_ResetCauseClear()
297 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); in RMU_ResetCauseClear()
298 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); in RMU_ResetCauseClear()
332 rstCause = EMU->RSTCAUSE; in RMU_ResetCauseGet()
Dem_msc.c801 EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); in MSC_Init()
802 EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); in MSC_Init()
1129 EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); in MSC_WriteWordI()
1130 EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); in MSC_WriteWordI()
1243 EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); in MSC_ErasePage()
1244 EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); in MSC_ErasePage()
/hal_silabs-latest/gecko/emlib/src/
Dem_emu.c418 vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) in emState()
433 EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); in emState()
466 if ((EMU->CTRL & _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK) != 0U) { in emState()
619 emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL; in dcdcFetCntSet()
620 tmp = EMU->DCDCMISCCTRL in dcdcFetCntSet()
624 EMU->DCDCMISCCTRL = tmp; in dcdcFetCntSet()
627 EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg; in dcdcFetCntSet()
639 if ((EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) { in dcdcHsFixLnBlock()
662 uint32_t em23vs = (EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) >> _EMU_CTRL_EM23VSCALE_SHIFT; in vScaleDownEM23Setup()
663 uint32_t em01vs = (EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT; in vScaleDownEM23Setup()
[all …]
Dem_rmu.c250 BUS_RegBitWrite(&EMU->RSTCTRL, (uint32_t)shift, mode ? 1 : 0); in RMU_ResetControl()
271 EMU->CMD_SET = EMU_CMD_RSTCAUSECLR; in RMU_ResetCauseClear()
282 locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED; in RMU_ResetCauseClear()
287 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); in RMU_ResetCauseClear()
288 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); in RMU_ResetCauseClear()
317 return EMU->RSTCAUSE; in RMU_ResetCauseGet()
Dem_msc.c799 EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); in MSC_Init()
800 EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); in MSC_Init()
1127 EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); in MSC_WriteWordI()
1128 EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); in MSC_WriteWordI()
1241 EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); in MSC_ErasePage()
1242 EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); in MSC_ErasePage()
/hal_silabs-latest/simplicity_sdk/platform/emlib/inc/
Dem_emu.h1403 while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) { in EMU_VScaleWait()
1420 ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) in EMU_VScaleGet()
1436 return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U; in EMU_VmonStatusGet()
1452 EMU->IF_CLR = flags; in EMU_IntClear()
1454 EMU->IFC = flags; in EMU_IntClear()
1469 EMU->IEN_CLR = flags; in EMU_IntDisable()
1471 EMU->IEN &= ~flags; in EMU_IntDisable()
1491 EMU->IEN_SET = flags; in EMU_IntEnable()
1493 EMU->IEN |= flags; in EMU_IntEnable()
1508 EMU->EFPIEN_CLR = flags; in EMU_EFPIntDisable()
[all …]
Dem_chip.h253 BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); in CHIP_Init()
456 EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; in CHIP_Reset()
457 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; in CHIP_Reset()
460 if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) { in CHIP_Reset()
465 uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; in CHIP_Reset()
Dem_dbg.h115 EMU->CTRL_SET = EMU_CTRL_EM2DBGEN; in DBG_EM2DebugEnable()
117 EMU->CTRL_CLR = EMU_CTRL_EM2DBGEN; in DBG_EM2DebugEnable()
Dem_gpio.h866 uint32_t mode = EMU->EM4CTRL & _EMU_EM4CTRL_EM4IORETMODE_MASK; in GPIO_EM4SetPinRetention()
872 EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) in GPIO_EM4SetPinRetention()
875 EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) in GPIO_EM4SetPinRetention()
/hal_silabs-latest/gecko/emlib/inc/
Dem_emu.h1332 while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) { in EMU_VScaleWait()
1349 ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) in EMU_VScaleGet()
1365 return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U; in EMU_VmonStatusGet()
1381 EMU->IF_CLR = flags; in EMU_IntClear()
1383 EMU->IFC = flags; in EMU_IntClear()
1398 EMU->IEN_CLR = flags; in EMU_IntDisable()
1400 EMU->IEN &= ~flags; in EMU_IntDisable()
1420 EMU->IEN_SET = flags; in EMU_IntEnable()
1422 EMU->IEN |= flags; in EMU_IntEnable()
1437 EMU->EFPIEN_CLR = flags; in EMU_EFPIntDisable()
[all …]
Dem_chip.h249 BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); in CHIP_Init()
435 EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; in CHIP_Reset()
436 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; in CHIP_Reset()
439 if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) { in CHIP_Reset()
444 uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; in CHIP_Reset()
Dem_dbg.h119 EMU->CTRL_SET = EMU_CTRL_EM2DBGEN; in DBG_EM2DebugEnable()
121 EMU->CTRL_CLR = EMU_CTRL_EM2DBGEN; in DBG_EM2DebugEnable()
Dem_gpio.h781 uint32_t mode = EMU->EM4CTRL & _EMU_EM4CTRL_EM4IORETMODE_MASK; in GPIO_EM4SetPinRetention()
787 EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) in GPIO_EM4SetPinRetention()
790 EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) in GPIO_EM4SetPinRetention()
/hal_silabs-latest/simplicity_sdk/platform/service/power_manager/src/common/
Dsl_power_manager_em4.c94 EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) in sli_power_manager_init_em4()
139 uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) in sl_power_manager_enter_em4()
141 uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) in sl_power_manager_enter_em4()
145 EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; in sl_power_manager_enter_em4()
165 EMU->EM4CTRL = em4seq2; in sl_power_manager_enter_em4()
166 EMU->EM4CTRL = em4seq3; in sl_power_manager_enter_em4()
168 EMU->EM4CTRL = em4seq2; in sl_power_manager_enter_em4()
187 EMU->CMD = EMU_CMD_EM4UNLATCH; in sl_power_manager_em4_unlatch_pin_retention()
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG12B/Source/
Dsystem_efm32pg12b.c311 EMU->DCDCCLIMCTRL |= 1U << _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT; in SystemInit()
312 EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) in SystemInit()
/hal_silabs-latest/gecko/Device/SiliconLabs/EFR32FG1P/Source/
Dsystem_efr32fg1p.c304 EMU->DCDCCLIMCTRL |= 1U << _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT; in SystemInit()
305 EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) in SystemInit()
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG1B/Source/
Dsystem_efm32pg1b.c311 EMU->DCDCCLIMCTRL |= 1U << _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT; in SystemInit()
312 EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) in SystemInit()
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32JG12B/Source/
Dsystem_efm32jg12b.c311 EMU->DCDCCLIMCTRL |= 1U << _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT; in SystemInit()
312 EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) in SystemInit()
/hal_silabs-latest/simplicity_sdk/platform/service/device_init/src/
Dsl_device_init_emu_s2.c39 EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM2DBGEN_MASK) in sl_device_init_emu()
/hal_silabs-latest/simplicity_sdk/platform/peripheral/inc/
Dsl_hal_gpio.h821 uint32_t mode = EMU->EM4CTRL & _EMU_EM4CTRL_EM4IORETMODE_MASK; in sl_hal_gpio_set_pin_em4_retention()
828 EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) in sl_hal_gpio_set_pin_em4_retention()
831 EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) in sl_hal_gpio_set_pin_em4_retention()
/hal_silabs-latest/simplicity_sdk/platform/service/power_manager/src/sleep_loop/
Dsl_power_manager.c217 EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM2DBGEN_MASK) in sl_power_manager_init()
/hal_silabs-latest/gecko/Device/SiliconLabs/EFM32PG1B/Include/
Defm32pg1b100f128gm32.h334 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ macro
Defm32pg1b100f128im32.h334 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ macro
Defm32pg1b100f256gm32.h334 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ macro

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