Lines Matching refs:EMU
418 vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) in emState()
433 EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); in emState()
466 if ((EMU->CTRL & _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK) != 0U) { in emState()
619 emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL; in dcdcFetCntSet()
620 tmp = EMU->DCDCMISCCTRL in dcdcFetCntSet()
624 EMU->DCDCMISCCTRL = tmp; in dcdcFetCntSet()
627 EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg; in dcdcFetCntSet()
639 if ((EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) { in dcdcHsFixLnBlock()
662 uint32_t em23vs = (EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) >> _EMU_CTRL_EM23VSCALE_SHIFT; in vScaleDownEM23Setup()
663 uint32_t em01vs = (EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT; in vScaleDownEM23Setup()
667 EMU->CTRL |= EMU_CTRL_EM23VSCALEAUTOWSEN; in vScaleDownEM23Setup()
675 EMU->CTRL &= ~EMU_CTRL_EM23VSCALEAUTOWSEN; in vScaleDownEM23Setup()
682 if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { in vScaleAfterWakeup()
801 EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG) in EMU_EM23Init()
802 : (EMU->CTRL & ~EMU_CTRL_EMVREG); in EMU_EM23Init()
804 EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG) in EMU_EM23Init()
805 : (EMU->CTRL & ~EMU_CTRL_EM23VREG); in EMU_EM23Init()
811 EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) in EMU_EM23Init()
1028 if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { in EMU_EnterEM2()
1228 if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { in EMU_EnterEM3()
1334 uint32_t em4conf = EMU->EM4CONF; in EMU_EM4Init()
1351 EMU->EM4CONF = em4conf; in EMU_EM4Init()
1356 uint32_t em4ctrl = EMU->EM4CTRL; in EMU_EM4Init()
1371 EMU->EM4CTRL = em4ctrl; in EMU_EM4Init()
1373 EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) in EMU_EM4Init()
1378 EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK) in EMU_EM4Init()
1431 uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) in EMU_EnterEM4()
1433 uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) in EMU_EnterEM4()
1436 uint32_t em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) in EMU_EnterEM4()
1438 uint32_t em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) in EMU_EnterEM4()
1449 if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { in EMU_EnterEM4()
1450 uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; in EMU_EnterEM4()
1476 if (EMU->EM4CTRL & EMU_EM4CTRL_EM4STATE_EM4H) { in EMU_EnterEM4()
1501 if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { in EMU_EnterEM4()
1502 if ((EMU->PWRCTRL & _EMU_PWRCTRL_ANASW_MASK) == EMU_PWRCTRL_ANASW_DVDD) { in EMU_EnterEM4()
1503 BUS_RegMaskedClear(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_MASK); in EMU_EnterEM4()
1525 EMU->EM4CTRL = em4seq2; in EMU_EnterEM4()
1526 EMU->EM4CTRL = em4seq3; in EMU_EnterEM4()
1528 EMU->EM4CTRL = em4seq2; in EMU_EnterEM4()
1530 EMU->CTRL = em4seq2; in EMU_EnterEM4()
1531 EMU->CTRL = em4seq3; in EMU_EnterEM4()
1533 EMU->CTRL = em4seq2;
1576 BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 1); in EMU_EnterEM4H()
1592 BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 0); in EMU_EnterEM4S()
1618 EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK; in EMU_MemPwrDown()
1620 EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK; in EMU_MemPwrDown()
1708 EMU->MEMCTRL = EMU->MEMCTRL | mask; in EMU_RamPowerDown()
1710 EMU->RAM0CTRL = EMU->RAM0CTRL | mask; in EMU_RamPowerDown()
1729 EMU->RAM1CTRL |= mask; in EMU_RamPowerDown()
1739 EMU->RAM2CTRL |= mask; in EMU_RamPowerDown()
1756 EMU->RAM0CTRL = 0x0UL; in EMU_RamPowerUp()
1759 EMU->RAM1CTRL = 0x0UL; in EMU_RamPowerUp()
1762 EMU->RAM2CTRL = 0x0UL; in EMU_RamPowerUp()
1791 EMU->EM23PERNORETAINCTRL = (uint32_t)periMask in EMU_PeripheralRetention()
1927 EMU->IF_CLR = EMU_IF_VSCALEDONE; in EMU_VScaleEM01()
1929 EMU->CMD = vScaleEM01Cmd(voltage); in EMU_VScaleEM01()
1933 while (((EMU->IF & EMU_IF_VSCALEDONE) == 0U) in EMU_VScaleEM01()
1934 && ((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U)) { in EMU_VScaleEM01()
1935 EFM_ASSERT((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U); in EMU_VScaleEM01()
1953 EMU->CMD = vScaleEM01Cmd(voltage); in EMU_VScaleEM01()
1980 reg = EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK in EMU_BUPDInit()
1990 EMU->PWRCONF = reg; in EMU_BUPDInit()
1993 reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK); in EMU_BUPDInit()
1995 EMU->BUINACT = reg; in EMU_BUPDInit()
1998 reg = EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK); in EMU_BUPDInit()
2000 EMU->BUACT = reg; in EMU_BUPDInit()
2003 reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK in EMU_BUPDInit()
2016 EMU->BUCTRL = reg; in EMU_BUPDInit()
2040 EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK) in EMU_BUThresholdSet()
2044 EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK) in EMU_BUThresholdSet()
2065 EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK) in EMU_BUThresRangeSet()
2069 EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK) in EMU_BUThresRangeSet()
2097 EMU->BUCTRL = reg; in EMU_BUInit()
2113 reg = EMU->BUCTRL & ~(_EMU_BUCTRL_DISMAXCOMP_MASK); in EMU_BUDisMaxCompSet()
2115 EMU->BUCTRL = reg; in EMU_BUDisMaxCompSet()
2131 reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUINACTPWRCON_MASK); in EMU_BUBuInactPwrConSet()
2133 EMU->BUCTRL = reg; in EMU_BUBuInactPwrConSet()
2149 reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUACTPWRCON_MASK); in EMU_BUBuActPwrConSet()
2151 EMU->BUCTRL = reg; in EMU_BUBuActPwrConSet()
2167 reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PWRRES_MASK); in EMU_BUPwrResSet()
2169 EMU->BUCTRL = reg; in EMU_BUPwrResSet()
2185 reg = EMU->BUCTRL & ~(_EMU_BUCTRL_VOUTRES_MASK); in EMU_BUVoutResSet()
2187 EMU->BUCTRL = reg; in EMU_BUVoutResSet()
2203 reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUVINPROBEEN_MASK); in EMU_BUBuVinProbeEnSet()
2205 EMU->BUCTRL = reg; in EMU_BUBuVinProbeEnSet()
2221 reg = EMU->BUCTRL & ~(_EMU_BUCTRL_STATEN_MASK); in EMU_BUStatEnSet()
2223 EMU->BUCTRL = reg; in EMU_BUStatEnSet()
2239 reg = EMU->BUCTRL & ~(_EMU_BUCTRL_EN_MASK); in EMU_BUEnableSet()
2241 EMU->BUCTRL = reg; in EMU_BUEnableSet()
2331 EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; in dcdcValidatedConfigSet()
2337 lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); in dcdcValidatedConfigSet()
2347 EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK; in dcdcValidatedConfigSet()
2348 EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS in dcdcValidatedConfigSet()
2358 dcdcTiming = EMU->DCDCTIMING; in dcdcValidatedConfigSet()
2366 EMU->DCDCTIMING = dcdcTiming; in dcdcValidatedConfigSet()
2398 pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK) in currentLimitersUpdate()
2420 EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK in currentLimitersUpdate()
2444 EMU->DCDCZDETCTRL = (EMU->DCDCZDETCTRL & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) in currentLimitersUpdate()
2478 EMU->DCDCLNCOMPCTRL = 0x57204077UL; in compCtrlSet()
2482 EMU->DCDCLNCOMPCTRL = 0xB7102137UL; in compCtrlSet()
2569 … EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; in lpCmpHystCalibrationLoad()
2581 …EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) | lpcmpHystSe… in lpCmpHystCalibrationLoad()
2707 EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; in EMU_DCDCInit()
2711 if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD) { in EMU_DCDCInit()
2761 EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK in EMU_DCDCInit()
2768 EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) in EMU_DCDCInit()
2806 BUS_RegBitWrite(&EMU->PWRCTRL, in EMU_DCDCInit()
2814 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; in EMU_DCDCInit()
2825 BUS_RegBitWrite(&EMU->PWRCTRL, in EMU_DCDCInit()
2846 dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); in EMU_DCDCModeSet()
2850 while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { in EMU_DCDCModeSet()
2852 currentDcdcMode = (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK); in EMU_DCDCModeSet()
2857 BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 1); in EMU_DCDCModeSet()
2864 BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); in EMU_DCDCModeSet()
2885 while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { in EMU_DCDCModeSet()
2887 EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE; in EMU_DCDCModeSet()
2894 while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { in EMU_DCDCModeSet()
2896 EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) in EMU_DCDCModeSet()
2901 while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { in EMU_DCDCModeSet()
2903 BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, in EMU_DCDCModeSet()
2924 dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); in EMU_DCDCModeEM23Set()
2928 while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { in EMU_DCDCModeEM23Set()
2930 EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODEEM23_MASK) in EMU_DCDCModeEM23Set()
2958 EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; in EMU_DCDCPowerOff()
2963 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; in EMU_DCDCPowerOff()
2965 EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; in EMU_DCDCPowerOff()
2970 while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { in EMU_DCDCPowerOff()
2972 EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF; in EMU_DCDCPowerOff()
2974 dcdcModeSet = (EMU->DCDCCTRL == EMU_DCDCCTRL_DCDCMODE_OFF); in EMU_DCDCPowerOff()
2995 (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK)); in EMU_DCDCConductionModeSet()
2998 ((EMU->DCDCLNFREQCTRL in EMU_DCDCConductionModeSet()
3006 while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { in EMU_DCDCConductionModeSet()
3011 EMU->DCDCMISCCTRL &= ~EMU_DCDCMISCCTRL_LNFORCECCM; in EMU_DCDCConductionModeSet()
3019 EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; in EMU_DCDCConductionModeSet()
3107 … ((EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) in EMU_DCDCOutputVoltageSet()
3117 ((EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) in EMU_DCDCOutputVoltageSet()
3156 …EMU->DCDCLNVCTRL = (EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MAS… in EMU_DCDCOutputVoltageSet()
3183 …EMU->DCDCLPVCTRL = (EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MAS… in EMU_DCDCOutputVoltageSet()
3202 uint32_t rcoBand = (EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) in EMU_DCDCOptimizeSlice()
3206 if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) in EMU_DCDCOptimizeSlice()
3215 } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) == 0U) in EMU_DCDCOptimizeSlice()
3224 } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) in EMU_DCDCOptimizeSlice()
3243 EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK in EMU_DCDCOptimizeSlice()
3261 forcedCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); in EMU_DCDCLnRcoBandSet()
3267 EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK) in EMU_DCDCLnRcoBandSet()
3370 EMU->BOOSTCTRL_CLR = EMU_BOOSTCTRL_BOOSTENCTRL; in EMU_BoostExternalShutdownEnable()
3372 EMU->BOOSTCTRL_SET = EMU_BOOSTCTRL_BOOSTENCTRL; in EMU_BoostExternalShutdownEnable()
3495 EMU->VREGVDDCMPCTRL = ((uint32_t)dcdcInit->cmpThreshold in EMU_DCDCInit()
3844 EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) in EMU_VmonInit()
3853 EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT) in EMU_VmonInit()
3860 EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT) in EMU_VmonInit()
3867 EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT) in EMU_VmonInit()
3876 EMU->VMONIO1CTRL = (thresholdCoarse << _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT) in EMU_VmonInit()
3886 EMU->VMONBUVDDCTRL = (thresholdCoarse << _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT) in EMU_VmonInit()
3928 EMU->VMONAVDDCTRL = ((riseThreshold / 10U) << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) in EMU_VmonHystInit()
3959 reg = &(EMU->VMONAVDDCTRL); in EMU_VmonEnable()
3963 reg = &(EMU->VMONALTAVDDCTRL); in EMU_VmonEnable()
3967 reg = &(EMU->VMONDVDDCTRL); in EMU_VmonEnable()
3971 reg = &(EMU->VMONIO0CTRL); in EMU_VmonEnable()
3976 reg = &(EMU->VMONIO1CTRL); in EMU_VmonEnable()
3982 reg = &(EMU->VMONBUVDDCTRL); in EMU_VmonEnable()
4036 return BUS_RegBitRead(&EMU->STATUS, bit) != 0U; in EMU_VmonChannelStatusGet()
4096 return ((float) ((EMU->TEMP & (_EMU_TEMP_TEMP_MASK | _EMU_TEMP_TEMPLSB_MASK) ) in EMU_TemperatureGet()
4112 val1 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) in EMU_TemperatureGet()
4114 val2 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) in EMU_TemperatureGet()
4134 EMU->CTRL_SET = EMU_CTRL_EFPDIRECTMODEEN; in EMU_EFPDirectModeEnable()
4136 EMU->CTRL_CLR = EMU_CTRL_EFPDIRECTMODEEN; in EMU_EFPDirectModeEnable()
4158 EMU->CTRL_SET = EMU_CTRL_EFPDRVDECOUPLE; in EMU_EFPDriveDecoupleSet()
4160 EMU->CTRL_CLR = EMU_CTRL_EFPDRVDECOUPLE; in EMU_EFPDriveDecoupleSet()
4180 EMU->CTRL_SET = EMU_CTRL_EFPDRVDVDD; in EMU_EFPDriveDvddSet()
4182 EMU->CTRL_CLR = EMU_CTRL_EFPDRVDVDD; in EMU_EFPDriveDvddSet()