1 /***************************************************************************//**
2 * @file
3 * @brief Energy Management Unit (EMU) peripheral API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30
31 #ifndef EM_EMU_H
32 #define EM_EMU_H
33
34 #include "em_device.h"
35 #include "sl_status.h"
36 #if defined(EMU_PRESENT)
37
38 #include <stdbool.h>
39 #include "em_bus.h"
40 #include "sl_common.h"
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /***************************************************************************//**
47 * @addtogroup emu
48 * @{
49 ******************************************************************************/
50
51 /*******************************************************************************
52 ******************************* DEFINES ***********************************
53 ******************************************************************************/
54
55 #if (defined(_EMU_STATUS_VSCALE_MASK) || defined(_EMU_CTRL_EM23VSCALE_MASK)) \
56 && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200)
57 /** Voltage scaling present */
58 #define EMU_VSCALE_PRESENT
59 #if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
60 /** Voltage scaling for EM01 present */
61 #define EMU_VSCALE_EM01_PRESENT
62 #endif
63 #endif
64
65 #if defined(_EMU_DCDCCTRL_MASK)
66 /** DC-DC buck converter present */
67 #define EMU_SERIES1_DCDC_BUCK_PRESENT
68 #endif
69
70 #if defined(_SILICON_LABS_DCDC_FEATURE) \
71 && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK) \
72 || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB))
73 /** DC-DC buck converter present */
74 #define EMU_SERIES2_DCDC_BUCK_PRESENT
75 #endif
76
77 #if defined(_SILICON_LABS_DCDC_FEATURE) \
78 && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST) \
79 || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB))
80 /** DC-DC boost converter present */
81 #define EMU_SERIES2_DCDC_BOOST_PRESENT
82 #endif
83
84 /*******************************************************************************
85 ******************************** ENUMS ************************************
86 ******************************************************************************/
87
88 #if defined(_EMU_EM4CONF_OSC_MASK)
89 /** EM4 duty oscillator. */
90 typedef enum {
91 /** Select ULFRCO as duty oscillator in EM4. */
92 emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
93 /** Select LFXO as duty oscillator in EM4. */
94 emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
95 /** Select LFRCO as duty oscillator in EM4. */
96 emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO
97 } EMU_EM4Osc_TypeDef;
98 #endif
99
100 #if defined(_EMU_BUCTRL_PROBE_MASK)
101 /** Backup Power Voltage Probe types. */
102 typedef enum {
103 /** Disable voltage probe. */
104 emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE,
105 /** Connect probe to VDD_DREG. */
106 emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG,
107 /** Connect probe to BU_IN. */
108 emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN,
109 /** Connect probe to BU_OUT. */
110 emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT
111 } EMU_Probe_TypeDef;
112 #endif
113
114 #if defined(_EMU_PWRCONF_PWRRES_MASK)
115 /** Backup Power Domain resistor selection. */
116 typedef enum {
117 /** Main power and backup power connected with RES0 series resistance. */
118 emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0,
119 /** Main power and backup power connected with RES1 series resistance. */
120 emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1,
121 /** Main power and backup power connected with RES2 series resistance. */
122 emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2,
123 /** Main power and backup power connected with RES3 series resistance. */
124 emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3,
125 } EMU_Resistor_TypeDef;
126 #endif
127
128 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
129 /** Backup Power Domain power connection. */
130 typedef enum {
131 /** No connection between main and backup power. */
132 emuPower_None = EMU_BUINACT_PWRCON_NONE,
133 /** Main power and backup power connected through diode,
134 allowing current from backup to main only. */
135 emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN,
136 /** Main power and backup power connected through diode,
137 allowing current from main to backup only. */
138 emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU,
139 /** Main power and backup power connected without diode. */
140 emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE,
141 } EMU_Power_TypeDef;
142 #endif
143
144 #if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK)
145 /** Backup Power Domain power connection configuration when not in backup mode selection. */
146 typedef enum {
147 /** No connection. */
148 emuBuBuInactPwrCon_None = EMU_BUCTRL_BUINACTPWRCON_NONE,
149 /** Allow power from main to backup. */
150 emuBuBuInactPwrCon_MainBu = EMU_BUCTRL_BUINACTPWRCON_MAINBU,
151 /** Allow power from backup to main. */
152 emuBuBuInactPwrCon_BuMain = EMU_BUCTRL_BUINACTPWRCON_BUMAIN,
153 /** Backup and main power are connected. */
154 emuBuBuInactPwrCon_NoDiode = EMU_BUCTRL_BUINACTPWRCON_NODIODE,
155 } EMU_BUBuInactPwrCon_TypeDef;
156 #endif
157
158 #if defined(_EMU_BUCTRL_BUACTPWRCON_MASK)
159 /** Backup Power Domain power connection configuration in backup mode selection. */
160 typedef enum {
161 /** No connection. */
162 emuBuBuActPwrCon_None = EMU_BUCTRL_BUACTPWRCON_NONE,
163 /** Allow power from main to backup. */
164 emuBuBuActPwrCon_MainBu = EMU_BUCTRL_BUACTPWRCON_MAINBU,
165 /** Allow power from backup to main. */
166 emuBuBuActPwrCon_BuMain = EMU_BUCTRL_BUACTPWRCON_BUMAIN,
167 /** Backup and main power are connected. */
168 emuBuBuActPwrCon_NoDiode = EMU_BUCTRL_BUACTPWRCON_NODIODE,
169 } EMU_BUBuActPwrCon_TypeDef;
170 #endif
171
172 #if defined(_EMU_BUCTRL_PWRRES_MASK)
173 /** Backup Power Domain resistor selection. */
174 typedef enum {
175 /** Main power and backup power connected with RES0 series resistance. */
176 emuBuPwrRes_Res0 = EMU_BUCTRL_PWRRES_RES0,
177 /** Main power and backup power connected with RES1 series resistance. */
178 emuBuPwrRes_Res1 = EMU_BUCTRL_PWRRES_RES1,
179 /** Main power and backup power connected with RES2 series resistance. */
180 emuBuPwrRes_Res2 = EMU_BUCTRL_PWRRES_RES2,
181 /** Main power and backup power connected with RES3 series resistance. */
182 emuBuPwrRes_Res3 = EMU_BUCTRL_PWRRES_RES3,
183 } EMU_BUPwrRes_TypeDef;
184 #endif
185
186 #if defined(_EMU_BUCTRL_VOUTRES_MASK)
187 /** Resistance between backup domain power supply and BU_VOUT. */
188 typedef enum {
189 /** BU_VOUT is not connected. */
190 emuBuVoutRes_Dis = EMU_BUCTRL_VOUTRES_DIS,
191 /** Enable weak switch. */
192 emuBuVoutRes_Weak = EMU_BUCTRL_VOUTRES_WEAK,
193 /** Enable medium switch. */
194 emuBuVoutRes_Med = EMU_BUCTRL_VOUTRES_MED,
195 /** Enable strong switch. */
196 emuBuVoutRes_Strong = EMU_BUCTRL_VOUTRES_STRONG,
197 } EMU_BUVoutRes_TypeDef;
198 #endif
199
200 /** BOD threshold setting selector, active or inactive mode. */
201 typedef enum {
202 /** Configure BOD threshold for active mode. */
203 emuBODMode_Active,
204 /** Configure BOD threshold for inactive mode. */
205 emuBODMode_Inactive,
206 } EMU_BODMode_TypeDef;
207
208 /** EM4 modes. */
209 typedef enum {
210 /** EM4 Shutoff. */
211 emuEM4Shutoff = 0,
212 /** EM4 Hibernate. */
213 emuEM4Hibernate = 1,
214 } EMU_EM4State_TypeDef;
215
216 #if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK)
217 /** EM4 Pin Retention Type. */
218 typedef enum {
219 /** No Retention: Pads enter reset state when entering EM4. */
220 emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,
221 /** Retention through EM4: Pads enter reset state when exiting EM4. */
222 emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,
223 /** Retention through EM4 and wakeup: call @ref EMU_UnlatchPinRetention() to
224 release pins from retention after EM4 wakeup. */
225 emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,
226 } EMU_EM4PinRetention_TypeDef;
227 #endif
228
229 #if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK)
230 /** HDREG Stop Gear Max Current Type. */
231 typedef enum {
232 /** HDREG current limit is 4mA. */
233 emuHdregStopGearILmt4mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_4MA,
234 /** HDREG current limit is 8mA. */
235 emuHdregStopGearILmt8mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_8MA,
236 /** HDREG current limit is 12mA. */
237 emuHdregStopGearILmt12mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_12MA,
238 /** HDREG current limit is 16mA. */
239 emuHdregStopGearILmt16mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_16MA,
240 /** HDREG current limit is 24mA. */
241 emuHdregStopGearILmt24mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_24MA,
242 /** HDREG current limit is 48mA. */
243 emuHdregStopGearILmt48mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_48MA,
244 /** HDREG current limit is 64mA. */
245 emuHdregStopGearILmt64mA = _EMU_CTRL_HDREGSTOPGEAR_ILMT_64MA,
246 /** HDREG current limit is 64mA. */
247 emuHdregStopGearILmtMax = _EMU_CTRL_HDREGSTOPGEAR_ILMT_MAX,
248 } EMU_HdregStopGearILmt_TypeDef;
249 #endif
250
251 /** Power configurations. DCDC-to-DVDD is currently the only supported mode. */
252 typedef enum {
253 /** DCDC is connected to DVDD. */
254 emuPowerConfig_DcdcToDvdd,
255 } EMU_PowerConfig_TypeDef;
256
257 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
258 /** DCDC operating modes. */
259 typedef enum {
260 /** DCDC regulator bypass. */
261 emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,
262 /** DCDC low-noise mode. */
263 emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE,
264 #if defined(_EMU_DCDCLPEM01CFG_MASK)
265 /** DCDC low-power mode. */
266 emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER,
267 #endif
268 } EMU_DcdcMode_TypeDef;
269
270 /** DCDC operating modes in EM2 or EM3. */
271 typedef enum {
272 /** DCDC mode is low power. */
273 emuDcdcModeEM23_LowPower = EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER,
274 /** DCDC mode is according to DCDCMODE field. */
275 emuDcdcModeEM23_Sw = EMU_DCDCCTRL_DCDCMODEEM23_EM23SW,
276 } EMU_DcdcModeEM23_TypeDef;
277
278 #endif
279
280 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
281 /** DCDC conduction modes. */
282 typedef enum {
283 /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization
284 features are available in this mode. */
285 emuDcdcConductionMode_ContinuousLN,
286 /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or
287 for EFR32 when its radio is not enabled. */
288 emuDcdcConductionMode_DiscontinuousLN,
289 } EMU_DcdcConductionMode_TypeDef;
290 #endif
291
292 #if defined(_EMU_PWRCTRL_MASK)
293 /** DCDC to DVDD mode analog peripheral power supply select. */
294 typedef enum {
295 /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */
296 emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,
297 /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */
298 emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD
299 } EMU_DcdcAnaPeripheralPower_TypeDef;
300 #endif
301
302 #if defined(_EMU_DCDCMISCCTRL_MASK)
303 /** DCDC Forced CCM and reverse current limiter control. Positive values have unit mA. */
304 typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef;
305
306 /** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */
307 #define emuDcdcLnHighEfficiency -1
308
309 /** Default reverse current for fast transient response mode (low noise). */
310 #define emuDcdcLnFastTransient 160
311 #endif
312
313 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
314 /** DCDC Low-noise RCO band select. */
315 typedef enum {
316 /** Set RCO to 3MHz. */
317 emuDcdcLnRcoBand_3MHz = 0,
318 /** Set RCO to 4MHz. */
319 emuDcdcLnRcoBand_4MHz = 1,
320 /** Set RCO to 5MHz. */
321 emuDcdcLnRcoBand_5MHz = 2,
322 /** Set RCO to 6MHz. */
323 emuDcdcLnRcoBand_6MHz = 3,
324 /** Set RCO to 7MHz. */
325 emuDcdcLnRcoBand_7MHz = 4,
326 /** Set RCO to 8MHz. */
327 emuDcdcLnRcoBand_8MHz = 5,
328 /** Set RCO to 9MHz. */
329 emuDcdcLnRcoBand_9MHz = 6,
330 /** Set RCO to 10MHz. */
331 emuDcdcLnRcoBand_10MHz = 7,
332 } EMU_DcdcLnRcoBand_TypeDef;
333
334 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
335 /* Deprecated. */
336 #define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz
337 #define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz
338 #define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz
339 #define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz
340 #define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz
341 #define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz
342 #define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz
343 #define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz
344 /** @endcond */
345
346 /** DCDC Low Noise Compensator Control register. */
347 typedef enum {
348 /** DCDC capacitor is 1uF. */
349 emuDcdcLnCompCtrl_1u0F,
350 /** DCDC capacitor is 4.7uF. */
351 emuDcdcLnCompCtrl_4u7F,
352 } EMU_DcdcLnCompCtrl_TypeDef;
353 #endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */
354
355 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \
356 || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
357
358 /** DCDC mode. */
359 typedef enum {
360 emuDcdcMode_Bypass = _DCDC_CTRL_MODE_BYPASS, /**< DCDC regulator bypass. */
361 emuDcdcMode_Regulation = _DCDC_CTRL_MODE_DCDCREGULATION /**< DCDC regulator on. */
362 } EMU_DcdcMode_TypeDef;
363 #endif
364
365 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
366 /** VREGIN comparator threshold. */
367 typedef enum {
368 emuVreginCmpThreshold_2v0 = 0, /**< Comparator threshold is 2.0V. */
369 emuVreginCmpThreshold_2v1 = 1, /**< Comparator threshold is 2.1V. */
370 emuVreginCmpThreshold_2v2 = 2, /**< Comparator threshold is 2.2V. */
371 emuVreginCmpThreshold_2v3 = 3 /**< Comparator threshold is 2.3V. */
372 } EMU_VreginCmpThreshold_TypeDef;
373
374 /** DCDC Buck Ton max timeout. */
375 typedef enum {
376 #if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \
377 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \
378 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9))
379 emuDcdcTonMaxTimeout_Off = _DCDC_CTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */
380 emuDcdcTonMaxTimeout_0P35us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */
381 emuDcdcTonMaxTimeout_0P63us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */
382 emuDcdcTonMaxTimeout_0P91us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */
383 emuDcdcTonMaxTimeout_1P19us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */
384 emuDcdcTonMaxTimeout_1P47us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */
385 emuDcdcTonMaxTimeout_1P75us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */
386 emuDcdcTonMaxTimeout_2P03us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us /**< Ton max is 2.03us. */
387 #else
388 emuDcdcTonMaxTimeout_Off = 0, /**< Ton max off. */
389 emuDcdcTonMaxTimeout_0P14us = 1, /**< Ton max is 0.14us. */
390 emuDcdcTonMaxTimeout_0P21us = 2, /**< Ton max is 0.21us. */
391 emuDcdcTonMaxTimeout_0P28us = 3, /**< Ton max is 0.28us. */
392 emuDcdcTonMaxTimeout_0P35us = 4, /**< Ton max is 0.35us. */
393 emuDcdcTonMaxTimeout_0P42us = 5, /**< Ton max is 0.42us. */
394 emuDcdcTonMaxTimeout_0P49us = 6, /**< Ton max is 0.49us. */
395 emuDcdcTonMaxTimeout_0P56us = 7, /**< Ton max is 0.56us. */
396 emuDcdcTonMaxTimeout_0P63us = 8, /**< Ton max is 0.63us. */
397 emuDcdcTonMaxTimeout_0P70us = 9, /**< Ton max is 0.70us. */
398 emuDcdcTonMaxTimeout_0P77us = 10, /**< Ton max is 0.77us. */
399 emuDcdcTonMaxTimeout_0P84us = 11, /**< Ton max is 0.84us. */
400 emuDcdcTonMaxTimeout_0P91us = 12, /**< Ton max is 0.91us. */
401 emuDcdcTonMaxTimeout_0P98us = 13, /**< Ton max is 0.98us. */
402 emuDcdcTonMaxTimeout_1P05us = 14, /**< Ton max is 1.05us. */
403 emuDcdcTonMaxTimeout_1P12us = 15, /**< Ton max is 1.12us. */
404 emuDcdcTonMaxTimeout_1P19us = 16, /**< Ton max is 1.19us. */
405 emuDcdcTonMaxTimeout_1P26us = 17, /**< Ton max is 1.26us. */
406 emuDcdcTonMaxTimeout_1P33us = 18, /**< Ton max is 1.33us. */
407 emuDcdcTonMaxTimeout_1P40us = 19, /**< Ton max is 1.40us. */
408 emuDcdcTonMaxTimeout_1P47us = 20, /**< Ton max is 1.47us. */
409 emuDcdcTonMaxTimeout_1P54us = 21, /**< Ton max is 1.54us. */
410 emuDcdcTonMaxTimeout_1P61us = 22, /**< Ton max is 1.61us. */
411 emuDcdcTonMaxTimeout_1P68us = 23, /**< Ton max is 1.68us. */
412 emuDcdcTonMaxTimeout_1P75us = 24, /**< Ton max is 1.75us. */
413 emuDcdcTonMaxTimeout_1P82us = 25, /**< Ton max is 1.82us. */
414 emuDcdcTonMaxTimeout_1P89us = 26, /**< Ton max is 1.89us. */
415 emuDcdcTonMaxTimeout_1P96us = 27, /**< Ton max is 1.96us. */
416 emuDcdcTonMaxTimeout_2P03us = 28, /**< Ton max is 2.03us. */
417 emuDcdcTonMaxTimeout_2P10us = 29, /**< Ton max is 2.10us. */
418 emuDcdcTonMaxTimeout_2P17us = 30, /**< Ton max is 2.17us. */
419 emuDcdcTonMaxTimeout_2P24us = 31 /**< Ton max is 2.24us. */
420 #endif
421 } EMU_DcdcTonMaxTimeout_TypeDef;
422
423 /** DCDC Buck drive speed. */
424 typedef enum {
425 emuDcdcDriveSpeed_BestEmi = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
426 emuDcdcDriveSpeed_Default = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
427 emuDcdcDriveSpeed_Intermediate = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
428 emuDcdcDriveSpeed_BestEfficiency = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
429 } EMU_DcdcDriveSpeed_TypeDef;
430
431 /** DCDC Buck peak current setting. */
432 typedef enum {
433 #if defined(_DCDC_EM23CTRL0_IPKVAL_Load5mA)
434 emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_Load5mA, /**< Load 5mA, peak current 90mA. */
435 #endif
436 #if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD5MA)
437 emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_LOAD5MA, /**< Load 5mA, peak current 90mA. */
438 #endif
439 #if defined(_DCDC_EM23CTRL0_IPKVAL_Load10mA)
440 emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_Load10mA, /**< Load 10mA, peak current 150mA. */
441 #endif
442 #if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD10MA)
443 emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_LOAD10MA, /**< Load 10mA, peak current 150mA. */
444 #endif
445 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load28mA)
446 emuDcdcPeakCurrent_Load28mA = _DCDC_EM01CTRL0_IPKVAL_Load28mA, /**< Load 28mA, peak current 70mA. */
447 #endif
448 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load32mA)
449 emuDcdcPeakCurrent_Load32mA = _DCDC_EM01CTRL0_IPKVAL_Load32mA, /**< Load 32mA, peak current 80mA. */
450 #endif
451 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load36mA)
452 emuDcdcPeakCurrent_Load36mA = _DCDC_EM01CTRL0_IPKVAL_Load36mA, /**< Load 36mA, peak current 90mA. */
453 #endif
454 emuDcdcPeakCurrent_Load40mA = _DCDC_EM01CTRL0_IPKVAL_Load40mA, /**< Load 40mA, peak current 100mA. */
455 emuDcdcPeakCurrent_Load44mA = _DCDC_EM01CTRL0_IPKVAL_Load44mA, /**< Load 44mA, peak current 110mA. */
456 emuDcdcPeakCurrent_Load48mA = _DCDC_EM01CTRL0_IPKVAL_Load48mA, /**< Load 48mA, peak current 120mA. */
457 emuDcdcPeakCurrent_Load52mA = _DCDC_EM01CTRL0_IPKVAL_Load52mA, /**< Load 52mA, peak current 130mA. */
458 emuDcdcPeakCurrent_Load56mA = _DCDC_EM01CTRL0_IPKVAL_Load56mA, /**< Load 56mA, peak current 140mA. */
459 emuDcdcPeakCurrent_Load60mA = _DCDC_EM01CTRL0_IPKVAL_Load60mA, /**< Load 60mA, peak current 150mA. */
460 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load64mA)
461 emuDcdcPeakCurrent_Load64mA = _DCDC_EM01CTRL0_IPKVAL_Load64mA, /**< Load 64mA, peak current 160mA. */
462 #endif
463 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load68mA)
464 emuDcdcPeakCurrent_Load68mA = _DCDC_EM01CTRL0_IPKVAL_Load68mA, /**< Load 68mA, peak current 170mA. */
465 #endif
466 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load72mA)
467 emuDcdcPeakCurrent_Load72mA = _DCDC_EM01CTRL0_IPKVAL_Load72mA, /**< Load 72mA, peak current 180mA. */
468 #endif
469 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load76mA)
470 emuDcdcPeakCurrent_Load76mA = _DCDC_EM01CTRL0_IPKVAL_Load76mA, /**< Load 76mA, peak current 190mA. */
471 #endif
472 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load80mA)
473 emuDcdcPeakCurrent_Load80mA = _DCDC_EM01CTRL0_IPKVAL_Load80mA /**< Load 80mA, peak current 200mA. */
474 #endif
475 } EMU_DcdcPeakCurrent_TypeDef;
476 #endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */
477
478 #if defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
479 /** DCDC Boost drive speed. */
480 typedef enum {
481 emuDcdcBoostDriveSpeed_BestEmi = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
482 emuDcdcBoostDriveSpeed_Default = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
483 emuDcdcBoostDriveSpeed_Intermediate = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
484 emuDcdcBoostDriveSpeed_BestEfficiency = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
485 } EMU_DcdcBoostDriveSpeed_TypeDef;
486
487 /** DCDC Boost EM01 peak current setting. */
488 typedef enum {
489 emuDcdcBoostEM01PeakCurrent_Load10mA = _DCDC_BSTEM01CTRL_IPKVAL_Load10mA, /**< Load 10mA */
490 emuDcdcBoostEM01PeakCurrent_Load11mA = _DCDC_BSTEM01CTRL_IPKVAL_Load11mA, /**< Load 11mA */
491 emuDcdcBoostEM01PeakCurrent_Load13mA = _DCDC_BSTEM01CTRL_IPKVAL_Load13mA, /**< Load 13mA */
492 emuDcdcBoostEM01PeakCurrent_Load15mA = _DCDC_BSTEM01CTRL_IPKVAL_Load15mA, /**< Load 15mA */
493 emuDcdcBoostEM01PeakCurrent_Load16mA = _DCDC_BSTEM01CTRL_IPKVAL_Load16mA, /**< Load 16mA */
494 emuDcdcBoostEM01PeakCurrent_Load18mA = _DCDC_BSTEM01CTRL_IPKVAL_Load18mA, /**< Load 18mA */
495 emuDcdcBoostEM01PeakCurrent_Load20mA = _DCDC_BSTEM01CTRL_IPKVAL_Load20mA, /**< Load 20mA */
496 emuDcdcBoostEM01PeakCurrent_Load21mA = _DCDC_BSTEM01CTRL_IPKVAL_Load21mA, /**< Load 21mA */
497 emuDcdcBoostEM01PeakCurrent_Load23mA = _DCDC_BSTEM01CTRL_IPKVAL_Load23mA, /**< Load 23mA */
498 emuDcdcBoostEM01PeakCurrent_Load25mA = _DCDC_BSTEM01CTRL_IPKVAL_Load25mA, /**< Load 25mA */
499 } EMU_DcdcBoostEM01PeakCurrent_TypeDef;
500
501 /** DCDC Boost Toff max timeout */
502 typedef enum {
503 emuDcdcBoostToffMaxTimeout_Off = _DCDC_BSTCTRL_BSTTOFFMAX_OFF, /**< Toff max off. */
504 emuDcdcBoostToffMaxTimeout_0P35us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us, /**< Toff max is 0.35us. */
505 emuDcdcBoostToffMaxTimeout_0P63us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us, /**< Toff max is 0.63us. */
506 emuDcdcBoostToffMaxTimeout_0P91us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us, /**< Toff max is 0.91us. */
507 emuDcdcBoostToffMaxTimeout_1P19us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us, /**< Toff max is 1.19us. */
508 emuDcdcBoostToffMaxTimeout_1P47us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us, /**< Toff max is 1.47us. */
509 emuDcdcBoostToffMaxTimeout_1P75us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us, /**< Toff max is 1.75us. */
510 emuDcdcBoostToffMaxTimeout_2P03us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us, /**< Toff max is 2.03us. */
511 } EMU_DcdcBoostToffMaxTimeout_TypeDef;
512
513 /** DCDC Boost peak current detection maximum timeout */
514 typedef enum {
515 emuDcdcBoostTonMaxTimeout_Off = _DCDC_BSTCTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */
516 emuDcdcBoostTonMaxTimeout_0P35us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */
517 emuDcdcBoostTonMaxTimeout_0P63us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */
518 emuDcdcBoostTonMaxTimeout_0P91us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */
519 emuDcdcBoostTonMaxTimeout_1P19us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */
520 emuDcdcBoostTonMaxTimeout_1P47us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */
521 emuDcdcBoostTonMaxTimeout_1P75us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */
522 emuDcdcBoostTonMaxTimeout_2P03us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us, /**< Ton max is 2.03us. */
523 } EMU_DcdcBoostTonMaxTimeout_TypeDef;
524
525 /** DCDC Boost EM23 peak current setting. */
526 typedef enum {
527 emuDcdcBoostEM23PeakCurrent_Load10mA = _DCDC_BSTEM23CTRL_IPKVAL_Load10mA, /**< Load 10mA */
528 } EMU_DcdcBoostEM23PeakCurrent_TypeDef;
529
530 #if defined(_DCDC_CTRL_DVDDBSTPRG_MASK)
531 /** DCDC Boost output voltage */
532 typedef enum {
533 emuDcdcBoostOutputVoltage_1v8 = _DCDC_CTRL_DVDDBSTPRG_BOOST_1V8, /**< Output voltage is 1.8V. */
534 emuDcdcBoostOutputVoltage_1v9 = _DCDC_CTRL_DVDDBSTPRG_BOOST_1V9, /**< Output voltage is 1.9V. */
535 emuDcdcBoostOutputVoltage_2v0 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V, /**< Output voltage is 2.0V. */
536 emuDcdcBoostOutputVoltage_2v1 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V1, /**< Output voltage is 2.1V. */
537 emuDcdcBoostOutputVoltage_2v2 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V2, /**< Output voltage is 2.2V. */
538 emuDcdcBoostOutputVoltage_2v3 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V3, /**< Output voltage is 2.3V. */
539 emuDcdcBoostOutputVoltage_2v4 = _DCDC_CTRL_DVDDBSTPRG_BOOST_2V4, /**< Output voltage is 2.4V. */
540 } EMU_DcdcBoostOutputVoltage_TypeDef;
541 #endif
542
543 #endif /* EMU_SERIES2_DCDC_BOOST_PRESENT) */
544
545 #if defined(EMU_STATUS_VMONRDY)
546 /** VMON channels. */
547 typedef enum {
548 emuVmonChannel_AVDD,
549 emuVmonChannel_ALTAVDD,
550 emuVmonChannel_DVDD,
551 emuVmonChannel_IOVDD0,
552 #if defined(_EMU_VMONIO1CTRL_EN_MASK)
553 emuVmonChannel_IOVDD1,
554 #endif
555 #if defined(_EMU_VMONBUVDDCTRL_EN_MASK)
556 emuVmonChannel_BUVDD,
557 #endif
558 } EMU_VmonChannel_TypeDef;
559 #endif /* EMU_STATUS_VMONRDY */
560
561 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
562 /** Bias mode configurations. */
563 typedef enum {
564 emuBiasMode_1KHz,
565 emuBiasMode_4KHz,
566 emuBiasMode_Continuous
567 } EMU_BiasMode_TypeDef;
568 #endif
569
570 #if defined(EMU_VSCALE_EM01_PRESENT)
571 /** Supported EM0/1 Voltage Scaling Levels. */
572 typedef enum {
573 /** High-performance voltage level. HF clock can be set to any frequency. */
574 emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2,
575 /** Low-power optimized voltage level. HF clock must be limited
576 to CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage.
577 EM0/1 voltage scaling is applied when core clock frequency is
578 changed from @ref cmu or when calling @ref EMU_EM01Init() when HF
579 clock is already below the limit. */
580 #if defined(_SILICON_LABS_32B_SERIES_2)
581 /** Minimum VSCALE level in EM0/1 is VSCALE1. */
582 emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE1,
583 #else
584 emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0,
585 #endif
586 } EMU_VScaleEM01_TypeDef;
587 #endif
588
589 #if defined(EMU_VSCALE_PRESENT)
590 /** Supported EM2/3 Voltage Scaling Levels. */
591 typedef enum {
592 /** Fast-wakeup voltage level. */
593 emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2,
594 /** Low-power optimized voltage level. Using this voltage level in EM2 and 3
595 adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled
596 up to emuVScaleEM01_HighPerformance on EM2 or 3 exit. */
597 emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0,
598 } EMU_VScaleEM23_TypeDef;
599 #endif
600
601 #if defined(_EMU_CTRL_EM4HVSCALE_MASK)
602 /** Supported EM4H Voltage Scaling Levels */
603 typedef enum {
604 /** Fast-wakeup voltage level. */
605 emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2,
606 /** Low-power optimized voltage level. Using this voltage level in EM4H
607 adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled
608 up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */
609 emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0,
610 } EMU_VScaleEM4H_TypeDef;
611 #endif
612
613 #if defined(_EMU_EM23PERNORETAINCTRL_MASK)
614 /** Peripheral EM2 and 3 retention control. */
615 typedef enum {
616 #if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK)
617 emuPeripheralRetention_USB = _EMU_EM23PERNORETAINCTRL_USBDIS_MASK, /**< Select USB retention control. */
618 #endif
619 #if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK)
620 emuPeripheralRetention_RTC = _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK, /**< Select RTC retention control. */
621 #endif
622 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK)
623 emuPeripheralRetention_ACMP3 = _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK, /**< Select ACMP3 retention control. */
624 #endif
625 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK)
626 emuPeripheralRetention_ACMP2 = _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK, /**< Select ACMP2 retention control. */
627 #endif
628 #if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK)
629 emuPeripheralRetention_ADC1 = _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK, /**< Select ADC1 retention control. */
630 #endif
631 #if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK)
632 emuPeripheralRetention_I2C2 = _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK, /**< Select I2C2 retention control. */
633 #endif
634 #if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK)
635 emuPeripheralRetention_LETIMER1 = _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK, /**< Select LETIMER1 retention control. */
636 #endif
637 #if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK)
638 emuPeripheralRetention_LCD = _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK, /**< Select LCD retention control. */
639 #endif
640 #if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK)
641 emuPeripheralRetention_LEUART1 = _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK, /**< Select LEUART1 retention control. */
642 #endif
643 emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /**< Select LEUART0 retention control. */
644 #if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK)
645 emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /**< Select CSEN retention control. */
646 #endif
647 emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /**< Select LESENSE0 retention control. */
648 #if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK)
649 emuPeripheralRetention_WDOG1 = _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK, /**< Select WDOG1 retention control. */
650 #endif
651 emuPeripheralRetention_WDOG0 = _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK, /**< Select WDOG0 retention control. */
652 emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /**< Select LETIMER0 retention control. */
653 emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /**< Select ADC0 retention control. */
654 #if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK)
655 emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /**< Select IDAC0 retention control. */
656 #endif
657 #if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK)
658 emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK, /**< Select VDAC0 retention control. */
659 #endif
660 #if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK)
661 emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /**< Select I2C1 retention control. */
662 #endif
663 emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /**< Select I2C0 retention control. */
664 emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /**< Select ACMP1 retention control. */
665 emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /**< Select ACMP0 retention control. */
666 #if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK)
667 emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /**< Select PCNT2 retention control. */
668 emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /**< Select PCNT1 retention control. */
669 #endif
670 emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /**< Select PCNT0 retention control. */
671
672 emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK
673 | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK
674 | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK
675 | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK
676 | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/**< Select all peripherals in domain 1. */
677 emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK
678 #if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK)
679 | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK
680 #endif
681 #if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK)
682 | _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK
683 #endif
684 #if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK)
685 | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK
686 #endif
687 | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK
688 #if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK)
689 | _EMU_EM23PERNORETAINCTRL_USBDIS_MASK
690 #endif
691 #if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK)
692 | _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK
693 #endif
694 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK)
695 | _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK
696 #endif
697 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK)
698 | _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK
699 #endif
700 #if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK)
701 | _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK
702 #endif
703 #if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK)
704 | _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK
705 #endif
706 #if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK)
707 | _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK
708 #endif
709 #if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK)
710 | _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK
711 #endif
712 #if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK)
713 | _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK
714 #endif
715 #if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK)
716 | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK
717 | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK
718 #endif
719 #if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK)
720 | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK /**< Select all peripherals in domain 2. */
721 #endif
722 | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK,
723 emuPeripheralRetention_ALL = emuPeripheralRetention_D1
724 | emuPeripheralRetention_D2
725 #if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK)
726 | emuPeripheralRetention_WDOG1
727 #endif
728 | emuPeripheralRetention_WDOG0, /**< Select all peripherals with retention control. */
729 } EMU_PeripheralRetention_TypeDef;
730 #endif
731
732 #if defined(_EMU_TEMP_TEMPAVG_MASK)
733 /** Number of samples to use for temperature averaging. */
734 typedef enum {
735 /** 16 samples used for temperature averaging. */
736 emuTempAvgNum_16 = _EMU_CTRL_TEMPAVGNUM_N16,
737 /** 64 samples used for temperature averaging. */
738 emuTempAvgNum_64 = _EMU_CTRL_TEMPAVGNUM_N64,
739 } EMU_TempAvgNum_TypeDef;
740 #endif
741
742 /*******************************************************************************
743 ******************************* STRUCTS ***********************************
744 ******************************************************************************/
745
746 #if defined(EMU_VSCALE_EM01_PRESENT)
747 /** EM0 and 1 initialization structure. Voltage scaling is applied when
748 the core clock frequency is changed from @ref cmu. EM0 and 1 emuVScaleEM01_HighPerformance
749 is always enabled. */
750 typedef struct {
751 bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status. */
752 #if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK)
753 EMU_HdregStopGearILmt_TypeDef current; /**< limit HDREG max current capability. */
754 #endif
755 } EMU_EM01Init_TypeDef;
756
757 /** Default initialization of EM0 and 1 configuration. */
758 #if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK)
759 #define EMU_EM01INIT_DEFAULT \
760 { \
761 false, /* Do not scale down in EM0/1.*/ \
762 emuHdregStopGearILmt64mA /* HDREG current limit is 64mA. */ \
763 }
764 #else
765 #define EMU_EM01INIT_DEFAULT \
766 { \
767 false /* Do not scale down in EM0/1.*/ \
768 }
769 #endif
770 #endif
771 /** EM2 and 3 initialization structure. */
772 typedef struct {
773 bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3. */
774 #if defined(EMU_VSCALE_PRESENT)
775 EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level. */
776 #endif
777 } EMU_EM23Init_TypeDef;
778
779 /** Default initialization of EM2 and 3 configuration. */
780 #if defined(EMU_VSCALE_PRESENT)
781 #define EMU_EM23INIT_DEFAULT \
782 { \
783 false, /* Reduced voltage regulator drive strength in EM2/3.*/ \
784 emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3. */ \
785 }
786 #else
787 #define EMU_EM23INIT_DEFAULT \
788 { \
789 false, /* Reduced voltage regulator drive strength in EM2/3.*/ \
790 }
791 #endif
792 #if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK)
793 /** EM4 initialization structure. */
794 typedef struct {
795 #if defined(_EMU_EM4CONF_MASK)
796 /* Initialization parameters for platforms with EMU->EM4CONF register (Series 0). */
797 bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator. */
798 bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4. */
799 EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator. */
800 bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt. */
801 bool vreg; /**< Enable EM4 voltage regulator. */
802 #elif defined(_EMU_EM4CTRL_MASK)
803 /* Initialization parameters for platforms with EMU->EM4CTRL register (Series 1). */
804 bool retainLfxo; /**< Disable LFXO upon EM4 entry. */
805 bool retainLfrco; /**< Disable LFRCO upon EM4 entry. */
806 bool retainUlfrco; /**< Disable ULFRCO upon EM4 entry. */
807 EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state. */
808 EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode. */
809 #endif
810 #if defined(_EMU_CTRL_EM4HVSCALE_MASK)
811 EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level. */
812 #endif
813 } EMU_EM4Init_TypeDef;
814 #endif
815
816 #if defined(_EMU_EM4CONF_MASK)
817 /** Default initialization of EM4 configuration (Series 0). */
818 #define EMU_EM4INIT_DEFAULT \
819 { \
820 false, /* Do not lock configuration after it's been set. */ \
821 false, /* No reset will be asserted due to BOD in EM4. */ \
822 emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator. */ \
823 true, /* Wake up on EM4 BURTC interrupt. */ \
824 true, /* Enable VREG. */ \
825 }
826
827 #elif defined(_EMU_CTRL_EM4HVSCALE_MASK)
828 /** Default initialization of EM4 configuration (Series 1 with VSCALE). */
829 #define EMU_EM4INIT_DEFAULT \
830 { \
831 false, /* Retain LFXO configuration upon EM4 entry. */ \
832 false, /* Retain LFRCO configuration upon EM4 entry. */ \
833 false, /* Retain ULFRCO configuration upon EM4 entry. */ \
834 emuEM4Shutoff, /* Use EM4 shutoff state. */ \
835 emuPinRetentionDisable, /* Do not retain pins in EM4. */ \
836 emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H. */ \
837 }
838
839 #elif defined(_EMU_EM4CTRL_MASK)
840 /** Default initialization of EM4 configuration (Series 1 without VSCALE). */
841 #define EMU_EM4INIT_DEFAULT \
842 { \
843 false, /* Retain LFXO configuration upon EM4 entry. */ \
844 false, /* Retain LFRCO configuration upon EM4 entry. */ \
845 false, /* Retain ULFRCO configuration upon EM4 entry. */ \
846 emuEM4Shutoff, /* Use EM4 shutoff state. */ \
847 emuPinRetentionDisable, /* Do not retain pins in EM4. */ \
848 }
849 #endif
850
851 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
852 /** Backup Power Domain Initialization structure. */
853 typedef struct {
854 /* Backup Power Domain power configuration. */
855
856 /** Voltage probe select, selects ADC voltage. */
857 EMU_Probe_TypeDef probe;
858 /** Enable BOD calibration mode. */
859 bool bodCal;
860 /** Enable BU_STAT status pin for active BU mode. */
861 bool statusPinEnable;
862
863 /* Backup Power Domain connection configuration. */
864 /** Power domain resistor. */
865 EMU_Resistor_TypeDef resistor;
866 /** BU_VOUT strong enable. */
867 bool voutStrong;
868 /** BU_VOUT medium enable. */
869 bool voutMed;
870 /** BU_VOUT weak enable. */
871 bool voutWeak;
872 /** Power connection, when not in Backup Mode. */
873 EMU_Power_TypeDef inactivePower;
874 /** Power connection, when in Backup Mode. */
875 EMU_Power_TypeDef activePower;
876 /** Enable backup power domain, and release reset, enable BU_VIN pin. */
877 bool enable;
878 } EMU_BUPDInit_TypeDef;
879
880 /** Default Backup Power Domain configuration. */
881 #define EMU_BUPDINIT_DEFAULT \
882 { \
883 emuProbe_Disable, /* Do not enable voltage probe. */ \
884 false, /* Disable BOD calibration mode. */ \
885 false, /* Disable BU_STAT pin for backup mode indication. */ \
886 \
887 emuRes_Res0, /* RES0 series resistance between main and backup power. */ \
888 false, /* Do not enable strong switch. */ \
889 false, /* Do not enable medium switch. */ \
890 false, /* Do not enable weak switch. */ \
891 \
892 emuPower_None, /* No connection between main and backup power. (inactive mode) */ \
893 emuPower_None, /* No connection between main and backup power. (active mode) */ \
894 true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset. */ \
895 }
896 #endif
897
898 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1)
899 /** Backup Power Domain Initialization structure. */
900 typedef struct {
901 bool disMaxComp; /**< Disable MAIN-BU Comparator. */
902 EMU_BUBuInactPwrCon_TypeDef inactivePwrCon; /**< Power connection configuration when not in backup mode. */
903 EMU_BUBuActPwrCon_TypeDef activePwrCon; /**< Power connection configuration when in backup mode. */
904 EMU_BUPwrRes_TypeDef pwrRes; /**< Power domain resistor. */
905 EMU_BUVoutRes_TypeDef voutRes; /**< BU_VOUT resistor select. */
906 bool buVinProbeEn; /**< Enable BU_VIN probing. */
907 bool staEn; /**< Enable backup mode status export. */
908 bool enable; /**< Enable backup power domain. */
909 } EMU_BUInit_TypeDef;
910
911 /** Default Backup Power Domain configuration. */
912 #define EMU_BUINIT_DEFAULT \
913 { \
914 false, /* MAIN-BU Comparator is not disabled */ \
915 emuBuBuInactPwrCon_None, /* No power connection wen not in backup mode */ \
916 emuBuBuActPwrCon_None, /* No power connection when in backup mode */ \
917 emuBuPwrRes_Res0, /* RES0 series resistance between main and backup power. */ \
918 emuBuVoutRes_Dis, /* Vout resistor is set to not connected */ \
919 false, /* BU_VIN probe is disabled */ \
920 false, /* Status export is disabled */ \
921 true /* Enable backup mode */ \
922 }
923 #endif
924
925 #if defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
926 /** DCDC Boost regulator initialization structure. */
927 typedef struct {
928 EMU_DcdcBoostTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */
929 bool externalShutdownEn; /**< true = disable DCDC boost mode with BOOST_EN=0 */
930 EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */
931 EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */
932 EMU_DcdcBoostEM01PeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */
933 EMU_DcdcBoostEM23PeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */
934 #if defined(_DCDC_CTRL_DVDDBSTPRG_MASK)
935 EMU_DcdcBoostOutputVoltage_TypeDef outputVoltage; /**< DCDC Boost output voltage. */
936 #endif
937 } EMU_DCDCBoostInit_TypeDef;
938
939 /** Default DCDC Boost initialization. */
940 #if defined(_DCDC_CTRL_DVDDBSTPRG_MASK)
941 #define EMU_DCDCBOOSTINIT_DEFAULT \
942 { \
943 emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
944 true, /**< disable DCDC boost mode with BOOST_EN=0 */ \
945 emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
946 emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
947 emuDcdcBoostEM01PeakCurrent_Load23mA, /**< Default peak current in EM0/1. */ \
948 emuDcdcBoostEM23PeakCurrent_Load10mA, /**< Default peak current in EM2/3. */ \
949 emuDcdcBoostOutputVoltage_1v8 /**< DCDC Boost output voltage. */ \
950 }
951 #else
952 #define EMU_DCDCBOOSTINIT_DEFAULT \
953 { \
954 emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
955 true, /**< disable DCDC boost mode with BOOST_EN=0 */ \
956 emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
957 emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
958 emuDcdcBoostEM01PeakCurrent_Load23mA, /**< Default peak current in EM0/1. */ \
959 emuDcdcBoostEM23PeakCurrent_Load10mA /**< Default peak current in EM2/3. */ \
960 }
961 #endif
962 #endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */
963
964 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
965 /** DCDC regulator initialization structure. */
966 typedef struct {
967 EMU_DcdcMode_TypeDef mode; /**< DCDC mode. */
968 EMU_VreginCmpThreshold_TypeDef cmpThreshold; /**< VREGIN comparator threshold. */
969 EMU_DcdcTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */
970 #if defined(_DCDC_CTRL_DCMONLYEN_MASK)
971 bool dcmOnlyEn; /**< DCM only mode enable. */
972 #endif
973 EMU_DcdcDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */
974 EMU_DcdcDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */
975 EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */
976 EMU_DcdcPeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */
977 } EMU_DCDCInit_TypeDef;
978
979 /** Default DCDC Buck initialization. */
980 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2)
981 #define EMU_DCDCINIT_DEFAULT \
982 { \
983 emuDcdcMode_Regulation, /**< DCDC regulator on. */ \
984 emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \
985 emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
986 true, /**< Enable DCM only mode. */ \
987 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
988 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
989 emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \
990 emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \
991 }
992 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \
993 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \
994 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \
995 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \
996 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \
997 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \
998 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)
999 #define EMU_DCDCINIT_DEFAULT \
1000 { \
1001 emuDcdcMode_Regulation, /**< DCDC regulator on. */ \
1002 emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \
1003 emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
1004 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
1005 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
1006 emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \
1007 emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \
1008 }
1009 #endif
1010 #endif /* SERIES2_DCDC_BUCK_PRESENT */
1011
1012 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
1013 /** DCDC initialization structure. */
1014 typedef struct {
1015 EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration.
1016 @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */
1017 EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1. */
1018 uint16_t mVout; /**< Target output voltage (mV). */
1019 uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1. (mA).
1020 This estimate is also used for EM1 optimization;
1021 if EM1 current is expected to be higher than EM0,
1022 then this parameter should hold the higher EM1 current. */
1023 uint16_t em234LoadCurrent_uA; /**< Estimated average load current in EM2 (uA).
1024 This estimate is also used for EM3 and 4 optimization;
1025 if EM3 or 4 current is expected to be higher than EM2,
1026 then this parameter should hold the higher EM3 or 4 current. */
1027 uint16_t maxCurrent_mA; /**< Maximum average DCDC output current (mA).
1028 This can be set to the maximum for the power source,
1029 for example the maximum for a battery. */
1030 EMU_DcdcAnaPeripheralPower_TypeDef
1031 anaPeripheralPower; /**< Select analog peripheral power in DCDC-to-DVDD mode. */
1032 EMU_DcdcLnReverseCurrentControl_TypeDef
1033 reverseCurrentControl; /**< Low-noise reverse current control.
1034 NOTE: this parameter uses special encoding:
1035 >= 0 is forced CCM mode where the parameter is used as the
1036 reverse current threshold in mA.
1037 -1 is encoded as emuDcdcLnHighEfficiencyMode (EFM32 only). */
1038 EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl; /**< DCDC Low-noise mode compensator control. */
1039 } EMU_DCDCInit_TypeDef;
1040
1041 /** Default DCDC initialization. */
1042 #if defined(_EFM_DEVICE)
1043 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
1044 #define EMU_DCDCINIT_DEFAULT \
1045 { \
1046 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1047 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
1048 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1049 5, /* Nominal EM0/1 load current of less than 5mA. */ \
1050 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1051 200, /* Maximum average current of 200mA
1052 (assume strong battery or other power source). */ \
1053 emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \
1054 emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \
1055 emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \
1056 }
1057 #elif defined(WGM160PX22KGA2)
1058 #define EMU_DCDCINIT_DEFAULT \
1059 { \
1060 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1061 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
1062 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1063 5, /* Nominal EM0/1 load current of less than 5mA. */ \
1064 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1065 200, /* Maximum average current of 200mA
1066 (assume strong battery or other power source). */ \
1067 emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \
1068 emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \
1069 emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \
1070 }
1071 #else
1072 #define EMU_DCDCINIT_DEFAULT \
1073 { \
1074 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1075 emuDcdcMode_LowPower, /* Low-power mode in EM0. */ \
1076 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1077 5, /* Nominal EM0/1 load current of less than 5mA. */ \
1078 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1079 200, /* Maximum average current of 200mA
1080 (assume strong battery or other power source). */ \
1081 emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \
1082 emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \
1083 emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \
1084 }
1085 #endif
1086
1087 #else /* EFR32 device. */
1088 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
1089 #define EMU_DCDCINIT_DEFAULT \
1090 { \
1091 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1092 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
1093 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1094 15, /* Nominal EM0/1 load current of less than 15mA. */ \
1095 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1096 200, /* Maximum average current of 200mA
1097 (assume strong battery or other power source). */ \
1098 emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \
1099 160, /* Maximum reverse current of 160mA. */ \
1100 emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \
1101 }
1102 #else
1103 #define EMU_DCDCINIT_DEFAULT \
1104 { \
1105 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1106 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
1107 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1108 15, /* Nominal EM0/1 load current of less than 15mA. */ \
1109 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1110 200, /* Maximum average current of 200mA
1111 (assume strong battery or other power source). */ \
1112 emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \
1113 160, /* Maximum reverse current of 160mA. */ \
1114 emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \
1115 }
1116 #endif
1117 #endif
1118 #endif
1119
1120 #if defined(EMU_STATUS_VMONRDY)
1121 /** VMON initialization structure. */
1122 typedef struct {
1123 EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */
1124 int threshold; /**< Trigger threshold (mV). Supported range is 1620 mV to 3400 mV. */
1125 bool riseWakeup; /**< Wake up from EM4H on rising edge. */
1126 bool fallWakeup; /**< Wake up from EM4H on falling edge. */
1127 bool enable; /**< Enable VMON channel. */
1128 bool retDisable; /**< Disable IO0 retention when voltage drops below threshold (IOVDD only). */
1129 } EMU_VmonInit_TypeDef;
1130
1131 /** Default VMON initialization structure. */
1132 #define EMU_VMONINIT_DEFAULT \
1133 { \
1134 emuVmonChannel_AVDD, /* AVDD VMON channel. */ \
1135 3200, /* 3.2 V threshold. */ \
1136 false, /* Do not wake from EM4H on rising edge. */ \
1137 false, /* Do not wake from EM4H on falling edge. */ \
1138 true, /* Enable VMON channel. */ \
1139 false /* Do not disable IO0 retention */ \
1140 }
1141
1142 /** VMON Hysteresis initialization structure. */
1143 typedef struct {
1144 EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */
1145 int riseThreshold; /**< Rising threshold (mV). */
1146 int fallThreshold; /**< Falling threshold (mV). */
1147 bool riseWakeup; /**< Wake up from EM4H on rising edge. */
1148 bool fallWakeup; /**< Wake up from EM4H on falling edge. */
1149 bool enable; /**< Enable VMON channel. */
1150 } EMU_VmonHystInit_TypeDef;
1151
1152 /** Default VMON Hysteresis initialization structure. */
1153 #define EMU_VMONHYSTINIT_DEFAULT \
1154 { \
1155 emuVmonChannel_AVDD, /* AVDD VMON channel. */ \
1156 3200, /* 3.2 V rise threshold. */ \
1157 3200, /* 3.2 V fall threshold. */ \
1158 false, /* Do not wake from EM4H on rising edge. */ \
1159 false, /* Do not wake from EM4H on falling edge. */ \
1160 true /* Enable VMON channel. */ \
1161 }
1162 #endif /* EMU_STATUS_VMONRDY */
1163
1164 /*******************************************************************************
1165 ***************************** PROTOTYPES **********************************
1166 ******************************************************************************/
1167
1168 #if defined(EMU_VSCALE_EM01_PRESENT)
1169 void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init);
1170 #endif
1171 void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init);
1172 void EMU_EM23PresleepHook(void);
1173 void EMU_EM23PostsleepHook(void);
1174 void EMU_EFPEM23PresleepHook(void);
1175 void EMU_EFPEM23PostsleepHook(void);
1176 void EMU_EnterEM2(bool restore);
1177 void EMU_EnterEM3(bool restore);
1178 void EMU_Save(void);
1179 void EMU_Restore(void);
1180 #if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK)
1181 void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init);
1182 #endif
1183 void EMU_EM4PresleepHook(void);
1184 void EMU_EFPEM4PresleepHook(void);
1185 void EMU_EnterEM4(void);
1186 void EMU_EnterEM4Wait(void);
1187 #if defined(_EMU_EM4CTRL_MASK)
1188 void EMU_EnterEM4H(void);
1189 void EMU_EnterEM4S(void);
1190 #endif
1191 void EMU_MemPwrDown(uint32_t blocks) SL_DEPRECATED_API_SDK_4_1;
1192 void EMU_RamPowerDown(uint32_t start, uint32_t end);
1193 void EMU_RamPowerUp(void);
1194 #if defined(_EMU_EM23PERNORETAINCTRL_MASK)
1195 void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable);
1196 #endif
1197 void EMU_UpdateOscConfig(void) SL_DEPRECATED_API_SDK_4_1;
1198 #if defined(EMU_VSCALE_EM01_PRESENT)
1199 #if defined(_SILICON_LABS_32B_SERIES_2)
1200 void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage);
1201 #endif
1202 void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait);
1203 void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait);
1204 #endif
1205 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
1206 void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit);
1207 void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value);
1208 void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value);
1209 #endif
1210 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1)
1211 void EMU_BUInit(const EMU_BUInit_TypeDef *buInit);
1212 #endif
1213 #if defined(_EMU_BUCTRL_DISMAXCOMP_MASK)
1214 void EMU_BUDisMaxCompSet(bool disableMainBuComparator);
1215 #endif
1216 #if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK)
1217 void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon);
1218 #endif
1219 #if defined(_EMU_BUCTRL_BUACTPWRCON_MASK)
1220 void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon);
1221 #endif
1222 #if defined(_EMU_BUCTRL_PWRRES_MASK)
1223 void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes);
1224 #endif
1225 #if defined(_EMU_BUCTRL_VOUTRES_MASK)
1226 void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel);
1227 #endif
1228 #if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK)
1229 void EMU_BUBuVinProbeEnSet(bool enable);
1230 #endif
1231 #if defined(_EMU_BUCTRL_STATEN_MASK)
1232 void EMU_BUStatEnSet(bool enable);
1233 #endif
1234 #if defined(_EMU_BUCTRL_EN_MASK)
1235 void EMU_BUEnableSet(bool enable);
1236 #endif
1237
1238 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
1239 void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);
1240 #endif
1241
1242 #if (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \
1243 || defined(EMU_SERIES2_DCDC_BOOST_PRESENT))
1244 sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);
1245 #endif
1246
1247 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \
1248 || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
1249 void EMU_DCDCUpdatedHook(void);
1250 #endif
1251
1252 #if defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
1253 bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit);
1254 void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01);
1255 void EMU_BoostExternalShutdownEnable(bool enable);
1256 #if defined(_DCDC_CTRL_DVDDBSTPRG_MASK)
1257 void EMU_DCDCBoostOutputVoltageSet(const EMU_DcdcBoostOutputVoltage_TypeDef boostOutputVoltage);
1258 #endif
1259 #endif
1260
1261 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \
1262 || defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
1263 bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit);
1264 bool EMU_DCDCPowerOff(void);
1265 #endif
1266
1267 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
1268 void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01);
1269 #if defined(_DCDC_PFMXCTRL_IPKVAL_MASK)
1270 void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value);
1271 #endif
1272 #if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK)
1273 void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value);
1274 #endif
1275 #endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */
1276
1277 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
1278 #if defined(EMU_DCDCCTRL_DCDCMODEEM23)
1279 void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23);
1280 #endif
1281 void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet);
1282 bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage);
1283 void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA);
1284 void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band);
1285 #endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */
1286
1287 #if defined(EMU_STATUS_VMONRDY)
1288 void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit);
1289 void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit);
1290 void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable);
1291 bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel);
1292 #endif
1293 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
1294 void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode);
1295 #endif
1296 #if defined(_EMU_TEMP_TEMP_MASK)
1297 float EMU_TemperatureGet(void);
1298 #endif
1299 #if defined(EMU_CTRL_EFPDIRECTMODEEN)
1300 void EMU_EFPDirectModeEnable(bool enable);
1301 #endif
1302 #if defined(EMU_CTRL_EFPDRVDECOUPLE)
1303 void EMU_EFPDriveDecoupleSet(bool enable);
1304 #endif
1305 #if defined(EMU_CTRL_EFPDRVDVDD)
1306 void EMU_EFPDriveDvddSet(bool enable);
1307 #endif
1308 #if defined(_EMU_CTRL_HDREGEM2EXITCLIM_MASK)
1309 void EMU_HDRegEM2ExitCurrentLimitEnable(bool enable);
1310 #endif
1311 #if defined(_EMU_CTRL_HDREGSTOPGEAR_MASK)
1312 void EMU_HDRegStopGearSet(EMU_HdregStopGearILmt_TypeDef current);
1313 #endif
1314 #if defined(_DCDC_CTRL_MASK)
1315 /***************************************************************************//**
1316 * @brief
1317 * Lock DCDC registers in order to protect them against unintended
1318 * modification.
1319 ******************************************************************************/
EMU_DCDCLock(void)1320 __STATIC_INLINE void EMU_DCDCLock(void)
1321 {
1322 DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY;
1323 }
1324 #endif
1325
1326 #if defined(_DCDC_CTRL_MASK)
1327 /***************************************************************************//**
1328 * @brief
1329 * Unlock the DCDC so that writing to locked registers again is possible.
1330 ******************************************************************************/
EMU_DCDCUnlock(void)1331 __STATIC_INLINE void EMU_DCDCUnlock(void)
1332 {
1333 DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY;
1334 }
1335 #endif
1336
1337 #if defined(_DCDC_SYNCBUSY_MASK)
1338 /***************************************************************************//**
1339 * @brief
1340 * Wait for the DCDC to complete all synchronization of register changes.
1341 *
1342 * @param[in] mask
1343 * A bitmask corresponding to SYNCBUSY register defined bits indicating
1344 * registers that must complete any ongoing synchronization.
1345 ******************************************************************************/
EMU_DCDCSync(uint32_t mask)1346 __STATIC_INLINE void EMU_DCDCSync(uint32_t mask)
1347 {
1348 while (0UL != (DCDC->SYNCBUSY & mask)) {
1349 /* Wait for previous synchronization to finish */
1350 }
1351 }
1352 #endif
1353
1354 #if defined(_SILICON_LABS_32B_SERIES_1)
1355 /***************************************************************************//**
1356 * @brief
1357 * Check status of the internal LDO regulator.
1358 *
1359 * @return
1360 * Return true if the regulator is on, false if regulator is off.
1361 ******************************************************************************/
EMU_LDOStatusGet(void)1362 __STATIC_INLINE bool EMU_LDOStatusGet(void)
1363 {
1364 if ((*(volatile uint32_t*)0x400E303C & 0x00000040UL) == 0UL) {
1365 return true;
1366 } else {
1367 return false;
1368 }
1369 }
1370 #endif
1371
1372 /***************************************************************************//**
1373 * @brief
1374 * Enter energy mode 1 (EM1).
1375 *
1376 * @note
1377 * This function is incompatible with the Power Manager module. When the
1378 * Power Manager module is present, it must be the one deciding at which
1379 * EM level the device sleeps to ensure the application properly works. Using
1380 * both at the same time could lead to undefined behavior in the application.
1381 ******************************************************************************/
EMU_EnterEM1(void)1382 __STATIC_INLINE void EMU_EnterEM1(void)
1383 {
1384 /* Enter sleep mode. */
1385 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
1386 __WFI();
1387 }
1388
1389 #if defined(EMU_VSCALE_EM01_PRESENT)
1390 /***************************************************************************//**
1391 * @brief
1392 * Wait for voltage scaling to complete.
1393 ******************************************************************************/
EMU_VScaleWait(void)1394 __STATIC_INLINE void EMU_VScaleWait(void)
1395 {
1396 #if defined(_SILICON_LABS_32B_SERIES_1)
1397 if (EMU_LDOStatusGet() == false) {
1398 /* Skip waiting if the LDO regulator is turned off. */
1399 return;
1400 }
1401 #endif
1402
1403 while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) {
1404 }
1405 }
1406 #endif
1407
1408 #if defined(EMU_VSCALE_EM01_PRESENT)
1409 /***************************************************************************//**
1410 * @brief
1411 * Get current voltage scaling level.
1412 *
1413 * @return
1414 * Current voltage scaling level.
1415 ******************************************************************************/
EMU_VScaleGet(void)1416 __STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void)
1417 {
1418 EMU_VScaleWait();
1419 return (EMU_VScaleEM01_TypeDef)((uint32_t)
1420 ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK)
1421 >> _EMU_STATUS_VSCALE_SHIFT));
1422 }
1423 #endif
1424
1425 #if defined(_EMU_STATUS_VMONRDY_MASK)
1426 /***************************************************************************//**
1427 * @brief
1428 * Get the status of the voltage monitor (VMON).
1429 *
1430 * @return
1431 * Status of the VMON. True if all the enabled channels are ready, false if
1432 * one or more of the enabled channels are not ready.
1433 ******************************************************************************/
EMU_VmonStatusGet(void)1434 __STATIC_INLINE bool EMU_VmonStatusGet(void)
1435 {
1436 return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U;
1437 }
1438 #endif /* _EMU_STATUS_VMONRDY_MASK */
1439
1440 #if defined(_EMU_IF_MASK)
1441 /***************************************************************************//**
1442 * @brief
1443 * Clear one or more pending EMU interrupts.
1444 *
1445 * @param[in] flags
1446 * Pending EMU interrupt sources to clear. Use one or more valid
1447 * interrupt flags for the EMU module (EMU_IFC_nnn or EMU_IF_nnn).
1448 ******************************************************************************/
EMU_IntClear(uint32_t flags)1449 __STATIC_INLINE void EMU_IntClear(uint32_t flags)
1450 {
1451 #if defined(EMU_HAS_SET_CLEAR)
1452 EMU->IF_CLR = flags;
1453 #else
1454 EMU->IFC = flags;
1455 #endif
1456 }
1457
1458 /***************************************************************************//**
1459 * @brief
1460 * Disable one or more EMU interrupts.
1461 *
1462 * @param[in] flags
1463 * EMU interrupt sources to disable. Use one or more valid
1464 * interrupt flags for the EMU module (EMU_IEN_nnn).
1465 ******************************************************************************/
EMU_IntDisable(uint32_t flags)1466 __STATIC_INLINE void EMU_IntDisable(uint32_t flags)
1467 {
1468 #if defined(EMU_HAS_SET_CLEAR)
1469 EMU->IEN_CLR = flags;
1470 #else
1471 EMU->IEN &= ~flags;
1472 #endif
1473 }
1474
1475 /***************************************************************************//**
1476 * @brief
1477 * Enable one or more EMU interrupts.
1478 *
1479 * @note
1480 * Depending on the use, a pending interrupt may already be set prior to
1481 * enabling the interrupt. To ignore a pending interrupt, consider using
1482 * @ref EMU_IntClear() prior to enabling the interrupt.
1483 *
1484 * @param[in] flags
1485 * EMU interrupt sources to enable. Use one or more valid
1486 * interrupt flags for the EMU module (EMU_IEN_nnn).
1487 ******************************************************************************/
EMU_IntEnable(uint32_t flags)1488 __STATIC_INLINE void EMU_IntEnable(uint32_t flags)
1489 {
1490 #if defined(EMU_HAS_SET_CLEAR)
1491 EMU->IEN_SET = flags;
1492 #else
1493 EMU->IEN |= flags;
1494 #endif
1495 }
1496
1497 #if defined(EMU_CTRL_EFPDRVDVDD)
1498 /***************************************************************************//**
1499 * @brief
1500 * Disable one or more EFP interrupts.
1501 *
1502 * @param[in] flags
1503 * EFP interrupt sources to disable. Use one or more valid
1504 * interrupt flags for the EFP module (EFPIENnnn).
1505 ******************************************************************************/
EMU_EFPIntDisable(uint32_t flags)1506 __STATIC_INLINE void EMU_EFPIntDisable(uint32_t flags)
1507 {
1508 EMU->EFPIEN_CLR = flags;
1509 }
1510
1511 /***************************************************************************//**
1512 * @brief
1513 * Enable one or more EFP interrupts.
1514 *
1515 * @param[in] flags
1516 * EFP interrupt sources to enable. Use one or more valid
1517 * interrupt flags for the EFP module (EFPIENnnn).
1518 ******************************************************************************/
EMU_EFPIntEnable(uint32_t flags)1519 __STATIC_INLINE void EMU_EFPIntEnable(uint32_t flags)
1520 {
1521 EMU->EFPIEN_SET = flags;
1522 }
1523
1524 /***************************************************************************//**
1525 * @brief
1526 * Get pending EMU EFP interrupt flags.
1527 *
1528 * @note
1529 * Event bits are not cleared by the use of this function.
1530 *
1531 * @return
1532 * EMU EFP interrupt sources pending. .
1533 ******************************************************************************/
EMU_EFPIntGet(void)1534 __STATIC_INLINE uint32_t EMU_EFPIntGet(void)
1535 {
1536 return EMU->EFPIF;
1537 }
1538
1539 /***************************************************************************//**
1540 * @brief
1541 * Get enabled and pending EMU EFP interrupt flags.
1542 * Useful for handling more interrupt sources in the same interrupt handler.
1543 *
1544 * @note
1545 * Interrupt flags are not cleared by the use of this function.
1546 *
1547 * @return
1548 * Pending and enabled EMU EFP interrupt sources
1549 * Return value is the bitwise AND of
1550 * - the enabled interrupt sources in EMU_EFPIEN and
1551 * - the pending interrupt flags EMU_EFPIF.
1552 ******************************************************************************/
EMU_EFPIntGetEnabled(void)1553 __STATIC_INLINE uint32_t EMU_EFPIntGetEnabled(void)
1554 {
1555 uint32_t ien;
1556
1557 ien = EMU->EFPIEN;
1558 return EMU->EFPIF & ien;
1559 }
1560
1561 /***************************************************************************//**
1562 * @brief
1563 * Set one or more pending EMU EFP interrupts.
1564 *
1565 * @param[in] flags
1566 * EMU EFP interrupt sources to set to pending. Use one or more valid
1567 * interrupt flags for the EMU EFP module (EMU_EFPIFSnnn).
1568 ******************************************************************************/
EMU_EFPIntSet(uint32_t flags)1569 __STATIC_INLINE void EMU_EFPIntSet(uint32_t flags)
1570 {
1571 EMU->EFPIF_SET = flags;
1572 }
1573
1574 /***************************************************************************//**
1575 * @brief
1576 * Clear one or more pending EMU EFP interrupts.
1577 *
1578 * @param[in] flags
1579 * Pending EMU EFP interrupt sources to clear. Use one or more valid
1580 * interrupt flags for the EMU EFP module.
1581 ******************************************************************************/
EMU_EFPIntClear(uint32_t flags)1582 __STATIC_INLINE void EMU_EFPIntClear(uint32_t flags)
1583 {
1584 EMU->EFPIF_CLR = flags;
1585 }
1586 #endif
1587
1588 /***************************************************************************//**
1589 * @brief
1590 * Get pending EMU interrupt flags.
1591 *
1592 * @note
1593 * Event bits are not cleared by the use of this function.
1594 *
1595 * @return
1596 * EMU interrupt sources pending. Returns one or more valid
1597 * interrupt flags for the EMU module (EMU_IF_nnn).
1598 ******************************************************************************/
EMU_IntGet(void)1599 __STATIC_INLINE uint32_t EMU_IntGet(void)
1600 {
1601 return EMU->IF;
1602 }
1603
1604 /***************************************************************************//**
1605 * @brief
1606 * Get enabled and pending EMU interrupt flags.
1607 * Useful for handling more interrupt sources in the same interrupt handler.
1608 *
1609 * @note
1610 * Interrupt flags are not cleared by the use of this function.
1611 *
1612 * @return
1613 * Pending and enabled EMU interrupt sources
1614 * Return value is the bitwise AND of
1615 * - the enabled interrupt sources in EMU_IEN and
1616 * - the pending interrupt flags EMU_IF.
1617 ******************************************************************************/
EMU_IntGetEnabled(void)1618 __STATIC_INLINE uint32_t EMU_IntGetEnabled(void)
1619 {
1620 uint32_t ien;
1621
1622 ien = EMU->IEN;
1623 return EMU->IF & ien;
1624 }
1625
1626 /***************************************************************************//**
1627 * @brief
1628 * Set one or more pending EMU interrupts.
1629 *
1630 * @param[in] flags
1631 * EMU interrupt sources to set to pending. Use one or more valid
1632 * interrupt flags for the EMU module (EMU_IFS_nnn).
1633 ******************************************************************************/
EMU_IntSet(uint32_t flags)1634 __STATIC_INLINE void EMU_IntSet(uint32_t flags)
1635 {
1636 #if defined(EMU_HAS_SET_CLEAR)
1637 EMU->IF_SET = flags;
1638 #else
1639 EMU->IFS = flags;
1640 #endif
1641 }
1642 #endif /* _EMU_IF_MASK */
1643
1644 #if defined(_EMU_EM4CONF_LOCKCONF_MASK)
1645 /***************************************************************************//**
1646 * @brief
1647 * Enable or disable EM4 lock configuration.
1648 * @param[in] enable
1649 * If true, locks down EM4 configuration.
1650 ******************************************************************************/
EMU_EM4Lock(bool enable)1651 __STATIC_INLINE void EMU_EM4Lock(bool enable)
1652 {
1653 BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable);
1654 }
1655 #endif
1656
1657 #if defined(_EMU_STATUS_BURDY_MASK)
1658 /***************************************************************************//**
1659 * @brief
1660 * Halts until backup power functionality is ready.
1661 ******************************************************************************/
EMU_BUReady(void)1662 __STATIC_INLINE void EMU_BUReady(void)
1663 {
1664 while (!(EMU->STATUS & EMU_STATUS_BURDY))
1665 ;
1666 }
1667 #endif
1668
1669 #if defined(_EMU_ROUTE_BUVINPEN_MASK)
1670 /***************************************************************************//**
1671 * @brief
1672 * Disable BU_VIN support.
1673 * @param[in] enable
1674 * If true, enables BU_VIN input pin support, if false disables it.
1675 ******************************************************************************/
EMU_BUPinEnable(bool enable)1676 __STATIC_INLINE void EMU_BUPinEnable(bool enable)
1677 {
1678 BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable);
1679 }
1680 #endif
1681
1682 /***************************************************************************//**
1683 * @brief
1684 * Lock EMU registers in order to protect them against unintended
1685 * modification.
1686 *
1687 * @note
1688 * If locking EMU registers, they must be unlocked prior to using any
1689 * EMU API functions modifying EMU registers, excluding interrupt control
1690 * and regulator control if the architecture has a EMU_PWRCTRL register.
1691 * An exception to this is the energy mode entering API (EMU_EnterEMn()),
1692 * which can be used when the EMU registers are locked.
1693 ******************************************************************************/
EMU_Lock(void)1694 __STATIC_INLINE void EMU_Lock(void)
1695 {
1696 EMU->LOCK = 0x0;
1697 }
1698
1699 /***************************************************************************//**
1700 * @brief
1701 * Unlock the EMU so that writing to locked registers again is possible.
1702 ******************************************************************************/
EMU_Unlock(void)1703 __STATIC_INLINE void EMU_Unlock(void)
1704 {
1705 EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;
1706 }
1707
1708 #if defined(_EMU_PWRLOCK_MASK)
1709 /***************************************************************************//**
1710 * @brief
1711 * Lock the EMU regulator control registers in order to protect against
1712 * unintended modification.
1713 ******************************************************************************/
EMU_PowerLock(void)1714 __STATIC_INLINE void EMU_PowerLock(void)
1715 {
1716 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
1717 }
1718
1719 /***************************************************************************//**
1720 * @brief
1721 * Unlock the EMU power control registers so that writing to
1722 * locked registers again is possible.
1723 ******************************************************************************/
EMU_PowerUnlock(void)1724 __STATIC_INLINE void EMU_PowerUnlock(void)
1725 {
1726 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK;
1727 }
1728 #endif
1729
1730 #if defined(_EMU_CTRL_EM2BLOCK_MASK)
1731 /***************************************************************************//**
1732 * @brief
1733 * Block entering EM2 or higher number energy modes.
1734 ******************************************************************************/
EMU_EM2Block(void)1735 __STATIC_INLINE void EMU_EM2Block(void)
1736 {
1737 BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 1U);
1738 }
1739
1740 /***************************************************************************//**
1741 * @brief
1742 * Unblock entering EM2 or higher number energy modes.
1743 ******************************************************************************/
EMU_EM2UnBlock(void)1744 __STATIC_INLINE void EMU_EM2UnBlock(void)
1745 {
1746 BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 0U);
1747 }
1748 #endif
1749
1750 #if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK)
1751 /***************************************************************************//**
1752 * @brief
1753 * When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained
1754 * through EM4 entry and wakeup. The pin state is released by calling this function.
1755 * The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset),
1756 * and when initialization is done, this function can release pins and return control
1757 * to the peripherals or GPIO.
1758 ******************************************************************************/
EMU_UnlatchPinRetention(void)1759 __STATIC_INLINE void EMU_UnlatchPinRetention(void)
1760 {
1761 EMU->CMD = EMU_CMD_EM4UNLATCH;
1762 }
1763 #endif
1764
1765 #if defined(_EMU_TEMP_TEMP_MASK)
1766 /** Zero degrees Celcius in Kelvin */
1767 #define EMU_TEMP_ZERO_C_IN_KELVIN (273.15f)
1768 /***************************************************************************//**
1769 * @brief
1770 * Temperature measurement ready status
1771 *
1772 * @return
1773 * True if temperature measurement is ready
1774 ******************************************************************************/
EMU_TemperatureReady(void)1775 __STATIC_INLINE bool EMU_TemperatureReady(void)
1776 {
1777 #if defined(EMU_STATUS_FIRSTTEMPDONE)
1778 return (0UL != (EMU->STATUS & EMU_STATUS_FIRSTTEMPDONE));
1779 #else
1780 return !((EMU->TEMP & _EMU_TEMP_TEMP_MASK) == 0u);
1781 #endif
1782 }
1783
1784 #if defined(_EMU_TEMP_TEMPAVG_MASK)
1785 /***************************************************************************//**
1786 * @brief
1787 * Get averaged temperature in degrees Celsius.
1788 *
1789 * @note
1790 * An averaged temperature measurement must first be requested by calling
1791 * @ref EMU_TemperatureAvgRequest() and waiting for the TEMPAVG interrupt flag
1792 * to go high.
1793 *
1794 * @return
1795 * Averaged temperature
1796 ******************************************************************************/
EMU_TemperatureAvgGet(void)1797 __STATIC_INLINE float EMU_TemperatureAvgGet(void)
1798 {
1799 uint32_t tmp = ((EMU->TEMP & _EMU_TEMP_TEMPAVG_MASK)
1800 >> _EMU_TEMP_TEMPAVG_SHIFT);
1801 return (float)tmp / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN;
1802 }
1803
1804 /***************************************************************************//**
1805 * @brief
1806 * Request averaged temperature.
1807 *
1808 * @note
1809 * EMU must be unlocked by calling @ref EMU_Unlock() before this function
1810 * can be called.
1811 *
1812 * @param[in] numSamples
1813 * Number of temperature samples to average
1814 ******************************************************************************/
EMU_TemperatureAvgRequest(EMU_TempAvgNum_TypeDef numSamples)1815 __STATIC_INLINE void EMU_TemperatureAvgRequest(EMU_TempAvgNum_TypeDef numSamples)
1816 {
1817 BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_TEMPAVGNUM_SHIFT, (unsigned int)numSamples);
1818 EMU->CMD = 1u << _EMU_CMD_TEMPAVGREQ_SHIFT;
1819 }
1820
1821 #endif //defined(_EMU_TEMP_TEMPAVG_MASK)
1822 #endif //defined(_EMU_TEMP_TEMP_MASK)
1823
1824 /** @} (end addtogroup emu) */
1825
1826 #ifdef __cplusplus
1827 }
1828 #endif
1829
1830 #endif /* defined( EMU_PRESENT ) */
1831 #endif /* EM_EMU_H */
1832
