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Searched refs:CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (Results 1 – 21 of 21) sorted by relevance

/hal_silabs-latest/simplicity_sdk/platform/service/clock_manager/config/EFX32XG21/
Dsl_clock_manager_tree_config.h150 #define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
/hal_silabs-latest/simplicity_sdk/platform/service/clock_manager/config/EFX32XG22/
Dsl_clock_manager_tree_config.h165 #define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
/hal_silabs-latest/simplicity_sdk/platform/service/clock_manager/config/EFX32XG27/
Dsl_clock_manager_tree_config.h176 #define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
/hal_silabs-latest/simplicity_sdk/platform/service/clock_manager/config/EFX32XG29/
Dsl_clock_manager_tree_config.h187 #define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
/hal_silabs-latest/simplicity_sdk/platform/service/clock_manager/config/EFX32XG25/
Dsl_clock_manager_tree_config.h182 #define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
/hal_silabs-latest/simplicity_sdk/platform/service/clock_manager/config/EFX32XG24/
Dsl_clock_manager_tree_config.h181 #define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
/hal_silabs-latest/simplicity_sdk/platform/service/clock_manager/config/EFX32XG23/
Dsl_clock_manager_tree_config.h169 #define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
/hal_silabs-latest/simplicity_sdk/platform/service/clock_manager/config/EFX32XG26/
Dsl_clock_manager_tree_config.h181 #define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
/hal_silabs-latest/simplicity_sdk/platform/service/clock_manager/config/EFX32XG28/
Dsl_clock_manager_tree_config.h181 #define SL_CLOCK_MANAGER_IADCCLK_SOURCE CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21_cmu.h576 #define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< … macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27_cmu.h903 #define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< … macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22_cmu.h885 #define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< … macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG29/Include/
Defr32mg29_cmu.h931 #define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**… macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32BG29/Include/
Defr32bg29_cmu.h931 #define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**… macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32FG23/Include/
Defr32fg23_cmu.h984 #define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< … macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24_cmu.h985 #define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< … macro
/hal_silabs-latest/simplicity_sdk/platform/Device/SiliconLabs/EFR32ZG23/Include/
Defr32zg23_cmu.h984 #define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< … macro
/hal_silabs-latest/simplicity_sdk/platform/emlib/inc/
Dsli_em_cmu.h143 | CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; \
/hal_silabs-latest/gecko/emlib/inc/
Dsli_em_cmu.h143 | CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; \
/hal_silabs-latest/simplicity_sdk/platform/emlib/src/
Dem_cmu.c1669 tmp = CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; in CMU_ClockSelectSet()
5075 case CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK: in iadcClkGet()
/hal_silabs-latest/gecko/emlib/src/
Dem_cmu.c1644 tmp = CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; in CMU_ClockSelectSet()
5022 case CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK: in iadcClkGet()