1 /***************************************************************************//** 2 * @file 3 * @brief Clock Management Unit Private API definition. 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #ifndef SLI_EM_CMU_H 32 #define SLI_EM_CMU_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ 39 #if defined(_SILICON_LABS_32B_SERIES_2) 40 41 /***************************************************************************//** 42 * @brief Performs pre-clock-selection operations to initialize the system clock. 43 * 44 * @note FOR INTERNAL USE ONLY. 45 * 46 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 47 * the clock is SYSCLK. 48 ******************************************************************************/ 49 void sli_em_cmu_SYSCLKInitPreClockSelect(void); 50 51 /***************************************************************************//** 52 * @brief Performs post-clock-selection operations to initialize the system clock. 53 * 54 * @note FOR INTERNAL USE ONLY. 55 * 56 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 57 * the clock is SYSCLK. 58 ******************************************************************************/ 59 void sli_em_cmu_SYSCLKInitPostClockSelect(bool optimize_divider); 60 61 /***************************************************************************//** 62 * @brief Sets the HFXO0 FORCEEN bit. 63 * 64 * @note FOR INTERNAL USE ONLY. 65 * 66 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 67 * the clock is SYSCLK and the selected clock source is HFXO. 68 ******************************************************************************/ 69 void sli_em_cmu_HFXOSetForceEnable(void); 70 71 /***************************************************************************//** 72 * @brief This function will set the SYSCFG->CFGSYSTIC<SYSTICEXTCLKEN> bit. 73 * 74 * @note FOR INTERNAL USE ONLY. 75 * 76 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 77 * the clock is SYSTICK. 78 ******************************************************************************/ 79 void sli_em_cmu_SYSTICEXTCLKENSet(void); 80 81 /***************************************************************************//** 82 * @brief This function will clear the SYSCFG->CFGSYSTIC<SYSTICEXTCLKEN> bit. 83 * 84 * @note FOR INTERNAL USE ONLY. 85 * 86 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 87 * the clock is SYSTICK. 88 ******************************************************************************/ 89 void sli_em_cmu_SYSTICEXTCLKENClear(void); 90 91 #define CMU_SYSCLK_SELECT_HFRCODPLL \ 92 do { \ 93 sli_em_cmu_SYSCLKInitPreClockSelect(); \ 94 CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ 95 | CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; \ 96 sli_em_cmu_SYSCLKInitPostClockSelect(true); \ 97 } while (0) 98 99 #define CMU_SYSCLK_SELECT_HFXO \ 100 do { \ 101 sli_em_cmu_HFXOSetForceEnable(); \ 102 sli_em_cmu_SYSCLKInitPreClockSelect(); \ 103 CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ 104 | CMU_SYSCLKCTRL_CLKSEL_HFXO; \ 105 sli_em_cmu_SYSCLKInitPostClockSelect(true); \ 106 if ((HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) == 0) { \ 107 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; \ 108 } \ 109 } while (0) 110 111 #define CMU_SYSCLK_SELECT_CLKIN0 \ 112 do { \ 113 sli_em_cmu_SYSCLKInitPreClockSelect(); \ 114 CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ 115 | CMU_SYSCLKCTRL_CLKSEL_CLKIN0; \ 116 sli_em_cmu_SYSCLKInitPostClockSelect(true); \ 117 } while (0) 118 119 #define CMU_SYSCLK_SELECT_FSRCO \ 120 do { \ 121 sli_em_cmu_SYSCLKInitPreClockSelect(); \ 122 CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ 123 | CMU_SYSCLKCTRL_CLKSEL_FSRCO; \ 124 sli_em_cmu_SYSCLKInitPostClockSelect(true); \ 125 } while (0) 126 127 #if defined(RFFPLL_PRESENT) 128 129 #define CMU_SYSCLK_SELECT_RFFPLLSYS \ 130 do { \ 131 sli_em_cmu_SYSCLKInitPreClockSelect(); \ 132 CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ 133 | CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; \ 134 sli_em_cmu_SYSCLKInitPostClockSelect(true); \ 135 } while (0) 136 137 #endif /* RFFPLL_PRESENT */ 138 139 #if defined(IADC_PRESENT) 140 #define CMU_IADCCLK_SELECT_EM01GRPACLK \ 141 do { \ 142 CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ 143 | CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; \ 144 } while (0) 145 146 #define CMU_IADC0_SELECT_EM01GRPACLK CMU_IADCCLK_SELECT_EM01GRPACLK 147 148 #if defined(HFRCOEM23_PRESENT) 149 #define CMU_IADCCLK_SELECT_HFRCOEM23 \ 150 do { \ 151 CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ 152 | CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; \ 153 } while (0) 154 155 #define CMU_IADC0_SELECT_HFRCOEM23 CMU_IADCCLK_SELECT_HFRCOEM23 156 #endif /* HFRCOEM23_PRESENT */ 157 158 #define CMU_IADCCLK_SELECT_FSRCO \ 159 do { \ 160 CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ 161 | CMU_IADCCLKCTRL_CLKSEL_FSRCO; \ 162 } while (0) 163 164 #define CMU_IADC0_SELECT_FSRCO CMU_IADCCLK_SELECT_FSRCO 165 #endif /* IADC_PRESENT */ 166 167 #define CMU_EM01GRPACLK_SELECT_HFRCODPLL \ 168 do { \ 169 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 170 | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; \ 171 } while (0) 172 173 #define CMU_TIMER0_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 174 #define CMU_TIMER1_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 175 #define CMU_TIMER2_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 176 #define CMU_TIMER3_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 177 #if TIMER_COUNT > 4 178 #define CMU_TIMER4_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 179 #endif /* TIMER_COUNT > 4 */ 180 #if TIMER_COUNT > 7 181 #define CMU_TIMER5_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 182 #define CMU_TIMER6_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 183 #define CMU_TIMER7_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 184 #endif /* TIMER_COUNT > 7 */ 185 #if TIMER_COUNT > 9 186 #define CMU_TIMER8_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 187 #define CMU_TIMER9_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 188 #endif /* TIMER_COUNT > 9 */ 189 #if defined(KEYSCAN_PRESENT) 190 #define CMU_KEYSCAN_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 191 #endif /* KEYSCAN_PRESENT*/ 192 193 #define CMU_EM01GRPACLK_SELECT_HFXO \ 194 do { \ 195 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 196 | CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; \ 197 } while (0) 198 199 #define CMU_TIMER0_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 200 #define CMU_TIMER1_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 201 #define CMU_TIMER2_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 202 #define CMU_TIMER3_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 203 #if TIMER_COUNT > 4 204 #define CMU_TIMER4_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 205 #endif /* TIMER_COUNT > 4 */ 206 #if TIMER_COUNT > 7 207 #define CMU_TIMER5_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 208 #define CMU_TIMER6_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 209 #define CMU_TIMER7_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 210 #endif /* TIMER_COUNT > 7 */ 211 #if TIMER_COUNT > 9 212 #define CMU_TIMER8_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 213 #define CMU_TIMER9_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 214 #endif /* TIMER_COUNT > 9 */ 215 #if defined(KEYSCAN_PRESENT) 216 #define CMU_KEYSCAN_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 217 #endif /* KEYSCAN_PRESENT*/ 218 219 #if defined(HFRCOEM23_PRESENT) 220 #define CMU_EM01GRPACLK_SELECT_HFRCOEM23 \ 221 do { \ 222 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 223 | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; \ 224 } while (0) 225 226 #define CMU_TIMER0_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 227 #define CMU_TIMER1_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 228 #define CMU_TIMER2_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 229 #define CMU_TIMER3_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 230 #if TIMER_COUNT > 4 231 #define CMU_TIMER4_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 232 #endif /* TIMER_COUNT > 4 */ 233 #if TIMER_COUNT > 7 234 #define CMU_TIMER5_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 235 #define CMU_TIMER6_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 236 #define CMU_TIMER7_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 237 #endif /* TIMER_COUNT > 7 */ 238 #if TIMER_COUNT > 9 239 #define CMU_TIMER8_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 240 #define CMU_TIMER9_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 241 #endif /* TIMER_COUNT > 9 */ 242 #if defined(KEYSCAN_PRESENT) 243 #define CMU_KEYSCAN_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 244 #endif /* KEYSCAN_PRESENT*/ 245 #endif /* HFRCOEM23_PRESENT */ 246 247 #define CMU_EM01GRPACLK_SELECT_FSRCO \ 248 do { \ 249 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 250 | CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; \ 251 } while (0) 252 253 #define CMU_TIMER0_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 254 #define CMU_TIMER1_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 255 #define CMU_TIMER2_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 256 #define CMU_TIMER3_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 257 #if TIMER_COUNT > 4 258 #define CMU_TIMER4_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 259 #endif /* TIMER_COUNT > 4 */ 260 #if TIMER_COUNT > 7 261 #define CMU_TIMER5_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 262 #define CMU_TIMER6_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 263 #define CMU_TIMER7_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 264 #endif /* TIMER_COUNT > 7 */ 265 #if TIMER_COUNT > 9 266 #define CMU_TIMER8_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 267 #define CMU_TIMER9_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 268 #endif /* TIMER_COUNT > 9 */ 269 #if defined(KEYSCAN_PRESENT) 270 #define CMU_KEYSCAN_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 271 #endif /* KEYSCAN_PRESENT*/ 272 273 #define CMU_EM01GRPACLK_SELECT_DISABLED \ 274 do { \ 275 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 276 | CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; \ 277 } while (0) 278 279 #if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) 280 #define CMU_EM01GRPACLK_SELECT_HFRCODPLLRT \ 281 do { \ 282 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 283 | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; \ 284 } while (0) 285 286 #define CMU_TIMER0_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 287 #define CMU_TIMER1_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 288 #define CMU_TIMER2_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 289 #define CMU_TIMER3_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 290 #if TIMER_COUNT > 4 291 #define CMU_TIMER4_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 292 #endif /* TIMER_COUNT > 4 */ 293 #if TIMER_COUNT > 7 294 #define CMU_TIMER5_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 295 #define CMU_TIMER6_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 296 #define CMU_TIMER7_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 297 #endif /* TIMER_COUNT > 7 */ 298 #if TIMER_COUNT > 9 299 #define CMU_TIMER8_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 300 #define CMU_TIMER9_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 301 #endif /* TIMER_COUNT > 9 */ 302 #if defined(KEYSCAN_PRESENT) 303 #define CMU_KEYSCAN_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 304 #endif /* KEYSCAN_PRESENT*/ 305 #endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT */ 306 307 #if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) 308 #define CMU_EM01GRPACLK_SELECT_HFXORT \ 309 do { \ 310 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 311 | CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; \ 312 } while (0) 313 314 #define CMU_TIMER0_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 315 #define CMU_TIMER1_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 316 #define CMU_TIMER2_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 317 #define CMU_TIMER3_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 318 #if TIMER_COUNT > 4 319 #define CMU_TIMER4_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 320 #endif /* TIMER_COUNT > 4 */ 321 #if TIMER_COUNT > 7 322 #define CMU_TIMER5_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 323 #define CMU_TIMER6_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 324 #define CMU_TIMER7_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 325 #endif /* TIMER_COUNT > 7 */ 326 #if TIMER_COUNT > 9 327 #define CMU_TIMER8_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 328 #define CMU_TIMER9_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 329 #endif /* TIMER_COUNT > 9 */ 330 #if defined(KEYSCAN_PRESENT) 331 #define CMU_KEYSCAN_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 332 #endif /* KEYSCAN_PRESENT*/ 333 #endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT */ 334 335 #define CMU_SYSTICK_SELECT_EM23GRPACLK \ 336 do { \ 337 sli_em_cmu_SYSTICEXTCLKENSet(); \ 338 SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); \ 339 } while (0) 340 341 #define CMU_SYSTICK_SELECT_LFXO CMU_SYSTICK_SELECT_EM23GRPACLK 342 #define CMU_SYSTICK_SELECT_LFRCO CMU_SYSTICK_SELECT_EM23GRPACLK 343 #define CMU_SYSTICK_SELECT_ULFRCO CMU_SYSTICK_SELECT_EM23GRPACLK 344 345 #define CMU_SYSTICK_SELECT_HCLK \ 346 do { \ 347 sli_em_cmu_SYSTICEXTCLKENClear(); \ 348 SysTick->CTRL = (SysTick->CTRL | SysTick_CTRL_CLKSOURCE_Msk); \ 349 } while (0) 350 351 #define CMU_EM23GRPACLK_SELECT_LFRCO \ 352 do { \ 353 CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ 354 | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ 355 } while (0) 356 357 #define CMU_LETIMER0_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO 358 #if defined(LESENSE_PRESENT) 359 #define CMU_LESENSE_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO 360 #define CMU_LESENSECLK_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO 361 #endif /* LESENSE_PRESENT */ 362 363 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 364 #define CMU_EM23GRPACLK_SELECT_PLFRCO \ 365 do { \ 366 CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ 367 | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ 368 } while (0) 369 370 #define CMU_LETIMER0_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO 371 #if defined(LESENSE_PRESENT) 372 #define CMU_LESENSE_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO 373 #define CMU_LESENSECLK_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO 374 #endif /* LESENSE_PRESENT */ 375 #endif /* LFRCO_PRECISION_MODE */ 376 377 #define CMU_EM23GRPACLK_SELECT_LFXO \ 378 do { \ 379 CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ 380 | CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; \ 381 } while (0) 382 383 #define CMU_LETIMER0_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO 384 #if defined(LESENSE_PRESENT) 385 #define CMU_LESENSE_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO 386 #define CMU_LESENSECLK_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO 387 #endif /* LESENSE_PRESENT */ 388 389 #define CMU_EM23GRPACLK_SELECT_ULFRCO \ 390 do { \ 391 CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ 392 | CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; \ 393 } while (0) 394 395 #define CMU_LETIMER0_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO 396 #if defined(LESENSE_PRESENT) 397 #define CMU_LESENSE_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO 398 #define CMU_LESENSECLK_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO 399 #endif /* LESENSE_PRESENT */ 400 401 #define CMU_EM23GRPACLK_SELECT_DISABLED \ 402 do { \ 403 CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ 404 | CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; \ 405 } while (0) 406 407 #define CMU_EM4GRPACLK_SELECT_LFRCO \ 408 do { \ 409 CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ 410 | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ 411 } while (0) 412 413 #define CMU_BURTC_SELECT_LFRCO CMU_EM4GRPACLK_SELECT_LFRCO 414 415 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 416 #define CMU_EM4GRPACLK_SELECT_PLFRCO \ 417 do { \ 418 CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ 419 | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ 420 } while (0) 421 422 #define CMU_BURTC_SELECT_PLFRCO CMU_EM4GRPACLK_SELECT_PLFRCO 423 #endif /* LFRCO_PRECISION_MODE */ 424 425 #define CMU_EM4GRPACLK_SELECT_LFXO \ 426 do { \ 427 CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ 428 | CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; \ 429 } while (0) 430 431 #define CMU_BURTC_SELECT_LFXO CMU_EM4GRPACLK_SELECT_LFXO 432 433 #define CMU_EM4GRPACLK_SELECT_ULFRCO \ 434 do { \ 435 CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ 436 | CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; \ 437 } while (0) 438 439 #define CMU_BURTC_SELECT_ULFRCO CMU_EM4GRPACLK_SELECT_ULFRCO 440 441 #define CMU_EM4GRPACLK_SELECT_DISABLED \ 442 do { \ 443 CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ 444 | CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; \ 445 } while (0) 446 447 #if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) 448 #define CMU_EM01GRPBCLK_SELECT_HFRCODPLL \ 449 do { \ 450 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 451 | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; \ 452 } while (0) 453 454 #define CMU_PDMREF_SELECT_HFRCODPLL CMU_EM01GRPBCLK_SELECT_HFRCODPLL 455 456 #define CMU_EM01GRPBCLK_SELECT_HFXO \ 457 do { \ 458 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 459 | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; \ 460 } while (0) 461 462 #define CMU_PDMREF_SELECT_HFXO CMU_EM01GRPBCLK_SELECT_HFXO 463 464 #define CMU_EM01GRPBCLK_SELECT_FSRCO \ 465 do { \ 466 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 467 | CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; \ 468 } while (0) 469 470 #define CMU_PDMREF_SELECT_FSRCO CMU_EM01GRPBCLK_SELECT_FSRCO 471 472 #define CMU_EM01GRPBCLK_SELECT_CLKIN0 \ 473 do { \ 474 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 475 | CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; \ 476 } while (0) 477 478 #define CMU_PDMREF_SELECT_CLKIN0 CMU_EM01GRPBCLK_SELECT_CLKIN0 479 480 #define CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT \ 481 do { \ 482 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 483 | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; \ 484 } while (0) 485 486 #define CMU_PDMREF_SELECT_HFRCODPLLRT CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT 487 488 #define CMU_EM01GRPBCLK_SELECT_HFXORT \ 489 do { \ 490 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 491 | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; \ 492 } while (0) 493 494 #define CMU_PDMREF_SELECT_HFXORT CMU_EM01GRPBCLK_SELECT_HFXORT 495 496 #define CMU_EM01GRPBCLK_SELECT_DISABLED \ 497 do { \ 498 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 499 | CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; \ 500 } while (0) 501 502 #endif /* defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) */ 503 504 #define CMU_WDOG0_SELECT_LFRCO \ 505 do { \ 506 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 507 | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ 508 } while (0) 509 510 #define CMU_WDOG0CLK_SELECT_LFRCO CMU_WDOG0_SELECT_LFRCO 511 512 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 513 #define CMU_WDOG0_SELECT_PLFRCO \ 514 do { \ 515 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 516 | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ 517 } while (0) 518 519 #define CMU_WDOG0CLK_SELECT_PLFRCO CMU_WDOG0_SELECT_PLFRCO 520 #endif /* LFRCO_PRECISION_MODE */ 521 522 #define CMU_WDOG0_SELECT_LFXO \ 523 do { \ 524 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 525 | CMU_WDOG0CLKCTRL_CLKSEL_LFXO; \ 526 } while (0) 527 528 #define CMU_WDOG0CLK_SELECT_LFXO CMU_WDOG0_SELECT_LFXO 529 530 #define CMU_WDOG0_SELECT_ULFRCO \ 531 do { \ 532 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 533 | CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; \ 534 } while (0) 535 536 #define CMU_WDOG0CLK_SELECT_ULFRCO CMU_WDOG0_SELECT_ULFRCO 537 538 #define CMU_WDOG0_SELECT_HCLKDIV1024 \ 539 do { \ 540 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 541 | CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; \ 542 } while (0) 543 544 #define CMU_WDOG0CLK_SELECT_HCLKDIV1024 CMU_WDOG0_SELECT_HCLKDIV1024 545 546 #define CMU_WDOG0_SELECT_DISABLED \ 547 do { \ 548 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 549 | CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; \ 550 } while (0) 551 #define CMU_WDOG0CLK_SELECT_DISABLED CMU_WDOG0_SELECT_DISABLED 552 553 #if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) 554 #define CMU_WDOG1_SELECT_LFRCO \ 555 do { \ 556 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 557 | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ 558 } while (0) 559 560 #define CMU_WDOG1CLK_SELECT_LFRCO CMU_WDOG1_SELECT_LFRCO 561 562 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 563 #define CMU_WDOG1_SELECT_PLFRCO \ 564 do { \ 565 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 566 | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ 567 } while (0) 568 569 #define CMU_WDOG1CLK_SELECT_PLFRCO CMU_WDOG1_SELECT_PLFRCO 570 #endif /* LFRCO_PRECISION_MODE */ 571 572 #define CMU_WDOG1_SELECT_LFXO \ 573 do { \ 574 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 575 | CMU_WDOG1CLKCTRL_CLKSEL_LFXO; \ 576 } while (0) 577 578 #define CMU_WDOG1CLK_SELECT_LFXO CMU_WDOG1_SELECT_LFXO 579 580 #define CMU_WDOG1_SELECT_ULFRCO \ 581 do { \ 582 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 583 | CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; \ 584 } while (0) 585 586 #define CMU_WDOG1CLK_SELECT_ULFRCO CMU_WDOG1_SELECT_ULFRCO 587 588 #define CMU_WDOG1_SELECT_HCLKDIV1024 \ 589 do { \ 590 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 591 | CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; \ 592 } while (0) 593 594 #define CMU_WDOG1CLK_SELECT_HCLKDIV1024 CMU_WDOG1_SELECT_HCLKDIV1024 595 596 #define CMU_WDOG1_SELECT_DISABLED \ 597 do { \ 598 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 599 | CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; \ 600 } while (0) 601 #define CMU_WDOG1CLK_SELECT_DISABLED CMU_WDOG1_SELECT_DISABLED 602 #endif /* defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) */ 603 604 #define CMU_DPLLREFCLK_SELECT_HFXO \ 605 do { \ 606 CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ 607 | CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; \ 608 } while (0) 609 610 #define CMU_DPLLREFCLK_SELECT_LFXO \ 611 do { \ 612 CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ 613 | CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; \ 614 } while (0) 615 616 #define CMU_DPLLREFCLK_SELECT_CLKIN0 \ 617 do { \ 618 CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ 619 | CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; \ 620 } while (0) 621 622 #define CMU_DPLLREFCLK_SELECT_DISABLED \ 623 do { \ 624 CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ 625 | CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; \ 626 } while (0) 627 628 #if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ 629 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ 630 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ 631 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ 632 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ 633 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9)) \ 634 && defined(CoreDebug_DEMCR_TRCENA_Msk) 635 #define CMU_TRACECLK_RESTORE_TRACE_PRE() \ 636 bool restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; \ 637 if (restoreTrace) { \ 638 CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; \ 639 } \ 640 do {} while (0) 641 642 #define CMU_TRACECLK_RESTORE_TRACE_POST() \ 643 if (restoreTrace) { \ 644 CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; \ 645 } \ 646 do {} while (0) 647 648 #else 649 #define CMU_TRACECLK_RESTORE_TRACE_PRE() do {} while (0) 650 #define CMU_TRACECLK_RESTORE_TRACE_POST() do {} while (0) 651 #endif 652 653 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) 654 #define CMU_TRACECLK_SELECT_HCLK \ 655 do { \ 656 CMU_TRACECLK_RESTORE_TRACE_PRE(); \ 657 CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ 658 | CMU_TRACECLKCTRL_CLKSEL_HCLK; \ 659 CMU_TRACECLK_RESTORE_TRACE_POST(); \ 660 } while (0) 661 662 #endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_1 */ 663 664 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ 665 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ 666 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ 667 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ 668 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ 669 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_9) 670 #define CMU_TRACECLK_SELECT_SYSCLK \ 671 do { \ 672 CMU_TRACECLK_RESTORE_TRACE_PRE(); \ 673 CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ 674 | CMU_TRACECLKCTRL_CLKSEL_SYSCLK; \ 675 CMU_TRACECLK_RESTORE_TRACE_POST(); \ 676 } while (0) 677 678 #define CMU_TRACECLK_SELECT_HFRCODPLLRT \ 679 do { \ 680 CMU_TRACECLK_RESTORE_TRACE_PRE(); \ 681 CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ 682 | CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; \ 683 CMU_TRACECLK_RESTORE_TRACE_POST(); \ 684 } while (0) 685 686 #endif 687 688 #if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) 689 #define CMU_TRACECLK_SELECT_HFRCOEM23 \ 690 do { \ 691 CMU_TRACECLK_RESTORE_TRACE_PRE(); \ 692 CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ 693 | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; \ 694 CMU_TRACECLK_RESTORE_TRACE_POST(); \ 695 } while (0) 696 697 #endif /* CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 */ 698 699 #if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) 700 #define CMU_EUART0_SELECT_EM01GRPACLK \ 701 do { \ 702 CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ 703 | _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; \ 704 } while (0) 705 706 #define CMU_EUART0CLK_SELECT_EM01GRPACLK CMU_EUART0_SELECT_EM01GRPACLK 707 708 #define CMU_EUART0_SELECT_EM23GRPACLK \ 709 do { \ 710 CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ 711 | _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; \ 712 } while (0) 713 714 #define CMU_EUART0CLK_SELECT_EM23GRPACLK CMU_EUART0_SELECT_EM23GRPACLK 715 716 #define CMU_EUART0_SELECT_DISABLED \ 717 do { \ 718 CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ 719 | _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; \ 720 } while (0) 721 #define CMU_EUART0CLK_SELECT_DISABLED CMU_EUART0_SELECT_DISABLED 722 #endif /* _CMU_EUART0CLKCTRL_CLKSEL_MASK */ 723 724 #if defined(EUSART_PRESENT) 725 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) 726 #define CMU_EUSART0_SELECT_EM01GRPACLK \ 727 do { \ 728 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 729 | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; \ 730 } while (0) 731 732 #define CMU_EUSART0CLK_SELECT_EM01GRPACLK CMU_EUSART0_SELECT_EM01GRPACLK 733 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK */ 734 735 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) 736 #define CMU_EUSART0_SELECT_EM01GRPCCLK \ 737 do { \ 738 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 739 | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; \ 740 } while (0) 741 742 #define CMU_EUSART0CLK_SELECT_EM01GRPCCLK CMU_EUSART0_SELECT_EM01GRPCCLK 743 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK */ 744 745 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) 746 #define CMU_EUSART0_SELECT_EM23GRPACLK \ 747 do { \ 748 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 749 | _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; \ 750 } while (0) 751 752 #define CMU_EUSART0CLK_SELECT_EM23GRPACLK CMU_EUSART0_SELECT_EM23GRPACLK 753 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK */ 754 755 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) 756 #define CMU_EUSART0_SELECT_FSRCO \ 757 do { \ 758 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 759 | _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; \ 760 } while (0) 761 762 #define CMU_EUSART0CLK_SELECT_FSRCO CMU_EUSART0_SELECT_FSRCO 763 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO */ 764 765 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) 766 #define CMU_EUSART0_SELECT_HFRCOEM23 \ 767 do { \ 768 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 769 | _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; \ 770 } while (0) 771 772 #define CMU_EUSART0CLK_SELECT_HFRCOEM23 CMU_EUSART0_SELECT_HFRCOEM23 773 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 */ 774 775 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) 776 #define CMU_EUSART0_SELECT_LFRCO \ 777 do { \ 778 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 779 | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ 780 } while (0) 781 782 #define CMU_EUSART0CLK_SELECT_LFRCO CMU_EUSART0_SELECT_LFRCO 783 784 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 785 #define CMU_EUSART0_SELECT_PLFRCO \ 786 do { \ 787 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 788 | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ 789 } while (0) 790 791 #define CMU_EUSART0CLK_SELECT_PLFRCO CMU_EUSART0_SELECT_PLFRCO 792 #endif /* LFRCO_PRECISION_MODE */ 793 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO */ 794 795 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) 796 #define CMU_EUSART0_SELECT_LFXO \ 797 do { \ 798 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 799 | _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; \ 800 } while (0) 801 802 #define CMU_EUSART0CLK_SELECT_LFXO CMU_EUSART0_SELECT_LFXO 803 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFXO */ 804 805 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) 806 #define CMU_EUSART0_SELECT_DISABLED \ 807 do { \ 808 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 809 | _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; \ 810 } while (0) 811 812 #define CMU_EUSART0CLK_SELECT_DISABLED CMU_EUSART0_SELECT_DISABLED 813 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED */ 814 #endif /* EUSART_PRESENT */ 815 816 #if defined(_CMU_EM01GRPCCLKCTRL_MASK) 817 #define CMU_EM01GRPCCLK_SELECT_HFRCODPLL \ 818 do { \ 819 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 820 | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; \ 821 } while (0) 822 823 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 824 #define CMU_EUSART1_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL 825 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 826 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 827 #define CMU_EUSART2_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL 828 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 829 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 830 #define CMU_EUSART3_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL 831 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 832 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 833 #define CMU_EUSART4_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL 834 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 835 836 #if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) 837 #define CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT \ 838 do { \ 839 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 840 | CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; \ 841 } while (0) 842 843 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 844 #define CMU_EUSART1_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT 845 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 846 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 847 #define CMU_EUSART2_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT 848 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 849 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 850 #define CMU_EUSART3_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT 851 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 852 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 853 #define CMU_EUSART4_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT 854 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 855 #endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT */ 856 857 #if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23) 858 #define CMU_EM01GRPCCLK_SELECT_HFRCOEM23 \ 859 do { \ 860 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 861 | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; \ 862 } while (0) 863 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 864 #define CMU_EUSART1_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 865 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 866 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 867 #define CMU_EUSART2_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 868 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 869 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 870 #define CMU_EUSART3_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 871 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 872 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 873 #define CMU_EUSART4_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 874 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 875 #endif 876 877 #define CMU_EM01GRPCCLK_SELECT_FSRCO \ 878 do { \ 879 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 880 | _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; \ 881 } while (0) 882 883 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 884 #define CMU_EUSART1_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO 885 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 886 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 887 #define CMU_EUSART2_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO 888 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 889 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 890 #define CMU_EUSART3_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO 891 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 892 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 893 #define CMU_EUSART4_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO 894 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 895 896 #define CMU_EM01GRPCCLK_SELECT_HFXO \ 897 do { \ 898 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 899 | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; \ 900 } while (0) 901 902 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 903 #define CMU_EUSART1_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO 904 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 905 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 906 #define CMU_EUSART2_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO 907 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 908 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 909 #define CMU_EUSART3_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO 910 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 911 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 912 #define CMU_EUSART4_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO 913 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 914 915 #if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) 916 #define CMU_EM01GRPCCLK_SELECT_HFXORT \ 917 do { \ 918 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 919 | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; \ 920 } while (0) 921 922 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 923 #define CMU_EUSART1_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT 924 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 925 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 926 #define CMU_EUSART2_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT 927 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 928 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 929 #define CMU_EUSART3_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT 930 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 931 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 932 #define CMU_EUSART4_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT 933 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 934 #endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT */ 935 #endif /* _CMU_EM01GRPCCLKCTRL_MASK */ 936 937 #if defined (RTCC_PRESENT) 938 #define CMU_RTCC_SELECT_LFRCO \ 939 do { \ 940 CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ 941 | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ 942 } while (0) 943 944 #define CMU_RTCCCLK_SELECT_LFRCO CMU_RTCC_SELECT_LFRCO 945 946 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 947 #define CMU_RTCC_SELECT_PLFRCO \ 948 do { \ 949 CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ 950 | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ 951 } while (0) 952 953 #define CMU_RTCCCLK_SELECT_PLFRCO CMU_RTCC_SELECT_PLFRCO 954 #endif /* LFRCO_PRECISION_MODE */ 955 956 #define CMU_RTCC_SELECT_LFXO \ 957 do { \ 958 CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ 959 | CMU_RTCCCLKCTRL_CLKSEL_LFXO; \ 960 } while (0) 961 962 #define CMU_RTCCCLK_SELECT_LFXO CMU_RTCC_SELECT_LFXO 963 964 #define CMU_RTCC_SELECT_ULFRCO \ 965 do { \ 966 CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ 967 | CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; \ 968 } while (0) 969 970 #define CMU_RTCCCLK_SELECT_ULFRCO CMU_RTCC_SELECT_ULFRCO 971 972 #endif /* RTCC_PRESENT */ 973 974 #if defined(SYSRTC_PRESENT) 975 #define CMU_SYSRTC_SELECT_LFRCO \ 976 do { \ 977 CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ 978 | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ 979 } while (0) 980 981 #define CMU_SYSRTCCLK_SELECT_LFRCO CMU_SYSRTC_SELECT_LFRCO 982 983 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 984 #define CMU_SYSRTC_SELECT_PLFRCO \ 985 do { \ 986 CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ 987 | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ 988 } while (0) 989 990 #define CMU_SYSRTCCLK_SELECT_PLFRCO CMU_SYSRTC_SELECT_PLFRCO 991 #endif /* LFRCO_PRECISION_MODE */ 992 993 #define CMU_SYSRTC_SELECT_LFXO \ 994 do { \ 995 CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ 996 | CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; \ 997 } while (0) 998 999 #define CMU_SYSRTCCLK_SELECT_LFXO CMU_SYSRTC_SELECT_LFXO 1000 1001 #define CMU_SYSRTC_SELECT_ULFRCO \ 1002 do { \ 1003 CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ 1004 | CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; \ 1005 } while (0) 1006 1007 #define CMU_SYSRTCCLK_SELECT_ULFRCO CMU_SYSRTC_SELECT_ULFRCO 1008 1009 #define CMU_SYSRTC_SELECT_DISABLED \ 1010 do { \ 1011 CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ 1012 | CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; \ 1013 } while (0) 1014 1015 #define CMU_SYSRTCCLK_SELECT_DISABLED CMU_SYSRTC_SELECT_DISABLED 1016 #endif /* SYSRTC_PRESENT */ 1017 1018 #if defined(LCD_PRESENT) 1019 #define CMU_LCD_SELECT_LFRCO \ 1020 do { \ 1021 CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ 1022 | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ 1023 } while (0) 1024 1025 #define CMU_LCDCLK_SELECT_LFRCO CMU_LCD_SELECT_LFRCO 1026 1027 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 1028 #define CMU_LCD_SELECT_PLFRCO \ 1029 do { \ 1030 CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ 1031 | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ 1032 } while (0) 1033 1034 #define CMU_LCDCLK_SELECT_PLFRCO CMU_LCD_SELECT_PLFRCO 1035 #endif /* LFRCO_PRECISION_MODE */ 1036 1037 #define CMU_LCD_SELECT_LFXO \ 1038 do { \ 1039 CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ 1040 | CMU_LCDCLKCTRL_CLKSEL_LFXO; \ 1041 } while (0) 1042 1043 #define CMU_LCDCLK_SELECT_LFXO CMU_LCD_SELECT_LFXO 1044 1045 #define CMU_LCD_SELECT_ULFRCO \ 1046 do { \ 1047 CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ 1048 | CMU_LCDCLKCTRL_CLKSEL_ULFRCO; \ 1049 } while (0) 1050 1051 #define CMU_LCDCLK_SELECT_ULFRCO CMU_LCD_SELECT_ULFRCO 1052 #endif /* LCD_PRESENT */ 1053 1054 #if defined(VDAC_PRESENT) 1055 #define CMU_VDAC0_SELECT_FSRCO \ 1056 do { \ 1057 CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ 1058 | CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; \ 1059 } while (0) 1060 1061 #define CMU_VDAC0CLK_SELECT_FSRCO CMU_VDAC_SELECT_FSRCO 1062 1063 #define CMU_VDAC0_SELECT_HFRCOEM23 \ 1064 do { \ 1065 CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ 1066 | CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; \ 1067 } while (0) 1068 1069 #define CMU_VDAC0CLK_SELECT_HFRCOEM23 CMU_VDAC_SELECT_HFRCOEM23 1070 1071 #define CMU_VDAC0_SELECT_EM01GRPACLK \ 1072 do { \ 1073 CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ 1074 | CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; \ 1075 } while (0) 1076 1077 #define CMU_VDAC0CLK_SELECT_EM01GRPACLK CMU_VDAC_SELECT_EM01GRPACLK 1078 1079 #define CMU_VDAC0_SELECT_EM23GRPACLK \ 1080 do { \ 1081 CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ 1082 | CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; \ 1083 } while (0) 1084 1085 #define CMU_VDAC0CLK_SELECT_EM23GRPACLK CMU_VDAC_SELECT_EM23GRPACLK 1086 1087 #if (VDAC_COUNT > 1) 1088 #define CMU_VDAC1_SELECT_FSRCO \ 1089 do { \ 1090 CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ 1091 | CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; \ 1092 } while (0) 1093 1094 #define CMU_VDAC1CLK_SELECT_FSRCO CMU_VDAC1_SELECT_FSRCO 1095 1096 #define CMU_VDAC1_SELECT_HFRCOEM23 \ 1097 do { \ 1098 CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ 1099 | CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; \ 1100 } while (0) 1101 1102 #define CMU_VDAC1CLK_SELECT_HFRCOEM23 CMU_VDAC1_SELECT_HFRCOEM23 1103 1104 #define CMU_VDAC1_SELECT_EM01GRPACLK \ 1105 do { \ 1106 CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ 1107 | CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; \ 1108 } while (0) 1109 1110 #define CMU_VDAC1CLK_SELECT_EM01GRPACLK CMU_VDAC1_SELECT_EM01GRPACLK 1111 1112 #define CMU_VDAC1_SELECT_EM23GRPACLK \ 1113 do { \ 1114 CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ 1115 | CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; \ 1116 } while (0) 1117 1118 #define CMU_VDAC1CLK_SELECT_EM23GRPACLK CMU_VDAC1_SELECT_EM23GRPACLK 1119 #endif /* VDAC_COUNT > 1 */ 1120 #endif /* VDAC_PRESENT */ 1121 1122 #if defined(PCNT_PRESENT) 1123 #define CMU_PCNT0_SELECT_EM23GRPACLK \ 1124 do { \ 1125 CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ 1126 | CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; \ 1127 } while (0) 1128 1129 #define CMU_PCNT0CLK_SELECT_EM23GRPACLK CMU_PCNT0_SELECT_EM23GRPACLK 1130 1131 #define CMU_PCNT0_SELECT_PCNTEXTCLK \ 1132 do { \ 1133 CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ 1134 | CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; \ 1135 } while (0) 1136 1137 #define CMU_PCNT0CLK_SELECT_PCNTEXTCLK CMU_PCNT0_SELECT_PCNTEXTCLK 1138 #endif /* PCNT_PRESENT */ 1139 1140 #if defined(LESENSE_PRESENT) 1141 #define CMU_LESENSEHFCLK_SELECT_FSRCO \ 1142 do { \ 1143 CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ 1144 | CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; \ 1145 } while (0) 1146 1147 #define CMU_LESENSEHFCLK_SELECT_HFRCOEM23 \ 1148 do { \ 1149 CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ 1150 | CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; \ 1151 } while (0) 1152 #endif /* LESENSE_PRESENT */ 1153 1154 #if defined(USB_PRESENT) 1155 #define CMU_USB_SELECT_USBPLL0 \ 1156 do { \ 1157 CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ 1158 | CMU_USB0CLKCTRL_CLKSEL_USBPLL0; \ 1159 } while (0) 1160 1161 #define CMU_USB_SELECT_LFXO \ 1162 do { \ 1163 CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ 1164 | CMU_USB0CLKCTRL_CLKSEL_LFXO; \ 1165 } while (0) 1166 1167 #define CMU_USB_SELECT_LFRCO \ 1168 do { \ 1169 CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ 1170 | CMU_USB0CLKCTRL_CLKSEL_LFRCO; \ 1171 } while (0) 1172 #endif /* USB_PRESENT */ 1173 1174 #elif defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_0) 1175 1176 /***************************************************************************//** 1177 * @brief This function configures the HFLE wait-states and divider suitable 1178 * for the System Core Clock. 1179 * 1180 * @note FOR INTERNAL USE ONLY. 1181 * 1182 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1183 * the clock source is HFCLKLE. 1184 ******************************************************************************/ 1185 void sli_em_cmu_SetHFLEConfigSystemCoreClock(void); 1186 1187 /***************************************************************************//** 1188 * @brief This function configures the HFLE wait-states and divider suitable 1189 * for the HF Clock. 1190 * 1191 * @note FOR INTERNAL USE ONLY. 1192 * 1193 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1194 * the clock source is HFCLKLE. 1195 ******************************************************************************/ 1196 void sli_em_cmu_SetHFLEConfigHFClock(void); 1197 1198 /***************************************************************************//** 1199 * @brief This function is used to initialize the HF clock and selecting 1200 * an LF clock source. 1201 * 1202 * @note FOR INTERNAL USE ONLY. 1203 * 1204 * @param[in]osc 1205 * Reference to a low-frequency oscillator. One of the following values is valid: 1206 * - cmuOsc_LFXO 1207 * - cmuOsc_LFRCO 1208 * 1209 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1210 * the clock is HF and LFXO or LFRCO is selected as the clock source. 1211 ******************************************************************************/ 1212 void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc); 1213 1214 /***************************************************************************//** 1215 * @brief This function is used to initialize the HF clock and selecting 1216 * HFXO as the clock source. 1217 * 1218 * @note FOR INTERNAL USE ONLY. 1219 * 1220 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1221 * the clock is HF and HFXO is selected as the clock source. 1222 ******************************************************************************/ 1223 void sli_em_cmu_HFClockSelectHFXO(void); 1224 1225 /***************************************************************************//** 1226 * @brief This function is used to initialize the HF clock and selecting 1227 * HFRCO as the clock source. 1228 * 1229 * @note FOR INTERNAL USE ONLY. 1230 * 1231 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1232 * the clock is HF and HFRCO is selected as the clock source. 1233 ******************************************************************************/ 1234 void sli_em_cmu_HFClockSelectHFRCO(void); 1235 1236 #if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) 1237 /***************************************************************************//** 1238 * @brief This function is used to initialize the HF clock and selecting 1239 * USHFRCODIV2 as the clock source. 1240 * 1241 * @note FOR INTERNAL USE ONLY. 1242 * 1243 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1244 * the clock is HF and USHFRCODIV2 is selected as the clock source. 1245 ******************************************************************************/ 1246 void sli_em_cmu_HFClockSelectUSHFRCODIV2(void); 1247 #endif 1248 1249 #if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) 1250 /***************************************************************************//** 1251 * @brief This function is used to initialize the HF clock and selecting 1252 * HFRCODIV2 as the clock source. 1253 * 1254 * @note FOR INTERNAL USE ONLY. 1255 * 1256 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1257 * the clock is HF and HFRCODIV2 is selected as the clock source. 1258 ******************************************************************************/ 1259 void sli_em_cmu_HFClockSelectHFRCODIV2(void); 1260 #endif 1261 1262 #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) 1263 /***************************************************************************//** 1264 * @brief This function is used to initialize the HF clock and selecting 1265 * CLKIN0 as the clock source. 1266 * 1267 * @note FOR INTERNAL USE ONLY. 1268 * 1269 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1270 * the clock is HF and CLKIN0 is selected as the clock source. 1271 ******************************************************************************/ 1272 void sli_em_cmu_HFClockSelectCLKIN0(void); 1273 #endif 1274 1275 #if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) 1276 /***************************************************************************//** 1277 * @brief This function is used to initialize the HF clock and selecting 1278 * USHFRCO as the clock source. 1279 * 1280 * @note FOR INTERNAL USE ONLY. 1281 * 1282 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1283 * the clock is HF and USHFRCO is selected as the clock source. 1284 ******************************************************************************/ 1285 void sli_em_cmu_HFClockSelectUSHFRCO(void); 1286 #endif 1287 1288 #define CMU_HF_SELECT_LFXO \ 1289 do { \ 1290 sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFXO); \ 1291 } while (0) 1292 1293 #define CMU_HF_SELECT_LFRCO \ 1294 do { \ 1295 sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFRCO); \ 1296 } while (0) 1297 1298 #define CMU_HF_SELECT_HFXO \ 1299 do { \ 1300 sli_em_cmu_HFClockSelectHFXO(); \ 1301 } while (0) 1302 1303 #define CMU_HF_SELECT_HFRCO \ 1304 do { \ 1305 sli_em_cmu_HFClockSelectHFRCO(); \ 1306 } while (0) 1307 1308 #if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) 1309 #define CMU_HF_SELECT_USHFRCODIV2 \ 1310 do { \ 1311 sli_em_cmu_HFClockSelectUSHFRCODIV2(); \ 1312 } while (0) 1313 #endif 1314 1315 #if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) 1316 #define CMU_HF_SELECT_HFRCODIV2 \ 1317 do { \ 1318 sli_em_cmu_HFClockSelectHFRCODIV2(); \ 1319 } while (0) 1320 #endif 1321 1322 #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) 1323 #define CMU_HF_SELECT_CLKIN0 \ 1324 do { \ 1325 sli_em_cmu_HFClockSelectCLKIN0(); \ 1326 } while (0) 1327 #endif 1328 1329 #if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) 1330 #define CMU_HF_SELECT_USHFRCO \ 1331 do { \ 1332 sli_em_cmu_HFClockSelectUSHFRCO(); \ 1333 } while (0) 1334 #endif 1335 1336 #if defined(_SILICON_LABS_32B_SERIES_1) 1337 #define CMU_LFA_SELECT_DISABLED \ 1338 do { \ 1339 CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_DISABLED; \ 1340 } while (0) 1341 1342 #define CMU_LFA_SELECT_LFXO \ 1343 do { \ 1344 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1345 CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFXO; \ 1346 } while (0) 1347 1348 #define CMU_LFA_SELECT_LFRCO \ 1349 do { \ 1350 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1351 CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFRCO; \ 1352 } while (0) 1353 1354 #define CMU_LFA_SELECT_ULFRCO \ 1355 do { \ 1356 CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_ULFRCO; \ 1357 } while (0) 1358 1359 #if defined(CMU_OSCENCMD_PLFRCOEN) 1360 #define CMU_LFA_SELECT_PLFRCO \ 1361 do { \ 1362 CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ 1363 CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_PLFRCO; \ 1364 } while (0) 1365 #endif /* CMU_OSCENCMD_PLFRCOEN */ 1366 1367 #define CMU_LFB_SELECT_DISABLED \ 1368 do { \ 1369 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_DISABLED; \ 1370 } while (0) 1371 1372 #define CMU_LFB_SELECT_LFXO \ 1373 do { \ 1374 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1375 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFXO; \ 1376 } while (0) 1377 1378 #define CMU_LFB_SELECT_LFRCO \ 1379 do { \ 1380 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1381 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFRCO; \ 1382 } while (0) 1383 1384 #define CMU_LFB_SELECT_HFCLKLE \ 1385 do { \ 1386 sli_em_cmu_SetHFLEConfigHFClock(); \ 1387 BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); \ 1388 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_HFCLKLE; \ 1389 } while (0) 1390 1391 #define CMU_LFB_SELECT_ULFRCO \ 1392 do { \ 1393 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_ULFRCO; \ 1394 } while (0) 1395 1396 #if defined(CMU_OSCENCMD_PLFRCOEN) 1397 #define CMU_LFB_SELECT_PLFRCO \ 1398 do { \ 1399 CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ 1400 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_PLFRCO; \ 1401 } while (0) 1402 #endif /* CMU_OSCENCMD_PLFRCOEN */ 1403 1404 #if defined(_CMU_LFCCLKSEL_MASK) 1405 #define CMU_LFC_SELECT_DISABLED \ 1406 do { \ 1407 CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_DISABLED; \ 1408 } while (0) 1409 1410 #define CMU_LFC_SELECT_LFXO \ 1411 do { \ 1412 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1413 CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFXO; \ 1414 } while (0) 1415 1416 #define CMU_LFC_SELECT_LFRCO \ 1417 do { \ 1418 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1419 CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFRCO; \ 1420 } while (0) 1421 1422 #define CMU_LFC_SELECT_ULFRCO \ 1423 do { \ 1424 CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_ULFRCO; \ 1425 } while (0) 1426 1427 #endif /* _CMU_LFCCLKSEL_MASK */ 1428 1429 #define CMU_LFE_SELECT_DISABLED \ 1430 do { \ 1431 CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_DISABLED; \ 1432 } while (0) 1433 1434 #define CMU_LFE_SELECT_LFXO \ 1435 do { \ 1436 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1437 CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFXO; \ 1438 } while (0) 1439 1440 #define CMU_LFE_SELECT_LFRCO \ 1441 do { \ 1442 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1443 CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFRCO; \ 1444 } while (0) 1445 1446 #define CMU_LFE_SELECT_ULFRCO \ 1447 do { \ 1448 CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_ULFRCO; \ 1449 } while (0) 1450 1451 #if defined(CMU_OSCENCMD_PLFRCOEN) 1452 #define CMU_LFE_SELECT_PLFRCO \ 1453 do { \ 1454 CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ 1455 CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_PLFRCO; \ 1456 } while (0) 1457 #endif /* CMU_OSCENCMD_PLFRCOEN */ 1458 #endif /* _SILICON_LABS_32B_SERIES_1 */ 1459 1460 #if defined(_SILICON_LABS_32B_SERIES_0) 1461 #if defined(_CMU_LFCLKSEL_LFAE_MASK) 1462 #define CMU_LFA_SELECT_DISABLED \ 1463 do { \ 1464 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1465 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ 1466 | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ 1467 | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ 1468 } while (0) 1469 1470 #define CMU_LFA_SELECT_LFXO \ 1471 do { \ 1472 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1473 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1474 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ 1475 | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT) \ 1476 | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ 1477 } while (0) 1478 1479 #define CMU_LFA_SELECT_LFRCO \ 1480 do { \ 1481 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1482 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1483 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ 1484 | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT) \ 1485 | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ 1486 } while (0) 1487 1488 #define CMU_LFA_SELECT_HFCLKLE \ 1489 do { \ 1490 sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ 1491 BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ 1492 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1493 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ 1494 | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT) \ 1495 | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ 1496 } while (0) 1497 1498 #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) 1499 #define CMU_LFA_SELECT_ULFRCO \ 1500 do { \ 1501 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1502 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ 1503 | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ 1504 | (1 << _CMU_LFCLKSEL_LFAE_SHIFT); \ 1505 } while (0) 1506 #endif 1507 1508 #else 1509 #define CMU_LFA_SELECT_DISABLED \ 1510 do { \ 1511 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ 1512 | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ 1513 } while (0) 1514 1515 #define CMU_LFA_SELECT_LFXO \ 1516 do { \ 1517 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1518 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ 1519 | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT); \ 1520 } while (0) 1521 1522 #define CMU_LFA_SELECT_LFRCO \ 1523 do { \ 1524 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1525 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ 1526 | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT); \ 1527 } while (0) 1528 1529 #define CMU_LFA_SELECT_HFCLKLE \ 1530 do { \ 1531 sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ 1532 BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ 1533 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ 1534 | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT); \ 1535 } while (0) 1536 1537 #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) 1538 #define CMU_LFA_SELECT_ULFRCO \ 1539 do { \ 1540 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ 1541 | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ 1542 } while (0) 1543 #endif /* CMU_LFA_SELECT_HFCLKLE */ 1544 #endif /* _CMU_LFCLKSEL_LFAE_MASK */ 1545 1546 #if defined(_CMU_LFCLKSEL_LFBE_MASK) 1547 #define CMU_LFB_SELECT_DISABLED \ 1548 do { \ 1549 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1550 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ 1551 | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ 1552 | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ 1553 } while (0) 1554 1555 #define CMU_LFB_SELECT_LFXO \ 1556 do { \ 1557 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1558 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1559 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ 1560 | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT) \ 1561 | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ 1562 } while (0) 1563 1564 #define CMU_LFB_SELECT_LFRCO \ 1565 do { \ 1566 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1567 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1568 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ 1569 | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT) \ 1570 | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ 1571 } while (0) 1572 1573 #define CMU_LFB_SELECT_HFCLKLE \ 1574 do { \ 1575 sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ 1576 BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ 1577 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1578 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ 1579 | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT) \ 1580 | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ 1581 } while (0) 1582 1583 #if defined(CMU_LFCLKSEL_LFBE_ULFRCO) 1584 #define CMU_LFB_SELECT_ULFRCO \ 1585 do { \ 1586 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1587 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ 1588 | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ 1589 | (1 << _CMU_LFCLKSEL_LFBE_SHIFT); \ 1590 } while (0) 1591 #endif 1592 1593 #else 1594 #define CMU_LFB_SELECT_DISABLED \ 1595 do { \ 1596 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ 1597 | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ 1598 } while (0) 1599 1600 #define CMU_LFB_SELECT_LFXO \ 1601 do { \ 1602 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1603 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ 1604 | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT); \ 1605 } while (0) 1606 1607 #define CMU_LFB_SELECT_LFRCO \ 1608 do { \ 1609 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1610 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ 1611 | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT); \ 1612 } while (0) 1613 1614 #define CMU_LFB_SELECT_HFCLKLE \ 1615 do { \ 1616 sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ 1617 BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ 1618 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ 1619 | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT); \ 1620 } while (0) 1621 1622 #if defined(CMU_LFCLKSEL_LFBE_ULFRCO) 1623 #define CMU_LFB_SELECT_ULFRCO \ 1624 do { \ 1625 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ 1626 | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ 1627 } while (0) 1628 #endif /* CMU_LFCLKSEL_LFBE_ULFRCO */ 1629 #endif /* _CMU_LFCLKSEL_LFBE_MASK */ 1630 1631 #define CMU_LFC_SELECT_DISABLED \ 1632 do { \ 1633 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ 1634 | (_CMU_LFCLKSEL_LFC_DISABLED << _CMU_LFCLKSEL_LFC_SHIFT); \ 1635 } while (0) 1636 1637 #define CMU_LFC_SELECT_LFXO \ 1638 do { \ 1639 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1640 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ 1641 | (_CMU_LFCLKSEL_LFC_LFXO << _CMU_LFCLKSEL_LFC_SHIFT); \ 1642 } while (0) 1643 1644 #define CMU_LFC_SELECT_LFRCO \ 1645 do { \ 1646 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1647 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ 1648 | (_CMU_LFCLKSEL_LFC_LFRCO << _CMU_LFCLKSEL_LFC_SHIFT); \ 1649 } while (0) 1650 #endif /* _SILICON_LABS_32B_SERIES_0 */ 1651 1652 #if defined(_CMU_DBGCLKSEL_DBG_MASK) 1653 #define CMU_DBG_SELECT_AUXHFRCO \ 1654 do { \ 1655 CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; \ 1656 } while (0) 1657 1658 #define CMU_DBG_SELECT_HFCLK \ 1659 do { \ 1660 CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; \ 1661 } while (0) 1662 #endif /* _CMU_DBGCLKSEL_DBG_MASK */ 1663 1664 #if defined(CMU_CTRL_DBGCLK) 1665 #define CMU_DBG_SELECT_AUXHFRCO \ 1666 do { \ 1667 CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ 1668 | CMU_CTRL_DBGCLK_AUXHFRCO; \ 1669 } while (0) 1670 1671 #define CMU_DBG_SELECT_HFCLK \ 1672 do { \ 1673 CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ 1674 | CMU_CTRL_DBGCLK_HFCLK; \ 1675 } while (0) 1676 #endif /* CMU_CTRL_DBGCLK */ 1677 1678 #if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) 1679 #define CMU_USBC_SELECT_LFXO \ 1680 do { \ 1681 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1682 CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; \ 1683 while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) {} \ 1684 } while (0) 1685 1686 #define CMU_USBC_SELECT_LFRCO \ 1687 do { \ 1688 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1689 CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; \ 1690 while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) {} \ 1691 } while (0) 1692 1693 #if defined(CMU_STATUS_USBCHFCLKSEL) 1694 #define CMU_USBC_SELECT_HFCLK \ 1695 do { \ 1696 CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; \ 1697 while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) {} \ 1698 } while (0) 1699 #endif /* CMU_STATUS_USBCHFCLKSEL */ 1700 1701 #if defined(CMU_CMD_USBCCLKSEL_USHFRCO) 1702 #define CMU_USBC_SELECT_USHFRCO \ 1703 do { \ 1704 CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ 1705 CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; \ 1706 while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) {} \ 1707 } while (0) 1708 #endif /* CMU_CMD_USBCCLKSEL_USHFRCO */ 1709 #endif /* USB_PRESENT && _CMU_HFCORECLKEN0_USBC_MASK */ 1710 1711 #if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) 1712 #define CMU_ADC0ASYNC_SELECT_DISABLED \ 1713 do { \ 1714 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ 1715 | (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ 1716 } while (0) 1717 1718 #define CMU_ADC0ASYNC_SELECT_AUXHFRCO \ 1719 do { \ 1720 CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ 1721 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ 1722 | (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ 1723 } while (0) 1724 1725 #define CMU_ADC0ASYNC_SELECT_HFXO \ 1726 do { \ 1727 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1728 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ 1729 | (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ 1730 } while (0) 1731 1732 #define CMU_ADC0ASYNC_SELECT_HFSRCCLK \ 1733 do { \ 1734 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ 1735 | (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ 1736 } while (0) 1737 #endif /* _CMU_ADCCTRL_ADC0CLKSEL_MASK */ 1738 1739 #if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) 1740 #define CMU_ADC1ASYNC_SELECT_DISABLED \ 1741 do { \ 1742 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ 1743 | (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ 1744 } while (0) 1745 1746 #define CMU_ADC1ASYNC_SELECT_AUXHFRCO \ 1747 do { \ 1748 CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ 1749 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ 1750 | (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ 1751 } while (0) 1752 1753 #define CMU_ADC1ASYNC_SELECT_HFXO \ 1754 do { \ 1755 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1756 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ 1757 | (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ 1758 } while (0) 1759 1760 #define CMU_ADC1ASYNC_SELECT_HFSRCCLK \ 1761 do { \ 1762 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ 1763 | (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ 1764 } while (0) 1765 #endif /* _CMU_ADCCTRL_ADC1CLKSEL_MASK */ 1766 1767 #if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) 1768 #define CMU_SDIOREF_SELECT_HFRCO \ 1769 do { \ 1770 CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ 1771 CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ 1772 | (_CMU_SDIOCTRL_SDIOCLKSEL_HFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ 1773 } while (0) 1774 1775 #define CMU_SDIOREF_SELECT_HFXO \ 1776 do { \ 1777 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1778 CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ 1779 | (_CMU_SDIOCTRL_SDIOCLKSEL_HFXO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ 1780 } while (0) 1781 1782 #define CMU_SDIOREF_SELECT_AUXHFRCO \ 1783 do { \ 1784 CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ 1785 CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ 1786 | (_CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ 1787 } while (0) 1788 1789 #define CMU_SDIOREF_SELECT_USHFRCO \ 1790 do { \ 1791 CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ 1792 CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ 1793 | (_CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ 1794 } while (0) 1795 #endif /* _CMU_SDIOCTRL_SDIOCLKSEL_MASK */ 1796 1797 #if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) 1798 #define CMU_QSPI0REF_SELECT_HFRCO \ 1799 do { \ 1800 CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ 1801 CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ 1802 | (_CMU_QSPICTRL_QSPI0CLKSEL_HFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ 1803 } while (0) 1804 1805 #define CMU_QSPI0REF_SELECT_HFXO \ 1806 do { \ 1807 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1808 CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ 1809 | (_CMU_QSPICTRL_QSPI0CLKSEL_HFXO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ 1810 } while (0) 1811 1812 #define CMU_QSPI0REF_SELECT_AUXHFRCO \ 1813 do { \ 1814 CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ 1815 CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ 1816 | (_CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ 1817 } while (0) 1818 1819 #define CMU_QSPI0REF_SELECT_USHFRCO \ 1820 do { \ 1821 CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ 1822 CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ 1823 | (_CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ 1824 } while (0) 1825 #endif /* _CMU_QSPICTRL_QSPI0CLKSEL_MASK */ 1826 1827 #if defined(_CMU_USBCTRL_USBCLKSEL_MASK) 1828 #define CMU_USBR_SELECT_USHFRCO \ 1829 do { \ 1830 CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ 1831 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1832 | (_CMU_USBCTRL_USBCLKSEL_USHFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1833 } while (0) 1834 1835 #define CMU_USBR_SELECT_HFXO \ 1836 do { \ 1837 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1838 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1839 | (_CMU_USBCTRL_USBCLKSEL_HFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1840 } while (0) 1841 1842 #define CMU_USBR_SELECT_HFXOX2 \ 1843 do { \ 1844 EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); \ 1845 CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; \ 1846 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1847 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1848 | (_CMU_USBCTRL_USBCLKSEL_HFXOX2 << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1849 } while (0) 1850 1851 #define CMU_USBR_SELECT_HFRCO \ 1852 do { \ 1853 CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ 1854 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1855 | (_CMU_USBCTRL_USBCLKSEL_HFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1856 } while (0) 1857 1858 #define CMU_USBR_SELECT_LFXO \ 1859 do { \ 1860 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1861 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1862 | (_CMU_USBCTRL_USBCLKSEL_LFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1863 } while (0) 1864 1865 #define CMU_USBR_SELECT_LFRCO \ 1866 do { \ 1867 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1868 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1869 | (_CMU_USBCTRL_USBCLKSEL_LFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1870 } while (0) 1871 #endif /* _CMU_USBCTRL_USBCLKSEL_MASK */ 1872 1873 #if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) 1874 #define CMU_PDMREF_SELECT_USHFRCO \ 1875 do { \ 1876 CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ 1877 CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ 1878 | (_CMU_PDMCTRL_PDMCLKSEL_USHFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ 1879 } while (0) 1880 1881 #define CMU_PDMREF_SELECT_HFXO \ 1882 do { \ 1883 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1884 CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ 1885 | (_CMU_PDMCTRL_PDMCLKSEL_HFXO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ 1886 } while (0) 1887 1888 #define CMU_PDMREF_SELECT_HFRCO \ 1889 do { \ 1890 CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ 1891 CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ 1892 | (_CMU_PDMCTRL_PDMCLKSEL_HFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ 1893 } while (0) 1894 #endif /* _CMU_PDMCTRL_PDMCLKSEL_MASK */ 1895 #endif /* _SILICON_LABS_32B_SERIES_2 */ 1896 /** @endcond */ 1897 1898 #ifdef __cplusplus 1899 } 1900 #endif 1901 1902 #endif /* SLI_EM_CMU_H */ 1903
