1 /***************************************************************************//** 2 * @file 3 * @brief Clock Management Unit Private API definition. 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #ifndef SLI_EM_CMU_H 32 #define SLI_EM_CMU_H 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ 39 #if defined(_SILICON_LABS_32B_SERIES_2) 40 41 /***************************************************************************//** 42 * @brief Performs pre-clock-selection operations to initialize the system clock. 43 * 44 * @note FOR INTERNAL USE ONLY. 45 * 46 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 47 * the clock is SYSCLK. 48 ******************************************************************************/ 49 void sli_em_cmu_SYSCLKInitPreClockSelect(void); 50 51 /***************************************************************************//** 52 * @brief Performs post-clock-selection operations to initialize the system clock. 53 * 54 * @note FOR INTERNAL USE ONLY. 55 * 56 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 57 * the clock is SYSCLK. 58 ******************************************************************************/ 59 void sli_em_cmu_SYSCLKInitPostClockSelect(void); 60 61 /***************************************************************************//** 62 * @brief Sets the HFXO0 FORCEEN bit. 63 * 64 * @note FOR INTERNAL USE ONLY. 65 * 66 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 67 * the clock is SYSCLK and the selected clock source is HFXO. 68 ******************************************************************************/ 69 void sli_em_cmu_HFXOSetForceEnable(void); 70 71 /***************************************************************************//** 72 * @brief This function will set the SYSCFG->CFGSYSTIC<SYSTICEXTCLKEN> bit. 73 * 74 * @note FOR INTERNAL USE ONLY. 75 * 76 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 77 * the clock is SYSTICK. 78 ******************************************************************************/ 79 void sli_em_cmu_SYSTICEXTCLKENSet(void); 80 81 /***************************************************************************//** 82 * @brief This function will clear the SYSCFG->CFGSYSTIC<SYSTICEXTCLKEN> bit. 83 * 84 * @note FOR INTERNAL USE ONLY. 85 * 86 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 87 * the clock is SYSTICK. 88 ******************************************************************************/ 89 void sli_em_cmu_SYSTICEXTCLKENClear(void); 90 91 #define CMU_SYSCLK_SELECT_HFRCODPLL \ 92 do { \ 93 sli_em_cmu_SYSCLKInitPreClockSelect(); \ 94 CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ 95 | CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; \ 96 sli_em_cmu_SYSCLKInitPostClockSelect(); \ 97 } while (0) 98 99 #define CMU_SYSCLK_SELECT_HFXO \ 100 do { \ 101 sli_em_cmu_HFXOSetForceEnable(); \ 102 sli_em_cmu_SYSCLKInitPreClockSelect(); \ 103 CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ 104 | CMU_SYSCLKCTRL_CLKSEL_HFXO; \ 105 sli_em_cmu_SYSCLKInitPostClockSelect(); \ 106 if ((HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) == 0) { \ 107 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; \ 108 } \ 109 } while (0) 110 111 #define CMU_SYSCLK_SELECT_CLKIN0 \ 112 do { \ 113 sli_em_cmu_SYSCLKInitPreClockSelect(); \ 114 CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ 115 | CMU_SYSCLKCTRL_CLKSEL_CLKIN0; \ 116 sli_em_cmu_SYSCLKInitPostClockSelect(); \ 117 } while (0) 118 119 #define CMU_SYSCLK_SELECT_FSRCO \ 120 do { \ 121 sli_em_cmu_SYSCLKInitPreClockSelect(); \ 122 CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ 123 | CMU_SYSCLKCTRL_CLKSEL_FSRCO; \ 124 sli_em_cmu_SYSCLKInitPostClockSelect(); \ 125 } while (0) 126 127 #if defined(RFFPLL_PRESENT) 128 129 #define CMU_SYSCLK_SELECT_RFFPLLSYS \ 130 do { \ 131 sli_em_cmu_SYSCLKInitPreClockSelect(); \ 132 CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ 133 | CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; \ 134 sli_em_cmu_SYSCLKInitPostClockSelect(); \ 135 } while (0) 136 137 #endif /* RFFPLL_PRESENT */ 138 139 #if defined(IADC_PRESENT) 140 #define CMU_IADCCLK_SELECT_EM01GRPACLK \ 141 do { \ 142 CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ 143 | CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; \ 144 } while (0) 145 146 #define CMU_IADC0_SELECT_EM01GRPACLK CMU_IADCCLK_SELECT_EM01GRPACLK 147 148 #if defined(HFRCOEM23_PRESENT) 149 #define CMU_IADCCLK_SELECT_HFRCOEM23 \ 150 do { \ 151 CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ 152 | CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; \ 153 } while (0) 154 155 #define CMU_IADC0_SELECT_HFRCOEM23 CMU_IADCCLK_SELECT_HFRCOEM23 156 #endif /* HFRCOEM23_PRESENT */ 157 158 #define CMU_IADCCLK_SELECT_FSRCO \ 159 do { \ 160 CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ 161 | CMU_IADCCLKCTRL_CLKSEL_FSRCO; \ 162 } while (0) 163 164 #define CMU_IADC0_SELECT_FSRCO CMU_IADCCLK_SELECT_FSRCO 165 #endif /* IADC_PRESENT */ 166 167 #define CMU_EM01GRPACLK_SELECT_HFRCODPLL \ 168 do { \ 169 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 170 | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; \ 171 } while (0) 172 173 #define CMU_TIMER0_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 174 #define CMU_TIMER1_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 175 #define CMU_TIMER2_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 176 #define CMU_TIMER3_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 177 #if TIMER_COUNT > 4 178 #define CMU_TIMER4_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 179 #endif /* TIMER_COUNT > 4 */ 180 #if TIMER_COUNT > 7 181 #define CMU_TIMER5_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 182 #define CMU_TIMER6_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 183 #define CMU_TIMER7_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 184 #endif /* TIMER_COUNT > 7 */ 185 #if TIMER_COUNT > 9 186 #define CMU_TIMER8_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 187 #define CMU_TIMER9_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 188 #endif /* TIMER_COUNT > 9 */ 189 #if defined(KEYSCAN_PRESENT) 190 #define CMU_KEYSCAN_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL 191 #endif /* KEYSCAN_PRESENT*/ 192 193 #define CMU_EM01GRPACLK_SELECT_HFXO \ 194 do { \ 195 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 196 | CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; \ 197 } while (0) 198 199 #define CMU_TIMER0_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 200 #define CMU_TIMER1_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 201 #define CMU_TIMER2_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 202 #define CMU_TIMER3_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 203 #if TIMER_COUNT > 4 204 #define CMU_TIMER4_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 205 #endif /* TIMER_COUNT > 4 */ 206 #if TIMER_COUNT > 7 207 #define CMU_TIMER5_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 208 #define CMU_TIMER6_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 209 #define CMU_TIMER7_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 210 #endif /* TIMER_COUNT > 7 */ 211 #if TIMER_COUNT > 9 212 #define CMU_TIMER8_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 213 #define CMU_TIMER9_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 214 #endif /* TIMER_COUNT > 9 */ 215 #if defined(KEYSCAN_PRESENT) 216 #define CMU_KEYSCAN_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO 217 #endif /* KEYSCAN_PRESENT*/ 218 219 #if defined(HFRCOEM23_PRESENT) 220 #define CMU_EM01GRPACLK_SELECT_HFRCOEM23 \ 221 do { \ 222 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 223 | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; \ 224 } while (0) 225 226 #define CMU_TIMER0_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 227 #define CMU_TIMER1_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 228 #define CMU_TIMER2_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 229 #define CMU_TIMER3_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 230 #if TIMER_COUNT > 4 231 #define CMU_TIMER4_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 232 #endif /* TIMER_COUNT > 4 */ 233 #if TIMER_COUNT > 7 234 #define CMU_TIMER5_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 235 #define CMU_TIMER6_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 236 #define CMU_TIMER7_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 237 #endif /* TIMER_COUNT > 7 */ 238 #if TIMER_COUNT > 9 239 #define CMU_TIMER8_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 240 #define CMU_TIMER9_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 241 #endif /* TIMER_COUNT > 9 */ 242 #if defined(KEYSCAN_PRESENT) 243 #define CMU_KEYSCAN_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 244 #endif /* KEYSCAN_PRESENT*/ 245 #endif /* HFRCOEM23_PRESENT */ 246 247 #define CMU_EM01GRPACLK_SELECT_FSRCO \ 248 do { \ 249 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 250 | CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; \ 251 } while (0) 252 253 #define CMU_TIMER0_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 254 #define CMU_TIMER1_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 255 #define CMU_TIMER2_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 256 #define CMU_TIMER3_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 257 #if TIMER_COUNT > 4 258 #define CMU_TIMER4_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 259 #endif /* TIMER_COUNT > 4 */ 260 #if TIMER_COUNT > 7 261 #define CMU_TIMER5_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 262 #define CMU_TIMER6_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 263 #define CMU_TIMER7_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 264 #endif /* TIMER_COUNT > 7 */ 265 #if TIMER_COUNT > 9 266 #define CMU_TIMER8_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 267 #define CMU_TIMER9_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 268 #endif /* TIMER_COUNT > 9 */ 269 #if defined(KEYSCAN_PRESENT) 270 #define CMU_KEYSCAN_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO 271 #endif /* KEYSCAN_PRESENT*/ 272 273 #define CMU_EM01GRPACLK_SELECT_DISABLED \ 274 do { \ 275 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 276 | CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; \ 277 } while (0) 278 279 #if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) 280 #define CMU_EM01GRPACLK_SELECT_HFRCODPLLRT \ 281 do { \ 282 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 283 | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; \ 284 } while (0) 285 286 #define CMU_TIMER0_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 287 #define CMU_TIMER1_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 288 #define CMU_TIMER2_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 289 #define CMU_TIMER3_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 290 #if TIMER_COUNT > 4 291 #define CMU_TIMER4_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 292 #endif /* TIMER_COUNT > 4 */ 293 #if TIMER_COUNT > 7 294 #define CMU_TIMER5_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 295 #define CMU_TIMER6_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 296 #define CMU_TIMER7_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 297 #endif /* TIMER_COUNT > 7 */ 298 #if TIMER_COUNT > 9 299 #define CMU_TIMER8_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 300 #define CMU_TIMER9_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 301 #endif /* TIMER_COUNT > 9 */ 302 #if defined(KEYSCAN_PRESENT) 303 #define CMU_KEYSCAN_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT 304 #endif /* KEYSCAN_PRESENT*/ 305 #endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT */ 306 307 #if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) 308 #define CMU_EM01GRPACLK_SELECT_HFXORT \ 309 do { \ 310 CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ 311 | CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; \ 312 } while (0) 313 314 #define CMU_TIMER0_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 315 #define CMU_TIMER1_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 316 #define CMU_TIMER2_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 317 #define CMU_TIMER3_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 318 #if TIMER_COUNT > 4 319 #define CMU_TIMER4_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 320 #endif /* TIMER_COUNT > 4 */ 321 #if TIMER_COUNT > 7 322 #define CMU_TIMER5_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 323 #define CMU_TIMER6_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 324 #define CMU_TIMER7_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 325 #endif /* TIMER_COUNT > 7 */ 326 #if TIMER_COUNT > 9 327 #define CMU_TIMER8_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 328 #define CMU_TIMER9_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 329 #endif /* TIMER_COUNT > 9 */ 330 #if defined(KEYSCAN_PRESENT) 331 #define CMU_KEYSCAN_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT 332 #endif /* KEYSCAN_PRESENT*/ 333 #endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT */ 334 335 #define CMU_SYSTICK_SELECT_EM23GRPACLK \ 336 do { \ 337 sli_em_cmu_SYSTICEXTCLKENSet(); \ 338 SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); \ 339 } while (0) 340 341 #define CMU_SYSTICK_SELECT_LFXO CMU_SYSTICK_SELECT_EM23GRPACLK 342 #define CMU_SYSTICK_SELECT_LFRCO CMU_SYSTICK_SELECT_EM23GRPACLK 343 #define CMU_SYSTICK_SELECT_ULFRCO CMU_SYSTICK_SELECT_EM23GRPACLK 344 345 #define CMU_SYSTICK_SELECT_HCLK \ 346 do { \ 347 sli_em_cmu_SYSTICEXTCLKENClear(); \ 348 SysTick->CTRL = (SysTick->CTRL | ~SysTick_CTRL_CLKSOURCE_Msk); \ 349 } while (0) 350 351 #define CMU_EM23GRPACLK_SELECT_LFRCO \ 352 do { \ 353 CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ 354 | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ 355 } while (0) 356 357 #define CMU_LETIMER0_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO 358 #if defined(LESENSE_PRESENT) 359 #define CMU_LESENSE_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO 360 #define CMU_LESENSECLK_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO 361 #endif /* LESENSE_PRESENT */ 362 363 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 364 #define CMU_EM23GRPACLK_SELECT_PLFRCO \ 365 do { \ 366 CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ 367 | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ 368 } while (0) 369 370 #define CMU_LETIMER0_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO 371 #if defined(LESENSE_PRESENT) 372 #define CMU_LESENSE_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO 373 #define CMU_LESENSECLK_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO 374 #endif /* LESENSE_PRESENT */ 375 #endif /* LFRCO_PRECISION_MODE */ 376 377 #define CMU_EM23GRPACLK_SELECT_LFXO \ 378 do { \ 379 CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ 380 | CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; \ 381 } while (0) 382 383 #define CMU_LETIMER0_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO 384 #if defined(LESENSE_PRESENT) 385 #define CMU_LESENSE_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO 386 #define CMU_LESENSECLK_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO 387 #endif /* LESENSE_PRESENT */ 388 389 #define CMU_EM23GRPACLK_SELECT_ULFRCO \ 390 do { \ 391 CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ 392 | CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; \ 393 } while (0) 394 395 #define CMU_LETIMER0_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO 396 #if defined(LESENSE_PRESENT) 397 #define CMU_LESENSE_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO 398 #define CMU_LESENSECLK_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO 399 #endif /* LESENSE_PRESENT */ 400 401 #define CMU_EM23GRPACLK_SELECT_DISABLED \ 402 do { \ 403 CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ 404 | CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; \ 405 } while (0) 406 407 #define CMU_EM4GRPACLK_SELECT_LFRCO \ 408 do { \ 409 CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ 410 | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ 411 } while (0) 412 413 #define CMU_BURTC_SELECT_LFRCO CMU_EM4GRPACLK_SELECT_LFRCO 414 415 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 416 #define CMU_EM4GRPACLK_SELECT_PLFRCO \ 417 do { \ 418 CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ 419 | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ 420 } while (0) 421 422 #define CMU_BURTC_SELECT_PLFRCO CMU_EM4GRPACLK_SELECT_PLFRCO 423 #endif /* LFRCO_PRECISION_MODE */ 424 425 #define CMU_EM4GRPACLK_SELECT_LFXO \ 426 do { \ 427 CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ 428 | CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; \ 429 } while (0) 430 431 #define CMU_BURTC_SELECT_LFXO CMU_EM4GRPACLK_SELECT_LFXO 432 433 #define CMU_EM4GRPACLK_SELECT_ULFRCO \ 434 do { \ 435 CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ 436 | CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; \ 437 } while (0) 438 439 #define CMU_BURTC_SELECT_ULFRCO CMU_EM4GRPACLK_SELECT_ULFRCO 440 441 #define CMU_EM4GRPACLK_SELECT_DISABLED \ 442 do { \ 443 CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ 444 | CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; \ 445 } while (0) 446 447 #if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) 448 #define CMU_EM01GRPBCLK_SELECT_HFRCODPLL \ 449 do { \ 450 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 451 | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; \ 452 } while (0) 453 454 #define CMU_PDMREF_SELECT_HFRCODPLL CMU_EM01GRPBCLK_SELECT_HFRCODPLL 455 456 #define CMU_EM01GRPBCLK_SELECT_HFXO \ 457 do { \ 458 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 459 | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; \ 460 } while (0) 461 462 #define CMU_PDMREF_SELECT_HFXO CMU_EM01GRPBCLK_SELECT_HFXO 463 464 #define CMU_EM01GRPBCLK_SELECT_FSRCO \ 465 do { \ 466 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 467 | CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; \ 468 } while (0) 469 470 #define CMU_PDMREF_SELECT_FSRCO CMU_EM01GRPBCLK_SELECT_FSRCO 471 472 #define CMU_EM01GRPBCLK_SELECT_CLKIN0 \ 473 do { \ 474 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 475 | CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; \ 476 } while (0) 477 478 #define CMU_PDMREF_SELECT_CLKIN0 CMU_EM01GRPBCLK_SELECT_CLKIN0 479 480 #define CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT \ 481 do { \ 482 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 483 | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; \ 484 } while (0) 485 486 #define CMU_PDMREF_SELECT_HFRCODPLLRT CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT 487 488 #define CMU_EM01GRPBCLK_SELECT_HFXORT \ 489 do { \ 490 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 491 | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; \ 492 } while (0) 493 494 #define CMU_PDMREF_SELECT_HFXORT CMU_EM01GRPBCLK_SELECT_HFXORT 495 496 #define CMU_EM01GRPBCLK_SELECT_DISABLED \ 497 do { \ 498 CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ 499 | CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; \ 500 } while (0) 501 502 #endif /* defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) */ 503 504 #define CMU_WDOG0_SELECT_LFRCO \ 505 do { \ 506 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 507 | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ 508 } while (0) 509 510 #define CMU_WDOG0CLK_SELECT_LFRCO CMU_WDOG0_SELECT_LFRCO 511 512 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 513 #define CMU_WDOG0_SELECT_PLFRCO \ 514 do { \ 515 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 516 | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ 517 } while (0) 518 519 #define CMU_WDOG0CLK_SELECT_PLFRCO CMU_WDOG0_SELECT_PLFRCO 520 #endif /* LFRCO_PRECISION_MODE */ 521 522 #define CMU_WDOG0_SELECT_LFXO \ 523 do { \ 524 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 525 | CMU_WDOG0CLKCTRL_CLKSEL_LFXO; \ 526 } while (0) 527 528 #define CMU_WDOG0CLK_SELECT_LFXO CMU_WDOG0_SELECT_LFXO 529 530 #define CMU_WDOG0_SELECT_ULFRCO \ 531 do { \ 532 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 533 | CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; \ 534 } while (0) 535 536 #define CMU_WDOG0CLK_SELECT_ULFRCO CMU_WDOG0_SELECT_ULFRCO 537 538 #define CMU_WDOG0_SELECT_HCLKDIV1024 \ 539 do { \ 540 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 541 | CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; \ 542 } while (0) 543 544 #define CMU_WDOG0CLK_SELECT_HCLKDIV1024 CMU_WDOG0_SELECT_HCLKDIV1024 545 546 #define CMU_WDOG0_SELECT_DISABLED \ 547 do { \ 548 CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ 549 | CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; \ 550 } while (0) 551 #define CMU_WDOG0CLK_SELECT_DISABLED CMU_WDOG0_SELECT_DISABLED 552 553 #if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) 554 #define CMU_WDOG1_SELECT_LFRCO \ 555 do { \ 556 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 557 | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ 558 } while (0) 559 560 #define CMU_WDOG1CLK_SELECT_LFRCO CMU_WDOG1_SELECT_LFRCO 561 562 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 563 #define CMU_WDOG1_SELECT_PLFRCO \ 564 do { \ 565 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 566 | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ 567 } while (0) 568 569 #define CMU_WDOG1CLK_SELECT_PLFRCO CMU_WDOG1_SELECT_PLFRCO 570 #endif /* LFRCO_PRECISION_MODE */ 571 572 #define CMU_WDOG1_SELECT_LFXO \ 573 do { \ 574 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 575 | CMU_WDOG1CLKCTRL_CLKSEL_LFXO; \ 576 } while (0) 577 578 #define CMU_WDOG1CLK_SELECT_LFXO CMU_WDOG1_SELECT_LFXO 579 580 #define CMU_WDOG1_SELECT_ULFRCO \ 581 do { \ 582 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 583 | CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; \ 584 } while (0) 585 586 #define CMU_WDOG1CLK_SELECT_ULFRCO CMU_WDOG1_SELECT_ULFRCO 587 588 #define CMU_WDOG1_SELECT_HCLKDIV1024 \ 589 do { \ 590 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 591 | CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; \ 592 } while (0) 593 594 #define CMU_WDOG1CLK_SELECT_HCLKDIV1024 CMU_WDOG1_SELECT_HCLKDIV1024 595 596 #define CMU_WDOG1_SELECT_DISABLED \ 597 do { \ 598 CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ 599 | CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; \ 600 } while (0) 601 #define CMU_WDOG1CLK_SELECT_DISABLED CMU_WDOG1_SELECT_DISABLED 602 #endif /* defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) */ 603 604 #define CMU_DPLLREFCLK_SELECT_HFXO \ 605 do { \ 606 CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ 607 | CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; \ 608 } while (0) 609 610 #define CMU_DPLLREFCLK_SELECT_LFXO \ 611 do { \ 612 CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ 613 | CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; \ 614 } while (0) 615 616 #define CMU_DPLLREFCLK_SELECT_CLKIN0 \ 617 do { \ 618 CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ 619 | CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; \ 620 } while (0) 621 622 #define CMU_DPLLREFCLK_SELECT_DISABLED \ 623 do { \ 624 CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ 625 | CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; \ 626 } while (0) 627 628 #if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ 629 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ 630 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ 631 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ 632 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ 633 && defined(CoreDebug_DEMCR_TRCENA_Msk) 634 #define CMU_TRACECLK_RESTORE_TRACE_PRE() \ 635 bool restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; \ 636 if (restoreTrace) { \ 637 CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; \ 638 } \ 639 do {} while (0) 640 641 #define CMU_TRACECLK_RESTORE_TRACE_POST() \ 642 if (restoreTrace) { \ 643 CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; \ 644 } \ 645 do {} while (0) 646 647 #else 648 #define CMU_TRACECLK_RESTORE_TRACE_PRE() do {} while (0) 649 #define CMU_TRACECLK_RESTORE_TRACE_POST() do {} while (0) 650 #endif 651 652 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) 653 #define CMU_TRACECLK_SELECT_HCLK \ 654 do { \ 655 CMU_TRACECLK_RESTORE_TRACE_PRE(); \ 656 CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ 657 | CMU_TRACECLKCTRL_CLKSEL_HCLK; \ 658 CMU_TRACECLK_RESTORE_TRACE_POST(); \ 659 } while (0) 660 661 #endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_1 */ 662 663 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ 664 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ 665 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ 666 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ 667 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) 668 #define CMU_TRACECLK_SELECT_SYSCLK \ 669 do { \ 670 CMU_TRACECLK_RESTORE_TRACE_PRE(); \ 671 CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ 672 | CMU_TRACECLKCTRL_CLKSEL_SYSCLK; \ 673 CMU_TRACECLK_RESTORE_TRACE_POST(); \ 674 } while (0) 675 676 #define CMU_TRACECLK_SELECT_HFRCODPLLRT \ 677 do { \ 678 CMU_TRACECLK_RESTORE_TRACE_PRE(); \ 679 CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ 680 | CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; \ 681 CMU_TRACECLK_RESTORE_TRACE_POST(); \ 682 } while (0) 683 684 #endif 685 686 #if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) 687 #define CMU_TRACECLK_SELECT_HFRCOEM23 \ 688 do { \ 689 CMU_TRACECLK_RESTORE_TRACE_PRE(); \ 690 CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ 691 | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; \ 692 CMU_TRACECLK_RESTORE_TRACE_POST(); \ 693 } while (0) 694 695 #endif /* CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 */ 696 697 #if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) 698 #define CMU_EUART0_SELECT_EM01GRPACLK \ 699 do { \ 700 CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ 701 | _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; \ 702 } while (0) 703 704 #define CMU_EUART0CLK_SELECT_EM01GRPACLK CMU_EUART0_SELECT_EM01GRPACLK 705 706 #define CMU_EUART0_SELECT_EM23GRPACLK \ 707 do { \ 708 CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ 709 | _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; \ 710 } while (0) 711 712 #define CMU_EUART0CLK_SELECT_EM23GRPACLK CMU_EUART0_SELECT_EM23GRPACLK 713 714 #define CMU_EUART0_SELECT_DISABLED \ 715 do { \ 716 CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ 717 | _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; \ 718 } while (0) 719 #define CMU_EUART0CLK_SELECT_DISABLED CMU_EUART0_SELECT_DISABLED 720 #endif /* _CMU_EUART0CLKCTRL_CLKSEL_MASK */ 721 722 #if defined(EUSART_PRESENT) 723 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) 724 #define CMU_EUSART0_SELECT_EM01GRPACLK \ 725 do { \ 726 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 727 | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; \ 728 } while (0) 729 730 #define CMU_EUSART0CLK_SELECT_EM01GRPACLK CMU_EUSART0_SELECT_EM01GRPACLK 731 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK */ 732 733 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) 734 #define CMU_EUSART0_SELECT_EM01GRPCCLK \ 735 do { \ 736 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 737 | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; \ 738 } while (0) 739 740 #define CMU_EUSART0CLK_SELECT_EM01GRPCCLK CMU_EUSART0_SELECT_EM01GRPCCLK 741 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK */ 742 743 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) 744 #define CMU_EUSART0_SELECT_EM23GRPACLK \ 745 do { \ 746 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 747 | _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; \ 748 } while (0) 749 750 #define CMU_EUSART0CLK_SELECT_EM23GRPACLK CMU_EUSART0_SELECT_EM23GRPACLK 751 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK */ 752 753 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) 754 #define CMU_EUSART0_SELECT_FSRCO \ 755 do { \ 756 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 757 | _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; \ 758 } while (0) 759 760 #define CMU_EUSART0CLK_SELECT_FSRCO CMU_EUSART0_SELECT_FSRCO 761 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO */ 762 763 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) 764 #define CMU_EUSART0_SELECT_HFRCOEM23 \ 765 do { \ 766 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 767 | _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; \ 768 } while (0) 769 770 #define CMU_EUSART0CLK_SELECT_HFRCOEM23 CMU_EUSART0_SELECT_HFRCOEM23 771 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 */ 772 773 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) 774 #define CMU_EUSART0_SELECT_LFRCO \ 775 do { \ 776 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 777 | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ 778 } while (0) 779 780 #define CMU_EUSART0CLK_SELECT_LFRCO CMU_EUSART0_SELECT_LFRCO 781 782 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 783 #define CMU_EUSART0_SELECT_PLFRCO \ 784 do { \ 785 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 786 | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ 787 } while (0) 788 789 #define CMU_EUSART0CLK_SELECT_PLFRCO CMU_EUSART0_SELECT_PLFRCO 790 #endif /* LFRCO_PRECISION_MODE */ 791 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO */ 792 793 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) 794 #define CMU_EUSART0_SELECT_LFXO \ 795 do { \ 796 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 797 | _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; \ 798 } while (0) 799 800 #define CMU_EUSART0CLK_SELECT_LFXO CMU_EUSART0_SELECT_LFXO 801 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFXO */ 802 803 #if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) 804 #define CMU_EUSART0_SELECT_DISABLED \ 805 do { \ 806 CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ 807 | _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; \ 808 } while (0) 809 810 #define CMU_EUSART0CLK_SELECT_DISABLED CMU_EUSART0_SELECT_DISABLED 811 #endif /* _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED */ 812 #endif /* EUSART_PRESENT */ 813 814 #if defined(_CMU_EM01GRPCCLKCTRL_MASK) 815 #define CMU_EM01GRPCCLK_SELECT_HFRCODPLL \ 816 do { \ 817 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 818 | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; \ 819 } while (0) 820 821 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 822 #define CMU_EUSART1_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL 823 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 824 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 825 #define CMU_EUSART2_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL 826 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 827 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 828 #define CMU_EUSART3_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL 829 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 830 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 831 #define CMU_EUSART4_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL 832 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 833 834 #if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) 835 #define CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT \ 836 do { \ 837 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 838 | CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; \ 839 } while (0) 840 841 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 842 #define CMU_EUSART1_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT 843 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 844 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 845 #define CMU_EUSART2_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT 846 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 847 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 848 #define CMU_EUSART3_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT 849 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 850 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 851 #define CMU_EUSART4_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT 852 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 853 #endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT */ 854 855 #define CMU_EM01GRPCCLK_SELECT_HFRCOEM23 \ 856 do { \ 857 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 858 | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; \ 859 } while (0) 860 861 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 862 #define CMU_EUSART1_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 863 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 864 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 865 #define CMU_EUSART2_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 866 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 867 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 868 #define CMU_EUSART3_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 869 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 870 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 871 #define CMU_EUSART4_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 872 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 873 874 #define CMU_EM01GRPCCLK_SELECT_FSRCO \ 875 do { \ 876 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 877 | _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; \ 878 } while (0) 879 880 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 881 #define CMU_EUSART1_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO 882 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 883 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 884 #define CMU_EUSART2_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO 885 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 886 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 887 #define CMU_EUSART3_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO 888 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 889 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 890 #define CMU_EUSART4_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO 891 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 892 893 #define CMU_EM01GRPCCLK_SELECT_HFXO \ 894 do { \ 895 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 896 | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; \ 897 } while (0) 898 899 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 900 #define CMU_EUSART1_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO 901 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 902 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 903 #define CMU_EUSART2_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO 904 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 905 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 906 #define CMU_EUSART3_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO 907 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 908 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 909 #define CMU_EUSART4_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO 910 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 911 912 #if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) 913 #define CMU_EM01GRPCCLK_SELECT_HFXORT \ 914 do { \ 915 CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ 916 | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; \ 917 } while (0) 918 919 #if defined(EUSART_PRESENT) && EUSART_COUNT > 1 920 #define CMU_EUSART1_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT 921 #endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ 922 #if defined(EUSART_PRESENT) && EUSART_COUNT > 2 923 #define CMU_EUSART2_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT 924 #endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ 925 #if defined(EUSART_PRESENT) && EUSART_COUNT > 3 926 #define CMU_EUSART3_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT 927 #endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ 928 #if defined(EUSART_PRESENT) && EUSART_COUNT > 4 929 #define CMU_EUSART4_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT 930 #endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ 931 #endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT */ 932 #endif /* _CMU_EM01GRPCCLKCTRL_MASK */ 933 934 #if defined (RTCC_PRESENT) 935 #define CMU_RTCC_SELECT_LFRCO \ 936 do { \ 937 CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ 938 | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ 939 } while (0) 940 941 #define CMU_RTCCCLK_SELECT_LFRCO CMU_RTCC_SELECT_LFRCO 942 943 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 944 #define CMU_RTCC_SELECT_PLFRCO \ 945 do { \ 946 CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ 947 | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ 948 } while (0) 949 950 #define CMU_RTCCCLK_SELECT_PLFRCO CMU_RTCC_SELECT_PLFRCO 951 #endif /* LFRCO_PRECISION_MODE */ 952 953 #define CMU_RTCC_SELECT_LFXO \ 954 do { \ 955 CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ 956 | CMU_RTCCCLKCTRL_CLKSEL_LFXO; \ 957 } while (0) 958 959 #define CMU_RTCCCLK_SELECT_LFXO CMU_RTCC_SELECT_LFXO 960 961 #define CMU_RTCC_SELECT_ULFRCO \ 962 do { \ 963 CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ 964 | CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; \ 965 } while (0) 966 967 #define CMU_RTCCCLK_SELECT_ULFRCO CMU_RTCC_SELECT_ULFRCO 968 969 #endif /* RTCC_PRESENT */ 970 971 #if defined(SYSRTC_PRESENT) 972 #define CMU_SYSRTC_SELECT_LFRCO \ 973 do { \ 974 CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ 975 | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ 976 } while (0) 977 978 #define CMU_SYSRTCCLK_SELECT_LFRCO CMU_SYSRTC_SELECT_LFRCO 979 980 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 981 #define CMU_SYSRTC_SELECT_PLFRCO \ 982 do { \ 983 CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ 984 | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ 985 } while (0) 986 987 #define CMU_SYSRTCCLK_SELECT_PLFRCO CMU_SYSRTC_SELECT_PLFRCO 988 #endif /* LFRCO_PRECISION_MODE */ 989 990 #define CMU_SYSRTC_SELECT_LFXO \ 991 do { \ 992 CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ 993 | CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; \ 994 } while (0) 995 996 #define CMU_SYSRTCCLK_SELECT_LFXO CMU_SYSRTC_SELECT_LFXO 997 998 #define CMU_SYSRTC_SELECT_ULFRCO \ 999 do { \ 1000 CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ 1001 | CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; \ 1002 } while (0) 1003 1004 #define CMU_SYSRTCCLK_SELECT_ULFRCO CMU_SYSRTC_SELECT_ULFRCO 1005 1006 #define CMU_SYSRTC_SELECT_DISABLED \ 1007 do { \ 1008 CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ 1009 | CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; \ 1010 } while (0) 1011 1012 #define CMU_SYSRTCCLK_SELECT_DISABLED CMU_SYSRTC_SELECT_DISABLED 1013 #endif /* SYSRTC_PRESENT */ 1014 1015 #if defined(LCD_PRESENT) 1016 #define CMU_LCD_SELECT_LFRCO \ 1017 do { \ 1018 CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ 1019 | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ 1020 } while (0) 1021 1022 #define CMU_LCDCLK_SELECT_LFRCO CMU_LCD_SELECT_LFRCO 1023 1024 #if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) 1025 #define CMU_LCD_SELECT_PLFRCO \ 1026 do { \ 1027 CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ 1028 | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ 1029 } while (0) 1030 1031 #define CMU_LCDCLK_SELECT_PLFRCO CMU_LCD_SELECT_PLFRCO 1032 #endif /* LFRCO_PRECISION_MODE */ 1033 1034 #define CMU_LCD_SELECT_LFXO \ 1035 do { \ 1036 CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ 1037 | CMU_LCDCLKCTRL_CLKSEL_LFXO; \ 1038 } while (0) 1039 1040 #define CMU_LCDCLK_SELECT_LFXO CMU_LCD_SELECT_LFXO 1041 1042 #define CMU_LCD_SELECT_ULFRCO \ 1043 do { \ 1044 CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ 1045 | CMU_LCDCLKCTRL_CLKSEL_ULFRCO; \ 1046 } while (0) 1047 1048 #define CMU_LCDCLK_SELECT_ULFRCO CMU_LCD_SELECT_ULFRCO 1049 #endif /* LCD_PRESENT */ 1050 1051 #if defined(VDAC_PRESENT) 1052 #define CMU_VDAC0_SELECT_FSRCO \ 1053 do { \ 1054 CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ 1055 | CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; \ 1056 } while (0) 1057 1058 #define CMU_VDAC0CLK_SELECT_FSRCO CMU_VDAC_SELECT_FSRCO 1059 1060 #define CMU_VDAC0_SELECT_HFRCOEM23 \ 1061 do { \ 1062 CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ 1063 | CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; \ 1064 } while (0) 1065 1066 #define CMU_VDAC0CLK_SELECT_HFRCOEM23 CMU_VDAC_SELECT_HFRCOEM23 1067 1068 #define CMU_VDAC0_SELECT_EM01GRPACLK \ 1069 do { \ 1070 CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ 1071 | CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; \ 1072 } while (0) 1073 1074 #define CMU_VDAC0CLK_SELECT_EM01GRPACLK CMU_VDAC_SELECT_EM01GRPACLK 1075 1076 #define CMU_VDAC0_SELECT_EM23GRPACLK \ 1077 do { \ 1078 CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ 1079 | CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; \ 1080 } while (0) 1081 1082 #define CMU_VDAC0CLK_SELECT_EM23GRPACLK CMU_VDAC_SELECT_EM23GRPACLK 1083 1084 #if (VDAC_COUNT > 1) 1085 #define CMU_VDAC1_SELECT_FSRCO \ 1086 do { \ 1087 CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ 1088 | CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; \ 1089 } while (0) 1090 1091 #define CMU_VDAC1CLK_SELECT_FSRCO CMU_VDAC1_SELECT_FSRCO 1092 1093 #define CMU_VDAC1_SELECT_HFRCOEM23 \ 1094 do { \ 1095 CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ 1096 | CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; \ 1097 } while (0) 1098 1099 #define CMU_VDAC1CLK_SELECT_HFRCOEM23 CMU_VDAC1_SELECT_HFRCOEM23 1100 1101 #define CMU_VDAC1_SELECT_EM01GRPACLK \ 1102 do { \ 1103 CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ 1104 | CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; \ 1105 } while (0) 1106 1107 #define CMU_VDAC1CLK_SELECT_EM01GRPACLK CMU_VDAC1_SELECT_EM01GRPACLK 1108 1109 #define CMU_VDAC1_SELECT_EM23GRPACLK \ 1110 do { \ 1111 CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ 1112 | CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; \ 1113 } while (0) 1114 1115 #define CMU_VDAC1CLK_SELECT_EM23GRPACLK CMU_VDAC1_SELECT_EM23GRPACLK 1116 #endif /* VDAC_COUNT > 1 */ 1117 #endif /* VDAC_PRESENT */ 1118 1119 #if defined(PCNT_PRESENT) 1120 #define CMU_PCNT0_SELECT_EM23GRPACLK \ 1121 do { \ 1122 CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ 1123 | CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; \ 1124 } while (0) 1125 1126 #define CMU_PCNT0CLK_SELECT_EM23GRPACLK CMU_PCNT0_SELECT_EM23GRPACLK 1127 1128 #define CMU_PCNT0_SELECT_PCNTEXTCLK \ 1129 do { \ 1130 CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ 1131 | CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; \ 1132 } while (0) 1133 1134 #define CMU_PCNT0CLK_SELECT_PCNTEXTCLK CMU_PCNT0_SELECT_PCNTEXTCLK 1135 #endif /* PCNT_PRESENT */ 1136 1137 #if defined(LESENSE_PRESENT) 1138 #define CMU_LESENSEHFCLK_SELECT_FSRCO \ 1139 do { \ 1140 CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ 1141 | CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; \ 1142 } while (0) 1143 1144 #define CMU_LESENSEHFCLK_SELECT_HFRCOEM23 \ 1145 do { \ 1146 CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ 1147 | CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; \ 1148 } while (0) 1149 #endif /* LESENSE_PRESENT */ 1150 1151 #if defined(USB_PRESENT) 1152 #define CMU_USB_SELECT_USBPLL0 \ 1153 do { \ 1154 CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ 1155 | CMU_USB0CLKCTRL_CLKSEL_USBPLL0; \ 1156 } while (0) 1157 1158 #define CMU_USB_SELECT_LFXO \ 1159 do { \ 1160 CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ 1161 | CMU_USB0CLKCTRL_CLKSEL_LFXO; \ 1162 } while (0) 1163 1164 #define CMU_USB_SELECT_LFRCO \ 1165 do { \ 1166 CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ 1167 | CMU_USB0CLKCTRL_CLKSEL_LFRCO; \ 1168 } while (0) 1169 #endif /* USB_PRESENT */ 1170 1171 #elif defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_0) 1172 1173 /***************************************************************************//** 1174 * @brief This function configures the HFLE wait-states and divider suitable 1175 * for the System Core Clock. 1176 * 1177 * @note FOR INTERNAL USE ONLY. 1178 * 1179 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1180 * the clock source is HFCLKLE. 1181 ******************************************************************************/ 1182 void sli_em_cmu_SetHFLEConfigSystemCoreClock(void); 1183 1184 /***************************************************************************//** 1185 * @brief This function configures the HFLE wait-states and divider suitable 1186 * for the HF Clock. 1187 * 1188 * @note FOR INTERNAL USE ONLY. 1189 * 1190 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1191 * the clock source is HFCLKLE. 1192 ******************************************************************************/ 1193 void sli_em_cmu_SetHFLEConfigHFClock(void); 1194 1195 /***************************************************************************//** 1196 * @brief This function is used to initialize the HF clock and selecting 1197 * an LF clock source. 1198 * 1199 * @note FOR INTERNAL USE ONLY. 1200 * 1201 * @param[in]osc 1202 * Reference to a low-frequency oscillator. One of the following values is valid: 1203 * - cmuOsc_LFXO 1204 * - cmuOsc_LFRCO 1205 * 1206 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1207 * the clock is HF and LFXO or LFRCO is selected as the clock source. 1208 ******************************************************************************/ 1209 void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc); 1210 1211 /***************************************************************************//** 1212 * @brief This function is used to initialize the HF clock and selecting 1213 * HFXO as the clock source. 1214 * 1215 * @note FOR INTERNAL USE ONLY. 1216 * 1217 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1218 * the clock is HF and HFXO is selected as the clock source. 1219 ******************************************************************************/ 1220 void sli_em_cmu_HFClockSelectHFXO(void); 1221 1222 /***************************************************************************//** 1223 * @brief This function is used to initialize the HF clock and selecting 1224 * HFRCO as the clock source. 1225 * 1226 * @note FOR INTERNAL USE ONLY. 1227 * 1228 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1229 * the clock is HF and HFRCO is selected as the clock source. 1230 ******************************************************************************/ 1231 void sli_em_cmu_HFClockSelectHFRCO(void); 1232 1233 #if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) 1234 /***************************************************************************//** 1235 * @brief This function is used to initialize the HF clock and selecting 1236 * USHFRCODIV2 as the clock source. 1237 * 1238 * @note FOR INTERNAL USE ONLY. 1239 * 1240 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1241 * the clock is HF and USHFRCODIV2 is selected as the clock source. 1242 ******************************************************************************/ 1243 void sli_em_cmu_HFClockSelectUSHFRCODIV2(void); 1244 #endif 1245 1246 #if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) 1247 /***************************************************************************//** 1248 * @brief This function is used to initialize the HF clock and selecting 1249 * HFRCODIV2 as the clock source. 1250 * 1251 * @note FOR INTERNAL USE ONLY. 1252 * 1253 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1254 * the clock is HF and HFRCODIV2 is selected as the clock source. 1255 ******************************************************************************/ 1256 void sli_em_cmu_HFClockSelectHFRCODIV2(void); 1257 #endif 1258 1259 #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) 1260 /***************************************************************************//** 1261 * @brief This function is used to initialize the HF clock and selecting 1262 * CLKIN0 as the clock source. 1263 * 1264 * @note FOR INTERNAL USE ONLY. 1265 * 1266 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1267 * the clock is HF and CLKIN0 is selected as the clock source. 1268 ******************************************************************************/ 1269 void sli_em_cmu_HFClockSelectCLKIN0(void); 1270 #endif 1271 1272 #if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) 1273 /***************************************************************************//** 1274 * @brief This function is used to initialize the HF clock and selecting 1275 * USHFRCO as the clock source. 1276 * 1277 * @note FOR INTERNAL USE ONLY. 1278 * 1279 * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when 1280 * the clock is HF and USHFRCO is selected as the clock source. 1281 ******************************************************************************/ 1282 void sli_em_cmu_HFClockSelectUSHFRCO(void); 1283 #endif 1284 1285 #define CMU_HF_SELECT_LFXO \ 1286 do { \ 1287 sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFXO); \ 1288 } while (0) 1289 1290 #define CMU_HF_SELECT_LFRCO \ 1291 do { \ 1292 sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFRCO); \ 1293 } while (0) 1294 1295 #define CMU_HF_SELECT_HFXO \ 1296 do { \ 1297 sli_em_cmu_HFClockSelectHFXO(); \ 1298 } while (0) 1299 1300 #define CMU_HF_SELECT_HFRCO \ 1301 do { \ 1302 sli_em_cmu_HFClockSelectHFRCO(); \ 1303 } while (0) 1304 1305 #if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) 1306 #define CMU_HF_SELECT_USHFRCODIV2 \ 1307 do { \ 1308 sli_em_cmu_HFClockSelectUSHFRCODIV2(); \ 1309 } while (0) 1310 #endif 1311 1312 #if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) 1313 #define CMU_HF_SELECT_HFRCODIV2 \ 1314 do { \ 1315 sli_em_cmu_HFClockSelectHFRCODIV2(); \ 1316 } while (0) 1317 #endif 1318 1319 #if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) 1320 #define CMU_HF_SELECT_CLKIN0 \ 1321 do { \ 1322 sli_em_cmu_HFClockSelectCLKIN0(); \ 1323 } while (0) 1324 #endif 1325 1326 #if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) 1327 #define CMU_HF_SELECT_USHFRCO \ 1328 do { \ 1329 sli_em_cmu_HFClockSelectUSHFRCO(); \ 1330 } while (0) 1331 #endif 1332 1333 #if defined(_SILICON_LABS_32B_SERIES_1) 1334 #define CMU_LFA_SELECT_DISABLED \ 1335 do { \ 1336 CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_DISABLED; \ 1337 } while (0) 1338 1339 #define CMU_LFA_SELECT_LFXO \ 1340 do { \ 1341 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1342 CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFXO; \ 1343 } while (0) 1344 1345 #define CMU_LFA_SELECT_LFRCO \ 1346 do { \ 1347 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1348 CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFRCO; \ 1349 } while (0) 1350 1351 #define CMU_LFA_SELECT_ULFRCO \ 1352 do { \ 1353 CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_ULFRCO; \ 1354 } while (0) 1355 1356 #if defined(CMU_OSCENCMD_PLFRCOEN) 1357 #define CMU_LFA_SELECT_PLFRCO \ 1358 do { \ 1359 CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ 1360 CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_PLFRCO; \ 1361 } while (0) 1362 #endif /* CMU_OSCENCMD_PLFRCOEN */ 1363 1364 #define CMU_LFB_SELECT_DISABLED \ 1365 do { \ 1366 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_DISABLED; \ 1367 } while (0) 1368 1369 #define CMU_LFB_SELECT_LFXO \ 1370 do { \ 1371 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1372 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFXO; \ 1373 } while (0) 1374 1375 #define CMU_LFB_SELECT_LFRCO \ 1376 do { \ 1377 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1378 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFRCO; \ 1379 } while (0) 1380 1381 #define CMU_LFB_SELECT_HFCLKLE \ 1382 do { \ 1383 sli_em_cmu_SetHFLEConfigHFClock(); \ 1384 BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); \ 1385 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_HFCLKLE; \ 1386 } while (0) 1387 1388 #define CMU_LFB_SELECT_ULFRCO \ 1389 do { \ 1390 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_ULFRCO; \ 1391 } while (0) 1392 1393 #if defined(CMU_OSCENCMD_PLFRCOEN) 1394 #define CMU_LFB_SELECT_PLFRCO \ 1395 do { \ 1396 CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ 1397 CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_PLFRCO; \ 1398 } while (0) 1399 #endif /* CMU_OSCENCMD_PLFRCOEN */ 1400 1401 #if defined(_CMU_LFCCLKSEL_MASK) 1402 #define CMU_LFC_SELECT_DISABLED \ 1403 do { \ 1404 CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_DISABLED; \ 1405 } while (0) 1406 1407 #define CMU_LFC_SELECT_LFXO \ 1408 do { \ 1409 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1410 CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFXO; \ 1411 } while (0) 1412 1413 #define CMU_LFC_SELECT_LFRCO \ 1414 do { \ 1415 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1416 CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFRCO; \ 1417 } while (0) 1418 1419 #define CMU_LFC_SELECT_ULFRCO \ 1420 do { \ 1421 CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_ULFRCO; \ 1422 } while (0) 1423 1424 #endif /* _CMU_LFCCLKSEL_MASK */ 1425 1426 #define CMU_LFE_SELECT_DISABLED \ 1427 do { \ 1428 CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_DISABLED; \ 1429 } while (0) 1430 1431 #define CMU_LFE_SELECT_LFXO \ 1432 do { \ 1433 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1434 CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFXO; \ 1435 } while (0) 1436 1437 #define CMU_LFE_SELECT_LFRCO \ 1438 do { \ 1439 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1440 CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFRCO; \ 1441 } while (0) 1442 1443 #define CMU_LFE_SELECT_ULFRCO \ 1444 do { \ 1445 CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_ULFRCO; \ 1446 } while (0) 1447 1448 #if defined(CMU_OSCENCMD_PLFRCOEN) 1449 #define CMU_LFE_SELECT_PLFRCO \ 1450 do { \ 1451 CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ 1452 CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_PLFRCO; \ 1453 } while (0) 1454 #endif /* CMU_OSCENCMD_PLFRCOEN */ 1455 #endif /* _SILICON_LABS_32B_SERIES_1 */ 1456 1457 #if defined(_SILICON_LABS_32B_SERIES_0) 1458 #if defined(_CMU_LFCLKSEL_LFAE_MASK) 1459 #define CMU_LFA_SELECT_DISABLED \ 1460 do { \ 1461 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1462 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ 1463 | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ 1464 | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ 1465 } while (0) 1466 1467 #define CMU_LFA_SELECT_LFXO \ 1468 do { \ 1469 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1470 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1471 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ 1472 | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT) \ 1473 | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ 1474 } while (0) 1475 1476 #define CMU_LFA_SELECT_LFRCO \ 1477 do { \ 1478 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1479 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1480 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ 1481 | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT) \ 1482 | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ 1483 } while (0) 1484 1485 #define CMU_LFA_SELECT_HFCLKLE \ 1486 do { \ 1487 sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ 1488 BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ 1489 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1490 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ 1491 | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT) \ 1492 | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ 1493 } while (0) 1494 1495 #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) 1496 #define CMU_LFA_SELECT_ULFRCO \ 1497 do { \ 1498 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1499 & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ 1500 | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ 1501 | (1 << _CMU_LFCLKSEL_LFAE_SHIFT); \ 1502 } while (0) 1503 #endif 1504 1505 #else 1506 #define CMU_LFA_SELECT_DISABLED \ 1507 do { \ 1508 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ 1509 | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ 1510 } while (0) 1511 1512 #define CMU_LFA_SELECT_LFXO \ 1513 do { \ 1514 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1515 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ 1516 | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT); \ 1517 } while (0) 1518 1519 #define CMU_LFA_SELECT_LFRCO \ 1520 do { \ 1521 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1522 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ 1523 | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT); \ 1524 } while (0) 1525 1526 #define CMU_LFA_SELECT_HFCLKLE \ 1527 do { \ 1528 sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ 1529 BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ 1530 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ 1531 | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT); \ 1532 } while (0) 1533 1534 #if defined(CMU_LFCLKSEL_LFAE_ULFRCO) 1535 #define CMU_LFA_SELECT_ULFRCO \ 1536 do { \ 1537 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ 1538 | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ 1539 } while (0) 1540 #endif /* CMU_LFA_SELECT_HFCLKLE */ 1541 #endif /* _CMU_LFCLKSEL_LFAE_MASK */ 1542 1543 #if defined(_CMU_LFCLKSEL_LFBE_MASK) 1544 #define CMU_LFB_SELECT_DISABLED \ 1545 do { \ 1546 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1547 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ 1548 | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ 1549 | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ 1550 } while (0) 1551 1552 #define CMU_LFB_SELECT_LFXO \ 1553 do { \ 1554 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1555 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1556 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ 1557 | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT) \ 1558 | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ 1559 } while (0) 1560 1561 #define CMU_LFB_SELECT_LFRCO \ 1562 do { \ 1563 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1564 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1565 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ 1566 | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT) \ 1567 | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ 1568 } while (0) 1569 1570 #define CMU_LFB_SELECT_HFCLKLE \ 1571 do { \ 1572 sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ 1573 BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ 1574 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1575 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ 1576 | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT) \ 1577 | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ 1578 } while (0) 1579 1580 #if defined(CMU_LFCLKSEL_LFBE_ULFRCO) 1581 #define CMU_LFB_SELECT_ULFRCO \ 1582 do { \ 1583 CMU->LFCLKSEL = (CMU->LFCLKSEL \ 1584 & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ 1585 | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ 1586 | (1 << _CMU_LFCLKSEL_LFBE_SHIFT); \ 1587 } while (0) 1588 #endif 1589 1590 #else 1591 #define CMU_LFB_SELECT_DISABLED \ 1592 do { \ 1593 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ 1594 | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ 1595 } while (0) 1596 1597 #define CMU_LFB_SELECT_LFXO \ 1598 do { \ 1599 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1600 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ 1601 | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT); \ 1602 } while (0) 1603 1604 #define CMU_LFB_SELECT_LFRCO \ 1605 do { \ 1606 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1607 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ 1608 | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT); \ 1609 } while (0) 1610 1611 #define CMU_LFB_SELECT_HFCLKLE \ 1612 do { \ 1613 sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ 1614 BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ 1615 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ 1616 | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT); \ 1617 } while (0) 1618 1619 #if defined(CMU_LFCLKSEL_LFBE_ULFRCO) 1620 #define CMU_LFB_SELECT_ULFRCO \ 1621 do { \ 1622 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ 1623 | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ 1624 } while (0) 1625 #endif /* CMU_LFCLKSEL_LFBE_ULFRCO */ 1626 #endif /* _CMU_LFCLKSEL_LFBE_MASK */ 1627 1628 #define CMU_LFC_SELECT_DISABLED \ 1629 do { \ 1630 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ 1631 | (_CMU_LFCLKSEL_LFC_DISABLED << _CMU_LFCLKSEL_LFC_SHIFT); \ 1632 } while (0) 1633 1634 #define CMU_LFC_SELECT_LFXO \ 1635 do { \ 1636 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1637 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ 1638 | (_CMU_LFCLKSEL_LFC_LFXO << _CMU_LFCLKSEL_LFC_SHIFT); \ 1639 } while (0) 1640 1641 #define CMU_LFC_SELECT_LFRCO \ 1642 do { \ 1643 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1644 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ 1645 | (_CMU_LFCLKSEL_LFC_LFRCO << _CMU_LFCLKSEL_LFC_SHIFT); \ 1646 } while (0) 1647 #endif /* _SILICON_LABS_32B_SERIES_0 */ 1648 1649 #if defined(_CMU_DBGCLKSEL_DBG_MASK) 1650 #define CMU_DBG_SELECT_AUXHFRCO \ 1651 do { \ 1652 CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; \ 1653 } while (0) 1654 1655 #define CMU_DBG_SELECT_HFCLK \ 1656 do { \ 1657 CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; \ 1658 } while (0) 1659 #endif /* _CMU_DBGCLKSEL_DBG_MASK */ 1660 1661 #if defined(CMU_CTRL_DBGCLK) 1662 #define CMU_DBG_SELECT_AUXHFRCO \ 1663 do { \ 1664 CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ 1665 | CMU_CTRL_DBGCLK_AUXHFRCO; \ 1666 } while (0) 1667 1668 #define CMU_DBG_SELECT_HFCLK \ 1669 do { \ 1670 CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ 1671 | CMU_CTRL_DBGCLK_HFCLK; \ 1672 } while (0) 1673 #endif /* CMU_CTRL_DBGCLK */ 1674 1675 #if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) 1676 #define CMU_USBC_SELECT_LFXO \ 1677 do { \ 1678 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1679 CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; \ 1680 while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) {} \ 1681 } while (0) 1682 1683 #define CMU_USBC_SELECT_LFRCO \ 1684 do { \ 1685 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1686 CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; \ 1687 while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) {} \ 1688 } while (0) 1689 1690 #if defined(CMU_STATUS_USBCHFCLKSEL) 1691 #define CMU_USBC_SELECT_HFCLK \ 1692 do { \ 1693 CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; \ 1694 while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) {} \ 1695 } while (0) 1696 #endif /* CMU_STATUS_USBCHFCLKSEL */ 1697 1698 #if defined(CMU_CMD_USBCCLKSEL_USHFRCO) 1699 #define CMU_USBC_SELECT_USHFRCO \ 1700 do { \ 1701 CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ 1702 CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; \ 1703 while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) {} \ 1704 } while (0) 1705 #endif /* CMU_CMD_USBCCLKSEL_USHFRCO */ 1706 #endif /* USB_PRESENT && _CMU_HFCORECLKEN0_USBC_MASK */ 1707 1708 #if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) 1709 #define CMU_ADC0ASYNC_SELECT_DISABLED \ 1710 do { \ 1711 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ 1712 | (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ 1713 } while (0) 1714 1715 #define CMU_ADC0ASYNC_SELECT_AUXHFRCO \ 1716 do { \ 1717 CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ 1718 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ 1719 | (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ 1720 } while (0) 1721 1722 #define CMU_ADC0ASYNC_SELECT_HFXO \ 1723 do { \ 1724 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1725 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ 1726 | (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ 1727 } while (0) 1728 1729 #define CMU_ADC0ASYNC_SELECT_HFSRCCLK \ 1730 do { \ 1731 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ 1732 | (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ 1733 } while (0) 1734 #endif /* _CMU_ADCCTRL_ADC0CLKSEL_MASK */ 1735 1736 #if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) 1737 #define CMU_ADC1ASYNC_SELECT_DISABLED \ 1738 do { \ 1739 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ 1740 | (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ 1741 } while (0) 1742 1743 #define CMU_ADC1ASYNC_SELECT_AUXHFRCO \ 1744 do { \ 1745 CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ 1746 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ 1747 | (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ 1748 } while (0) 1749 1750 #define CMU_ADC1ASYNC_SELECT_HFXO \ 1751 do { \ 1752 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1753 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ 1754 | (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ 1755 } while (0) 1756 1757 #define CMU_ADC1ASYNC_SELECT_HFSRCCLK \ 1758 do { \ 1759 CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ 1760 | (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ 1761 } while (0) 1762 #endif /* _CMU_ADCCTRL_ADC1CLKSEL_MASK */ 1763 1764 #if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) 1765 #define CMU_SDIOREF_SELECT_HFRCO \ 1766 do { \ 1767 CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ 1768 CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ 1769 | (_CMU_SDIOCTRL_SDIOCLKSEL_HFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ 1770 } while (0) 1771 1772 #define CMU_SDIOREF_SELECT_HFXO \ 1773 do { \ 1774 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1775 CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ 1776 | (_CMU_SDIOCTRL_SDIOCLKSEL_HFXO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ 1777 } while (0) 1778 1779 #define CMU_SDIOREF_SELECT_AUXHFRCO \ 1780 do { \ 1781 CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ 1782 CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ 1783 | (_CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ 1784 } while (0) 1785 1786 #define CMU_SDIOREF_SELECT_USHFRCO \ 1787 do { \ 1788 CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ 1789 CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ 1790 | (_CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ 1791 } while (0) 1792 #endif /* _CMU_SDIOCTRL_SDIOCLKSEL_MASK */ 1793 1794 #if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) 1795 #define CMU_QSPI0REF_SELECT_HFRCO \ 1796 do { \ 1797 CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ 1798 CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ 1799 | (_CMU_QSPICTRL_QSPI0CLKSEL_HFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ 1800 } while (0) 1801 1802 #define CMU_QSPI0REF_SELECT_HFXO \ 1803 do { \ 1804 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1805 CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ 1806 | (_CMU_QSPICTRL_QSPI0CLKSEL_HFXO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ 1807 } while (0) 1808 1809 #define CMU_QSPI0REF_SELECT_AUXHFRCO \ 1810 do { \ 1811 CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ 1812 CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ 1813 | (_CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ 1814 } while (0) 1815 1816 #define CMU_QSPI0REF_SELECT_USHFRCO \ 1817 do { \ 1818 CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ 1819 CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ 1820 | (_CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ 1821 } while (0) 1822 #endif /* _CMU_QSPICTRL_QSPI0CLKSEL_MASK */ 1823 1824 #if defined(_CMU_USBCTRL_USBCLKSEL_MASK) 1825 #define CMU_USBR_SELECT_USHFRCO \ 1826 do { \ 1827 CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ 1828 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1829 | (_CMU_USBCTRL_USBCLKSEL_USHFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1830 } while (0) 1831 1832 #define CMU_USBR_SELECT_HFXO \ 1833 do { \ 1834 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1835 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1836 | (_CMU_USBCTRL_USBCLKSEL_HFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1837 } while (0) 1838 1839 #define CMU_USBR_SELECT_HFXOX2 \ 1840 do { \ 1841 EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); \ 1842 CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; \ 1843 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1844 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1845 | (_CMU_USBCTRL_USBCLKSEL_HFXOX2 << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1846 } while (0) 1847 1848 #define CMU_USBR_SELECT_HFRCO \ 1849 do { \ 1850 CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ 1851 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1852 | (_CMU_USBCTRL_USBCLKSEL_HFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1853 } while (0) 1854 1855 #define CMU_USBR_SELECT_LFXO \ 1856 do { \ 1857 CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ 1858 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1859 | (_CMU_USBCTRL_USBCLKSEL_LFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1860 } while (0) 1861 1862 #define CMU_USBR_SELECT_LFRCO \ 1863 do { \ 1864 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ 1865 CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ 1866 | (_CMU_USBCTRL_USBCLKSEL_LFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ 1867 } while (0) 1868 #endif /* _CMU_USBCTRL_USBCLKSEL_MASK */ 1869 1870 #if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) 1871 #define CMU_PDMREF_SELECT_USHFRCO \ 1872 do { \ 1873 CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ 1874 CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ 1875 | (_CMU_PDMCTRL_PDMCLKSEL_USHFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ 1876 } while (0) 1877 1878 #define CMU_PDMREF_SELECT_HFXO \ 1879 do { \ 1880 CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ 1881 CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ 1882 | (_CMU_PDMCTRL_PDMCLKSEL_HFXO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ 1883 } while (0) 1884 1885 #define CMU_PDMREF_SELECT_HFRCO \ 1886 do { \ 1887 CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ 1888 CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ 1889 | (_CMU_PDMCTRL_PDMCLKSEL_HFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ 1890 } while (0) 1891 #endif /* _CMU_PDMCTRL_PDMCLKSEL_MASK */ 1892 #endif /* _SILICON_LABS_32B_SERIES_2 */ 1893 /** @endcond */ 1894 1895 #ifdef __cplusplus 1896 } 1897 #endif 1898 1899 #endif /* SLI_EM_CMU_H */ 1900
