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Searched refs:PPB_BASE (Results 1 – 20 of 20) sorted by relevance

/hal_rpi_pico-latest/src/rp2_common/hardware_exception/
Dexception.c79 if (num >= 8 && num < 16) shpr0 = (io_rw_32 *) (PPB_BASE + ARM_CPU_PREFIXED(SHPR2_OFFSET) - 8); in get_shpr0()
82 if (num >= 4 && num < 16) shpr0 = (io_rw_32 *)(PPB_BASE + ARM_CPU_PREFIXED(SHPR1_OFFSET) - 4); in get_shpr0()
/hal_rpi_pico-latest/src/rp2040/hardware_structs/include/hardware/structs/
Dsystick.h53 #define systick_hw ((systick_hw_t *)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET))
Dscb.h70 #define scb_hw ((armv6m_scb_hw_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET))
Dmpu.h62 #define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
Dnvic.h65 #define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))
Dm0plus.h193 #define ppb_hw ((m0plus_hw_t *)PPB_BASE)
/hal_rpi_pico-latest/src/rp2040/boot_stage2/asminclude/boot2_helpers/
Dexit_from_boot2.S22 ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
/hal_rpi_pico-latest/src/rp2350/hardware_structs/include/hardware/structs/
Dsystick.h57 #define systick_hw ((systick_hw_t *)(PPB_BASE + M33_SYST_CSR_OFFSET))
Dsau.h60 #define sau_hw ((armv8m_sau_hw_t *)(PPB_BASE + M33_SAU_CTRL_OFFSET))
Dnvic.h89 #define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET))
Dmpu.h121 #define mpu_hw ((mpu_hw_t *)(PPB_BASE + M33_MPU_TYPE_OFFSET))
Dscb.h259 #define scb_hw ((armv8m_scb_hw_t *)(PPB_BASE + M33_CPUID_OFFSET))
Dm33.h1646 #define m33_hw ((m33_hw_t *)PPB_BASE)
/hal_rpi_pico-latest/src/rp2040/hardware_regs/include/hardware/regs/
Daddressmap.h78 #define PPB_BASE _u(0xe0000000) macro
/hal_rpi_pico-latest/src/rp2_common/hardware_irq/include/hardware/
Dirq.h380 …*((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F… in irq_clear()
/hal_rpi_pico-latest/src/rp2350/hardware_regs/include/hardware/regs/
Daddressmap.h107 #define PPB_BASE _u(0xe0000000) macro
/hal_rpi_pico-latest/src/rp2_common/hardware_irq/
Dirq.c70 return 0 != ((1u << num) & *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))); in pico_irq_is_enabled()
125 *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num; in irq_set_pending()
583 return (io_rw_32 *)(PPB_BASE + ARM_CPU_PREFIXED(NVIC_IPR0_OFFSET)); in nvic_ipr0()
/hal_rpi_pico-latest/src/rp2_common/pico_crt0/
Dcrt0.S343 ldr r0, = PPB_BASE + M33_CPACR_OFFSET
366 ldr r1, =(PPB_BASE + ARM_CPU_PREFIXED(VTOR_OFFSET))
/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/
DRP2040.h2583 #define PPB_BASE 0xE0000000UL macro
2632 #define PPB ((PPB_Type*) PPB_BASE)
/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/
DRP2350.h5949 #define PPB_BASE 0xE0000000UL macro
6015 #define PPB ((PPB_Type*) PPB_BASE)