Searched refs:PPB_BASE (Results 1 – 20 of 20) sorted by relevance
79 if (num >= 8 && num < 16) shpr0 = (io_rw_32 *) (PPB_BASE + ARM_CPU_PREFIXED(SHPR2_OFFSET) - 8); in get_shpr0()82 if (num >= 4 && num < 16) shpr0 = (io_rw_32 *)(PPB_BASE + ARM_CPU_PREFIXED(SHPR1_OFFSET) - 4); in get_shpr0()
53 #define systick_hw ((systick_hw_t *)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET))
70 #define scb_hw ((armv6m_scb_hw_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET))
62 #define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
65 #define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))
193 #define ppb_hw ((m0plus_hw_t *)PPB_BASE)
22 ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
57 #define systick_hw ((systick_hw_t *)(PPB_BASE + M33_SYST_CSR_OFFSET))
60 #define sau_hw ((armv8m_sau_hw_t *)(PPB_BASE + M33_SAU_CTRL_OFFSET))
89 #define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET))
121 #define mpu_hw ((mpu_hw_t *)(PPB_BASE + M33_MPU_TYPE_OFFSET))
259 #define scb_hw ((armv8m_scb_hw_t *)(PPB_BASE + M33_CPUID_OFFSET))
1646 #define m33_hw ((m33_hw_t *)PPB_BASE)
78 #define PPB_BASE _u(0xe0000000) macro
380 …*((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F… in irq_clear()
107 #define PPB_BASE _u(0xe0000000) macro
70 return 0 != ((1u << num) & *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))); in pico_irq_is_enabled()125 *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num; in irq_set_pending()583 return (io_rw_32 *)(PPB_BASE + ARM_CPU_PREFIXED(NVIC_IPR0_OFFSET)); in nvic_ipr0()
343 ldr r0, = PPB_BASE + M33_CPACR_OFFSET366 ldr r1, =(PPB_BASE + ARM_CPU_PREFIXED(VTOR_OFFSET))
2583 #define PPB_BASE 0xE0000000UL macro2632 #define PPB ((PPB_Type*) PPB_BASE)
5949 #define PPB_BASE 0xE0000000UL macro6015 #define PPB ((PPB_Type*) PPB_BASE)