1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 #ifndef _HARDWARE_STRUCTS_NVIC_H
9 #define _HARDWARE_STRUCTS_NVIC_H
10 
11 /**
12  * \file rp2040/nvic.h
13  */
14 
15 #include "hardware/address_mapped.h"
16 #include "hardware/regs/m0plus.h"
17 
18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
19 //
20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21 // _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
22 //
23 // Bit-field descriptions are of the form:
24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25 
26 typedef struct {
27     _REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER
28     // Interrupt Set-Enable Register
29     // 0xffffffff [31:0]  SETENA       (0x00000000) Interrupt set-enable bits
30     io_rw_32 iser;
31 
32     uint32_t _pad0[31];
33 
34     _REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER
35     // Interrupt Clear-Enable Register
36     // 0xffffffff [31:0]  CLRENA       (0x00000000) Interrupt clear-enable bits
37     io_rw_32 icer;
38 
39     uint32_t _pad1[31];
40 
41     _REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR
42     // Interrupt Set-Pending Register
43     // 0xffffffff [31:0]  SETPEND      (0x00000000) Interrupt set-pending bits
44     io_rw_32 ispr;
45 
46     uint32_t _pad2[31];
47 
48     _REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR
49     // Interrupt Clear-Pending Register
50     // 0xffffffff [31:0]  CLRPEND      (0x00000000) Interrupt clear-pending bits
51     io_rw_32 icpr;
52 
53     uint32_t _pad3[95];
54 
55     // (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes)
56     _REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0
57     // Interrupt Priority Register 0
58     // 0xc0000000 [31:30] IP_3         (0x0) Priority of interrupt 3
59     // 0x00c00000 [23:22] IP_2         (0x0) Priority of interrupt 2
60     // 0x0000c000 [15:14] IP_1         (0x0) Priority of interrupt 1
61     // 0x000000c0 [7:6]   IP_0         (0x0) Priority of interrupt 0
62     io_rw_32 ipr[8];
63 } nvic_hw_t;
64 
65 #define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))
66 static_assert(sizeof (nvic_hw_t) == 0x0320, "");
67 
68 #endif // _HARDWARE_STRUCTS_NVIC_H
69 
70