Home
last modified time | relevance | path

Searched refs:p_reg (Results 1 – 25 of 47) sorted by relevance

12

/hal_renesas-latest/drivers/ra/fsp/src/r_usb_host/
Dr_usb_host.c314 p_ctrl->p_reg = (void *) R_USB_FS0_BASE; in R_USBH_Open()
318 p_ctrl->p_reg = (void *) R_USB_HS0_BASE; in R_USBH_Open()
377 R_USB_HS0_Type * p_reg = (R_USB_HS0_Type *) p_ctrl->p_reg; in R_USBH_PortStatusGet() local
380 uint16_t info = p_reg->INTSTS1; in R_USBH_PortStatusGet()
420 R_USB_HS0_Type * p_reg = (R_USB_HS0_Type *) p_ctrl->p_reg; in R_USBH_PortReset() local
427 p_reg->DCPCTR = USB_PIPE_CTR_PID_NAK; in R_USBH_PortReset()
429 FSP_HARDWARE_REGISTER_WAIT(p_reg->DCPCTR_b.PBUSY, 0); in R_USBH_PortReset()
433 p_reg->DVSTCTR0_b.UACT = 0; in R_USBH_PortReset()
434 if (p_reg->DCPCTR_b.SUREQ) in R_USBH_PortReset()
436 p_reg->DCPCTR_b.SUREQCLR = 1; in R_USBH_PortReset()
[all …]
/hal_renesas-latest/drivers/ra/fsp/src/r_dac/
Dr_dac.c109 …p_ctrl->p_reg = (R_DAC_Type *) ((uint32_t) R_DAC0 + (unit * ((uint32_t) R_DAC1 - (uint32_t) R_DAC0… in R_DAC_Open()
111 p_ctrl->p_reg = R_DAC; in R_DAC_Open()
126 …(0U == p_ctrl->channel_index) ? (p_ctrl->p_reg->DACR_b.DAOE0 = 0U) : (p_ctrl->p_reg->DACR_b.DAOE1 … in R_DAC_Open()
134 …p_ctrl->p_reg->DADPR = (uint8_t) ((uint8_t) p_extend->data_format << (uint8_t) DAC_DADPR_REG_DPSEL… in R_DAC_Open()
144 if ((0U == p_ctrl->p_reg->DAADSCR) && (p_cfg->ad_da_synchronized)) in R_DAC_Open()
158 p_ctrl->p_reg->DAADUSR = (uint8_t) BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK; in R_DAC_Open()
161 p_ctrl->p_reg->DAADSCR = (uint8_t) (1U << (uint8_t) DAC_DAADSCR_REG_DAADST_BIT_POS); in R_DAC_Open()
166 …p_ctrl->p_reg->DAADSCR = (uint8_t) (p_cfg->ad_da_synchronized << (uint8_t) DAC_DAADSCR_REG_DAADST_… in R_DAC_Open()
186 p_ctrl->p_reg->DAVREFCR = 0x00; in R_DAC_Open()
189 p_ctrl->p_reg->DADR[0] = 0x00U; in R_DAC_Open()
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzg/r_canfd/
Dr_canfd.c29 …#define CANFD_PRV_RXMB_PTR(buffer) ((volatile R_CANFD_CFDRM_RM_TYPE *) &p_reg->CFDRM[buffer >> …
43 #define CANFD_PRV_RXMB_PTR(buffer) (&p_reg->CFDRM[buffer])
103 static void r_canfd_mb_read(R_CANFD_Type * p_reg, uint32_t buffer, can_frame_t * const frame);
217 R_CANFD_Type * p_reg = in R_CANFD_Open() local
220 R_CANFD_Type * p_reg = R_CANFD; in R_CANFD_Open() local
222 p_ctrl->p_reg = p_reg; in R_CANFD_Open()
240 if (p_reg->CFDGSTS & R_CANFD_CFDGSTS_GRSTSTS_Msk) in R_CANFD_Open()
244 FSP_HARDWARE_REGISTER_WAIT((p_reg->CFDGSTS & R_CANFD_CFDGSTS_GRAMINIT_Msk), 0); in R_CANFD_Open()
252 p_reg->CFDGRMCFG_b.RCMC = 1; in R_CANFD_Open()
260 p_reg->CFDGCFG = p_global_cfg->global_config; in R_CANFD_Open()
[all …]
/hal_renesas-latest/drivers/ra/fsp/src/r_canfd/
Dr_canfd.c37 …#define CANFD_PRV_RXMB_PTR(buffer) ((volatile R_CANFD_CFDRM_RM_TYPE *) &p_reg->CFDRM[buffer >> …
54 #define CANFD_PRV_RXMB_PTR(buffer) (&p_reg->CFDRM[buffer])
113 static void r_canfd_mb_read(R_CANFD_Type * p_reg, uint32_t buffer, can_frame_t * const frame);
240 R_CANFD_Type * p_reg = in R_CANFD_Open() local
243 R_CANFD_Type * p_reg = R_CANFD; in R_CANFD_Open() local
245 p_ctrl->p_reg = p_reg; in R_CANFD_Open()
267 if (p_reg->CFDGSTS & R_CANFD_CFDGSTS_GRSTSTS_Msk) in R_CANFD_Open()
271 FSP_HARDWARE_REGISTER_WAIT((p_reg->CFDGSTS & R_CANFD_CFDGSTS_GRAMINIT_Msk), 0); in R_CANFD_Open()
278 p_reg->CFDGCFG = p_global_cfg->global_config; in R_CANFD_Open()
282 p_reg->CFDGAFLCFG0 = (CANFD_CFG_AFL_CH0_RULE_NUM << R_CANFD_CFDGAFLCFG0_RNC0_Pos); in R_CANFD_Open()
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzg/r_gpt/
Dr_gpt.c258 p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask; in R_GPT_Stop()
279 p_instance_ctrl->p_reg->GTSTR = p_instance_ctrl->channel_mask; in R_GPT_Start()
303 p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask; in R_GPT_Reset()
338 p_instance_ctrl->p_reg->GTPSR = gtpsr; in R_GPT_Enable()
339 p_instance_ctrl->p_reg->GTCSR = gtcsr; in R_GPT_Enable()
340 p_instance_ctrl->p_reg->GTSSR = gtssr; in R_GPT_Enable()
341 p_instance_ctrl->p_reg->GTICASR = p_extend->capture_a_source; in R_GPT_Enable()
342 p_instance_ctrl->p_reg->GTICBSR = p_extend->capture_b_source; in R_GPT_Enable()
410 p_instance_ctrl->p_reg->GTPBR = new_gtpr; in R_GPT_PeriodSet()
421 p_instance_ctrl->p_reg->GTCCRC = duty_cycle_50_percent; in R_GPT_PeriodSet()
[all …]
/hal_renesas-latest/drivers/ra/fsp/src/r_iic_master/
Dr_iic_master.c233 …p_ctrl->p_reg = (R_IIC0_Type *) ((uint32_t) R_IIC0 + (p_cfg->channel * ((uint32_t) R_IIC1 - (uint3… in R_IIC_MASTER_Open()
493 p_ctrl->p_reg->ICIER = 0x00; in R_IIC_MASTER_Close()
693 p_ctrl->p_reg->ICIER = 0x00; in iic_master_abort_seq_master()
713 p_ctrl->p_reg->ICIER = IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK; in iic_master_abort_seq_master()
726 p_ctrl->p_reg->ICCR1 = (uint8_t) IIC_MASTER_PRV_SCL_SDA_NOT_DRIVEN; in iic_master_open_hw_master()
729 …p_ctrl->p_reg->ICCR1 = (uint8_t) (IIC_MASTER_ICCR1_IICRST_BIT_MASK | IIC_MASTER_PRV_SCL_SDA_NOT_DR… in iic_master_open_hw_master()
732 p_ctrl->p_reg->ICCR1 = in iic_master_open_hw_master()
738 p_ctrl->p_reg->ICBRL = in iic_master_open_hw_master()
743 p_ctrl->p_reg->ICBRH = (uint8_t) (IIC_MASTER_BUS_RATE_REG_RESERVED_BITS | in iic_master_open_hw_master()
747 p_ctrl->p_reg->ICMR1 = (uint8_t) (IIC_MASTER_BUS_MODE_REGISTER_1_MASK | in iic_master_open_hw_master()
[all …]
/hal_renesas-latest/drivers/ra/fsp/src/r_gpt/
Dr_gpt.c283 p_instance_ctrl->p_reg->GTSTP = p_instance_ctrl->channel_mask; in R_GPT_Stop()
307 p_instance_ctrl->p_reg->GTSTR = p_instance_ctrl->channel_mask; in R_GPT_Start()
331 p_instance_ctrl->p_reg->GTCLR = p_instance_ctrl->channel_mask; in R_GPT_Reset()
369 p_instance_ctrl->p_reg->GTPSR = gtpsr; in R_GPT_Enable()
370 p_instance_ctrl->p_reg->GTCSR = gtcsr; in R_GPT_Enable()
371 p_instance_ctrl->p_reg->GTSSR = gtssr; in R_GPT_Enable()
372 p_instance_ctrl->p_reg->GTICASR = p_extend->capture_a_source; in R_GPT_Enable()
373 p_instance_ctrl->p_reg->GTICBSR = p_extend->capture_b_source; in R_GPT_Enable()
447 p_instance_ctrl->p_reg->GTPBR = new_gtpr; in R_GPT_PeriodSet()
458 p_instance_ctrl->p_reg->GTCCR[GPT_PRV_GTCCRC] = duty_cycle_50_percent; in R_GPT_PeriodSet()
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzg/r_riic_master/
Dr_riic_master.c210 p_ctrl->p_reg = in R_RIIC_MASTER_Open()
474 p_ctrl->p_reg->ICIER = 0x00000000UL; in R_RIIC_MASTER_Close()
669 p_ctrl->p_reg->ICIER = 0x00000000UL; in iic_master_abort_seq_master()
689 p_ctrl->p_reg->ICIER = IIC_MASTER_INTERRUPT_ENABLE_INIT_MASK; in iic_master_abort_seq_master()
704 p_ctrl->p_reg->ICCR1 = IIC_MASTER_PRV_SCL_SDA_NOT_DRIVEN; in iic_master_open_hw_master()
707 p_ctrl->p_reg->ICCR1 = in iic_master_open_hw_master()
711 p_ctrl->p_reg->ICCR1 = in iic_master_open_hw_master()
717 p_ctrl->p_reg->ICBRL = in iic_master_open_hw_master()
722 p_ctrl->p_reg->ICBRH = (IIC_MASTER_BUS_RATE_REG_RESERVED_BITS | in iic_master_open_hw_master()
726 p_ctrl->p_reg->ICMR1 = (uint8_t) (IIC_MASTER_BUS_MODE_REGISTER_1_MASK | in iic_master_open_hw_master()
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzg/r_dmac_b/
Dr_dmac_b.c142 p_ctrl->p_reg = (R_DMAC_B0_Type *) p_dmac_b_base_address[p_extend->unit]; in R_DMAC_B_Open()
237 p_ctrl->p_reg->GRP[group].CH[channel].CHCTRL = R_DMAC_B0_GRP_CH_CHCTRL_STG_Msk; in R_DMAC_B_SoftwareStart()
264 p_ctrl->p_reg->GRP[group].CH[channel].CHCTRL = R_DMAC_B0_GRP_CH_CHCTRL_SETSUS_Msk; in R_DMAC_B_SoftwareStop()
267 if (!(p_ctrl->p_reg->GRP[group].CH[channel].CHSTAT & R_DMAC_B0_GRP_CH_CHSTAT_EN_Msk)) in R_DMAC_B_SoftwareStop()
270 p_ctrl->p_reg->GRP[group].CH[channel].CHCTRL = R_DMAC_B0_GRP_CH_CHCTRL_SWRST_Msk; in R_DMAC_B_SoftwareStop()
276 FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->GRP[group].CH[channel].CHSTAT_b.SUS, 1); in R_DMAC_B_SoftwareStop()
279 p_ctrl->p_reg->GRP[group].CH[channel].CHCTRL = R_DMAC_B0_GRP_CH_CHCTRL_CLREN_Msk; in R_DMAC_B_SoftwareStop()
282 FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->GRP[group].CH[channel].CHSTAT_b.TACT, 0); in R_DMAC_B_SoftwareStop()
285 p_ctrl->p_reg->GRP[group].CH[channel].CHCTRL_b.SWRST = 1; in R_DMAC_B_SoftwareStop()
354 p_info->transfer_length_remaining = (p_ctrl->p_reg->GRP[group].CH[channel].CRTB); in R_DMAC_B_InfoGet()
[all …]
/hal_renesas-latest/drivers/ra/fsp/src/r_adc/
Dr_adc.c222 p_instance_ctrl->p_reg = (R_ADC0_Type *) ((uint32_t) R_ADC0 + (address_gap * p_cfg->unit)); in R_ADC_Open()
356 if (ADC_GROUP_A_GROUP_B_CONTINUOUS_SCAN != p_instance_ctrl->p_reg->ADGSPCR) in R_ADC_ScanStart()
358 FSP_ERROR_RETURN(0U == p_instance_ctrl->p_reg->ADCSR_b.ADST, FSP_ERR_IN_USE); in R_ADC_ScanStart()
363 p_instance_ctrl->p_reg->ADCSR = p_instance_ctrl->scan_start_adcsr; in R_ADC_ScanStart()
407 p_instance_ctrl->p_reg->ADCSR = 0U; in R_ADC_ScanStop()
431 p_status->state = (adc_state_t) p_instance_ctrl->p_reg->ADCSR_b.ADST; in R_ADC_StatusGet()
477 *p_data = p_instance_ctrl->p_reg->ADDR[reg_id]; in R_ADC_Read()
551 p_instance_ctrl->p_reg->ADSSTR[p_sample->reg_id] = p_sample->num_states; in R_ADC_SampleStateCountSet()
597 p_adc_info->p_address = &p_instance_ctrl->p_reg->ADDR[lowest_channel - 3]; in R_ADC_InfoGet()
684 p_instance_ctrl->p_reg->ADSTRGR = 0U; in R_ADC_Close()
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzg/r_scif_uart/
Dr_scif_uart.c241 p_ctrl->p_reg = ((R_SCIFA0_Type *) (R_SCIFA5_BASE)); in R_SCIF_UART_Open()
245 p_ctrl->p_reg = ((R_SCIFA0_Type *) (R_SCIFA0_BASE + (SCIF_REG_SIZE * p_cfg->channel))); in R_SCIF_UART_Open()
249 p_ctrl->p_reg = ((R_SCIFA0_Type *) (R_SCIFA0_BASE + (SCIF_REG_SIZE * p_cfg->channel))); in R_SCIF_UART_Open()
276 p_ctrl->p_reg->SCR = 0U; in R_SCIF_UART_Open()
277 uint32_t fcr = p_ctrl->p_reg->FCR; in R_SCIF_UART_Open()
279 p_ctrl->p_reg->FCR = (uint16_t) fcr; in R_SCIF_UART_Open()
280 p_ctrl->p_reg->FSR; in R_SCIF_UART_Open()
281 p_ctrl->p_reg->FSR = 0; in R_SCIF_UART_Open()
282 p_ctrl->p_reg->LSR; in R_SCIF_UART_Open()
283 p_ctrl->p_reg->LSR = 0; in R_SCIF_UART_Open()
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzn/r_sci_uart/
Dr_sci_uart.c401 p_instance_ctrl->p_reg = in R_SCI_UART_Open()
407 p_instance_ctrl->p_reg = (R_SCI0_Type *) BSP_FEATURE_SCI_SAFETY_CHANNEL_BASE_ADDRESS; in R_SCI_UART_Open()
418 p_instance_ctrl->p_reg->CCR0 = SCI_UART_CCR0_DEFAULT_VALUE; in R_SCI_UART_Open()
419 FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 0); in R_SCI_UART_Open()
420 FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 0); in R_SCI_UART_Open()
421 p_instance_ctrl->p_reg->CCR1 = SCI_UART_CCR1_DEFAULT_VALUE; in R_SCI_UART_Open()
422 p_instance_ctrl->p_reg->CCR2 = SCI_UART_CCR2_DEFAULT_VALUE; in R_SCI_UART_Open()
423 p_instance_ctrl->p_reg->CCR3 = SCI_UART_CCR3_DEFAULT_VALUE; in R_SCI_UART_Open()
424 p_instance_ctrl->p_reg->CCR4 = SCI_UART_CCR4_DEFAULT_VALUE; in R_SCI_UART_Open()
429 p_instance_ctrl->p_reg->CFCLR = SCI_UART_CFCLR_ALL_FLAG_CLEAR; in R_SCI_UART_Open()
[all …]
/hal_renesas-latest/drivers/ra/fsp/src/r_sci_b_uart/
Dr_sci_b_uart.c308 p_ctrl->p_reg = (R_SCI_B0_Type *) (R_SCI0_BASE + (SCI_B_REG_SIZE * p_cfg->channel)); in R_SCI_B_UART_Open()
352 p_ctrl->p_reg->CCR0 = ccr0; in R_SCI_B_UART_Open()
375 p_ctrl->p_reg->CFCLR = SCI_B_UART_CFCLR_CLEAR_ALL_MASK; in R_SCI_B_UART_Open()
378 p_ctrl->p_reg->FFCLR = SCI_B_UART_FFCLR_CLEAR_ALL_MASK; in R_SCI_B_UART_Open()
399 p_ctrl->p_reg->CCR0 = ccr0; in R_SCI_B_UART_Open()
404 FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->CESR_b.RIST, 1U); in R_SCI_B_UART_Open()
429 p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); in R_SCI_B_UART_Close()
435 p_ctrl->p_reg->FCR_b.TFRST = 1U; in R_SCI_B_UART_Close()
439 p_ctrl->p_reg->CCR3 = 0U; in R_SCI_B_UART_Close()
444 p_ctrl->p_reg->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk); in R_SCI_B_UART_Close()
[all …]
/hal_renesas-latest/drivers/ra/fsp/src/r_ulpt/
Dr_ulpt.c116 p_instance_ctrl->p_reg = (R_ULPT0_Type *) base_address; in R_ULPT_Open()
124 p_instance_ctrl->p_reg->ULPTCR = 0U; in R_ULPT_Open()
127 FSP_HARDWARE_REGISTER_WAIT(0U, p_instance_ctrl->p_reg->ULPTCR_b.TCSTF); in R_ULPT_Open()
130 p_instance_ctrl->p_reg->ULPTMR2 = 0U; in R_ULPT_Open()
172 p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_START_TIMER; in R_ULPT_Start()
195 p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_STOP_TIMER; in R_ULPT_Stop()
215 p_instance_ctrl->p_reg->ULPTCNT = p_instance_ctrl->period - 1U; in R_ULPT_Reset()
239 p_instance_ctrl->p_reg->ULPTCNT = p_instance_ctrl->period - 1U; in R_ULPT_Enable()
242 p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_START_TIMER; in R_ULPT_Enable()
266 p_instance_ctrl->p_reg->ULPTCR = ULPT_PRV_ULPTCR_STOP_TIMER; in R_ULPT_Disable()
[all …]
/hal_renesas-latest/drivers/ra/fsp/src/r_sci_uart/
Dr_sci_uart.c345 p_ctrl->p_reg = ((R_SCI0_Type *) (R_SCI0_BASE + (SCI_REG_SIZE * p_cfg->channel))); in R_SCI_UART_Open()
388 p_ctrl->p_reg->SCR = 0U; in R_SCI_UART_Open()
389 p_ctrl->p_reg->SSR = 0U; in R_SCI_UART_Open()
390 p_ctrl->p_reg->SIMR1 = 0U; in R_SCI_UART_Open()
391 p_ctrl->p_reg->SIMR2 = 0U; in R_SCI_UART_Open()
392 p_ctrl->p_reg->SIMR3 = 0U; in R_SCI_UART_Open()
393 p_ctrl->p_reg->CDR = 0U; in R_SCI_UART_Open()
398 p_ctrl->p_reg->DCCR = SCI_UART_DCCR_DEFAULT_VALUE; in R_SCI_UART_Open()
402 p_ctrl->p_reg->SPTR = (uint8_t) (1U << SPTR_SPB2D_BIT) | SPTR_OUTPUT_ENABLE_MASK; in R_SCI_UART_Open()
431 p_ctrl->p_reg->SCR = (uint8_t) scr; in R_SCI_UART_Open()
[all …]
/hal_renesas-latest/drivers/ra/fsp/src/r_sdhi/
Dr_sdhi.c366 p_ctrl->p_reg = p_cfg->channel ? R_SDHI1 : R_SDHI0; in R_SDHI_Open()
368 p_ctrl->p_reg = R_SDHI0; in R_SDHI_Open()
376 p_ctrl->p_reg->SD_INFO1 = 0U; in R_SDHI_Open()
379 p_ctrl->p_reg->SOFT_RST = 0x0U; in R_SDHI_Open()
380 p_ctrl->p_reg->SOFT_RST = 0x1U; in R_SDHI_Open()
385 p_ctrl->p_reg->SD_INFO1_MASK = SDHI_PRV_SD_INFO1_MASK_CD_ENABLE; in R_SDHI_Open()
389 p_ctrl->p_reg->SD_INFO1_MASK = SDHI_PRV_SD_INFO1_MASK_MASK_ALL; in R_SDHI_Open()
888 (p_ctrl->p_reg->SD_INFO2 & SDHI_PRV_SD_INFO2_CBSY_SDD0MON_IDLE_MASK), in R_SDHI_IoIntEnable()
894 p_ctrl->p_reg->SDIO_MODE = 1U; in R_SDHI_IoIntEnable()
895 p_ctrl->p_reg->SDIO_INFO1_MASK = 0x6U; in R_SDHI_IoIntEnable()
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/mcu/all/
Dbsp_slave_stop.c49 volatile uint32_t * p_reg; in R_BSP_SlaveStopRelease() local
51 …p_reg = (uint32_t *) &R_SSC->SSTPCR4 + ((bus_slave & BSP_SLAVE_STOP_SSTPCR_OFFSET_MASK) >> 1… in R_BSP_SlaveStopRelease()
54 *p_reg &= ~req_bit_msk; in R_BSP_SlaveStopRelease()
59 FSP_HARDWARE_REGISTER_WAIT((*p_reg & ack_bit_msk) >> ack_pos, 0); in R_BSP_SlaveStopRelease()
73 volatile uint32_t * p_reg; in R_BSP_SlaveStop() local
75 …p_reg = (uint32_t *) &R_SSC->SSTPCR4 + ((bus_slave & BSP_SLAVE_STOP_SSTPCR_OFFSET_MASK) >> 1… in R_BSP_SlaveStop()
78 *p_reg |= req_bit_msk; in R_BSP_SlaveStop()
83 FSP_HARDWARE_REGISTER_WAIT((*p_reg & ack_bit_msk) >> ack_pos, 1); in R_BSP_SlaveStop()
Dbsp_tzc400.c112 volatile uint32_t * p_reg; in bsp_tzc_400_cfg() local
121 p_reg = (uint32_t *) (basetzc400 + BSP_TZC_400_REGION_GATEKEEPER_OFFSET); in bsp_tzc_400_cfg()
122 *p_reg = g_bsp_tzc_module_cfg_data[tzc400module].gatekeeper; in bsp_tzc_400_cfg()
125 p_reg = (uint32_t *) (basetzc400 + BSP_TZC_400_REGION_SPEC_DISABLEULATION_CTL_OFFSET); in bsp_tzc_400_cfg()
126 *p_reg = (uint32_t) ((g_bsp_tzc_module_cfg_data[tzc400module].write_spec_disable << 1) | in bsp_tzc_400_cfg()
130 p_reg = (uint32_t *) (basetzc400 + BSP_TZC_400_REGION_ATTR_N_OFFSET(0)); in bsp_tzc_400_cfg()
131 *p_reg = (uint32_t) ((g_bsp_tzc_module_cfg_data[tzc400module].region[0].attr_rd_en << 30) | in bsp_tzc_400_cfg()
136 p_reg = (uint32_t *) (basetzc400 + BSP_TZC_400_REGION_ID_ACCESS_N_OFFSET(0)); in bsp_tzc_400_cfg()
137 *p_reg = in bsp_tzc_400_cfg()
Dbsp_reset.c316 uint32_t * p_reg; in R_BSP_ModuleResetEnable() local
320 p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA + in R_BSP_ModuleResetEnable()
326 *p_reg |= mrctl; in R_BSP_ModuleResetEnable()
329 mrctl = *(volatile uint32_t *) (p_reg); in R_BSP_ModuleResetEnable()
348 uint32_t * p_reg; in R_BSP_ModuleResetDisable() local
352 p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA + in R_BSP_ModuleResetDisable()
358 *p_reg &= ~mrctl; in R_BSP_ModuleResetDisable()
367 mrctl = *(volatile uint32_t *) (p_reg); in R_BSP_ModuleResetDisable()
/hal_renesas-latest/drivers/ra/fsp/src/r_agt/
Dr_agt.c65 … ? &(p_instance_ctrl)->p_reg->AGT32.CTRL \
66 … : &(p_instance_ctrl)->p_reg->AGT16.CTRL))
177 p_instance_ctrl->p_reg = (R_AGTX0_Type *) channel_base_address; in R_AGT_Open()
259 p_instance_ctrl->p_reg->AGT32.AGTCMA = UINT32_MAX; in R_AGT_Start()
260 p_instance_ctrl->p_reg->AGT32.AGTCMB = UINT32_MAX; in R_AGT_Start()
264 p_instance_ctrl->p_reg->AGT16.AGTCMA = UINT16_MAX; in R_AGT_Start()
265 p_instance_ctrl->p_reg->AGT16.AGTCMB = UINT16_MAX; in R_AGT_Start()
315 p_instance_ctrl->p_reg->AGT32.AGT = (uint32_t) (p_instance_ctrl->period - 1U); in R_AGT_Reset()
319 p_instance_ctrl->p_reg->AGT16.AGT = (uint16_t) (p_instance_ctrl->period - 1U); in R_AGT_Reset()
348 p_instance_ctrl->p_reg->AGT32.AGT = (uint32_t) (p_instance_ctrl->period - 1U); in R_AGT_Enable()
[all …]
/hal_renesas-latest/zephyr/ra/portable/
Dbsp_common.h204 BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg);
205 BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg);
206 BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg);
228 __STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg) in R_BSP_S_STYPE3_RegU8Read() argument
230 p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); in R_BSP_S_STYPE3_RegU8Read()
232 return *p_reg; in R_BSP_S_STYPE3_RegU8Read()
242 __STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg) in R_BSP_S_STYPE3_RegU16Read() argument
244 p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); in R_BSP_S_STYPE3_RegU16Read()
246 return *p_reg; in R_BSP_S_STYPE3_RegU16Read()
256 __STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg) in R_BSP_S_STYPE3_RegU32Read() argument
[all …]
/hal_renesas-latest/drivers/ra/fsp/src/bsp/mcu/all/
Dbsp_common.h202 BSP_CMSE_NONSECURE_ENTRY uint8_t R_BSP_NSC_STYPE3_RegU8Read(uint8_t volatile const * p_reg);
203 BSP_CMSE_NONSECURE_ENTRY uint16_t R_BSP_NSC_STYPE3_RegU16Read(uint16_t volatile const * p_reg);
204 BSP_CMSE_NONSECURE_ENTRY uint32_t R_BSP_NSC_STYPE3_RegU32Read(uint32_t volatile const * p_reg);
226 __STATIC_INLINE uint8_t R_BSP_S_STYPE3_RegU8Read (uint8_t volatile const * p_reg) in R_BSP_S_STYPE3_RegU8Read() argument
228 p_reg = (uint8_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); in R_BSP_S_STYPE3_RegU8Read()
230 return *p_reg; in R_BSP_S_STYPE3_RegU8Read()
240 __STATIC_INLINE uint16_t R_BSP_S_STYPE3_RegU16Read (uint16_t volatile const * p_reg) in R_BSP_S_STYPE3_RegU16Read() argument
242 p_reg = (uint16_t volatile const *) ((uint32_t) p_reg | BSP_FEATURE_TZ_NS_OFFSET); in R_BSP_S_STYPE3_RegU16Read()
244 return *p_reg; in R_BSP_S_STYPE3_RegU16Read()
254 __STATIC_INLINE uint32_t R_BSP_S_STYPE3_RegU32Read (uint32_t volatile const * p_reg) in R_BSP_S_STYPE3_RegU32Read() argument
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzg/r_adc_c/
Dr_adc_c.c120 p_instance_ctrl->p_reg = R_ADC_C; in R_ADC_C_Open()
245 FSP_ERROR_RETURN(0U == p_instance_ctrl->p_reg->ADM0_b.ADCE, FSP_ERR_IN_USE); in R_ADC_C_ScanStart()
249 p_instance_ctrl->p_reg->ADM0 = p_instance_ctrl->scan_start; in R_ADC_C_ScanStart()
290 …p_instance_ctrl->p_reg->ADM0 = (uint32_t) (p_instance_ctrl->scan_start & ADC_C_PRV_ADM0_CLEAR_ADCE… in R_ADC_C_ScanStop()
293 FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->ADM0_b.ADCE, 0U); in R_ADC_C_ScanStop()
316 p_status->state = (adc_state_t) p_instance_ctrl->p_reg->ADM0_b.ADBSY; in R_ADC_C_StatusGet()
349 *p_data = *((uint16_t *) (&p_instance_ctrl->p_reg->ADCR0 + reg_id)); in R_ADC_C_Read()
405 FSP_ERROR_RETURN(0 == p_instance_ctrl->p_reg->ADM0_b.ADBSY, FSP_ERR_IN_USE); in R_ADC_C_SampleStateCountSet()
414 p_instance_ctrl->p_reg->ADM3 = adm3; in R_ADC_C_SampleStateCountSet()
449 p_adc_info->p_address = &p_instance_ctrl->p_reg->ADCR0; in R_ADC_C_InfoGet()
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzg/r_gtm/
Dr_gtm.c108 p_instance_ctrl->p_reg = (R_GTM0_Type *) base_address; in R_GTM_Open()
115 p_instance_ctrl->p_reg->OSTMnTT = 1; in R_GTM_Open()
133 p_instance_ctrl->p_reg->OSTMnCTL = (uint8_t) gtmnmd; in R_GTM_Open()
167 p_instance_ctrl->p_reg->OSTMnTS = 1; in R_GTM_Start()
187 p_instance_ctrl->p_reg->OSTMnTT = 1; in R_GTM_Stop()
297 p_info->clock_frequency = r_gtm_clock_frequency_get(p_instance_ctrl->p_reg); in R_GTM_InfoGet()
301 (p_instance_ctrl->p_reg->OSTMnCTL & R_GTM0_OSTMnCTL_OSTMnMD1_Msk) ? in R_GTM_InfoGet()
326 p_status->state = p_instance_ctrl->p_reg->OSTMnTE_b.OSTMnTE ? in R_GTM_StatusGet()
330 p_status->counter = p_instance_ctrl->p_reg->OSTMnCNT; in R_GTM_StatusGet()
405 p_instance_ctrl->p_reg->OSTMnTT = 1; in R_GTM_Close()
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzn/r_ioport/
Dr_ioport.c62 uint32_t p_reg : 1; member
73 uint32_t p_reg : 1; member
1023 if (0U == p_cfg_data->p_reg) // Low output setting in r_ioport_pin_set_safety()
1027 else if (1U == p_cfg_data->p_reg) // High output setting in r_ioport_pin_set_safety()
1132 if (0U == p_cfg_data->p_reg) // Low output setting in r_ioport_pin_set_non_safety()
1136 else if (1U == p_cfg_data->p_reg) // High output setting in r_ioport_pin_set_non_safety()

12