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Searched refs:SCKDIVCR2 (Results 1 – 21 of 21) sorted by relevance

/hal_renesas-latest/drivers/ra/fsp/src/bsp/mcu/all/
Dbsp_clocks.c905 …uint8_t cpuck = (FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, secure) & R_SYSTEM_SCKDIVCR2_CPUCK_Msk)… in SystemCoreClockUpdate()
1048 R_SYSTEM->SCKDIVCR2 = sckdivcr2; in prv_clock_dividers_set()
1054 R_SYSTEM->SCKDIVCR2 = sckdivcr2; in prv_clock_dividers_set()
1118 R_SYSTEM->SCKDIVCR2 = (uint8_t) new_div; in bsp_prv_clock_set()
1126 R_SYSTEM->SCKDIVCR2 = in bsp_prv_clock_set()
1132 R_SYSTEM->SCKDIVCR2 = sckdivcr2 + 1; in bsp_prv_clock_set()
1178 if (R_SYSTEM->SCKDIVCR2 == ((current_sckdivcr >> R_SYSTEM_SCKDIVCR_ICK_Pos) & 0xF)) in bsp_prv_clock_set()
1194 R_SYSTEM->SCKDIVCR2 = (uint8_t) new_div; in bsp_prv_clock_set()
1251 R_SYSTEM->SCKDIVCR2 = in bsp_prv_clock_prepare_pre_sleep()
1270 R_SYSTEM->SCKDIVCR2 = BSP_CLOCKS_SYS_CLOCK_DIV_1; in bsp_prv_clock_prepare_post_sleep()
[all …]
Dbsp_common.h371 …uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_S… in R_FSP_SystemClockHzGet()
/hal_renesas-latest/zephyr/ra/portable/
Dbsp_common.h373 …uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_S… in R_FSP_SystemClockHzGet()
/hal_renesas-latest/drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
DR7FA2L1AB.h10177 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA2A1AB.h10439 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA4E10D.h10036 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA4W1AD.h10525 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA4M1AB.h10689 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA4M2AD.h11025 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA4M3AF.h11025 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA4E2B9.h11840 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA6E10F.h11454 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA6M1AD.h11221 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA6E2BB.h12044 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA6M4AF.h11788 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA6M2AF.h13202 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA6M3AH.h15860 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA6M5BH.h14050 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA8T1AH.h13649 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA8M1AH.h13684 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member
DR7FA8D1BH.h15273 …__IOM uint8_t SCKDIVCR2; /*!< (@ 0x00000024) System Clock Division Control Register 2 … member