Home
last modified time | relevance | path

Searched refs:FSP_PRV_SCKDIVCR_DIV_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_renesas-latest/zephyr/ra/portable/
Dbsp_common.h184 #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU) macro
186 #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U)
364 uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK; in R_FSP_SystemClockHzGet()
373 …div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; in R_FSP_SystemClockHzGet()
391 uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; in R_FSP_SystemClockHzGet()
452 …nt32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); in R_FSP_SciSpiClockHzGet()
469 uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); in R_FSP_SpiClockHzGet()
489 uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); in R_FSP_SciClockHzGet()
/hal_renesas-latest/drivers/ra/fsp/src/bsp/mcu/all/
Dbsp_common.h182 #define FSP_PRV_SCKDIVCR_DIV_MASK (0xFU) macro
184 #define FSP_PRV_SCKDIVCR_DIV_MASK (0x7U)
362 uint32_t clock_div = (sckdivcr >> clock) & FSP_PRV_SCKDIVCR_DIV_MASK; in R_FSP_SystemClockHzGet()
371 …div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_SCKDIVCR_DIV_MASK; in R_FSP_SystemClockHzGet()
389 uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; in R_FSP_SystemClockHzGet()
450 …nt32_t clock_div = R_FSP_ClockDividerGet(scispidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); in R_FSP_SciSpiClockHzGet()
467 uint32_t clock_div = R_FSP_ClockDividerGet(spidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); in R_FSP_SpiClockHzGet()
487 uint32_t clock_div = R_FSP_ClockDividerGet(scidivcr & FSP_PRV_SCKDIVCR_DIV_MASK); in R_FSP_SciClockHzGet()
Dbsp_clocks.h360 #define BSP_PRV_SCKDIVCR_ICLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24)
362 #define BSP_PRV_SCKDIVCR_PCLKD_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 0)
367 #define BSP_PRV_SCKDIVCR_PCLKC_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 4)
372 #define BSP_PRV_SCKDIVCR_PCLKB_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 8)
377 #define BSP_PRV_SCKDIVCR_PCLKA_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 12)
382 #define BSP_PRV_SCKDIVCR_BCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 16)
387 #define BSP_PRV_SCKDIVCR_PCLKE_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 24)
392 #define BSP_PRV_SCKDIVCR_FCLK_MASK (FSP_PRV_SCKDIVCR_DIV_MASK << 28)
Dbsp_clocks.c1040 (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK); in prv_clock_dividers_set()
1082 … uint32_t iclk_div = (sckdivcr >> FSP_PRIV_CLOCK_ICLK) & FSP_PRV_SCKDIVCR_DIV_MASK; in bsp_prv_clock_set()