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Searched refs:CRG_TOP (Results 1 – 8 of 8) sorted by relevance

/hal_renesas-latest/smartbond/da1469x_hal/
Dda1469x_clock.c93 uint32_t sys_stat_reg = CRG_TOP->SYS_STAT_REG; in da1469x_clock_check_device_div1_clock()
154 uint8_t hclk_div = (CRG_TOP->CLK_AMBA_REG & CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk); in da1469x_clock_adjust_otp_access_timings()
175 ret |= !((CRG_TOP->CLK_AMBA_REG & CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk) == 0 && in da1469x_clock_sys_pll_switch_check_restrictions()
176 (CRG_TOP->CLK_AMBA_REG & CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk) == 0); in da1469x_clock_sys_pll_switch_check_restrictions()
180 ret |= !((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk) || in da1469x_clock_sys_pll_switch_check_restrictions()
181 (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk)); in da1469x_clock_sys_pll_switch_check_restrictions()
193 ret |= !((CRG_TOP->POWER_CTRL_REG & CRG_TOP_POWER_CTRL_REG_LDO_RADIO_ENABLE_Msk) || in da1469x_clock_sys_xtal32m_switch_check_restrictions()
209 assert(CRG_TOP->SYS_STAT_REG & CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Msk); in da1469x_clock_sys_xtal32m_configure()
298 if (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk) { in da1469x_clock_sys_xtal32m_switch()
300 CRG_TOP->CLK_SWITCH2XTAL_REG = CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk; in da1469x_clock_sys_xtal32m_switch()
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Dda1469x_pd.c154 if (sys_read32(REG_TO_PTR(CRG_TOP->PMU_TRIM_REG)) == 0x00008800) { in da1469x_TSMC_pd_apply_preferred()
155 sys_write32(0x00007700, REG_TO_PTR(CRG_TOP->PMU_TRIM_REG)); in da1469x_TSMC_pd_apply_preferred()
157 write32_mask(0x00001000, 0x00001020, REG_TO_PTR(CRG_TOP->BANDGAP_REG)); in da1469x_TSMC_pd_apply_preferred()
158 sys_write32(0x000000ca, REG_TO_PTR(CRG_TOP->BIAS_VREF_SEL_REG)); in da1469x_TSMC_pd_apply_preferred()
159 write32_mask(0x0003ffff, 0x041e6ef4, REG_TO_PTR(CRG_TOP->BOD_LVL_CTRL0_REG)); in da1469x_TSMC_pd_apply_preferred()
183 write32_mask(0x00001000, 0x00001020, REG_TO_PTR(CRG_TOP->BANDGAP_REG)); in da1469x_GF_pd_apply_preferred()
184 sys_write32(0x000000ca, REG_TO_PTR(CRG_TOP->BIAS_VREF_SEL_REG)); in da1469x_GF_pd_apply_preferred()
185 write32_mask(0x0003ffff, 0x041e6ef4, REG_TO_PTR(CRG_TOP->BOD_LVL_CTRL0_REG)); in da1469x_GF_pd_apply_preferred()
186 write32_mask(0x00000f00, 0x00000dfc, REG_TO_PTR(CRG_TOP->CLK_RCX_REG)); in da1469x_GF_pd_apply_preferred()
187 write32_mask(0x0000007e, 0x00000024, REG_TO_PTR(CRG_TOP->CLK_XTAL32K_REG)); in da1469x_GF_pd_apply_preferred()
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Dda1469x_sleep.c43 if (CRG_TOP->SYS_STAT_REG & CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk) { in da1469x_is_sleep_allowed()
52 return (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) && in da1469x_is_sleep_allowed()
53 !(CRG_TOP->SYS_STAT_REG & CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk) && in da1469x_is_sleep_allowed()
73 sys_clock_selection = CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk; in da1469x_sleep()
Dda1469x_clock.h138 CRG_TOP->CLK_AMBA_REG |= mask; in da1469x_clock_amba_enable()
153 CRG_TOP->CLK_AMBA_REG &= ~mask; in da1469x_clock_amba_disable()
Dda1469x_otp.c42 CRG_TOP->CLK_AMBA_REG |= mask; in da1469x_clock_amba_enable()
52 CRG_TOP->CLK_AMBA_REG &= ~mask; in da1469x_clock_amba_disable()
Dsystem_da1469x.c58 remap_addr0 = CRG_TOP->SYS_CTRL_REG & CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk; in black_orca_phy_addr()
/hal_renesas-latest/smartbond/cmac/
Dshm.c216 CRG_TOP->POWER_CTRL_REG |= CRG_TOP_POWER_CTRL_REG_LDO_RADIO_ENABLE_Msk; in cmac_enable()
219 CRG_TOP->CLK_RADIO_REG = (1 << CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos) | in cmac_enable()
226 CRG_TOP->CLK_RADIO_REG &= ~CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Msk; in cmac_enable()
236 CRG_TOP->CLK_RADIO_REG = CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Msk; in cmac_disable()
/hal_renesas-latest/smartbond/sdk/bsp/include/
DDA1469xAB.h1839 #define CRG_TOP ((CRG_TOP_Type*) CRG_TOP_BASE) macro