93     uint32_t sys_stat_reg = CRG_TOP->SYS_STAT_REG;  in da1469x_clock_check_device_div1_clock()
154     uint8_t hclk_div = (CRG_TOP->CLK_AMBA_REG & CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk);  in da1469x_clock_adjust_otp_access_timings()
175     ret |= !((CRG_TOP->CLK_AMBA_REG & CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk) == 0 &&  in da1469x_clock_sys_pll_switch_check_restrictions()
176              (CRG_TOP->CLK_AMBA_REG & CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk) == 0);  in da1469x_clock_sys_pll_switch_check_restrictions()
180     ret |= !((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk) ||  in da1469x_clock_sys_pll_switch_check_restrictions()
181              (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk));  in da1469x_clock_sys_pll_switch_check_restrictions()
193     ret |= !((CRG_TOP->POWER_CTRL_REG & CRG_TOP_POWER_CTRL_REG_LDO_RADIO_ENABLE_Msk) ||  in da1469x_clock_sys_xtal32m_switch_check_restrictions()
209     assert(CRG_TOP->SYS_STAT_REG & CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Msk);  in da1469x_clock_sys_xtal32m_configure()
298     if (CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk) {  in da1469x_clock_sys_xtal32m_switch()
300         CRG_TOP->CLK_SWITCH2XTAL_REG = CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk;  in da1469x_clock_sys_xtal32m_switch()
303         CRG_TOP->CLK_CTRL_REG &= ~CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk;  in da1469x_clock_sys_xtal32m_switch()
306     while (!(CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk));  in da1469x_clock_sys_xtal32m_switch()
349     CRG_TOP->CLK_RC32M_REG &= ~CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk;  in da1469x_clock_sys_rc32m_disable()
355     CRG_TOP->CLK_XTAL32K_REG |= CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk;  in da1469x_clock_lp_xtal32k_enable()
361     CRG_TOP->CLK_CTRL_REG = (CRG_TOP->CLK_CTRL_REG &  in da1469x_clock_lp_xtal32k_switch()
369     CRG_TOP->CLK_RCX_REG  |= CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk;  in da1469x_clock_lp_rcx_enable()
375     CRG_TOP->CLK_CTRL_REG = (CRG_TOP->CLK_CTRL_REG &  in da1469x_clock_lp_rcx_switch()
434     return (CRG_TOP->CLK_RC32K_REG & CRG_TOP_CLK_RC32K_REG_RC32K_TRIM_Msk) >>  in rc32k_trim_get()
441     CRG_TOP->CLK_RC32K_REG =  in rc32k_trim_set()
442         (CRG_TOP->CLK_RC32K_REG & ~CRG_TOP_CLK_RC32K_REG_RC32K_TRIM_Msk) |  in rc32k_trim_set()
457     if (!(CRG_TOP->CLK_RC32K_REG & CRG_TOP_CLK_RC32K_REG_RC32K_ENABLE_Msk)) {  in da1469x_clock_lp_rc32k_calibrate()
539     CRG_TOP->CLK_RCX_REG &= ~CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk;  in da1469x_clock_lp_rcx_disable()
563     assert((CRG_TOP->POWER_CTRL_REG & CRG_TOP_POWER_CTRL_REG_VDD_LEVEL_Msk)  in da1469x_clock_sys_pll_enable()
651     CRG_TOP->CLK_CTRL_REG |= CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk;  in da1469x_clock_sys_pll_switch()
653     while (!(CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk));  in da1469x_clock_sys_pll_switch()