| /hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/mcu/all/cr/ |
| D | bsp_irq_core.c | 42 extern fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES];
53 void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
226 irq = (IRQn_Type) (gic_intid - BSP_CORTEX_VECTOR_TABLE_ENTRIES); in bsp_common_interrupt_handler()
236 if (BSP_CORTEX_VECTOR_TABLE_ENTRIES <= gic_intid) in bsp_common_interrupt_handler()
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| D | bsp_irq_core.h | 66 extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
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| /hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzn2l/ |
| D | bsp_mcu_family_cfg.h | 18 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (32) macro
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| /hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/ |
| D | bsp_mcu_family_cfg.h | 11 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m1/ |
| D | bsp_mcu_family_cfg.h | 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/ |
| D | bsp_mcu_family_cfg.h | 28 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4w1/ |
| D | bsp_mcu_family_cfg.h | 30 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/ |
| D | bsp_mcu_family_cfg.h | 30 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/ |
| D | bsp_mcu_family_cfg.h | 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
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| /hal_renesas-latest/zephyr/rz/portable/rzg/ |
| D | bsp_irq.h | 18 …fine BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES)
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| /hal_renesas-latest/zephyr/ra/portable/ |
| D | bsp_irq.h | 18 …fine BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES)
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m2/ |
| D | bsp_mcu_family_cfg.h | 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m3/ |
| D | bsp_mcu_family_cfg.h | 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e2/ |
| D | bsp_mcu_family_cfg.h | 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/ |
| D | bsp_mcu_family_cfg.h | 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e1/ |
| D | bsp_mcu_family_cfg.h | 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4l1/ |
| D | bsp_mcu_family_cfg.h | 40 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m2/ |
| D | bsp_mcu_family_cfg.h | 30 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m3/ |
| D | bsp_mcu_family_cfg.h | 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e1/ |
| D | bsp_mcu_family_cfg.h | 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m4/ |
| D | bsp_mcu_family_cfg.h | 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m5/ |
| D | bsp_mcu_family_cfg.h | 29 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8t1/ |
| D | bsp_mcu_family_cfg.h | 47 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8d1/ |
| D | bsp_mcu_family_cfg.h | 47 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
|
| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/ |
| D | bsp_mcu_family_cfg.h | 47 #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) macro
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