1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /** @} (end addtogroup BSP_MCU) */
8
9 #ifndef BSP_IRQ_H
10 #define BSP_IRQ_H
11
12 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
13 FSP_HEADER
14
15 /***********************************************************************************************************************
16 * Macro definitions
17 **********************************************************************************************************************/
18 #define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES)
19
20 /***********************************************************************************************************************
21 * Typedef definitions
22 **********************************************************************************************************************/
23
24 /***********************************************************************************************************************
25 * Exported global variables
26 **********************************************************************************************************************/
27 extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
28
29 /***********************************************************************************************************************
30 * Exported global functions (to be accessed by other files)
31 **********************************************************************************************************************/
32
33 /*******************************************************************************************************************//**
34 * @brief Sets the ISR context associated with the requested IRQ.
35 *
36 * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
37 * function.
38 * @param[in] p_context ISR context for IRQ.
39 **********************************************************************************************************************/
R_FSP_IsrContextSet(IRQn_Type const irq,void * p_context)40 __STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context)
41 {
42 /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
43 * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
44 gp_renesas_isr_context[irq] = p_context;
45 }
46
47 /*******************************************************************************************************************//**
48 * @brief Finds the ISR context associated with the requested IRQ.
49 *
50 * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
51 * function.
52 * @return ISR context for IRQ.
53 **********************************************************************************************************************/
R_FSP_IsrContextGet(IRQn_Type const irq)54 __STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq)
55 {
56 /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
57 * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
58 return gp_renesas_isr_context[irq];
59 }
60
61 #if BSP_CFG_INLINE_IRQ_FUNCTIONS
62
63 #if BSP_FEATURE_ICU_HAS_IELSR
64
65 /*******************************************************************************************************************//**
66 * Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit
67 * is set. If it is not cleared in the ISR then the interrupt will trigger again immediately.
68 *
69 * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are
70 * only those for the Cortex Processor Exceptions Numbers.
71 *
72 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
73 **********************************************************************************************************************/
R_BSP_IrqStatusClear(IRQn_Type irq)74 __STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq)
75 {
76 /* Clear the IR bit in the selected IELSR register. */
77 R_ICU->IELSR_b[irq].IR = 0U;
78
79 /* Read back the IELSR register to ensure that the IR bit is cleared.
80 * See section "13.5.1 Operations During an Interrupt" in the RA8M1 manual R01UH0994EJ0100. */
81 FSP_REGISTER_READ(R_ICU->IELSR[irq]);
82 }
83
84 #endif
85
86 /*******************************************************************************************************************//**
87 * Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt.
88 *
89 * @param[in] irq Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are
90 * only those for the Cortex Processor Exceptions Numbers.
91 *
92 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
93 **********************************************************************************************************************/
R_BSP_IrqClearPending(IRQn_Type irq)94 __STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
95 {
96 #if BSP_FEATURE_ICU_HAS_IELSR
97
98 /* Clear the IR bit in the selected IELSR register. */
99 R_BSP_IrqStatusClear(irq);
100
101 /* Flush memory transactions to ensure that the IR bit is cleared before clearing the pending bit in the NVIC. */
102 __DMB();
103 #endif
104
105 /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system
106 * exceptions every time an interrupt is cleared in the NVIC. */
107 uint32_t _irq = (uint32_t) irq;
108 NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
109 }
110
111 /*******************************************************************************************************************//**
112 * Sets the interrupt priority and context.
113 *
114 * @param[in] irq The IRQ to configure.
115 * @param[in] priority NVIC priority of the interrupt
116 * @param[in] p_context The interrupt context is a pointer to data required in the ISR.
117 *
118 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
119 **********************************************************************************************************************/
R_BSP_IrqCfg(IRQn_Type const irq,uint32_t priority,void * p_context)120 __STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context)
121 {
122 /* Zephyr interrupt priority will have offset, remove priority config in FSP to prevent override seting on Zephyr */
123 FSP_PARAMETER_NOT_USED(priority);
124 /* Store the context. The context is recovered in the ISR. */
125 R_FSP_IsrContextSet(irq, p_context);
126 }
127
128 /*******************************************************************************************************************//**
129 * Enable the IRQ in the NVIC (Without clearing the pending bit).
130 *
131 * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex
132 * Processor Exceptions Numbers.
133 *
134 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
135 **********************************************************************************************************************/
R_BSP_IrqEnableNoClear(IRQn_Type const irq)136 __STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq)
137 {
138 /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions
139 * every time an interrupt is enabled in the NVIC. */
140 uint32_t _irq = (uint32_t) irq;
141
142 __COMPILER_BARRIER();
143 NVIC->ISER[(_irq >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
144 __COMPILER_BARRIER();
145 }
146
147 /*******************************************************************************************************************//**
148 * Clears pending interrupts in both ICU and NVIC, then enables the interrupt.
149 *
150 * @param[in] irq Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed
151 * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.
152 *
153 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
154 **********************************************************************************************************************/
R_BSP_IrqEnable(IRQn_Type const irq)155 __STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq)
156 {
157 /* Clear pending interrupts in the ICU and NVIC. */
158 R_BSP_IrqClearPending(irq);
159
160 /* Enable the IRQ in the NVIC. */
161 R_BSP_IrqEnableNoClear(irq);
162 }
163
164 /*******************************************************************************************************************//**
165 * Disables interrupts in the NVIC.
166 *
167 * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are
168 * only those for the Cortex Processor Exceptions Numbers.
169 *
170 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
171 **********************************************************************************************************************/
R_BSP_IrqDisable(IRQn_Type const irq)172 __STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq)
173 {
174 /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system
175 * exceptions every time an interrupt is cleared in the NVIC. */
176 uint32_t _irq = (uint32_t) irq;
177 NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
178
179 __DSB();
180 __ISB();
181 }
182
183 /*******************************************************************************************************************//**
184 * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.
185 *
186 * @param[in] irq Interrupt number.
187 * @param[in] priority NVIC priority of the interrupt
188 * @param[in] p_context The interrupt context is a pointer to data required in the ISR.
189 *
190 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
191 **********************************************************************************************************************/
R_BSP_IrqCfgEnable(IRQn_Type const irq,uint32_t priority,void * p_context)192 __STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context)
193 {
194 R_BSP_IrqCfg(irq, priority, p_context);
195 R_BSP_IrqEnable(irq);
196 }
197
198 #else
199 #if BSP_FEATURE_ICU_HAS_IELSR
200 void R_BSP_IrqStatusClear(IRQn_Type irq);
201
202 #endif
203 void R_BSP_IrqClearPending(IRQn_Type irq);
204 void R_BSP_IrqCfg(IRQn_Type const irq, uint32_t priority, void * p_context);
205 void R_BSP_IrqEnableNoClear(IRQn_Type const irq);
206 void R_BSP_IrqEnable(IRQn_Type const irq);
207 void R_BSP_IrqDisable(IRQn_Type const irq);
208 void R_BSP_IrqCfgEnable(IRQn_Type const irq, uint32_t priority, void * p_context);
209
210 #endif
211
212 /*******************************************************************************************************************//**
213 * @internal
214 * @addtogroup BSP_MCU_PRV Internal BSP Documentation
215 * @ingroup RENESAS_INTERNAL
216 * @{
217 **********************************************************************************************************************/
218
219 /* Public functions defined in bsp.h */
220 void bsp_irq_cfg(void); // Used internally by BSP
221
222 /** @} (end addtogroup BSP_MCU_PRV) */
223
224 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
225 FSP_FOOTER
226
227 #endif
228
