1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /** @} (end addtogroup BSP_MCU) */
8
9 #ifndef BSP_IRQ_H
10 #define BSP_IRQ_H
11
12 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
13 FSP_HEADER
14
15 /***********************************************************************************************************************
16 * Macro definitions
17 **********************************************************************************************************************/
18 #define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES - BSP_CORTEX_VECTOR_TABLE_ENTRIES)
19
20 /***********************************************************************************************************************
21 * IM33 DISABLE
22 *
23 * @param
24 **********************************************************************************************************************/
25 #ifndef R_BSP_IM33_DISABLE
26 #define R_BSP_IM33_DISABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 | R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk;}
27 #endif
28
29 /***********************************************************************************************************************
30 * IM33 ENABLE
31 *
32 * @param
33 **********************************************************************************************************************/
34 #ifndef R_BSP_IM33_ENABLE
35 #define R_BSP_IM33_ENABLE() {R_SYSC->SYS_LP_CTL7 = R_SYSC->SYS_LP_CTL7 & ~R_SYSC_SYS_LP_CTL7_IM33_MASK_Msk;}
36 #endif
37
38 #define R_INTC_IM33_BEISR1_BESTAT_Msk (0x00001FFFUL)
39 #define R_INTC_IM33_EREISR_E1STAT_Msk (0x000000FFUL)
40 #define R_INTC_IM33_EREISR_E2STAT_Msk (0x0000FF00UL)
41 #define R_INTC_IM33_EREISR_OFSTAT_Msk (0x00FF0000UL)
42
43 /***********************************************************************************************************************
44 * Typedef definitions
45 **********************************************************************************************************************/
46
47 /***********************************************************************************************************************
48 * Exported global variables
49 **********************************************************************************************************************/
50 extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
51
52 /***********************************************************************************************************************
53 * Exported global functions (to be accessed by other files)
54 **********************************************************************************************************************/
55
56 /*******************************************************************************************************************//**
57 * @brief Sets the ISR context associated with the requested IRQ.
58 *
59 * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
60 * function.
61 * @param[in] p_context ISR context for IRQ.
62 **********************************************************************************************************************/
R_FSP_IsrContextSet(IRQn_Type const irq,void * p_context)63 __STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context)
64 {
65 /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
66 * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
67 gp_renesas_isr_context[irq] = p_context;
68 }
69
70 /*******************************************************************************************************************//**
71 * Clear the interrupt status flag for a given interrupt.
72 *
73 * @note This function does not implement processing on this device.
74 *
75 * @param[in] irq Not used
76 **********************************************************************************************************************/
R_BSP_IrqStatusClear(IRQn_Type irq)77 __STATIC_INLINE void R_BSP_IrqStatusClear (IRQn_Type irq)
78 {
79 FSP_PARAMETER_NOT_USED(irq);
80
81 /* Do nothing */
82 }
83
84 /*******************************************************************************************************************//**
85 * Clear the interrupt status flag for a given interrupt and clear the NVIC pending interrupt.
86 *
87 * @param[in] irq Interrupt for which to clear the status flag. Note that the enums listed for IRQn_Type are
88 * only those for the Cortex Processor Exceptions Numbers.
89 *
90 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
91 **********************************************************************************************************************/
R_BSP_IrqClearPending(IRQn_Type irq)92 __STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq)
93 {
94 /* Clear the status flag in IM33. */
95 R_BSP_IrqStatusClear(irq);
96
97 /* The following statement is used in place of NVIC_ClearPendingIRQ to avoid including a branch for system
98 * exceptions every time an interrupt is cleared in the NVIC. */
99 uint32_t _irq = (uint32_t) irq;
100 NVIC->ICPR[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
101 }
102
103 /*******************************************************************************************************************//**
104 * Sets the interrupt priority and context.
105 *
106 * @param[in] irq The IRQ to configure.
107 * @param[in] priority NVIC priority of the interrupt
108 * @param[in] p_context The interrupt context is a pointer to data required in the ISR.
109 *
110 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
111 **********************************************************************************************************************/
R_BSP_IrqCfg(IRQn_Type const irq,uint32_t priority,void * p_context)112 __STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context)
113 {
114 /* Zephyr interrupt priority will have offset, remove priority config in FSP to prevent override seting on Zephyr */
115 FSP_PARAMETER_NOT_USED(priority);
116
117 /* Store the context. The context is recovered in the ISR. */
118 R_FSP_IsrContextSet(irq, p_context);
119 }
120
121 /*******************************************************************************************************************//**
122 * Enable the IRQ in the NVIC (Without clearing the pending bit).
123 *
124 * @param[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex
125 * Processor Exceptions Numbers.
126 *
127 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
128 **********************************************************************************************************************/
R_BSP_IrqEnableNoClear(IRQn_Type const irq)129 __STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq)
130 {
131 /* The following statement is used in place of NVIC_EnableIRQ to avoid including a branch for system exceptions
132 * every time an interrupt is enabled in the NVIC. */
133 uint32_t _irq = (uint32_t) irq;
134 NVIC->ISER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
135 }
136
137 /*******************************************************************************************************************//**
138 * Clears pending interrupts in both IM33 and NVIC, then enables the interrupt.
139 *
140 * @param[in] irq Interrupt for which to clear status flag and enable in the NVIC. Note that the enums listed
141 * for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.
142 *
143 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
144 **********************************************************************************************************************/
R_BSP_IrqEnable(IRQn_Type const irq)145 __STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq)
146 {
147 /* Clear pending interrupts in the status flag and NVIC. */
148 R_BSP_IrqClearPending(irq);
149
150 /* Enable the IRQ in the NVIC. */
151 R_BSP_IrqEnableNoClear(irq);
152 }
153
154 /*******************************************************************************************************************//**
155 * Disables interrupts in the NVIC.
156 *
157 * @param[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are
158 * only those for the Cortex Processor Exceptions Numbers.
159 *
160 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
161 **********************************************************************************************************************/
R_BSP_IrqDisable(IRQn_Type const irq)162 __STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq)
163 {
164 /* The following statements is used in place of NVIC_DisableIRQ to avoid including a branch for system
165 * exceptions every time an interrupt is cleared in the NVIC. */
166 uint32_t _irq = (uint32_t) irq;
167 NVIC->ICER[(((uint32_t) irq) >> 5UL)] = (uint32_t) (1UL << (_irq & 0x1FUL));
168
169 __DSB();
170 __ISB();
171 }
172
173 /*******************************************************************************************************************//**
174 * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.
175 *
176 * @param[in] irq Interrupt number.
177 * @param[in] priority NVIC priority of the interrupt
178 * @param[in] p_context The interrupt context is a pointer to data required in the ISR.
179 *
180 * @warning Do not call this function for system exceptions where the IRQn_Type value is < 0.
181 **********************************************************************************************************************/
R_BSP_IrqCfgEnable(IRQn_Type const irq,uint32_t priority,void * p_context)182 __STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context)
183 {
184 R_BSP_IrqCfg(irq, priority, p_context);
185 R_BSP_IrqEnable(irq);
186 }
187
188 /*******************************************************************************************************************//**
189 * @brief Finds the ISR context associated with the requested IRQ.
190 *
191 * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this
192 * function.
193 * @return ISR context for IRQ.
194 **********************************************************************************************************************/
R_FSP_IsrContextGet(IRQn_Type const irq)195 __STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq)
196 {
197 /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of
198 * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */
199 return gp_renesas_isr_context[irq];
200 }
201
202 /*******************************************************************************************************************//**
203 * @internal
204 * @addtogroup BSP_MCU_PRV Internal BSP Documentation
205 * @ingroup RENESAS_INTERNAL
206 * @{
207 **********************************************************************************************************************/
208
209 /* Public functions defined in bsp.h */
210 void bsp_irq_cfg(void); // Used internally by BSP
211
212 /** @} (end addtogroup BSP_MCU_PRV) */
213
214 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
215 FSP_FOOTER
216
217 #endif
218
