Home
last modified time | relevance | path

Searched refs:BSP_CFG_CLOCKS_SECURE (Results 1 – 25 of 38) sorted by relevance

12

/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8t1/
Dbsp_mcu_family_cfg.h63 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
187 ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 \
188 : (0x002E0106U | (BSP_CFG_CLOCKS_SECURE == 0)))
201 #if BSP_CFG_CLOCKS_SECURE
289 (((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */ \
291 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \
305 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */)
346 ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U) | ((0U << 24U)) | ((0U << 25U)))
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8d1/
Dbsp_mcu_family_cfg.h63 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
188 ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 \
189 : (0x002E0106U | (BSP_CFG_CLOCKS_SECURE == 0)))
206 #if BSP_CFG_CLOCKS_SECURE
294 (((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */ \
296 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \
310 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */)
351 ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U) | ((0U << 24U)) | ((0U << 25U)))
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/
Dbsp_mcu_family_cfg.h63 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
186 #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 : (\
188 (BSP_CFG_CLOCKS_SECURE == 0)))
201 #if BSP_CFG_CLOCKS_SECURE
286 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */\
288 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \
301 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */)
340 …SEL (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x…
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e1/
Dbsp_mcu_family_cfg.h45 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
171 #if BSP_CFG_CLOCKS_SECURE
252 #if BSP_CFG_CLOCKS_SECURE
267 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
307 …G_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x…
/hal_renesas-latest/zephyr/ra/portable/
Dbsp_common.h363 uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); in R_FSP_SystemClockHzGet()
373 …uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_S… in R_FSP_SystemClockHzGet()
468 …t32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE); in R_FSP_SpiClockHzGet()
472 … BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >> in R_FSP_SpiClockHzGet()
488 …t32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE); in R_FSP_SciClockHzGet()
492 … BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >> in R_FSP_SciClockHzGet()
/hal_renesas-latest/drivers/ra/fsp/src/bsp/mcu/all/
Dbsp_common.h361 uint32_t sckdivcr = FSP_STYPE3_REG32_READ(R_SYSTEM->SCKDIVCR, BSP_CFG_CLOCKS_SECURE); in R_FSP_SystemClockHzGet()
371 …uint32_t cpuclk_div = FSP_STYPE3_REG8_READ(R_SYSTEM->SCKDIVCR2, BSP_CFG_CLOCKS_SECURE) & FSP_PRV_S… in R_FSP_SystemClockHzGet()
466 …t32_t spidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SPICKDIVCR, BSP_CFG_CLOCKS_SECURE); in R_FSP_SpiClockHzGet()
470 … BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SPICKCR_CKSEL_Msk) >> in R_FSP_SpiClockHzGet()
486 …t32_t scidivcr = FSP_STYPE3_REG8_READ(R_SYSTEM->SCICKDIVCR, BSP_CFG_CLOCKS_SECURE); in R_FSP_SciClockHzGet()
490 … BSP_CFG_CLOCKS_SECURE) & R_SYSTEM_SCICKCR_SCICKSEL_Msk >> in R_FSP_SciClockHzGet()
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m2/
Dbsp_mcu_family_cfg.h46 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
180 #if BSP_CFG_CLOCKS_SECURE
262 #if BSP_CFG_CLOCKS_SECURE
279 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
323 ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
Dbsp_clock_cfg.h13 #define BSP_CFG_CLOCKS_SECURE (0) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m3/
Dbsp_mcu_family_cfg.h45 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
181 #if BSP_CFG_CLOCKS_SECURE
263 #if BSP_CFG_CLOCKS_SECURE
280 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
324 ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
Dbsp_clock_cfg.h13 #define BSP_CFG_CLOCKS_SECURE (0) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e1/
Dbsp_mcu_family_cfg.h44 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
174 #if BSP_CFG_CLOCKS_SECURE
254 #if BSP_CFG_CLOCKS_SECURE
268 #define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U)
307 (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m4/
Dbsp_mcu_family_cfg.h44 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
174 #if BSP_CFG_CLOCKS_SECURE
254 #if BSP_CFG_CLOCKS_SECURE
268 #define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U)
307 (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m5/
Dbsp_mcu_family_cfg.h44 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
174 #if BSP_CFG_CLOCKS_SECURE
254 #if BSP_CFG_CLOCKS_SECURE
268 #define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U)
307 (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e2/
Dbsp_mcu_family_cfg.h45 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
156 #if BSP_CFG_CLOCKS_SECURE
236 #if BSP_CFG_CLOCKS_SECURE
250 #define BSP_TZ_CFG_SRAMSAR (1 | ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | 4 | 0xFFFFFFF8U)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/
Dbsp_mcu_family_cfg.h45 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
160 #if BSP_CFG_CLOCKS_SECURE
241 #if BSP_CFG_CLOCKS_SECURE
258 ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4l1/
Dbsp_mcu_family_cfg.h55 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
177 #if BSP_CFG_CLOCKS_SECURE
253 #if BSP_CFG_CLOCKS_SECURE
300 …G_ROM_REG_OFS1_SEL (0xFFFFF0FFU | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x…
/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/
Dbsp_mcu_family_cfg.h34 #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/
Dbsp_clock_cfg.h13 #define BSP_CFG_CLOCKS_SECURE (0) macro
/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzn2l/
Dbsp_clock_cfg.h9 #define BSP_CFG_CLOCKS_SECURE (0) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/
Dbsp_clock_cfg.h14 #define BSP_CFG_CLOCKS_SECURE (0) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4w1/
Dbsp_clock_cfg.h13 #define BSP_CFG_CLOCKS_SECURE (0) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m1/
Dbsp_clock_cfg.h13 #define BSP_CFG_CLOCKS_SECURE (0) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m2/
Dbsp_clock_cfg.h13 #define BSP_CFG_CLOCKS_SECURE (0) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/
Dbsp_clock_cfg.h13 #define BSP_CFG_CLOCKS_SECURE (0) macro
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m3/
Dbsp_clock_cfg.h13 #define BSP_CFG_CLOCKS_SECURE (0) macro

12