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Searched refs:reg_offset (Results 1 – 25 of 125) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/drivers/
Dfsl_clock.h681 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_EnableClock() local
683 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); in CLOCK_EnableClock()
693 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_EnableClock()
698 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_EnableClock()
719 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_DisableClock() local
721 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); in CLOCK_DisableClock()
731 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_DisableClock()
740 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_DisableClock()
Dfsl_clock.c70 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_AttachClk() local
75 CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); in CLOCK_AttachClk()
89 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_GetClockAttachId() local
98 actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); in CLOCK_GetClockAttachId()
99 clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); in CLOCK_GetClockAttachId()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/drivers/
Dfsl_clock.h681 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_EnableClock() local
683 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); in CLOCK_EnableClock()
693 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_EnableClock()
698 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_EnableClock()
719 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_DisableClock() local
721 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); in CLOCK_DisableClock()
731 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_DisableClock()
740 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_DisableClock()
Dfsl_clock.c70 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_AttachClk() local
75 CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); in CLOCK_AttachClk()
89 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_GetClockAttachId() local
98 actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); in CLOCK_GetClockAttachId()
99 clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); in CLOCK_GetClockAttachId()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/drivers/
Dfsl_clock.h681 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_EnableClock() local
683 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); in CLOCK_EnableClock()
693 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_EnableClock()
698 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_EnableClock()
719 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_DisableClock() local
721 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); in CLOCK_DisableClock()
731 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_DisableClock()
740 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_DisableClock()
Dfsl_clock.c70 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_AttachClk() local
75 CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); in CLOCK_AttachClk()
89 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_GetClockAttachId() local
98 actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); in CLOCK_GetClockAttachId()
99 clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); in CLOCK_GetClockAttachId()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/drivers/
Dfsl_clock.h681 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_EnableClock() local
683 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); in CLOCK_EnableClock()
693 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_EnableClock()
698 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_EnableClock()
719 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_DisableClock() local
721 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); in CLOCK_DisableClock()
731 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_DisableClock()
740 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_DisableClock()
Dfsl_clock.c70 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_AttachClk() local
75 CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); in CLOCK_AttachClk()
89 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_GetClockAttachId() local
98 actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); in CLOCK_GetClockAttachId()
99 clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); in CLOCK_GetClockAttachId()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/drivers/
Dfsl_clock.h681 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_EnableClock() local
683 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); in CLOCK_EnableClock()
693 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_EnableClock()
698 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_EnableClock()
719 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_DisableClock() local
721 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); in CLOCK_DisableClock()
731 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_DisableClock()
740 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_DisableClock()
Dfsl_clock.c70 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_AttachClk() local
75 CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); in CLOCK_AttachClk()
89 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_GetClockAttachId() local
98 actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); in CLOCK_GetClockAttachId()
99 clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); in CLOCK_GetClockAttachId()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/drivers/
Dfsl_clock.h681 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_EnableClock() local
683 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); in CLOCK_EnableClock()
693 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_EnableClock()
698 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_EnableClock()
719 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_DisableClock() local
721 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); in CLOCK_DisableClock()
731 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_DisableClock()
740 else if (reg_offset == REG_PWM1SUBCTL) in CLOCK_DisableClock()
Dfsl_clock.c70 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_AttachClk() local
75 CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); in CLOCK_AttachClk()
89 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_GetClockAttachId() local
98 actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); in CLOCK_GetClockAttachId()
99 clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); in CLOCK_GetClockAttachId()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/drivers/
Dfsl_clock.h548 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_EnableClock() local
550 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); in CLOCK_EnableClock()
560 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_EnableClock()
581 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_DisableClock() local
583 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); in CLOCK_DisableClock()
593 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_DisableClock()
Dfsl_clock.c70 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_AttachClk() local
75 CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); in CLOCK_AttachClk()
89 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_GetClockAttachId() local
98 actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); in CLOCK_GetClockAttachId()
99 clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); in CLOCK_GetClockAttachId()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/drivers/
Dfsl_clock.h548 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_EnableClock() local
550 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); in CLOCK_EnableClock()
560 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_EnableClock()
581 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_DisableClock() local
583 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); in CLOCK_DisableClock()
593 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_DisableClock()
Dfsl_clock.c70 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_AttachClk() local
75 CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); in CLOCK_AttachClk()
89 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_GetClockAttachId() local
98 actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); in CLOCK_GetClockAttachId()
99 clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); in CLOCK_GetClockAttachId()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/drivers/
Dfsl_clock.h548 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_EnableClock() local
550 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); in CLOCK_EnableClock()
560 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_EnableClock()
581 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_DisableClock() local
583 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); in CLOCK_DisableClock()
593 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_DisableClock()
Dfsl_clock.c70 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_AttachClk() local
75 CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); in CLOCK_AttachClk()
89 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_GetClockAttachId() local
98 actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); in CLOCK_GetClockAttachId()
99 clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); in CLOCK_GetClockAttachId()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/drivers/
Dfsl_clock.h548 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_EnableClock() local
550 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset); in CLOCK_EnableClock()
560 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_EnableClock()
581 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); in CLOCK_DisableClock() local
583 …le uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); in CLOCK_DisableClock()
593 if (reg_offset == REG_PWM0SUBCTL) in CLOCK_DisableClock()
Dfsl_clock.c70 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_AttachClk() local
75 CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); in CLOCK_AttachClk()
89 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); in CLOCK_GetClockAttachId() local
98 actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); in CLOCK_GetClockAttachId()
99 clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); in CLOCK_GetClockAttachId()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE02Z4/drivers/
Dfsl_clock.h207 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ argument
208 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/drivers/
Dfsl_clock.h204 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ argument
205 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE06Z4/drivers/
Dfsl_clock.h222 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ argument
223 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z1284/drivers/
Dfsl_clock.h222 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ argument
223 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z4/drivers/
Dfsl_clock.h216 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ argument
217 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \

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