1 /*
2 * Copyright 2023, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief CLOCK driver version 1.0.0. */
25 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
26 /*@}*/
27
28 /*! @brief Configure whether driver controls clock
29 *
30 * When set to 0, peripheral drivers will enable clock in initialize function
31 * and disable clock in de-initialize function. When set to 1, peripheral
32 * driver will not control the clock, application could control the clock out of
33 * the driver.
34 *
35 * @note All drivers share this feature switcher. If it is set to 1, application
36 * should handle clock enable and disable for all drivers.
37 */
38 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
39 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0U
40 #endif
41
42 /* Definition for delay API in clock driver, users can redefine it to the real application. */
43 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
44 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (96000000U)
45 #endif
46
47 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
48 /*------------------------------------------------------------------------------
49 clock_ip_name_t definition:
50 ------------------------------------------------------------------------------*/
51 #define CLK_GATE_REG_OFFSET(value) (((uint32_t)(value)) >> 16U)
52 #define CLK_GATE_BIT_SHIFT(value) (((uint32_t)(value)) & 0x0000FFFFU)
53
54 #define REG_PWM0SUBCTL (250U)
55
56 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
57 typedef enum _clock_ip_name
58 {
59 kCLOCK_GateINPUTMUX0 = (0x00000U | (0U)), /*!< Clock gate name: INPUTMUX0 */
60 kCLOCK_InputMux = (0x00000U | (0U)), /*!< Clock gate name: INPUTMUX0 */
61 kCLOCK_GateI3C0 = (0x00000U | (1U)), /*!< Clock gate name: I3C0 */
62 kCLOCK_GateCTIMER0 = (0x00000U | (2U)), /*!< Clock gate name: CTIMER0 */
63 kCLOCK_GateCTIMER1 = (0x00000U | (3U)), /*!< Clock gate name: CTIMER1 */
64 kCLOCK_GateCTIMER2 = (0x00000U | (4U)), /*!< Clock gate name: CTIMER2 */
65 kCLOCK_GateFREQME = (0x00000U | (5U)), /*!< Clock gate name: FREQME */
66 kCLOCK_GateUTICK0 = (0x00000U | (6U)), /*!< Clock gate name: UTICK0 */
67 kCLOCK_GateWWDT0 = (0x00000U | (7U)), /*!< Clock gate name: WWDT0 */
68 kCLOCK_GateDMA = (0x00000U | (8U)), /*!< Clock gate name: DMA */
69 kCLOCK_GateAOI0 = (0x00000U | (9U)), /*!< Clock gate name: AOI0 */
70 kCLOCK_GateCRC = (0x00000U | (10U)), /*!< Clock gate name: CRC */
71 kCLOCK_Crc0 = (0x00000U | (10U)), /*!< Clock gate name: CRC */
72 kCLOCK_GateEIM = (0x00000U | (11U)), /*!< Clock gate name: EIM */
73 kCLOCK_GateERM = (0x00000U | (12U)), /*!< Clock gate name: ERM */
74 kCLOCK_GateLPI2C0 = (0x00000U | (16U)), /*!< Clock gate name: LPI2C0 */
75 kCLOCK_GateLPSPI0 = (0x00000U | (17U)), /*!< Clock gate name: LPSPI0 */
76 kCLOCK_GateLPSPI1 = (0x00000U | (18U)), /*!< Clock gate name: LPSPI1 */
77 kCLOCK_GateLPUART0 = (0x00000U | (19U)), /*!< Clock gate name: LPUART0 */
78 kCLOCK_GateLPUART1 = (0x00000U | (20U)), /*!< Clock gate name: LPUART1 */
79 kCLOCK_GateLPUART2 = (0x00000U | (21U)), /*!< Clock gate name: LPUART2 */
80 kCLOCK_GateUSB0 = (0x00000U | (22U)), /*!< Clock gate name: USB0 */
81 kCLOCK_GateQDC0 = (0x00000U | (23U)), /*!< Clock gate name: QDC0 */
82 kCLOCK_GateFLEXPWM0 = (0x00000U | (24U)), /*!< Clock gate name: FLEXPWM0 */
83 kCLOCK_GateOSTIMER0 = (0x00000U | (25U)), /*!< Clock gate name: OSTIMER0 */
84 kCLOCK_GateADC0 = (0x00000U | (26U)), /*!< Clock gate name: ADC0 */
85 kCLOCK_GateCMP0 = (0x00000U | (27U)), /*!< Clock gate name: CMP0 */
86 kCLOCK_GateCMP1 = (0x00000U | (28U)), /*!< Clock gate name: CMP1 */
87 kCLOCK_GatePORT0 = (0x00000U | (29U)), /*!< Clock gate name: PORT0 */
88 kCLOCK_GatePORT1 = (0x00000U | (30U)), /*!< Clock gate name: PORT1 */
89 kCLOCK_GatePORT2 = (0x00000U | (31U)), /*!< Clock gate name: PORT2 */
90 kCLOCK_GatePORT3 = ((0x10U << 16U) | (0U)), /*!< Clock gate name: PORT3 */
91 kCLOCK_GateATX0 = ((0x10U << 16U) | (1U)), /*!< Clock gate name: ATX0 */
92 kCLOCK_GateMTR = ((0x10U << 16U) | (2U)), /*!< Clock gate name: MTR */
93 kCLOCK_GateTCU = ((0x10U << 16U) | (3U)), /*!< Clock gate name: TCU */
94 kCLOCK_GateEZRAMC_RAMA = ((0x10U << 16U) | (4U)), /*!< Clock gate name: EZRAMC_RAMA */
95 kCLOCK_GateGPIO0 = ((0x10U << 16U) | (5U)), /*!< Clock gate name: GPIO0 */
96 kCLOCK_GateGPIO1 = ((0x10U << 16U) | (6U)), /*!< Clock gate name: GPIO1 */
97 kCLOCK_GateGPIO2 = ((0x10U << 16U) | (7U)), /*!< Clock gate name: GPIO2 */
98 kCLOCK_GateGPIO3 = ((0x10U << 16U) | (8U)), /*!< Clock gate name: GPIO3 */
99 kCLOCK_GateROMCP = ((0x10U << 16U) | (9U)), /*!< Clock gate name: ROMCP */
100 kCLOCK_GatePWMSM0 = ((REG_PWM0SUBCTL << 16U) | (0U)), /*!< Clock gate name: FlexPWM SM0 */
101 kCLOCK_GatePWMSM1 = ((REG_PWM0SUBCTL << 16U) | (1U)), /*!< Clock gate name: FlexPWM SM1 */
102 kCLOCK_GatePWMSM2 = ((REG_PWM0SUBCTL << 16U) | (2U)), /*!< Clock gate name: FlexPWM SM2 */
103 kCLOCK_GateNotAvail = (0xFFFFFFFFU), /**< Clock gate name: None */
104 } clock_ip_name_t;
105
106 /*! @brief Clock ip name array for AOI. */
107 #define AOI_CLOCKS \
108 { \
109 kCLOCK_GateAOI0 \
110 }
111 /*! @brief Clock ip name array for CRC. */
112 #define CRC_CLOCKS \
113 { \
114 kCLOCK_GateCRC \
115 }
116 /*! @brief Clock ip name array for CTIMER. */
117 #define CTIMER_CLOCKS \
118 { \
119 kCLOCK_GateCTIMER0, kCLOCK_GateCTIMER1, kCLOCK_GateCTIMER2 \
120 }
121 /*! @brief Clock ip name array for DMA. */
122 #define DMA_CLOCKS \
123 { \
124 kCLOCK_GateDMA \
125 }
126 /*! @brief Clock gate name array for EDMA. */
127 #define EDMA_CLOCKS \
128 { \
129 kCLOCK_GateDMA \
130 }
131 /*! @brief Clock ip name array for ERM. */
132 #define ERM_CLOCKS \
133 { \
134 kCLOCK_GateERM \
135 }
136 /*! @brief Clock ip name array for EIM. */
137 #define EIM_CLOCKS \
138 { \
139 kCLOCK_GateEIM \
140 }
141 /*! @brief Clock ip name array for FREQME. */
142 #define FREQME_CLOCKS \
143 { \
144 kCLOCK_GateFREQME \
145 }
146 /*! @brief Clock ip name array for GPIO. */
147 #define GPIO_CLOCKS \
148 { \
149 kCLOCK_GateGPIO0, kCLOCK_GateGPIO1, kCLOCK_GateGPIO2, kCLOCK_GateGPIO3 \
150 }
151 /*! @brief Clock ip name array for I3C */
152 #define I3C_CLOCKS \
153 { \
154 kCLOCK_GateI3C0 \
155 }
156 /*! @brief Clock ip name array for INPUTMUX. */
157 #define INPUTMUX_CLOCKS \
158 { \
159 kCLOCK_GateINPUTMUX0 \
160 }
161 /*! @brief Clock ip name array for GPIO. */
162 #define LPCMP_CLOCKS \
163 { \
164 kCLOCK_GateCMP0, kCLOCK_GateCMP1 \
165 }
166 /*! @brief Clock ip name array for LPADC. */
167 #define LPADC_CLOCKS \
168 { \
169 kCLOCK_GateADC0 \
170 }
171 /*! @brief Clock ip name array for LPUART. */
172 #define LPUART_CLOCKS \
173 { \
174 kCLOCK_GateLPUART0, kCLOCK_GateLPUART1, kCLOCK_GateLPUART2 \
175 }
176 /*! @brief Clock ip name array for LPI2C. */
177 #define LPI2C_CLOCKS \
178 { \
179 kCLOCK_GateLPI2C0 \
180 }
181 /*! @brief Clock ip name array for LSPI. */
182 #define LPSPI_CLOCKS \
183 { \
184 kCLOCK_GateLPSPI0, kCLOCK_GateLPSPI1 \
185 }
186 /*! @brief Clock ip name array for MTR. */
187 #define MTR_CLOCKS \
188 { \
189 kCLOCK_GateMTR \
190 }
191 /*! @brief Clock ip name array for OSTIMER. */
192 #define OSTIMER_CLOCKS \
193 { \
194 kCLOCK_GateOSTIMER0 \
195 }
196
197 /*! @brief Clock ip name array for PWM. */
198 #define PWM_CLOCKS \
199 { \
200 { \
201 kCLOCK_GatePWMSM0, kCLOCK_GatePWMSM1, kCLOCK_GatePWMSM2 \
202 } \
203 }
204 /*! @brief Clock ip name array for QDC. */
205 #define QDC_CLOCKS \
206 { \
207 kCLOCK_GateQDC0 \
208 }
209 /*! @brief Clock ip name array for UTICK. */
210 #define UTICK_CLOCKS \
211 { \
212 kCLOCK_GateUTICK0 \
213 }
214 /*! @brief Clock ip name array for WWDT. */
215 #define WWDT_CLOCKS \
216 { \
217 kCLOCK_GateWWDT0 \
218 }
219
220 /*! @brief Peripherals clock source definition. */
221 #define BUS_CLK kCLOCK_BusClk
222
223 /*! @brief Clock name used to get clock frequency. */
224 typedef enum _clock_name
225 {
226 kCLOCK_MainClk, /*!< MAIN_CLK */
227 kCLOCK_CoreSysClk, /*!< Core/system clock(CPU_CLK) */
228 kCLOCK_SYSTEM_CLK, /*!< AHB clock */
229 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
230 kCLOCK_ExtClk, /*!< External Clock */
231 kCLOCK_FroHf, /*!< FRO192 */
232 kCLOCK_FroHfDiv, /*!< Divided by FRO192 */
233 kCLOCK_Clk48M, /*!< CLK48M */
234 kCLOCK_Fro12M, /*!< FRO12M */
235 kCLOCK_Clk1M, /*!< CLK1M */
236 kCLOCK_Fro16K, /*!< FRO16K */
237 kCLOCK_Clk16K0, /*!< CLK16K[0] */
238 kCLOCK_Clk16K1, /*!< CLK16K[1] */
239 kCLOCK_SLOW_CLK, /*!< SYSTEM_CLK divided by 4 */
240 } clock_name_t;
241
242 /*! @brief Clock Mux Switches
243 * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable
244 * starting from LSB upwards
245 *
246 * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*
247 *
248 */
249
250 #define CLK_ATTACH_REG_OFFSET(value) (((uint32_t)(value)) >> 16U)
251 #define CLK_ATTACH_CLK_SEL(value) (((uint32_t)(value)) & 0x0000FFFFU)
252 #define CLK_ATTACH_MUX(reg, sel) ((((uint32_t)(reg)) << 16U) | (sel))
253
254 /*! @brief Clock name used to get clock frequency. */
255 typedef enum _clock_select_name
256 {
257 kCLOCK_SelI3C0_FCLK = (0x0A0U), /*!< I3C0_FCLK clock selection */
258 kCLOCK_SelCTIMER0 = (0x0A8U), /*!< CTIMER0 clock selection */
259 kCLOCK_SelCTIMER1 = (0x0B0U), /*!< CTIMER1 clock selection */
260 kCLOCK_SelCTIMER2 = (0x0B8U), /*!< CTIMER2 clock selection */
261 kCLOCK_SelLPI2C0 = (0x0C8U), /*!< LPI2C0 clock selection */
262 kCLOCK_SelLPSPI0 = (0x0D0U), /*!< LPSPI0 clock selection */
263 kCLOCK_SelLPSPI1 = (0x0D8U), /*!< LPSPI1 clock selection */
264 kCLOCK_SelLPUART0 = (0x0E0U), /*!< LPUART0 clock selection */
265 kCLOCK_SelLPUART1 = (0x0E8U), /*!< LPUART1 clock selection */
266 kCLOCK_SelLPUART2 = (0x0F0U), /*!< LPUART2 clock selection */
267 kCLOCK_SelUSB0 = (0x0F8U), /*!< USB0 clock selection */
268 kCLOCK_SelLPTMR0 = (0x100U), /*!< LPTMR0 clock selection */
269 kCLOCK_SelOSTIMER0 = (0x108U), /*!< OSTIMER0 clock selection */
270 kCLOCK_SelADC0 = (0x110U), /*!< ADC0 clock selection */
271 kCLOCK_SelCMP0_RR = (0x120U), /*!< CMP0_RR clock selection */
272 kCLOCK_SelCMP1_RR = (0x130U), /*!< CMP1_RR clock selection */
273 kCLOCK_SelTRACE = (0x138U), /*!< TRACE clock selection */
274 kCLOCK_SelCLKOUT = (0x140U), /*!< CLKOUT clock selection */
275 kCLOCK_SelSYSTICK = (0x148U), /*!< SYSTICK clock selection */
276 kCLOCK_SelSCGSCS = (0x200U), /*!< SCG SCS clock selection */
277 kCLOCK_SelMax = (0x200U), /*!< MAX clock selection */
278 } clock_select_name_t;
279
280 /*!
281 * @brief The enumerator of clock attach Id.
282 */
283 typedef enum _clock_attach_id
284 {
285 kCLK_IN_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 1U), /*!< Attach clk_in to MAIN_CLK. */
286 kFRO12M_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 2U), /*!< Attach FRO_12M to MAIN_CLK. */
287 kFRO_HF_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 3U), /*!< Attach FRO_HF to MAIN_CLK. */
288 kCLK_16K_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 4U), /*!< Attach CLK_16K[1] to MAIN_CLK. */
289 kNONE_to_MAIN_CLK = CLK_ATTACH_MUX(kCLOCK_SelSCGSCS, 7U), /*!< Attach NONE to MAIN_CLK. */
290
291 kFRO12M_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 0U), /*!< Attach FRO12M to I3C0FCLK. */
292 kFRO_HF_DIV_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 2U), /*!< Attach FRO_HF_DIV to I3C0FCLK. */
293 kCLK_IN_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 3U), /*!< Attach CLK_IN to I3C0FCLK. */
294 kCLK_1M_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 5U), /*!< Attach CLK_1M to I3C0FCLK. */
295 kNONE_to_I3C0FCLK = CLK_ATTACH_MUX(kCLOCK_SelI3C0_FCLK, 7U), /*!< Attach NONE to I3C0FCLK. */
296
297 kFRO12M_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 0U), /*!< Attach FRO12M to CTIMER0. */
298 kFRO_HF_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 1U), /*!< Attach FRO_HF to CTIMER0. */
299 kCLK_IN_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 3U), /*!< Attach CLK_IN to CTIMER0. */
300 kCLK_16K_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 4U), /*!< Attach CLK_16K to CTIMER0. */
301 kCLK_1M_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 5U), /*!< Attach CLK_1M to CTIMER0. */
302 kNONE_to_CTIMER0 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER0, 7U), /*!< Attach NONE to CTIMER0. */
303
304 kFRO12M_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 0U), /*!< Attach FRO12M to CTIMER1. */
305 kFRO_HF_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 1U), /*!< Attach FRO_HF to CTIMER1. */
306 kCLK_IN_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 3U), /*!< Attach CLK_IN to CTIMER1. */
307 kCLK_16K_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 4U), /*!< Attach CLK_16K to CTIMER1. */
308 kCLK_1M_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 5U), /*!< Attach CLK_1M to CTIMER1. */
309 kNONE_to_CTIMER1 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER1, 7U), /*!< Attach NONE to CTIMER1. */
310
311 kFRO12M_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 0U), /*!< Attach FRO12M to CTIMER2. */
312 kFRO_HF_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 1U), /*!< Attach FRO_HF to CTIMER2. */
313 kCLK_IN_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 3U), /*!< Attach CLK_IN to CTIMER2. */
314 kCLK_16K_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 4U), /*!< Attach CLK_16K to CTIMER2. */
315 kCLK_1M_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 5U), /*!< Attach CLK_1M to CTIMER2. */
316 kNONE_to_CTIMER2 = CLK_ATTACH_MUX(kCLOCK_SelCTIMER2, 7U), /*!< Attach NONE to CTIMER2. */
317
318 kFRO12M_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 0U), /*!< Attach FRO12M to LPI2C0. */
319 kFRO_HF_DIV_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 2U), /*!< Attach FRO_HF_DIV to LPI2C0. */
320 kCLK_IN_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 3U), /*!< Attach CLK_IN to LPI2C0. */
321 kCLK_1M_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 5U), /*!< Attach CLK_1M to LPI2C0. */
322 kNONE_to_LPI2C0 = CLK_ATTACH_MUX(kCLOCK_SelLPI2C0, 7U), /*!< Attach NONE to LPI2C0. */
323
324 kFRO12M_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 0U), /*!< Attach FRO12M to LPSPI0. */
325 kFRO_HF_DIV_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 2U), /*!< Attach FRO_HF_DIV to LPSPI0. */
326 kCLK_IN_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 3U), /*!< Attach CLK_IN to LPSPI0. */
327 kCLK_1M_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 5U), /*!< Attach CLK_1M to LPSPI0. */
328 kNONE_to_LPSPI0 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI0, 7U), /*!< Attach NONE to LPSPI0. */
329
330 kFRO12M_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 0U), /*!< Attach FRO12M to LPSPI1. */
331 kFRO_HF_DIV_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 2U), /*!< Attach FRO_HF_DIV to LPSPI1. */
332 kCLK_IN_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 3U), /*!< Attach CLK_IN to LPSPI1. */
333 kCLK_1M_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 5U), /*!< Attach CLK_1M to LPSPI1. */
334 kNONE_to_LPSPI1 = CLK_ATTACH_MUX(kCLOCK_SelLPSPI1, 7U), /*!< Attach NONE to LPSPI1. */
335
336 kFRO12M_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 0U), /*!< Attach FRO12M to LPUART0. */
337 kFRO_HF_DIV_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 2U), /*!< Attach FRO_HF_DIV to LPUART0. */
338 kCLK_IN_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 3U), /*!< Attach CLK_IN to LPUART0. */
339 kCLK_16K_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 4U), /*!< Attach CLK_16K to LPUART0. */
340 kCLK_1M_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 5U), /*!< Attach CLK_1M to LPUART0. */
341 kNONE_to_LPUART0 = CLK_ATTACH_MUX(kCLOCK_SelLPUART0, 7U), /*!< Attach NONE to LPUART0. */
342
343 kFRO12M_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 0U), /*!< Attach FRO12M to LPUART1. */
344 kFRO_HF_DIV_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 2U), /*!< Attach FRO_HF_DIV to LPUART1. */
345 kCLK_IN_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 3U), /*!< Attach CLK_IN to LPUART1. */
346 kCLK_16K_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 4U), /*!< Attach CLK_16K to LPUART1. */
347 kCLK_1M_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 5U), /*!< Attach CLK_1M to LPUART1. */
348 kNONE_to_LPUART1 = CLK_ATTACH_MUX(kCLOCK_SelLPUART1, 7U), /*!< Attach NONE to LPUART1. */
349
350 kFRO12M_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 0U), /*!< Attach FRO12M to LPUART2. */
351 kFRO_HF_DIV_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 2U), /*!< Attach FRO_HF_DIV to LPUART2. */
352 kCLK_IN_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 3U), /*!< Attach CLK_IN to LPUART2. */
353 kCLK_16K_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 4U), /*!< Attach CLK_16K to LPUART2. */
354 kCLK_1M_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 5U), /*!< Attach CLK_1M to LPUART2. */
355 kNONE_to_LPUART2 = CLK_ATTACH_MUX(kCLOCK_SelLPUART2, 7U), /*!< Attach NONE to LPUART2. */
356
357 kCLK_48M_to_USB0 = CLK_ATTACH_MUX(kCLOCK_SelUSB0, 1U), /*!< Attach FRO12M to USB0. */
358 kCLK_IN_to_USB0 = CLK_ATTACH_MUX(kCLOCK_SelUSB0, 2U), /*!< Attach CLK_IN to USB0. */
359 kNONE_to_USB0 = CLK_ATTACH_MUX(kCLOCK_SelUSB0, 3U), /*!< Attach NONE to USB0. */
360
361 kFRO12M_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 0U), /*!< Attach FRO12M to LPTMR0. */
362 kFRO_HF_DIV_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 2U), /*!< Attach FRO_HF_DIV to LPTMR0. */
363 kCLK_IN_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 3U), /*!< Attach CLK_IN to LPTMR0. */
364 kCLK_1M_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 5U), /*!< Attach CLK_1M to LPTMR0. */
365 kNONE_to_LPTMR0 = CLK_ATTACH_MUX(kCLOCK_SelLPTMR0, 7U), /*!< Attach NONE to LPTMR0. */
366
367 kCLK_16K_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 0U), /*!< Attach FRO16K to OSTIMER0. */
368 kCLK_1M_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 2U), /*!< Attach CLK_1M to OSTIMER0. */
369 kNONE_to_OSTIMER = CLK_ATTACH_MUX(kCLOCK_SelOSTIMER0, 3U), /*!< Attach NONE to OSTIMER0. */
370
371 kFRO12M_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 0U), /*!< Attach FRO12M to ADC0. */
372 kFRO_HF_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 1U), /*!< Attach FRO_HF to ADC0. */
373 kCLK_IN_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 3U), /*!< Attach CLK_IN to ADC0. */
374 kCLK_1M_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 5U), /*!< Attach CLK_1M to ADC0. */
375 kNONE_to_ADC0 = CLK_ATTACH_MUX(kCLOCK_SelADC0, 7U), /*!< Attach NONE to ADC0. */
376
377 kFRO12M_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 0U), /*!< Attach FRO12M to CMP0. */
378 kFRO_HF_DIV_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 2U), /*!< Attach FRO_HF_DIV to CMP0. */
379 kCLK_IN_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 3U), /*!< Attach CLK_IN to CMP0. */
380 kCLK_1M_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 5U), /*!< Attach CLK_1M to CMP0. */
381 kNONE_to_CMP0 = CLK_ATTACH_MUX(kCLOCK_SelCMP0_RR, 7U), /*!< Attach NONE to CMP0. */
382
383 kFRO12M_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 0U), /*!< Attach FRO12M to CMP1. */
384 kFRO_HF_DIV_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 2U), /*!< Attach FRO_HF_DIV to CMP1. */
385 kCLK_IN_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 3U), /*!< Attach CLK_IN to CMP1. */
386 kCLK_1M_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 5U), /*!< Attach CLK_1M to CMP1. */
387 kNONE_to_CMP1 = CLK_ATTACH_MUX(kCLOCK_SelCMP1_RR, 7U), /*!< Attach NONE to CMP1. */
388
389 kCPU_CLK_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 0U), /*!< Attach CPU_CLK to TRACE. */
390 kCLK_1M_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 1U), /*!< Attach CLK_1M to TRACE. */
391 kCLK_16K_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 2U), /*!< Attach CLK_16K to TRACE. */
392 kNONE_to_TRACE = CLK_ATTACH_MUX(kCLOCK_SelTRACE, 3U), /*!< Attach NONE to TRACE. */
393
394 kFRO12M_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 0U), /*!< Attach FRO12M to CLKOUT. */
395 kFRO_HF_DIV_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 1U), /*!< Attach FRO_HF_DIV to CLKOUT. */
396 kCLK_IN_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 2U), /*!< Attach CLK_IN to CLKOUT. */
397 kCLK_16K_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 3U), /*!< Attach CLK_16K to CLKOUT. */
398 kSLOW_CLK_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 6U), /*!< Attach SLOW_CLK to CLKOUT. */
399 kNONE_to_CLKOUT = CLK_ATTACH_MUX(kCLOCK_SelCLKOUT, 7U), /*!< Attach NONE to CLKOUT. */
400
401 kCPU_CLK_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 0U), /*!< Attach CPU_CLK to SYSTICK. */
402 kCLK_1M_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 1U), /*!< Attach CLK_1M to SYSTICK. */
403 kCLK_16K_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 2U), /*!< Attach CLK_16K to SYSTICK. */
404 kNONE_to_SYSTICK = CLK_ATTACH_MUX(kCLOCK_SelSYSTICK, 3U), /*!< Attach NONE to SYSTICK. */
405
406 kNONE_to_NONE = (0xFFFFFFFFU), /*!< Attach NONE to NONE. */
407
408 } clock_attach_id_t;
409
410 /*! @brief Clock dividers */
411 typedef enum _clock_div_name
412 {
413 kCLOCK_DivI3C0_FCLK = (0x0A4U), /*!< I3C0_FCLK clock divider */
414 kCLOCK_DivCTIMER0 = (0x0ACU), /*!< CTIMER0 clock divider */
415 kCLOCK_DivCTIMER1 = (0x0B4U), /*!< CTIMER1 clock divider */
416 kCLOCK_DivCTIMER2 = (0x0BCU), /*!< CTIMER2 clock divider */
417 kCLOCK_DivWWDT0 = (0x0C4U), /*!< WWDT0 clock divider */
418 kCLOCK_DivLPI2C0 = (0x0CCU), /*!< LPI2C0 clock divider */
419 kCLOCK_DivLPSPI0 = (0x0D4U), /*!< LPSPI0 clock divider */
420 kCLOCK_DivLPSPI1 = (0x0DCU), /*!< LPSPI1 clock divider */
421 kCLOCK_DivLPUART0 = (0x0E4U), /*!< LPUART0 clock divider */
422 kCLOCK_DivLPUART1 = (0x0ECU), /*!< LPUART1 clock divider */
423 kCLOCK_DivLPUART2 = (0x0F4U), /*!< LPUART2 clock divider */
424 kCLOCK_DivLPTMR0 = (0x104U), /*!< LPTMR0 clock divider */
425 kCLOCK_DivADC0 = (0x114U), /*!< ADC0 clock divider */
426 kCLOCK_DivCMP0_FUNC = (0x11CU), /*!< CMP0_FUNC clock divider */
427 kCLOCK_DivCMP0_RR = (0x124U), /*!< CMP0_RR clock divider */
428 kCLOCK_DivCMP1_FUNC = (0x12CU), /*!< CMP1_FUNC clock divider */
429 kCLOCK_DivCMP1_RR = (0x134U), /*!< CMP1_RR clock divider */
430 kCLOCK_DivTRACE = (0x13CU), /*!< TRACE clock divider */
431 kCLOCK_DivCLKOUT = (0x144U), /*!< CLKOUT clock divider */
432 kCLOCK_DivSYSTICK = (0x14CU), /*!< SYSTICK clock divider */
433 kCLOCK_DivFRO_HF_DIV = (0x154U), /*!< FRO_HF_DIV clock divider */
434 kCLOCK_DivSLOWCLK = (0x378U), /*!< SLOWCLK clock divider */
435 kCLOCK_DivAHBCLK = (0x380U), /*!< System clock divider */
436 kCLOCK_DivMax = (0x380U), /*!< MAX clock divider */
437 } clock_div_name_t;
438
439 /*!
440 * @brief firc trim mode.
441 */
442 typedef enum _firc_trim_mode
443 {
444 kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK,
445 /*!< Trim enable but not enable trim value update. In this mode, the
446 trim value is fixed to the initialized value which is defined by
447 trimCoar and trimFine in configure structure \ref firc_trim_config_t.*/
448
449 kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK | SCG_FIRCCSR_FIRCTRUP_MASK
450 /*!< Trim enable and trim value update enable. In this mode, the trim
451 value is auto update. */
452
453 } firc_trim_mode_t;
454
455 /*!
456 * @brief firc trim source.
457 */
458 typedef enum _firc_trim_src
459 {
460 kSCG_FircTrimSrcUsb0 = 0U, /*!< USB0 start of frame (1kHz). */
461 kSCG_FircTrimSrcSysOsc = 2U, /*!< System OSC. */
462 } firc_trim_src_t;
463
464 /*!
465 * @brief firc trim configuration.
466 */
467 typedef struct _firc_trim_config
468 {
469 firc_trim_mode_t trimMode; /*!< Trim mode. */
470 firc_trim_src_t trimSrc; /*!< Trim source. */
471 uint16_t trimDiv; /*!< Divider of SOSC. */
472 uint8_t trimCoar; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */
473 uint8_t trimFine; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */
474 } firc_trim_config_t;
475
476 /*!
477 * @brief sirc trim mode.
478 */
479 typedef enum _sirc_trim_mode
480 {
481 kSCG_SircTrimNonUpdate = SCG_SIRCCSR_SIRCTREN_MASK,
482 /*!< Trim enable but not enable trim value update. In this mode, the
483 trim value is fixed to the initialized value which is defined by
484 trimCoar and trimFine in configure structure \ref sirc_trim_config_t.*/
485
486 kSCG_SircTrimUpdate = SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK
487 /*!< Trim enable and trim value update enable. In this mode, the trim
488 value is auto update. */
489
490 } sirc_trim_mode_t;
491
492 /*!
493 * @brief sirc trim source.
494 */
495 typedef enum _sirc_trim_src
496 {
497 kNoTrimSrc = 0, /*!< No external tirm source. */
498 kSCG_SircTrimSrcSysOsc = 2U, /*!< System OSC. */
499 } sirc_trim_src_t;
500
501 /*!
502 * @brief sirc trim configuration.
503 */
504 typedef struct _sirc_trim_config
505 {
506 sirc_trim_mode_t trimMode; /*!< Trim mode. */
507 sirc_trim_src_t trimSrc; /*!< Trim source. */
508 uint16_t trimDiv; /*!< Divider of SOSC. */
509 uint8_t cltrim; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */
510 uint8_t ccotrim; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */
511 } sirc_trim_config_t;
512
513 /*!
514 * @brief SCG system OSC monitor mode.
515 */
516 typedef enum _scg_sosc_monitor_mode
517 {
518 kSCG_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */
519 kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the SOSC error is detected. */
520 kSCG_SysOscMonitorReset =
521 SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the SOSC error is detected. */
522 } scg_sosc_monitor_mode_t;
523
524 /*!
525 * @brief firc trim source.
526 */
527 typedef enum _clke_16k
528 {
529 kCLKE_16K_SYSTEM = VBAT_FROCLKE_CLKE(1U), /*!< To VSYS domain. */
530 kCLKE_16K_COREMAIN = VBAT_FROCLKE_CLKE(2U) /*!< To VDD_CORE domain. */
531 } clke_16k_t;
532
533 /*******************************************************************************
534 * API
535 ******************************************************************************/
536
537 #if defined(__cplusplus)
538 extern "C" {
539 #endif /* __cplusplus */
540
541 /**
542 * @brief Enable the clock for specific IP.
543 * @param clk : Clock to be enabled.
544 * @return Nothing
545 */
CLOCK_EnableClock(clock_ip_name_t clk)546 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
547 {
548 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk);
549 uint32_t bit_shift = CLK_GATE_BIT_SHIFT(clk);
550 volatile uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_SET)) + reg_offset);
551
552 if (clk == kCLOCK_GateNotAvail)
553 {
554 return;
555 }
556
557 /* Unlock clock configuration */
558 SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
559
560 if (reg_offset == REG_PWM0SUBCTL)
561 {
562 SYSCON->PWM0SUBCTL |= (1UL << bit_shift);
563 MRCC0->MRCC_GLB_CC0_SET = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK;
564 }
565 else
566 {
567 *pClkCtrl = (1UL << bit_shift);
568 }
569
570 /* Freeze clock configuration */
571 SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
572 }
573
574 /**
575 * @brief Disable the clock for specific IP.
576 * @param clk : Clock to be Disabled.
577 * @return Nothing
578 */
CLOCK_DisableClock(clock_ip_name_t clk)579 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
580 {
581 uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk);
582 uint32_t bit_shift = CLK_GATE_BIT_SHIFT(clk);
583 volatile uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset);
584
585 if (clk == kCLOCK_GateNotAvail)
586 {
587 return;
588 }
589
590 /* Unlock clock configuration */
591 SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
592
593 if (reg_offset == REG_PWM0SUBCTL)
594 {
595 SYSCON->PWM0SUBCTL &= ~(1UL << bit_shift);
596
597 if (0U == (SYSCON->PWM0SUBCTL & 0xFU))
598 {
599 MRCC0->MRCC_GLB_CC0_CLR = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK;
600 }
601 }
602 else
603 {
604 *pClkCtrl = (1UL << bit_shift);
605 }
606
607 /* Freeze clock configuration */
608 SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
609 }
610
611 /**
612 * @brief Configure the clock selection muxes.
613 * @param connection : Clock to be configured.
614 * @return Nothing
615 */
616 void CLOCK_AttachClk(clock_attach_id_t connection);
617
618 /**
619 * @brief Get the actual clock attach id.
620 * This fuction uses the offset in input attach id, then it reads the actual source value in
621 * the register and combine the offset to obtain an actual attach id.
622 * @param connection : Clock attach id to get.
623 * @return Clock source value.
624 */
625 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection);
626
627 /**
628 * @brief Set the clock select value.
629 * This fuction set the peripheral clock select value.
630 * @param sel_name : Clock select.
631 * @param value : value to be set.
632 */
633 void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value);
634
635 /**
636 * @brief Get the clock select value.
637 * This fuction get the peripheral clock select value.
638 * @param sel_name : Clock select.
639 * @return Clock source value.
640 */
641 uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name);
642
643 /**
644 * @brief Setup peripheral clock dividers.
645 * @param div_name : Clock divider name
646 * @param value : Value to be divided
647 * @return Nothing
648 */
649 void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value);
650
651 /**
652 * @brief Get peripheral clock dividers.
653 * @param div_name : Clock divider name
654 * @return peripheral clock dividers
655 */
656 uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name);
657
658 /**
659 * @brief Halt peripheral clock dividers.
660 * @param div_name : Clock divider name
661 * @return Nothing
662 */
663 void CLOCK_HaltClockDiv(clock_div_name_t div_name);
664
665 /**
666 * @brief Initialize the FROHF to given frequency (48,64,96,192).
667 * This function turns on FIRC and select the given frequency as the source of fro_hf
668 * @param iFreq : Desired frequency.
669 * @return returns success or fail status.
670 */
671 status_t CLOCK_SetupFROHFClocking(uint32_t iFreq);
672
673 /**
674 * @brief Initialize the FRO12M.
675 * This function turns on FRO12M.
676 * @return returns success or fail status.
677 */
678 status_t CLOCK_SetupFRO12MClocking(void);
679
680 /**
681 * @brief Initialize the FRO16K.
682 * This function turns on FRO16K.
683 * @param clk_16k_enable_mask: 0-3
684 * 0b00: disable both clk_16k0 and clk_16k1
685 * 0b01: only enable clk_16k0
686 * 0b10: only enable clk_16k1
687 * 0b11: enable both clk_16k0 and clk_16k1
688 * @return returns success or fail status.
689 */
690 status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask);
691
692 /**
693 * @brief Initialize the external osc clock to given frequency.
694 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
695 * @return returns success or fail status.
696 */
697 status_t CLOCK_SetupExtClocking(uint32_t iFreq);
698
699 /**
700 * @brief Initialize the external reference clock to given frequency.
701 * @param iFreq : Desired frequency (must be equal to exact rate in Hz)
702 * @return returns success or fail status.
703 */
704 status_t CLOCK_SetupExtRefClocking(uint32_t iFreq);
705
706 /*! @brief Return Frequency of selected clock
707 * @return Frequency of selected clock
708 */
709 uint32_t CLOCK_GetFreq(clock_name_t clockName);
710
711 /*! @brief Return Frequency of core
712 * @return Frequency of the core
713 */
714 uint32_t CLOCK_GetCoreSysClkFreq(void);
715
716 /*! @brief Return Frequency of I3C FCLK
717 * @return Frequency of I3C FCLK.
718 */
719 uint32_t CLOCK_GetI3CFClkFreq(void);
720
721 /*! @brief Return Frequency of CTimer functional Clock
722 * @return Frequency of CTimer functional Clock
723 */
724 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);
725
726 /*! @brief Return Frequency of LPI2C0 functional Clock
727 * @return Frequency of LPI2C0 functional Clock
728 */
729 uint32_t CLOCK_GetLpi2cClkFreq(void);
730
731 /*! @brief Return Frequency of LPSPI functional Clock
732 * @return Frequency of LPSPI functional Clock
733 */
734 uint32_t CLOCK_GetLpspiClkFreq(uint32_t id);
735
736 /*! @brief Return Frequency of LPUART functional Clock
737 * @return Frequency of LPUART functional Clock
738 */
739 uint32_t CLOCK_GetLpuartClkFreq(uint32_t id);
740
741 /*! @brief Return Frequency of LPTMR functional Clock
742 * @return Frequency of LPTMR functional Clock
743 */
744 uint32_t CLOCK_GetLptmrClkFreq(void);
745
746 /*! @brief Return Frequency of OSTIMER
747 * @return Frequency of OSTIMER Clock
748 */
749 uint32_t CLOCK_GetOstimerClkFreq(void);
750
751 /*! @brief Return Frequency of Adc Clock
752 * @return Frequency of Adc.
753 */
754 uint32_t CLOCK_GetAdcClkFreq(void);
755
756 /*! @brief Return Frequency of CMP Function Clock
757 * @return Frequency of CMP Function.
758 */
759 uint32_t CLOCK_GetCmpFClkFreq(uint32_t id);
760
761 /*! @brief Return Frequency of CMP Round Robin Clock
762 * @return Frequency of CMP Round Robin.
763 */
764 uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id);
765
766 /*! @brief Return Frequency of Trace Clock
767 * @return Frequency of Trace.
768 */
769 uint32_t CLOCK_GetTraceClkFreq(void);
770
771 /*! @brief Return Frequency of CLKOUT Clock
772 * @return Frequency of CLKOUT.
773 */
774 uint32_t CLOCK_GetClkoutClkFreq(void);
775
776 /*! @brief Return Frequency of Systick Clock
777 * @return Frequency of Systick.
778 */
779 uint32_t CLOCK_GetSystickClkFreq(void);
780
781 /*! brief Return Frequency of Systick Clock
782 * return Frequency of Systick.
783 */
784 uint32_t CLOCK_GetWwdtClkFreq(void);
785
786 /**
787 * @brief Setup FROHF trim.
788 * @param config : FROHF trim value
789 * @return returns success or fail status.
790 */
791 status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config);
792
793 /**
794 * @brief Setup FRO 12M trim.
795 * @param config : FRO 12M trim value
796 * @return returns success or fail status.
797 */
798 status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config);
799
800 /*!
801 * @brief Sets the system OSC monitor mode.
802 *
803 * This function sets the system OSC monitor mode. The mode can be disabled,
804 * it can generate an interrupt when the error is disabled, or reset when the error is detected.
805 *
806 * @param mode Monitor mode to set.
807 */
808 void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode);
809
810 /*! brief Enable USB FS clock.
811 * Enable USB Full Speed clock.
812 */
813 bool CLOCK_EnableUsbfsClock(void);
814
815 #if defined(__cplusplus)
816 }
817 #endif /* __cplusplus */
818
819 /*! @} */
820
821 #endif /* _FSL_CLOCK_H_ */
822
