1 /*
2 * Copyright 2023, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_clock.h"
9 /*******************************************************************************
10 * Definitions
11 ******************************************************************************/
12 /* Component ID definition, used by tools. */
13 #ifndef FSL_COMPONENT_ID
14 #define FSL_COMPONENT_ID "platform.drivers.clock"
15 #endif
16
17 /*******************************************************************************
18 * Variables
19 ******************************************************************************/
20 /** External clock rate on the CLKIN pin in Hz. If not used,
21 set this to 0. Otherwise, set it to the exact rate in Hz this pin is
22 being driven at. */
23 volatile static uint32_t s_Ext_Clk_Freq = 16000000U;
24
25 /*******************************************************************************
26 * Prototypes
27 ******************************************************************************/
28 /* Get FRO 12M Clk */
29 static uint32_t CLOCK_GetFro12MFreq(void);
30 /* Get CLK 1M Clk */
31 static uint32_t CLOCK_GetClk1MFreq(void);
32 /* Get HF FRO Clk */
33 static uint32_t CLOCK_GetFroHfFreq(void);
34 /* Get CLK 48M Clk */
35 static uint32_t CLOCK_GetClk48MFreq(void);
36 /* Get CLK 16K Clk */
37 static uint32_t CLOCK_GetClk16KFreq(uint8_t id);
38 /* Get EXT OSC Clk */
39 static uint32_t CLOCK_GetExtClkFreq(void);
40 /* Get Main_Clk */
41 uint32_t CLOCK_GetMainClk(void);
42 /* Get FRO_16K */
43 static uint32_t CLOCK_GetFRO16KFreq(void);
44
45 /* Check if DIV is halt */
CLOCK_IsDivHalt(uint32_t div_value)46 static inline bool CLOCK_IsDivHalt(uint32_t div_value)
47 {
48 if (0U != (div_value & (1UL << 30U)))
49 {
50 return true;
51 }
52 else
53 {
54 return false;
55 }
56 }
57
58 /*******************************************************************************
59 * Code
60 ******************************************************************************/
61
62 /* Clock Selection for IP */
63 /**
64 * brief Configure the clock selection muxes.
65 * param connection : Clock to be configured.
66 * return Nothing
67 */
CLOCK_AttachClk(clock_attach_id_t connection)68 void CLOCK_AttachClk(clock_attach_id_t connection)
69 {
70 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection);
71 const uint32_t clk_sel = CLK_ATTACH_CLK_SEL(connection);
72
73 if (kNONE_to_NONE != connection)
74 {
75 CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel);
76 }
77 }
78
79 /* Return the actual clock attach id */
80 /**
81 * brief Get the actual clock attach id.
82 * This fuction uses the offset in input attach id, then it reads the actual source value in
83 * the register and combine the offset to obtain an actual attach id.
84 * param connection : Clock attach id to get.
85 * return Clock source value.
86 */
CLOCK_GetClockAttachId(clock_attach_id_t connection)87 clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection)
88 {
89 const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection);
90 uint32_t actual_sel = 0U;
91 uint32_t clock_attach_id = 0U;
92
93 if (kNONE_to_NONE == connection)
94 {
95 return kNONE_to_NONE;
96 }
97
98 actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset);
99 clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel);
100
101 return (clock_attach_id_t)clock_attach_id;
102 }
103
104 /* Set the clock selection value */
CLOCK_SetClockSelect(clock_select_name_t sel_name,uint32_t value)105 void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value)
106 {
107 volatile uint32_t *pClkCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)sel_name);
108 assert(sel_name <= kCLOCK_SelMax);
109
110 if (sel_name == kCLOCK_SelSCGSCS)
111 {
112 SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value);
113 while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value))
114 {
115 }
116 }
117 else
118 {
119 /* Unlock clock configuration */
120 SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
121
122 *pClkCtrl = value;
123
124 /* Freeze clock configuration */
125 SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
126 }
127 }
128
129 /* Get the clock selection value */
CLOCK_GetClockSelect(clock_select_name_t sel_name)130 uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name)
131 {
132 volatile uint32_t *pClkCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)sel_name);
133 uint32_t actual_sel = 0U;
134 assert(sel_name <= kCLOCK_SelMax);
135
136 if (sel_name == kCLOCK_SelSCGSCS)
137 {
138 actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT);
139 }
140 else
141 {
142 actual_sel = *pClkCtrl;
143 }
144
145 return actual_sel;
146 }
147
148 /* Set the clock divider value */
CLOCK_SetClockDiv(clock_div_name_t div_name,uint32_t value)149 void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value)
150 {
151 volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name);
152 assert(div_name <= kCLOCK_DivMax);
153
154 /* Unlock clock configuration */
155 SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
156
157 /* halt and reset clock dividers */
158 *pDivCtrl = 0x3UL << 29U;
159
160 if (value == 0U) /*!< halt */
161 {
162 *pDivCtrl |= (1UL << 30U);
163 }
164 else
165 {
166 *pDivCtrl = (value - 1U);
167 }
168
169 /* Freeze clock configuration */
170 SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
171 }
172
173 /* Get the clock divider value */
CLOCK_GetClockDiv(clock_div_name_t div_name)174 uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name)
175 {
176 volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name);
177 assert(div_name <= kCLOCK_DivMax);
178
179 if (((*pDivCtrl) & (1UL << 30U)) != 0U)
180 {
181 return 0;
182 }
183 else
184 {
185 return ((*pDivCtrl & 0xFFU) + 1U);
186 }
187 }
188
189 /* Halt the clock divider value */
CLOCK_HaltClockDiv(clock_div_name_t div_name)190 void CLOCK_HaltClockDiv(clock_div_name_t div_name)
191 {
192 volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name);
193 assert(div_name <= kCLOCK_DivMax);
194
195 /* Unlock clock configuration */
196 SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK;
197
198 *pDivCtrl |= (1UL << 30U);
199
200 /* Freeze clock configuration */
201 SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK;
202 }
203
204 /* Initialize the FROHF to given frequency (48,64,96,192) */
CLOCK_SetupFROHFClocking(uint32_t iFreq)205 status_t CLOCK_SetupFROHFClocking(uint32_t iFreq)
206 {
207 uint8_t freq_select = 0x0U;
208 switch (iFreq)
209 {
210 case 48000000U:
211 freq_select = 1U;
212 break;
213 case 64000000U:
214 freq_select = 3U;
215 break;
216 case 96000000U:
217 freq_select = 5U;
218 break;
219 case 192000000U:
220 freq_select = 7U;
221 break;
222 default:
223 freq_select = 0xFU;
224 break;
225 }
226
227 if (0xFU == freq_select)
228 {
229 return kStatus_Fail;
230 }
231
232 /* Set FIRC frequency */
233 SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select);
234
235 /* Unlock FIRCCSR */
236 SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK;
237
238 /* Enable CLK 48 MHz clock for peripheral use */
239 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK;
240 /* Enable FIRC HF clock for peripheral use */
241 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK;
242 /* Enable FIRC */
243 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK;
244
245 /* Lock FIRCCSR */
246 SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK;
247
248 /* Wait for FIRC clock to be valid. */
249 while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U)
250 {
251 }
252
253 return kStatus_Success;
254 }
255
256 /* Initialize the FRO12M. */
CLOCK_SetupFRO12MClocking(void)257 status_t CLOCK_SetupFRO12MClocking(void)
258 {
259 /* Unlock SIRCCSR */
260 SCG0->SIRCCSR &= ~SCG_SIRCCSR_LK_MASK;
261
262 /* Enable FRO12M clock for peripheral use */
263 SCG0->SIRCCSR |= SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK;
264
265 /* Lock SIRCCSR */
266 SCG0->SIRCCSR |= SCG_SIRCCSR_LK_MASK;
267
268 /* Wait for SIRC clock to be valid. */
269 while ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0U)
270 {
271 }
272
273 return kStatus_Success;
274 }
275
276 /*!
277 * brief Initialize the FRO16K.
278 * This function turns on FRO16K.
279 * return returns success or fail status.
280 */
CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask)281 status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask)
282 {
283 VBAT0->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK;
284 VBAT0->FROLCKA |= VBAT_FROLCKA_LOCK_MASK;
285
286 /* enable clk_16k output clock to corresponding modules according to the enable_mask. */
287 VBAT0->FROCLKE |= VBAT_FROCLKE_CLKE(((uint32_t)clk_16k_enable_mask));
288
289 return kStatus_Success;
290 }
291
292 /*!
293 * brief Initialize the external osc clock to given frequency.
294 * param iFreq : Desired frequency (must be equal to exact rate in Hz)
295 * return returns success or fail status.
296 */
CLOCK_SetupExtClocking(uint32_t iFreq)297 status_t CLOCK_SetupExtClocking(uint32_t iFreq)
298 {
299 uint8_t range = 0U;
300
301 if ((iFreq >= 8000000U) && (iFreq < 16000000U))
302 {
303 range = 0U;
304 }
305 else if ((iFreq >= 16000000U) && (iFreq < 25000000U))
306 {
307 range = 1U;
308 }
309 else if ((iFreq >= 25000000U) && (iFreq < 40000000U))
310 {
311 range = 2U;
312 }
313 else if ((iFreq >= 40000000U) && (iFreq <= 50000000U))
314 {
315 range = 3U;
316 }
317 else
318 {
319 return kStatus_InvalidArgument;
320 }
321
322 /* If configure register is locked, return error. */
323 if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U)
324 {
325 return kStatus_ReadOnly;
326 }
327
328 /* De-initializes the SCG SOSC */
329 SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
330
331 /* Select SOSC source (internal crystal oscillator) and Configure SOSC range */
332 SCG0->SOSCCFG = SCG_SOSCCFG_EREFS_MASK | SCG_SOSCCFG_RANGE(range);
333
334 /* Unlock SOSCCSR */
335 SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK;
336
337 /* Enable SOSC clock monitor and Enable SOSC */
338 SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK);
339
340 /* Wait for SOSC clock to be valid. */
341 while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U)
342 {
343 }
344
345 s_Ext_Clk_Freq = iFreq;
346
347 return kStatus_Success;
348 }
349
350 /*!
351 * @brief Initialize the external reference clock to given frequency.
352 * param iFreq : Desired frequency (must be equal to exact rate in Hz)
353 * return returns success or fail status.
354 */
CLOCK_SetupExtRefClocking(uint32_t iFreq)355 status_t CLOCK_SetupExtRefClocking(uint32_t iFreq)
356 {
357
358 if (iFreq > 50000000U)
359 {
360 return kStatus_InvalidArgument;
361 }
362
363 /* If configure register is locked, return error. */
364 if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U)
365 {
366 return kStatus_ReadOnly;
367 }
368
369 /* De-initializes the SCG SOSC */
370 SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
371
372 /* Select SOSC source (external reference clock)*/
373 SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK;
374
375 /* Unlock SOSCCSR */
376 SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK;
377
378 /* Enable SOSC clock monitor and Enable SOSC */
379 SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK);
380
381 /* Wait for SOSC clock to be valid. */
382 while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U)
383 {
384 }
385
386 s_Ext_Clk_Freq = iFreq;
387
388 return kStatus_Success;
389 }
390
391 /* Get IP Clk */
392 /*! brief Return Frequency of selected clock
393 * return Frequency of selected clock
394 */
CLOCK_GetFreq(clock_name_t clockName)395 uint32_t CLOCK_GetFreq(clock_name_t clockName)
396 {
397 uint32_t freq = 0U;
398
399 switch (clockName)
400 {
401 case kCLOCK_MainClk: /* MAIN_CLK */
402 freq = CLOCK_GetMainClk();
403 break;
404 case kCLOCK_CoreSysClk: /* Core/system clock(CPU_CLK) */
405 freq = CLOCK_GetCoreSysClkFreq();
406 break;
407 case kCLOCK_SYSTEM_CLK: /* AHB clock */
408 freq = CLOCK_GetCoreSysClkFreq();
409 break;
410 case kCLOCK_BusClk: /* Bus clock (AHB clock) */
411 freq = CLOCK_GetCoreSysClkFreq();
412 break;
413 case kCLOCK_ExtClk: /* External Clock */
414 freq = CLOCK_GetExtClkFreq();
415 break;
416 case kCLOCK_FroHf: /* FROHF */
417 freq = CLOCK_GetFroHfFreq();
418 break;
419 case kCLOCK_FroHfDiv: /* Divided by FROHF */
420 freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U);
421 break;
422 case kCLOCK_Clk48M: /* CLK48M */
423 freq = CLOCK_GetClk48MFreq();
424 break;
425 case kCLOCK_Fro12M: /* FRO12M */
426 freq = CLOCK_GetFro12MFreq();
427 break;
428 case kCLOCK_Clk1M: /* CLK1M */
429 freq = CLOCK_GetClk1MFreq();
430 break;
431 case kCLOCK_Fro16K: /* FRO16K */
432 freq = CLOCK_GetFRO16KFreq();
433 break;
434 case kCLOCK_Clk16K0: /* CLK16K[0] */
435 freq = CLOCK_GetClk16KFreq(0);
436 break;
437 case kCLOCK_Clk16K1: /* CLK16K[1] */
438 freq = CLOCK_GetClk16KFreq(1);
439 break;
440 case kCLOCK_SLOW_CLK: /* SYSTEM_CLK divided by 4 */
441 freq = CLOCK_GetCoreSysClkFreq() >> 2;
442 break;
443 default:
444 freq = 0U;
445 break;
446 }
447 return freq;
448 }
449
450 /* Get FRO 12M Clk */
451 /*! brief Return Frequency of FRO 12MHz
452 * return Frequency of FRO 12MHz
453 */
CLOCK_GetFro12MFreq(void)454 static uint32_t CLOCK_GetFro12MFreq(void)
455 {
456 return ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) != 0U) ? 12000000U : 0U;
457 }
458
459 /* Get CLK 1M Clk */
460 /*! brief Return Frequency of CLK 1MHz
461 * return Frequency of CLK 1MHz
462 */
CLOCK_GetClk1MFreq(void)463 static uint32_t CLOCK_GetClk1MFreq(void)
464 {
465 return 1000000U;
466 }
467
468 /* Get HF FRO Clk */
469 /*! brief Return Frequency of High-Freq output of FRO
470 * return Frequency of High-Freq output of FRO
471 */
CLOCK_GetFroHfFreq(void)472 static uint32_t CLOCK_GetFroHfFreq(void)
473 {
474 uint32_t freq;
475
476 if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) ||
477 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U))
478 {
479 freq = 0U;
480 }
481
482 switch ((SCG0->FIRCCFG & SCG_FIRCCFG_FREQ_SEL_MASK) >> SCG_FIRCCFG_FREQ_SEL_SHIFT)
483 {
484 case 0U:
485 freq = 36000000U;
486 break;
487 case 1U:
488 freq = 48000000U;
489 break;
490 case 2U:
491 freq = 48000000U;
492 break;
493 case 3U:
494 freq = 64000000U;
495 break;
496 case 4U:
497 freq = 72000000U;
498 break;
499 case 5U:
500 freq = 96000000U;
501 break;
502 case 6U:
503 freq = 144000000U;
504 break;
505 case 7U:
506 freq = 192000000U;
507 break;
508 default:
509 freq = 0U;
510 break;
511 }
512
513 return freq;
514 }
515
516 /* Get CLK 48M Clk */
517 /*! brief Return Frequency of CLK 48MHz
518 * return Frequency of CLK 48MHz
519 */
CLOCK_GetClk48MFreq(void)520 static uint32_t CLOCK_GetClk48MFreq(void)
521 {
522 return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) ||
523 ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ?
524 48000000U :
525 0U;
526 }
527
528 /*! brief Return Frequency of FRO16K
529 * return Frequency of FRO_16K
530 */
CLOCK_GetFRO16KFreq(void)531 static uint32_t CLOCK_GetFRO16KFreq(void)
532 {
533 return ((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) ? 16000U : 0U;
534 }
535 /* Get CLK 16K Clk */
536 /*! brief Return Frequency of CLK 16KHz
537 * return Frequency of CLK 16KHz
538 */
CLOCK_GetClk16KFreq(uint8_t id)539 static uint32_t CLOCK_GetClk16KFreq(uint8_t id)
540 {
541 return (((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) &&
542 ((VBAT0->FROCLKE & VBAT_FROCLKE_CLKE((((uint32_t)id) << 1U))) != 0U)) ?
543 16000U :
544 0U;
545 }
546
547 /* Get EXT OSC Clk */
548 /*! brief Return Frequency of External Clock
549 * return Frequency of External Clock. If no external clock is used returns 0.
550 */
CLOCK_GetExtClkFreq(void)551 static uint32_t CLOCK_GetExtClkFreq(void)
552 {
553 return ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) != 0U) ? s_Ext_Clk_Freq : 0U;
554 }
555
556 /* Get MAIN Clk */
557 /*! brief Return Frequency of Core System
558 * return Frequency of Core System
559 */
CLOCK_GetMainClk(void)560 uint32_t CLOCK_GetMainClk(void)
561 {
562 uint32_t freq = 0U;
563
564 switch ((SCG0->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)
565 {
566 case 1U:
567 freq = CLOCK_GetExtClkFreq();
568 break;
569 case 2U:
570 freq = CLOCK_GetFro12MFreq();
571 break;
572 case 3U:
573 freq = CLOCK_GetFroHfFreq();
574 break;
575 case 4U:
576 freq = CLOCK_GetClk16KFreq(1);
577 break;
578 default:
579 freq = 0U;
580 break;
581 }
582
583 return freq;
584 }
585
586 /*! brief Return Frequency of core
587 * return Frequency of the core
588 */
CLOCK_GetCoreSysClkFreq(void)589 uint32_t CLOCK_GetCoreSysClkFreq(void)
590 {
591 return CLOCK_GetMainClk() / ((SYSCON->AHBCLKDIV & 0xFFU) + 1U);
592 }
593
594 /* Get I3C Clk */
595 /*! brief Return Frequency of I3C Clock
596 * return Frequency of I3C Clock
597 */
CLOCK_GetI3CFClkFreq(void)598 uint32_t CLOCK_GetI3CFClkFreq(void)
599 {
600 uint32_t freq = 0U;
601 uint32_t clksel = (MRCC0->MRCC_I3C0_FCLK_CLKSEL);
602 uint32_t clkdiv = (MRCC0->MRCC_I3C0_FCLK_CLKDIV);
603
604 if (true == CLOCK_IsDivHalt(clkdiv))
605 {
606 return 0;
607 }
608
609 switch (clksel)
610 {
611 case 0U:
612 freq = CLOCK_GetFro12MFreq();
613 break;
614 case 2U:
615 freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U);
616 break;
617 case 3U:
618 freq = CLOCK_GetExtClkFreq();
619 break;
620 case 5U:
621 freq = CLOCK_GetClk1MFreq();
622 break;
623 default:
624 freq = 0U;
625 break;
626 }
627
628 return freq / ((clkdiv & 0xFFU) + 1U);
629 }
630
631 /* Get CTimer Clk */
632 /*! brief Return Frequency of CTimer functional Clock
633 * return Frequency of CTimer functional Clock
634 */
CLOCK_GetCTimerClkFreq(uint32_t id)635 uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)
636 {
637 uint32_t freq = 0U;
638 uint32_t clksel = 0U;
639 uint32_t clkdiv = 0U;
640
641 switch (id)
642 {
643 case 0U:
644 clksel = MRCC0->MRCC_CTIMER0_CLKSEL;
645 clkdiv = MRCC0->MRCC_CTIMER0_CLKDIV;
646 break;
647 case 1U:
648 clksel = MRCC0->MRCC_CTIMER1_CLKSEL;
649 clkdiv = MRCC0->MRCC_CTIMER1_CLKDIV;
650 break;
651 case 2U:
652 clksel = MRCC0->MRCC_CTIMER2_CLKSEL;
653 clkdiv = MRCC0->MRCC_CTIMER2_CLKDIV;
654 break;
655 case 3U:
656 clksel = MRCC0->MRCC_CTIMER3_CLKSEL;
657 clkdiv = MRCC0->MRCC_CTIMER3_CLKDIV;
658 break;
659 case 4U:
660 clksel = MRCC0->MRCC_CTIMER4_CLKSEL;
661 clkdiv = MRCC0->MRCC_CTIMER4_CLKDIV;
662 break;
663 default:
664 clksel = MRCC0->MRCC_CTIMER0_CLKSEL;
665 clkdiv = MRCC0->MRCC_CTIMER0_CLKDIV;
666 break;
667 }
668
669 if (true == CLOCK_IsDivHalt(clkdiv))
670 {
671 return 0;
672 }
673
674 switch (clksel)
675 {
676 case 0U:
677 freq = CLOCK_GetFro12MFreq();
678 break;
679 case 1U:
680 freq = CLOCK_GetFroHfFreq();
681 break;
682 case 3U:
683 freq = CLOCK_GetExtClkFreq();
684 break;
685 case 4U:
686 freq = CLOCK_GetClk16KFreq(1);
687 break;
688 case 5U:
689 freq = CLOCK_GetClk1MFreq();
690 break;
691 default:
692 freq = 0U;
693 break;
694 }
695
696 return freq / ((clkdiv & 0xFFU) + 1U);
697 }
698
699 /* Get LPI2C Clk */
700 /*! brief Return Frequency of LPI2C functional Clock
701 * return Frequency of LPI2C functional Clock
702 */
CLOCK_GetLpi2cClkFreq(uint32_t id)703 uint32_t CLOCK_GetLpi2cClkFreq(uint32_t id)
704 {
705 uint32_t freq = 0U;
706
707 uint32_t clksel = 0U;
708 uint32_t clkdiv = 0U;
709
710 switch (id)
711 {
712 case 0U:
713 clksel = MRCC0->MRCC_LPI2C0_CLKSEL;
714 clkdiv = MRCC0->MRCC_LPI2C0_CLKDIV;
715 break;
716 case 1U:
717 clksel = MRCC0->MRCC_LPI2C1_CLKSEL;
718 clkdiv = MRCC0->MRCC_LPI2C1_CLKDIV;
719 break;
720 case 2U:
721 clksel = MRCC0->MRCC_LPI2C2_CLKSEL;
722 clkdiv = MRCC0->MRCC_LPI2C2_CLKDIV;
723 break;
724 case 3U:
725 clksel = MRCC0->MRCC_LPI2C3_CLKSEL;
726 clkdiv = MRCC0->MRCC_LPI2C3_CLKDIV;
727 break;
728 default:
729 clksel = MRCC0->MRCC_LPI2C0_CLKSEL;
730 clkdiv = MRCC0->MRCC_LPI2C0_CLKDIV;
731 break;
732 }
733
734 if (true == CLOCK_IsDivHalt(clkdiv))
735 {
736 return 0;
737 }
738
739 switch (clksel)
740 {
741 case 0U:
742 freq = CLOCK_GetFro12MFreq();
743 break;
744 case 2U:
745 freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U);
746 break;
747 case 3U:
748 freq = CLOCK_GetExtClkFreq();
749 break;
750 case 5U:
751 freq = CLOCK_GetClk1MFreq();
752 break;
753 default:
754 freq = 0U;
755 break;
756 }
757
758 return freq / ((clkdiv & 0xFFU) + 1U);
759 }
760
761 /*! brief Return Frequency of LPSPI Clock
762 * return Frequency of LPSPI Clock
763 */
CLOCK_GetLpspiClkFreq(uint32_t id)764 uint32_t CLOCK_GetLpspiClkFreq(uint32_t id)
765 {
766 uint32_t freq = 0U;
767 uint32_t clksel = (0U == id) ? (MRCC0->MRCC_LPSPI0_CLKSEL) : (MRCC0->MRCC_LPSPI1_CLKSEL);
768 uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_LPSPI0_CLKDIV) : (MRCC0->MRCC_LPSPI1_CLKDIV);
769
770 if (true == CLOCK_IsDivHalt(clkdiv))
771 {
772 return 0;
773 }
774
775 switch (clksel)
776 {
777 case 0U:
778 freq = CLOCK_GetFro12MFreq();
779 break;
780 case 2U:
781 freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U);
782 break;
783 case 3U:
784 freq = CLOCK_GetExtClkFreq();
785 break;
786 case 5U:
787 freq = CLOCK_GetClk1MFreq();
788 break;
789 default:
790 freq = 0U;
791 break;
792 }
793
794 return freq / ((clkdiv & 0xFFU) + 1U);
795 }
796
797 /*! brief Return Frequency of LPUART Clock
798 * return Frequency of LPUART Clock
799 */
CLOCK_GetLpuartClkFreq(uint32_t id)800 uint32_t CLOCK_GetLpuartClkFreq(uint32_t id)
801 {
802 uint32_t freq = 0U;
803 uint32_t clksel = 0U;
804 uint32_t clkdiv = 0U;
805
806 switch (id)
807 {
808 case 0U:
809 clksel = MRCC0->MRCC_LPUART0_CLKSEL;
810 clkdiv = MRCC0->MRCC_LPUART0_CLKDIV;
811 break;
812 case 1U:
813 clksel = MRCC0->MRCC_LPUART1_CLKSEL;
814 clkdiv = MRCC0->MRCC_LPUART1_CLKDIV;
815 break;
816 case 2U:
817 clksel = MRCC0->MRCC_LPUART2_CLKSEL;
818 clkdiv = MRCC0->MRCC_LPUART2_CLKDIV;
819 break;
820 case 3U:
821 clksel = MRCC0->MRCC_LPUART3_CLKSEL;
822 clkdiv = MRCC0->MRCC_LPUART3_CLKDIV;
823 break;
824 case 4U:
825 clksel = MRCC0->MRCC_LPUART4_CLKSEL;
826 clkdiv = MRCC0->MRCC_LPUART4_CLKDIV;
827 break;
828 default:
829 clksel = MRCC0->MRCC_LPUART0_CLKSEL;
830 clkdiv = MRCC0->MRCC_LPUART0_CLKDIV;
831 break;
832 }
833 if (true == CLOCK_IsDivHalt(clkdiv))
834 {
835 return 0;
836 }
837
838 switch (clksel)
839 {
840 case 0U:
841 freq = CLOCK_GetFro12MFreq();
842 break;
843 case 2U:
844 freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U);
845 break;
846 case 3U:
847 freq = CLOCK_GetExtClkFreq();
848 break;
849 case 4U:
850 freq = CLOCK_GetClk16KFreq(1);
851 break;
852 case 5U:
853 freq = CLOCK_GetClk1MFreq();
854 break;
855 default:
856 freq = 0U;
857 break;
858 }
859
860 return freq / ((clkdiv & 0xFFU) + 1U);
861 }
862
863 /*! brief Return Frequency of LPTMR Clock
864 * return Frequency of LPTMR Clock
865 */
CLOCK_GetLptmrClkFreq(void)866 uint32_t CLOCK_GetLptmrClkFreq(void)
867 {
868 uint32_t freq = 0U;
869 uint32_t clksel = (MRCC0->MRCC_LPTMR0_CLKSEL);
870 uint32_t clkdiv = (MRCC0->MRCC_LPTMR0_CLKDIV);
871
872 if (true == CLOCK_IsDivHalt(clkdiv))
873 {
874 return 0;
875 }
876
877 switch (clksel)
878 {
879 case 0U:
880 freq = CLOCK_GetFro12MFreq();
881 break;
882 case 2U:
883 freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U);
884 break;
885 case 3U:
886 freq = CLOCK_GetExtClkFreq();
887 break;
888 case 5U:
889 freq = CLOCK_GetClk1MFreq();
890 break;
891 default:
892 freq = 0U;
893 break;
894 }
895
896 return freq / ((clkdiv & 0xFFU) + 1U);
897 }
898
899 /*! brief Return Frequency of OSTIMER
900 * return Frequency of OSTIMER Clock
901 */
CLOCK_GetOstimerClkFreq(void)902 uint32_t CLOCK_GetOstimerClkFreq(void)
903 {
904 uint32_t freq = 0U;
905 uint32_t clksel = (MRCC0->MRCC_OSTIMER0_CLKSEL);
906
907 switch (clksel)
908 {
909 case 0U:
910 freq = CLOCK_GetClk16KFreq(1);
911 break;
912 case 2U:
913 freq = CLOCK_GetClk1MFreq();
914 break;
915 default:
916 freq = 0U;
917 break;
918 }
919
920 return freq;
921 }
922
923 /*! brief Return Frequency of Adc Clock
924 * return Frequency of Adc.
925 */
CLOCK_GetAdcClkFreq(uint32_t id)926 uint32_t CLOCK_GetAdcClkFreq(uint32_t id)
927 {
928 uint32_t freq = 0U;
929
930 uint32_t clksel = (0U == id) ? (MRCC0->MRCC_ADC0_CLKSEL) : (MRCC0->MRCC_ADC1_CLKSEL);
931 uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_ADC0_CLKDIV) : (MRCC0->MRCC_ADC1_CLKDIV);
932
933 if (true == CLOCK_IsDivHalt(clkdiv))
934 {
935 return 0;
936 }
937
938 switch (clksel)
939 {
940 case 0U:
941 freq = CLOCK_GetFro12MFreq();
942 break;
943 case 1U:
944 freq = CLOCK_GetFroHfFreq();
945 break;
946 case 3U:
947 freq = CLOCK_GetExtClkFreq();
948 break;
949 case 5U:
950 freq = CLOCK_GetClk1MFreq();
951 break;
952 default:
953 freq = 0U;
954 break;
955 }
956
957 return freq / ((clkdiv & 0xFFU) + 1U);
958 }
959
960 /*! brief Return Frequency of Dac Clock
961 * return Frequency of Dac.
962 */
CLOCK_GetDacClkFreq(void)963 uint32_t CLOCK_GetDacClkFreq(void)
964 {
965 uint32_t freq = 0U;
966 uint32_t clksel = (MRCC0->MRCC_DAC0_CLKSEL);
967 uint32_t clkdiv = (MRCC0->MRCC_DAC0_CLKDIV);
968
969 if (true == CLOCK_IsDivHalt(clkdiv))
970 {
971 return 0;
972 }
973
974 switch (clksel)
975 {
976 case 0U:
977 freq = CLOCK_GetFro12MFreq();
978 break;
979 case 1U:
980 freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U);
981 break;
982 case 3U:
983 freq = CLOCK_GetExtClkFreq();
984 break;
985 case 5U:
986 freq = CLOCK_GetClk1MFreq();
987 break;
988 default:
989 freq = 0U;
990 break;
991 }
992
993 return freq / ((clkdiv & 0xFFU) + 1U);
994 }
995
996 /*! brief Return Frequency of CMP Function Clock
997 * return Frequency of CMP Function.
998 */
CLOCK_GetCmpFClkFreq(uint32_t id)999 uint32_t CLOCK_GetCmpFClkFreq(uint32_t id)
1000 {
1001 uint32_t freq = 0U;
1002 uint32_t clksel = (0U == id) ? (MRCC0->MRCC_CMP0_RR_CLKSEL) : (MRCC0->MRCC_CMP1_RR_CLKSEL);
1003 uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_CMP0_FUNC_CLKDIV) : (MRCC0->MRCC_CMP1_FUNC_CLKDIV);
1004
1005 if (true == CLOCK_IsDivHalt(clkdiv))
1006 {
1007 return 0;
1008 }
1009
1010 switch (clksel)
1011 {
1012 case 0U:
1013 freq = CLOCK_GetFro12MFreq();
1014 break;
1015 case 2U:
1016 freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U);
1017 break;
1018 case 3U:
1019 freq = CLOCK_GetExtClkFreq();
1020 break;
1021 case 5U:
1022 freq = CLOCK_GetClk1MFreq();
1023 break;
1024 default:
1025 freq = 0U;
1026 break;
1027 }
1028
1029 return freq / ((clkdiv & 0xFFU) + 1U);
1030 }
1031
1032 /*! brief Return Frequency of CMP Round Robin Clock
1033 * return Frequency of CMP Round Robin.
1034 */
CLOCK_GetCmpRRClkFreq(uint32_t id)1035 uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id)
1036 {
1037 uint32_t freq = 0U;
1038 uint32_t clksel = (0U == id) ? (MRCC0->MRCC_CMP0_RR_CLKSEL) : (MRCC0->MRCC_CMP1_RR_CLKSEL);
1039 uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_CMP0_RR_CLKDIV) : (MRCC0->MRCC_CMP1_RR_CLKDIV);
1040
1041 if (true == CLOCK_IsDivHalt(clkdiv))
1042 {
1043 return 0;
1044 }
1045
1046 switch (clksel)
1047 {
1048 case 0U:
1049 freq = CLOCK_GetFro12MFreq();
1050 break;
1051 case 2U:
1052 freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U);
1053 break;
1054 case 3U:
1055 freq = CLOCK_GetExtClkFreq();
1056 break;
1057 case 5U:
1058 freq = CLOCK_GetClk1MFreq();
1059 break;
1060 default:
1061 freq = 0U;
1062 break;
1063 }
1064
1065 return freq / ((clkdiv & 0xFFU) + 1U);
1066 }
1067
1068 /*! brief Return Frequency of Trace Clock
1069 * return Frequency of Trace.
1070 */
CLOCK_GetTraceClkFreq(void)1071 uint32_t CLOCK_GetTraceClkFreq(void)
1072 {
1073 uint32_t freq = 0U;
1074 uint32_t clksel = (MRCC0->MRCC_DBG_TRACE_CLKSEL);
1075 uint32_t clkdiv = (MRCC0->MRCC_DBG_TRACE_CLKDIV);
1076
1077 if (true == CLOCK_IsDivHalt(clkdiv))
1078 {
1079 return 0;
1080 }
1081
1082 switch (clksel)
1083 {
1084 case 0U:
1085 freq = CLOCK_GetCoreSysClkFreq();
1086 break;
1087 case 1U:
1088 freq = CLOCK_GetClk1MFreq();
1089 break;
1090 case 2U:
1091 freq = CLOCK_GetClk16KFreq(1);
1092 break;
1093 default:
1094 freq = 0U;
1095 break;
1096 }
1097
1098 return freq / ((clkdiv & 0xFFU) + 1U);
1099 }
1100
1101 /*! brief Return Frequency of CLKOUT Clock
1102 * return Frequency of CLKOUT.
1103 */
CLOCK_GetClkoutClkFreq(void)1104 uint32_t CLOCK_GetClkoutClkFreq(void)
1105 {
1106 uint32_t freq = 0U;
1107 uint32_t clksel = (MRCC0->MRCC_CLKOUT_CLKSEL);
1108 uint32_t clkdiv = (MRCC0->MRCC_CLKOUT_CLKDIV);
1109
1110 if (true == CLOCK_IsDivHalt(clkdiv))
1111 {
1112 return 0;
1113 }
1114
1115 switch (clksel)
1116 {
1117 case 0U:
1118 freq = CLOCK_GetFro12MFreq();
1119 break;
1120 case 1U:
1121 freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U);
1122 break;
1123 case 2U:
1124 freq = CLOCK_GetExtClkFreq();
1125 break;
1126 case 3U:
1127 freq = CLOCK_GetClk16KFreq(1);
1128 break;
1129 case 6U:
1130 freq = CLOCK_GetCoreSysClkFreq() >> 2;
1131 break;
1132 default:
1133 freq = 0U;
1134 break;
1135 }
1136
1137 return freq / ((clkdiv & 0xFFU) + 1U);
1138 }
1139
1140 /*! brief Return Frequency of Systick Clock
1141 * return Frequency of Systick.
1142 */
CLOCK_GetSystickClkFreq(void)1143 uint32_t CLOCK_GetSystickClkFreq(void)
1144 {
1145 uint32_t freq = 0U;
1146 uint32_t clksel = (MRCC0->MRCC_SYSTICK_CLKSEL);
1147 uint32_t clkdiv = (MRCC0->MRCC_SYSTICK_CLKDIV);
1148
1149 if (true == CLOCK_IsDivHalt(clkdiv))
1150 {
1151 return 0;
1152 }
1153
1154 switch (clksel)
1155 {
1156 case 0U:
1157 freq = CLOCK_GetCoreSysClkFreq();
1158 break;
1159 case 1U:
1160 freq = CLOCK_GetClk1MFreq();
1161 break;
1162 case 2U:
1163 freq = CLOCK_GetClk16KFreq(1);
1164 break;
1165 default:
1166 freq = 0U;
1167 break;
1168 }
1169
1170 return freq / ((clkdiv & 0xFFU) + 1U);
1171 }
1172
1173 /*! brief Return Frequency of Systick Clock
1174 * return Frequency of Systick.
1175 */
CLOCK_GetWwdtClkFreq(void)1176 uint32_t CLOCK_GetWwdtClkFreq(void)
1177 {
1178 uint32_t freq = 0U;
1179 uint32_t clkdiv = (MRCC0->MRCC_WWDT0_CLKDIV);
1180
1181 if (true == CLOCK_IsDivHalt(clkdiv))
1182 {
1183 return 0;
1184 }
1185
1186 freq = CLOCK_GetClk1MFreq();
1187
1188 return freq / ((clkdiv & 0xFFU) + 1U);
1189 }
1190
1191 /*! brief Return Frequency of FLEXIO FCLK
1192 * return Frequency of FLEXIO FCLK.
1193 */
CLOCK_GetFlexioClkFreq(void)1194 uint32_t CLOCK_GetFlexioClkFreq(void)
1195 {
1196 uint32_t freq = 0U;
1197
1198 uint32_t clksel = MRCC0->MRCC_FLEXIO0_CLKSEL;
1199 uint32_t clkdiv = MRCC0->MRCC_FLEXIO0_CLKDIV;
1200
1201 if (true == CLOCK_IsDivHalt(clkdiv))
1202 {
1203 return 0;
1204 }
1205
1206 switch (clksel)
1207 {
1208 case 0U:
1209 freq = CLOCK_GetFro12MFreq();
1210 break;
1211 case 1U:
1212 freq = CLOCK_GetFroHfFreq();
1213 break;
1214 case 3U:
1215 freq = CLOCK_GetExtClkFreq();
1216 break;
1217 case 5U:
1218 freq = CLOCK_GetClk1MFreq();
1219 break;
1220 default:
1221 freq = 0U;
1222 break;
1223 }
1224
1225 return freq / ((clkdiv & 0xFFU) + 1U);
1226 }
1227
1228 /*! brief Return Frequency of FlexCAN FCLK
1229 * return Frequency of FlexCAN FCLK.
1230 */
CLOCK_GetFlexcanClkFreq(void)1231 uint32_t CLOCK_GetFlexcanClkFreq(void)
1232 {
1233 uint32_t freq = 0U;
1234
1235 uint32_t clksel = MRCC0->MRCC_FLEXCAN0_CLKSEL;
1236 uint32_t clkdiv = MRCC0->MRCC_FLEXCAN0_CLKDIV;
1237
1238 if (true == CLOCK_IsDivHalt(clkdiv))
1239 {
1240 return 0;
1241 }
1242
1243 switch (clksel)
1244 {
1245 case 2U:
1246 freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U);
1247 break;
1248 case 3U:
1249 freq = CLOCK_GetExtClkFreq();
1250 break;
1251 default:
1252 freq = 0U;
1253 break;
1254 }
1255
1256 return freq / ((clkdiv & 0xFFU) + 1U);
1257 }
1258
1259 /**
1260 * @brief Setup FROHF trim.
1261 * @param config : FROHF trim value
1262 * @return returns success or fail status.
1263 */
CLOCK_FROHFTrimConfig(firc_trim_config_t config)1264 status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config)
1265 {
1266 SCG0->FIRCTCFG = SCG_FIRCTCFG_TRIMDIV(config.trimDiv) | SCG_FIRCTCFG_TRIMSRC(config.trimSrc);
1267
1268 if (kSCG_FircTrimNonUpdate == config.trimMode)
1269 {
1270 SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine);
1271 }
1272
1273 /* Set trim mode. */
1274 SCG0->FIRCCSR = (uint32_t)config.trimMode;
1275
1276 if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK)
1277 {
1278 return (status_t)kStatus_Fail;
1279 }
1280
1281 return (status_t)kStatus_Success;
1282 }
1283
1284 /**
1285 * @brief Setup FRO 12M trim.
1286 * @param config : FRO 12M trim value
1287 * @return returns success or fail status.
1288 */
CLOCK_FRO12MTrimConfig(sirc_trim_config_t config)1289 status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config)
1290 {
1291 SCG0->SIRCTCFG = SCG_SIRCTCFG_TRIMDIV(config.trimDiv) | SCG_SIRCTCFG_TRIMSRC(config.trimSrc);
1292
1293 if (kSCG_SircTrimNonUpdate == config.trimMode)
1294 {
1295 SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.cltrim);
1296 SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.ccotrim);
1297 }
1298
1299 /* Set trim mode. */
1300 SCG0->SIRCCSR = (uint32_t)config.trimMode;
1301
1302 if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCERR_MASK) == SCG_SIRCCSR_SIRCERR_MASK)
1303 {
1304 return (status_t)kStatus_Fail;
1305 }
1306
1307 return (status_t)kStatus_Success;
1308 }
1309
1310 /*!
1311 * @brief Sets the system OSC monitor mode.
1312 *
1313 * This function sets the system OSC monitor mode. The mode can be disabled,
1314 * it can generate an interrupt when the error is disabled, or reset when the error is detected.
1315 *
1316 * @param mode Monitor mode to set.
1317 */
CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode)1318 void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode)
1319 {
1320 uint32_t reg = SCG0->SOSCCSR;
1321
1322 reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK);
1323
1324 reg |= (uint32_t)mode;
1325
1326 SCG0->SOSCCSR = reg;
1327 }
1328
1329 /*! brief Enable USB FS clock.
1330 * Enable USB Full Speed clock.
1331 */
CLOCK_EnableUsbfsClock(void)1332 bool CLOCK_EnableUsbfsClock(void)
1333 {
1334 /* Enable USB clock */
1335 CLOCK_EnableClock(kCLOCK_GateUSB0);
1336
1337 /* Enable FROHF with 48MHZ if it is disabled */
1338 if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK))
1339 {
1340 if (kStatus_Success != CLOCK_SetupFROHFClocking(48000000U))
1341 {
1342 return false;
1343 }
1344 }
1345
1346 /* Enable CLK_48 MHz clock for peripheral use */
1347 SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK;
1348
1349 /* Use clk_48M for USB FS */
1350 CLOCK_AttachClk(kCLK_48M_to_USB0);
1351
1352 return true;
1353 }
1354
