Home
last modified time | relevance | path

Searched refs:pConfig (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/src/
DQspi_Ip_Sfdp.c940 static void Qspi_Ip_SfdpLutInitEnterLegacySPI(Qspi_Ip_MemoryConfigType const *pConfig);
988 const Qspi_Ip_MemoryConfigType *pConfig
997 const Qspi_Ip_MemoryConfigType *pConfig
1000 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_01(const Qspi_Ip_MemoryConfigType * pConfig);
1001 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_02(const Qspi_Ip_MemoryConfigType * pConfig);
1002 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_08(const Qspi_Ip_MemoryConfigType * pConfig);
1003 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_16(const Qspi_Ip_MemoryConfigType * pConfig);
1006 const Qspi_Ip_MemoryConfigType *pConfig
1010 const Qspi_Ip_MemoryConfigType *pConfig
1014 const Qspi_Ip_MemoryConfigType *pConfig
[all …]
DQspi_Ip.c1887 const Qspi_Ip_MemoryConfigType * pConfig, in Qspi_Ip_Init() argument
1896 DEV_ASSERT_QSPI(pConfig != NULL_PTR); in Qspi_Ip_Init()
1902 state->configuration = pConfig; in Qspi_Ip_Init()
1904 state->activeReadLut = pConfig->readLut; /* 0-X-X mode disabled by default */ in Qspi_Ip_Init()
1910 if (pConfig->ctrlAutoCfgPtr != NULL_PTR) in Qspi_Ip_Init()
1912 status = Qspi_Ip_ControllerInit(pConnect->qspiInstance, pConfig->ctrlAutoCfgPtr); in Qspi_Ip_Init()
1917 …status = Qspi_Ip_InitReset(instance, pConfig->initResetSettings.resetCmdLut, pConfig->initResetSet… in Qspi_Ip_Init()
1926 if ((STATUS_QSPI_IP_SUCCESS == status) && (NULL_PTR != pConfig->initCallout)) in Qspi_Ip_Init()
1928 status = pConfig->initCallout(instance); in Qspi_Ip_Init()
/hal_nxp-latest/s32/drivers/s32k3/Fls/src/
DQspi_Ip_Sfdp.c941 static void Qspi_Ip_SfdpLutInitEnterLegacySPI(const Qspi_Ip_MemoryConfigType *pConfig);
989 const Qspi_Ip_MemoryConfigType *pConfig
998 const Qspi_Ip_MemoryConfigType *pConfig
1001 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_01(const Qspi_Ip_MemoryConfigType * pConfig);
1002 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_02(const Qspi_Ip_MemoryConfigType * pConfig);
1003 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_08(const Qspi_Ip_MemoryConfigType * pConfig);
1004 static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_16(const Qspi_Ip_MemoryConfigType * pConfig);
1007 const Qspi_Ip_MemoryConfigType *pConfig
1011 const Qspi_Ip_MemoryConfigType *pConfig
1015 const Qspi_Ip_MemoryConfigType *pConfig
[all …]
DQspi_Ip.c1772 const Qspi_Ip_MemoryConfigType * pConfig, in Qspi_Ip_Init() argument
1780 DEV_ASSERT_QSPI(pConfig != NULL_PTR); in Qspi_Ip_Init()
1785 state->configuration = pConfig; in Qspi_Ip_Init()
1787 state->activeReadLut = pConfig->readLut; /* 0-X-X mode disabled by default */ in Qspi_Ip_Init()
1792 if (pConfig->ctrlAutoCfgPtr != NULL_PTR) in Qspi_Ip_Init()
1794 status = Qspi_Ip_ControllerInit(pConnect->qspiInstance, pConfig->ctrlAutoCfgPtr); in Qspi_Ip_Init()
1799 …status = Qspi_Ip_InitReset(instance, pConfig->initResetSettings.resetCmdLut, pConfig->initResetSet… in Qspi_Ip_Init()
1808 if ((STATUS_QSPI_IP_SUCCESS == status) && (NULL_PTR != pConfig->initCallout)) in Qspi_Ip_Init()
1810 status = pConfig->initCallout(instance); in Qspi_Ip_Init()
/hal_nxp-latest/mcux/mcux-sdk/drivers/flexcan/
Dfsl_flexcan.c878 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz) in FLEXCAN_Init() argument
881 assert(NULL != pConfig); in FLEXCAN_Init()
882 assert((pConfig->maxMbNum > 0U) && in FLEXCAN_Init()
883 … (pConfig->maxMbNum <= (uint8_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); in FLEXCAN_Init()
890 flexcan_timing_config_t timingCfg = pConfig->timingConfig; in FLEXCAN_Init()
896 uint32_t tqFre = pConfig->bitRate * quantum; in FLEXCAN_Init()
900 assert((pConfig->bitRate != 0U) && (pConfig->bitRate <= 1000000U) && (tqFre <= sourceClock_Hz)); in FLEXCAN_Init()
954 … base->CTRL1 = (kFLEXCAN_ClkSrc0 == pConfig->clkSrc) ? (base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK) : in FLEXCAN_Init()
971 base->MECR = (pConfig->enableMemoryErrorControl) ? (base->MECR & ~CAN_MECR_ECCDIS_MASK) : in FLEXCAN_Init()
975 …base->MECR = (pConfig->enableNonCorrectableErrorEnterFreeze) ? (base->MECR | CAN_MECR_NCEFAFRZ_MAS… in FLEXCAN_Init()
[all …]
Dfsl_flexcan.h1134 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz);
1188 …CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSi…
1222 void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig);
1242 void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig);
1273 void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig);
1419 …nhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable);
1431 void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig);
/hal_nxp-latest/mcux/mcux-sdk/drivers/sysctr/
Dfsl_sysctr.c88 …Init(SYS_CTR_CONTROL_Type *ctrlBase, SYS_CTR_COMPARE_Type *cmpBase, const sysctr_config_t *pConfig) in SYSCTR_Init() argument
90 assert(pConfig != NULL); in SYSCTR_Init()
100 reg = pConfig->enableDebugHalt ? (reg | SYS_CTR_CONTROL_CNTCR_HDBG_MASK) : in SYSCTR_Init()
107 reg = pConfig->enableHardwareFrequencyChange ? (reg | SYS_CTR_CONTROL_CNTCR2_HWFC_EN_MASK) : in SYSCTR_Init()
140 void SYSCTR_GetDefaultConfig(sysctr_config_t *pConfig) in SYSCTR_GetDefaultConfig() argument
142 pConfig->enableDebugHalt = false; in SYSCTR_GetDefaultConfig()
143 pConfig->enableHardwareFrequencyChange = false; in SYSCTR_GetDefaultConfig()
Dfsl_sysctr.h123 …nit(SYS_CTR_CONTROL_Type *ctrlBase, SYS_CTR_COMPARE_Type *cmpBase, const sysctr_config_t *pConfig);
147 void SYSCTR_GetDefaultConfig(sysctr_config_t *pConfig);
/hal_nxp-latest/s32/drivers/s32ze/Adc/src/
DAdc_Sar_Ip.c2140 const Adc_Sar_Ip_ConfigType * const pConfig) in Adc_Sar_Ip_Init() argument
2163 DevAssert(pConfig != NULL_PTR); in Adc_Sar_Ip_Init()
2167 DevAssert(pConfig->CtuMode != ADC_SAR_IP_CTU_MODE_TRIGGER); in Adc_Sar_Ip_Init()
2221 *MCRAddr = Adc_Sar_CollectMcrMasks(u32Instance, pConfig, *MCRAddr); in Adc_Sar_Ip_Init()
2223 Adc_Sar_Ip_axAdcSarState[u32Instance].DataAlign = pConfig->DataAlign; in Adc_Sar_Ip_Init()
2228 if (ADC_SAR_IP_CTU_MODE_TRIGGER == pConfig->CtuMode) in Adc_Sar_Ip_Init()
2235 Adc_Sar_EnableHighSpeed(AdcBasePtr, pConfig->HighSpeedConvEn); in Adc_Sar_Ip_Init()
2240 Adc_Sar_Ip_SetSampleTimes(u32Instance, pConfig->SampleTimeArr); in Adc_Sar_Ip_Init()
2243 *PDEDRAddr = ADC_PDEDR_PDED(pConfig->PowerDownDelay); in Adc_Sar_Ip_Init()
2247 Adc_Sar_EnableClkDiv(u32Instance, pConfig->ClkDivEnable); in Adc_Sar_Ip_Init()
[all …]
/hal_nxp-latest/s32/drivers/s32k3/Adc/src/
DAdc_Sar_Ip.c1954 const Adc_Sar_Ip_ConfigType * const pConfig) in Adc_Sar_Ip_Init() argument
1977 DevAssert(pConfig != NULL_PTR); in Adc_Sar_Ip_Init()
1981 DevAssert(pConfig->CtuMode != ADC_SAR_IP_CTU_MODE_TRIGGER); in Adc_Sar_Ip_Init()
2032 *MCRAddr = Adc_Sar_CollectMcrMasks(u32Instance, pConfig, *MCRAddr); in Adc_Sar_Ip_Init()
2034 Adc_Sar_Ip_axAdcSarState[u32Instance].DataAlign = pConfig->DataAlign; in Adc_Sar_Ip_Init()
2039 if (ADC_SAR_IP_CTU_MODE_TRIGGER == pConfig->CtuMode) in Adc_Sar_Ip_Init()
2046 Adc_Sar_EnableHighSpeed(AdcBasePtr, pConfig->HighSpeedConvEn); in Adc_Sar_Ip_Init()
2051 Adc_Sar_Ip_SetSampleTimes(u32Instance, pConfig->SampleTimeArr); in Adc_Sar_Ip_Init()
2054 *PDEDRAddr = ADC_PDEDR_PDED(pConfig->PowerDownDelay); in Adc_Sar_Ip_Init()
2058 Adc_Sar_EnableClkDiv(u32Instance, pConfig->ClkDivEnable); in Adc_Sar_Ip_Init()
[all …]
/hal_nxp-latest/s32/drivers/s32k3/Mcl/src/
DLcu_Ip.c184 …d Lcu_Ip_LogicInputInit(const uint8 LogicInput, const Lcu_Ip_LogicInputConfigType * const pConfig);
187 …cu_Ip_LogicOutputInit(const uint8 LogicOutput, const Lcu_Ip_LogicOutputConfigType * const pConfig);
190 static void Lcu_Ip_LogicInstanceInit(const Lcu_Ip_LogicInstanceType * pConfig);
291 static void Lcu_Ip_LogicInstanceInit(const Lcu_Ip_LogicInstanceType * pConfig) in Lcu_Ip_LogicInstanceInit() argument
302 LCU_IP_DEV_ASSERT(NULL_PTR != pConfig); in Lcu_Ip_LogicInstanceInit()
304 HwInstance = pConfig->HwInstId; in Lcu_Ip_LogicInstanceInit()
305 LocNumLogicCell = pConfig->NumLogicCellConfig; in Lcu_Ip_LogicInstanceInit()
307 HwAcc_Lcu_SetInstanceOperationMode(HwInstance, pConfig-> OperationMode); in Lcu_Ip_LogicInstanceInit()
313 ppxLocLogicCell = pConfig->ppxLogicCellConfigArray[CfgIdx]; in Lcu_Ip_LogicInstanceInit()
1934 …id Lcu_Ip_LogicInputInit(const uint8 LogicInput, const Lcu_Ip_LogicInputConfigType * const pConfig) in Lcu_Ip_LogicInputInit() argument
[all …]
DLcu_Ip_Hw_Access.c648 …ol(const uint8 LcuId, const uint8 HwLcOutputId, const Lcu_Ip_LogicOutputConfigType * const pConfig) in HwAcc_Lcu_SetLcForceControl() argument
656 Reg |= LCU_FCTRL_FORCE_SENSE(HwOutput, pConfig->ForceSignalSel); in HwAcc_Lcu_SetLcForceControl()
659 Reg |= LCU_FCTRL_FORCE_MODE(HwOutput, pConfig->ClearForceMode); in HwAcc_Lcu_SetLcForceControl()
662 Reg |= LCU_FCTRL_SYNC_SEL(HwOutput, pConfig->ForceSyncSel); in HwAcc_Lcu_SetLcForceControl()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/
Dfsl_clock.c651 cgc_hifi_sys_clk_config_t *pConfig = NULL; in CLOCK_GetHifiDspSysClkFreq() local
654 pConfig = (cgc_hifi_sys_clk_config_t *)(uint32_t)&sysClkConfig; in CLOCK_GetHifiDspSysClkFreq()
655 switch (pConfig->src) in CLOCK_GetHifiDspSysClkFreq()
677 freq /= (pConfig->divCore + 1U); in CLOCK_GetHifiDspSysClkFreq()
681 freq /= (pConfig->divPlat + 1U); in CLOCK_GetHifiDspSysClkFreq()
704 cgc_lpav_sys_clk_config_t *pConfig = NULL; in CLOCK_GetLpavSysClkFreq() local
707 pConfig = (cgc_lpav_sys_clk_config_t *)(uint32_t)&sysClkConfig; in CLOCK_GetLpavSysClkFreq()
709 switch (pConfig->src) in CLOCK_GetLpavSysClkFreq()
728 freq /= (pConfig->divAxi + 1U); in CLOCK_GetLpavSysClkFreq()
732 freq /= (pConfig->divAhb + 1U); in CLOCK_GetLpavSysClkFreq()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/
Dfsl_clock.c651 cgc_hifi_sys_clk_config_t *pConfig = NULL; in CLOCK_GetHifiDspSysClkFreq() local
654 pConfig = (cgc_hifi_sys_clk_config_t *)(uint32_t)&sysClkConfig; in CLOCK_GetHifiDspSysClkFreq()
655 switch (pConfig->src) in CLOCK_GetHifiDspSysClkFreq()
677 freq /= (pConfig->divCore + 1U); in CLOCK_GetHifiDspSysClkFreq()
681 freq /= (pConfig->divPlat + 1U); in CLOCK_GetHifiDspSysClkFreq()
704 cgc_lpav_sys_clk_config_t *pConfig = NULL; in CLOCK_GetLpavSysClkFreq() local
707 pConfig = (cgc_lpav_sys_clk_config_t *)(uint32_t)&sysClkConfig; in CLOCK_GetLpavSysClkFreq()
709 switch (pConfig->src) in CLOCK_GetLpavSysClkFreq()
728 freq /= (pConfig->divAxi + 1U); in CLOCK_GetLpavSysClkFreq()
732 freq /= (pConfig->divAhb + 1U); in CLOCK_GetLpavSysClkFreq()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/
Dfsl_clock.c651 cgc_hifi_sys_clk_config_t *pConfig = NULL; in CLOCK_GetHifiDspSysClkFreq() local
654 pConfig = (cgc_hifi_sys_clk_config_t *)(uint32_t)&sysClkConfig; in CLOCK_GetHifiDspSysClkFreq()
655 switch (pConfig->src) in CLOCK_GetHifiDspSysClkFreq()
677 freq /= (pConfig->divCore + 1U); in CLOCK_GetHifiDspSysClkFreq()
681 freq /= (pConfig->divPlat + 1U); in CLOCK_GetHifiDspSysClkFreq()
704 cgc_lpav_sys_clk_config_t *pConfig = NULL; in CLOCK_GetLpavSysClkFreq() local
707 pConfig = (cgc_lpav_sys_clk_config_t *)(uint32_t)&sysClkConfig; in CLOCK_GetLpavSysClkFreq()
709 switch (pConfig->src) in CLOCK_GetLpavSysClkFreq()
728 freq /= (pConfig->divAxi + 1U); in CLOCK_GetLpavSysClkFreq()
732 freq /= (pConfig->divAhb + 1U); in CLOCK_GetLpavSysClkFreq()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/
Dfsl_clock.c651 cgc_hifi_sys_clk_config_t *pConfig = NULL; in CLOCK_GetHifiDspSysClkFreq() local
654 pConfig = (cgc_hifi_sys_clk_config_t *)(uint32_t)&sysClkConfig; in CLOCK_GetHifiDspSysClkFreq()
655 switch (pConfig->src) in CLOCK_GetHifiDspSysClkFreq()
677 freq /= (pConfig->divCore + 1U); in CLOCK_GetHifiDspSysClkFreq()
681 freq /= (pConfig->divPlat + 1U); in CLOCK_GetHifiDspSysClkFreq()
704 cgc_lpav_sys_clk_config_t *pConfig = NULL; in CLOCK_GetLpavSysClkFreq() local
707 pConfig = (cgc_lpav_sys_clk_config_t *)(uint32_t)&sysClkConfig; in CLOCK_GetLpavSysClkFreq()
709 switch (pConfig->src) in CLOCK_GetLpavSysClkFreq()
728 freq /= (pConfig->divAxi + 1U); in CLOCK_GetLpavSysClkFreq()
732 freq /= (pConfig->divAhb + 1U); in CLOCK_GetLpavSysClkFreq()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/
Dfsl_clock.c651 cgc_hifi_sys_clk_config_t *pConfig = NULL; in CLOCK_GetHifiDspSysClkFreq() local
654 pConfig = (cgc_hifi_sys_clk_config_t *)(uint32_t)&sysClkConfig; in CLOCK_GetHifiDspSysClkFreq()
655 switch (pConfig->src) in CLOCK_GetHifiDspSysClkFreq()
677 freq /= (pConfig->divCore + 1U); in CLOCK_GetHifiDspSysClkFreq()
681 freq /= (pConfig->divPlat + 1U); in CLOCK_GetHifiDspSysClkFreq()
704 cgc_lpav_sys_clk_config_t *pConfig = NULL; in CLOCK_GetLpavSysClkFreq() local
707 pConfig = (cgc_lpav_sys_clk_config_t *)(uint32_t)&sysClkConfig; in CLOCK_GetLpavSysClkFreq()
709 switch (pConfig->src) in CLOCK_GetLpavSysClkFreq()
728 freq /= (pConfig->divAxi + 1U); in CLOCK_GetLpavSysClkFreq()
732 freq /= (pConfig->divAhb + 1U); in CLOCK_GetLpavSysClkFreq()
[all …]
/hal_nxp-latest/s32/drivers/s32k3/Fls/include/
DQspi_Ip.h104 const Qspi_Ip_MemoryConfigType * pConfig,
438 Qspi_Ip_StatusType Qspi_Ip_ReadSfdp(Qspi_Ip_MemoryConfigType * pConfig,
/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/include/
DQspi_Ip.h103 const Qspi_Ip_MemoryConfigType * pConfig,
437 Qspi_Ip_StatusType Qspi_Ip_ReadSfdp(Qspi_Ip_MemoryConfigType * pConfig,
/hal_nxp-latest/s32/drivers/s32ze/Adc/include/
DAdc_Sar_Ip.h189 const Adc_Sar_Ip_ConfigType * const pConfig);
491 const Adc_Sar_Ip_ClockConfigType * const pConfig);
/hal_nxp-latest/s32/drivers/s32k3/Adc/include/
DAdc_Sar_Ip.h189 const Adc_Sar_Ip_ConfigType * const pConfig);
488 const Adc_Sar_Ip_ClockConfigType * const pConfig);
/hal_nxp-latest/s32/drivers/s32k3/Mcl/include/
DLcu_Ip_Hw_Access.h198 …l(const uint8 LcuId, const uint8 HwLcOutputId, const Lcu_Ip_LogicOutputConfigType * const pConfig);