1 /*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup adc_sar_ip Adc Sar IPL
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Adc_Sar_Ip.h"
25 #include "Adc_Sar_Ip_Irq.h"
26 #include "Adc_Sar_Ip_HwAccess.h"
27 #include "Adc_Sar_Ip_TrustedFunctions.h"
28 #include "Reg_eSys.h"
29 #include "SchM_Adc.h"
30
31 #if defined(ADC_SAR_IP_DEV_ERROR_DETECT)
32 #include "OsIf.h"
33
34 /* local definitions on the limits of the clock frequency */
35 #define ADC_CLOCK_FREQ_MAX_RUNTIME (80000000U)
36 #define ADC_CLOCK_FREQ_MAX_CALIBRATION (40000000U)
37
38 #endif /* defined(ADC_SAR_IP_DEV_ERROR_DETECT) */
39
40 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
41 /* USER_MODE_REG_PROT_ENABLED is defined for Base sanity check in RegLockMacros.h */
42 #define USER_MODE_REG_PROT_ENABLED (ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
43 #include "RegLockMacros.h"
44 #endif /* (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT) */
45
46 /*==================================================================================================
47 * SOURCE FILE VERSION INFORMATION
48 ==================================================================================================*/
49 #define ADC_SAR_IP_VENDOR_ID_C 43
50 #define ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C 4
51 #define ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C 7
52 #define ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_C 0
53 #define ADC_SAR_IP_SW_MAJOR_VERSION_C 2
54 #define ADC_SAR_IP_SW_MINOR_VERSION_C 0
55 #define ADC_SAR_IP_SW_PATCH_VERSION_C 0
56
57 /*==================================================================================================
58 * FILE VERSION CHECKS
59 ==================================================================================================*/
60 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip.h file are of the same vendor */
61 #if (ADC_SAR_IP_VENDOR_ID_C != ADC_SAR_IP_VENDOR_ID)
62 #error "Adc_Sar_Ip.c and Adc_Sar_Ip.h have different vendor ids"
63 #endif
64
65 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip.h file are of the same Autosar version */
66 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION) || \
67 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MINOR_VERSION) || \
68 (ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_C != ADC_SAR_IP_AR_RELEASE_REVISION_VERSION) \
69 )
70 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip.h are different"
71 #endif
72
73 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip.h file are of the same Software version */
74 #if ((ADC_SAR_IP_SW_MAJOR_VERSION_C != ADC_SAR_IP_SW_MAJOR_VERSION) || \
75 (ADC_SAR_IP_SW_MINOR_VERSION_C != ADC_SAR_IP_SW_MINOR_VERSION) || \
76 (ADC_SAR_IP_SW_PATCH_VERSION_C != ADC_SAR_IP_SW_PATCH_VERSION) \
77 )
78 #error "Software Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip.h are different"
79 #endif
80
81 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_Irq.h file are of the same vendor */
82 #if (ADC_SAR_IP_VENDOR_ID_C != ADC_SAR_IP_VENDOR_ID_IRQ)
83 #error "Adc_Sar_Ip.c and Adc_Sar_Ip_Irq.h have different vendor ids"
84 #endif
85
86 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_Irq.h file are of the same Autosar version */
87 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_IRQ) || \
88 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_IRQ) || \
89 (ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_C != ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_IRQ) \
90 )
91 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_Irq.h are different"
92 #endif
93
94 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_Irq.h file are of the same Software version */
95 #if ((ADC_SAR_IP_SW_MAJOR_VERSION_C != ADC_SAR_IP_SW_MAJOR_VERSION_IRQ) || \
96 (ADC_SAR_IP_SW_MINOR_VERSION_C != ADC_SAR_IP_SW_MINOR_VERSION_IRQ) || \
97 (ADC_SAR_IP_SW_PATCH_VERSION_C != ADC_SAR_IP_SW_PATCH_VERSION_IRQ) \
98 )
99 #error "Software Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_Irq.h are different"
100 #endif
101
102 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_HwAccess.h file are of the same vendor */
103 #if (ADC_SAR_IP_VENDOR_ID_C != ADC_SAR_IP_VENDOR_ID_HWACCESS)
104 #error "Adc_Sar_Ip.c and Adc_Sar_Ip_HwAccess.h have different vendor ids"
105 #endif
106
107 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_HwAccess.h file are of the same Autosar version */
108 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS) || \
109 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_HWACCESS) || \
110 (ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_C != ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_HWACCESS) \
111 )
112 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_HwAccess.h are different"
113 #endif
114
115 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_HwAccess.h file are of the same Software version */
116 #if ((ADC_SAR_IP_SW_MAJOR_VERSION_C != ADC_SAR_IP_SW_MAJOR_VERSION_HWACCESS) || \
117 (ADC_SAR_IP_SW_MINOR_VERSION_C != ADC_SAR_IP_SW_MINOR_VERSION_HWACCESS) || \
118 (ADC_SAR_IP_SW_PATCH_VERSION_C != ADC_SAR_IP_SW_PATCH_VERSION_HWACCESS) \
119 )
120 #error "Software Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_HwAccess.h are different"
121 #endif
122
123 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_TrustedFunctions.h file are of the same vendor */
124 #if (ADC_SAR_IP_VENDOR_ID_C != ADC_SAR_IP_VENDOR_ID_TRUSTEDFUNCTIONS)
125 #error "Adc_Sar_Ip.c and Adc_Sar_Ip_TrustedFunctions.h have different vendor ids"
126 #endif
127
128 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_TrustedFunctions.h file are of the same Autosar version */
129 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_TRUSTEDFUNCTIONS) || \
130 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_TRUSTEDFUNCTIONS) || \
131 (ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_C != ADC_SAR_IP_AR_RELEASE_REVISION_VERSION_TRUSTEDFUNCTIONS) \
132 )
133 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_TrustedFunctions.h are different"
134 #endif
135
136 /* Check if Adc_Sar_Ip.c file and Adc_Sar_Ip_TrustedFunctions.h file are of the same Software version */
137 #if ((ADC_SAR_IP_SW_MAJOR_VERSION_C != ADC_SAR_IP_SW_MAJOR_VERSION_TRUSTEDFUNCTIONS) || \
138 (ADC_SAR_IP_SW_MINOR_VERSION_C != ADC_SAR_IP_SW_MINOR_VERSION_TRUSTEDFUNCTIONS) || \
139 (ADC_SAR_IP_SW_PATCH_VERSION_C != ADC_SAR_IP_SW_PATCH_VERSION_TRUSTEDFUNCTIONS) \
140 )
141 #error "Software Version Numbers of Adc_Sar_Ip.c and Adc_Sar_Ip_TrustedFunctions.h are different"
142 #endif
143
144 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
145 /* Check if Adc_Sar_Ip.c file and Reg_eSys.h file are of the same Autosar version */
146 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != REG_ESYS_AR_RELEASE_MAJOR_VERSION) || \
147 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != REG_ESYS_AR_RELEASE_MINOR_VERSION) \
148 )
149 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and Reg_eSys.h are different"
150 #endif
151
152 #if defined(ADC_SAR_IP_DEV_ERROR_DETECT)
153 /* Check if Adc_Sar_Ip.c file and OsIf.h file are of the same Autosar version */
154 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
155 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != OSIF_AR_RELEASE_MINOR_VERSION) \
156 )
157 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and OsIf.h are different"
158 #endif
159 #endif /* defined(ADC_SAR_IP_DEV_ERROR_DETECT) */
160
161 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
162 /* Checks against RegLockMacros.h */
163 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
164 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
165 #error "AUTOSAR Version Numbers of Adc_Sar_Ip.c and RegLockMacros.h are different"
166 #endif
167 #endif /* (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT) */
168
169 /* Check if Adc_Sar_Ip.c file and SchM_Adc.h file are of the same version */
170 #if ((ADC_SAR_IP_AR_RELEASE_MAJOR_VERSION_C != SCHM_ADC_AR_RELEASE_MAJOR_VERSION) || \
171 (ADC_SAR_IP_AR_RELEASE_MINOR_VERSION_C != SCHM_ADC_AR_RELEASE_MINOR_VERSION) \
172 )
173 #error "AutoSar Version Numbers of Adc_Sar_Ip.c and SchM_Adc.h are different"
174 #endif
175 #endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
176
177 /*******************************************************************************
178 * Pre-check
179 ******************************************************************************/
180 #ifndef MCAL_ENABLE_USER_MODE_SUPPORT
181 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
182 #error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running ADC in user mode the MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined
183 #endif /* (STD_ON == ADC_ENABLE_USER_MODE_SUPPORT) */
184 #endif /* ifndef MCAL_ENABLE_USER_MODE_SUPPORT*/
185
186 /*==================================================================================================
187 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
188 ==================================================================================================*/
189
190 /*==================================================================================================
191 * LOCAL MACROS
192 ==================================================================================================*/
193 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
194 /* ADC_SAR_IP_INST_HAS_REG_<bitwidth> macros. Checks the availability of a
195 register index based on the availability of the ADC channels
196 for the particular u32Instance on the platform.
197 <bitwidth> represents the width of the bitfield associated with each
198 ADC channel in the register series.
199 */
200 #define ADC_SAR_IP_INST_HAS_REG_4(inst,regIdx) ((Adc_Sar_Ip_au32AdcChanBitmap[inst][(regIdx) / 4u] & (0xFFUL << (((regIdx) % 4u) * 8u))) != 0u)
201 #define ADC_SAR_IP_INST_HAS_REG_32(inst,regIdx) ((Adc_Sar_Ip_au32AdcChanBitmap[inst][(regIdx) / 32u] & (0x01UL << ((regIdx) % 32u))) != 0u)
202
203 /* <bitwidth> = 4. Four bits in the register correspond to one ADC channel */
204 #define ADC_SAR_IP_INST_HAS_CWSELRn(inst,x) (ADC_SAR_IP_INST_HAS_REG_4(inst,x))
205
206 /* <bitwidth> = 32. The entire 4 byte register is associated with one ADC channel */
207 #define ADC_SAR_IP_INST_HAS_CDRn(inst,n) (ADC_SAR_IP_INST_HAS_REG_32(inst,n))
208 #define ADC_SAR_IP_INST_HAS_CHANn(inst,n) (ADC_SAR_IP_INST_HAS_REG_32(inst,n))
209
210 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
211
212 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
213
214 #ifdef ADC_DSDR_DSD
215 #define ADC_SAR_IP_INST_HAS_DSDR(inst) ((Adc_Sar_Ip_au32AdcFeatureBitmap[inst] & (1UL << 0u)) != 0u)
216 #endif /* ADC_DSDR_DSD */
217 #define ADC_SAR_IP_INST_HAS_PSCR(inst) ((Adc_Sar_Ip_au32AdcFeatureBitmap[inst] & (1UL << 1u)) != 0u)
218 #define ADC_SAR_IP_INST_HAS_CTU(inst) ((Adc_Sar_Ip_au32AdcFeatureBitmap[inst] & (1UL << 2u)) != 0u)
219 #define ADC_SAR_IP_INST_HAS_CTU_TRIGGER_MODE(inst) ((Adc_Sar_Ip_au32AdcFeatureBitmap[inst] & (1UL << 3u)) != 0u)
220 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
221
222 /* Macros for watchdog registers to help decode and compose bit mask for the functionality */
223 #define ADC_SAR_IP_WDG_REG_MASK_HIGH(registerIdx) ((uint32)((uint32)1UL << (((registerIdx) * 2u) + 1u)))
224 #define ADC_SAR_IP_WDG_REG_MASK_LOW(registerIdx) ((uint32)((uint32)1UL << ((registerIdx) * 2u)))
225 /*==================================================================================================
226 * LOCAL CONSTANTS
227 ==================================================================================================*/
228
229 /*==================================================================================================
230 * LOCAL VARIABLES
231 ==================================================================================================*/
232 #define ADC_START_SEC_CONST_UNSPECIFIED
233 #include "Adc_MemMap.h"
234
235 /* Table of pBase addresses for ADC instances. */
236 ADC_Type * const Adc_Sar_Ip_apxAdcBase[ADC_INSTANCE_COUNT] = IP_ADC_BASE_PTRS;
237 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
238 SAR_ADC_AE_Type * const Adc_Sar_AE_Ip_apxAdcBase[SAR_ADC_AE_INSTANCE_COUNT] = IP_SAR_ADC_AE_BASE_PTRS;
239 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
240 #if ADC_SAR_IP_HAS_TEMPSENSE_CHN
241 #if (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON)
242 static TEMPSENSE_Type * const Adc_Sar_Ip_apxTempsenseBase[TEMPSENSE_INSTANCE_COUNT] = IP_TEMPSENSE_BASE_PTRS;
243 #endif /* (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON) */
244 #endif
245
246 #define ADC_STOP_SEC_CONST_UNSPECIFIED
247 #include "Adc_MemMap.h"
248
249 #define ADC_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
250 #include "Adc_MemMap.h"
251 /* Global state structure */
252 VAR_SEC_NOCACHE(Adc_Sar_Ip_axAdcSarState) static Adc_Sar_Ip_StateStructType Adc_Sar_Ip_axAdcSarState[ADC_SAR_IP_INSTANCE_COUNT];
253
254 #define ADC_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
255 #include "Adc_MemMap.h"
256
257 #define ADC_START_SEC_CONST_32
258 #include "Adc_MemMap.h"
259
260 static const uint8 Adc_Sar_Ip_au8AdcGroupCount[ADC_SAR_IP_INSTANCE_COUNT] = FEATURE_ADC_MAX_GROUP_COUNT;
261
262 #if ((1U == ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL) || (ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) && (STD_ON == ADC_SAR_IP_EOC_ENABLED)))
263 static const uint32 Adc_Sar_Ip_au32AdcChanBitmap[ADC_SAR_IP_INSTANCE_COUNT][ADC_SAR_IP_NUM_GROUP_CHAN] = FEATURE_ADC_CHN_AVAIL_BITMAP;
264 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
265
266 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
267 static const uint32 Adc_Sar_Ip_au32AdcFeatureBitmap[ADC_SAR_IP_INSTANCE_COUNT] = FEATURE_ADC_FEAT_AVAIL_BITMAP;
268 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
269
270 #define ADC_STOP_SEC_CONST_32
271 #include "Adc_MemMap.h"
272
273 /*==================================================================================================
274 * GLOBAL CONSTANTS
275 ==================================================================================================*/
276
277 /*==================================================================================================
278 * GLOBAL VARIABLES
279 ==================================================================================================*/
280
281 /*==================================================================================================
282 * GLOBAL FUNCTION PROTOTYPES
283 ==================================================================================================*/
284
285 /*==================================================================================================
286 * LOCAL FUNCTION PROTOTYPES
287 ==================================================================================================*/
288 #define ADC_START_SEC_CODE
289 #include "Adc_MemMap.h"
290
291 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
292 static inline uint8 Adc_Sar_GetResolution(const uint32 Instance);
293 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
294
295 static inline uint16 Adc_Sar_GetMaskedResult(const uint32 Instance,
296 const uint32 Cdr);
297 static inline uint32 Adc_Sar_GetMsrFlags(const uint32 Instance);
298 static inline uint32 Adc_Sar_GetIsrFlags(const uint32 Instance);
299 #if ADC_SAR_IP_HAS_ADCLKSEL
300 static inline uint32 Adc_Sar_GetADCLKSELValue(Adc_Sar_Ip_ClockSelType ClockSel);
301 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
302 static inline uint32 Adc_Sar_CollectMcrMasks(const uint32 Instance,
303 const Adc_Sar_Ip_ConfigType * const Config,
304 uint32 InitialMcr);
305 static inline void Adc_Sar_ConfigChannels(const uint32 Instance,
306 const Adc_Sar_Ip_ChanConfigType * ChannelConfigsPtr,
307 uint8 NumChannels);
308 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
309 static inline Adc_Sar_Ip_StatusType Adc_Sar_CheckSelfTestProgress(const uint32 Instance);
310 static inline void Adc_Sar_ConfigSelftestThreshold(const uint32 Instance,
311 const Adc_Sar_Ip_SelfTestThresholdType * SelfTestThresholdConfig);
312 static inline void Adc_Sar_EnableSelftestThreshold(const uint32 Instance);
313 static inline void Adc_Sar_DisableSelftestThreshold(const uint32 Instance);
314 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
315 static uint32 Adc_Sar_GetConvResults(const uint32 Instance,
316 const Adc_Sar_Ip_ConvChainType ChainType,
317 uint16 * const ResultsRaw,
318 Adc_Sar_Ip_ChanResultType * const ResultsStruct,
319 const uint32 Length);
320
321 static void Adc_Sar_ResetWdog(const uint32 Instance);
322
323 #if FEATURE_ADC_HAS_CLOCK_DIVIDER
324 static inline void Adc_Sar_EnableClkDiv(const uint32 Instance,
325 const boolean ClkDivEnable);
326 #endif /* FEATURE_ADC_HAS_CLOCK_DIVIDER */
327
328 #if ( \
329 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || (STD_ON == ADC_SAR_IP_JECH_ENABLED) || \
330 ((ADC_SAR_IP_HAS_CTU == 1U) && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) && (STD_ON == ADC_SAR_IP_EOC_ENABLED)) \
331 )
332 static inline void Adc_Sar_CheckAndCallNotification(void (*Callback)(void));
333 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) .. */
334
335 #if (ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) && (STD_ON == ADC_SAR_IP_EOC_ENABLED))
336 static inline void Adc_Sar_CheckAndCallEoctuNotification(const uint32 Instance);
337 #endif
338
339 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
340 static inline void Adc_Sar_CheckAndCallEocNotification(uint32 Instance,
341 uint16 ChanIdx,
342 uint16 VectAdr,
343 uint32 EocFlag,
344 boolean * CeocfrFlag);
345 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
346
347 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
348 static inline uint32 Adc_Sar_CheckAndCallWorrNotification(uint32 Instance,
349 uint16 ChanIdx,
350 uint16 VectAdr);
351 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
352
353 #if ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED))
354 static inline void Adc_CheckAndCallAllChannelNotification(const uint32 Instance);
355 #endif /* ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
356
357 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
358 #if (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER)
359 static inline void Adc_Sar_ConfigExternalTrigger(const uint32 Instance,
360 const Adc_Sar_Ip_ExtTriggerEdgeType TriggerEdge,
361 const uint32 TrgEdgeSetMask,
362 const uint32 TrgEdgeClrMask,
363 const uint32 TrigSrcMask);
364 #endif /* (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER) */
365 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
366
367 #if ADC_SAR_IP_HAS_TEMPSENSE_CHN
368 #if (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON)
369 static inline uint32 Adc_Sar_TempsenseConvFp2Int(const uint32 FloatingPoint);
370 static inline uint16 Adc_Sar_TempsenseConvInt2Fp(const sint32 SignedInteger);
371 #endif /* (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON) */
372 #endif /* ADC_SAR_IP_HAS_TEMPSENSE_CHN */
373
374 static inline void Adc_Sar_SetNormalChain(const uint32 Instance,
375 const uint32 * const Mask);
376 static inline void Adc_Sar_SetInjectedChain(const uint32 Instance,
377 const uint32 * const Mask);
378
379 /* The function is used to reduce complexity for parent function */
380 static inline uint32 Adc_Sar_GetValueFromBool(const boolean bVal,
381 const uint32 TrueVal,
382 const uint32 FalseVal);
383
384 static inline Adc_Sar_Ip_StatusType Adc_Sar_CalibrationClkRestore(const uint32 u32Instance,
385 volatile uint32 * MCRAddr,
386 uint32 McrSavedValue);
387 static inline Adc_Sar_Ip_StatusType Adc_Sar_CalibrationClkSelect(const uint32 u32Instance,
388 volatile uint32 * MCRAddr,
389 uint32* McrSavedValue);
390 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
391 static inline Adc_Sar_Ip_StatusType Adc_Sar_CheckTimeoutStatus(const uint32 ActualTimeout,
392 const uint32 ExpectTimeout);
393 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
394
395 /*==================================================================================================
396 * LOCAL FUNCTIONS
397 ==================================================================================================*/
398 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
Adc_Sar_CheckTimeoutStatus(const uint32 ActualTimeout,const uint32 ExpectTimeout)399 static inline Adc_Sar_Ip_StatusType Adc_Sar_CheckTimeoutStatus(const uint32 ActualTimeout,
400 const uint32 ExpectTimeout)
401 {
402 Adc_Sar_Ip_StatusType RelValue = ADC_SAR_IP_STATUS_SUCCESS;
403 /* Check if the timeout is not expected */
404 if (ActualTimeout >= ExpectTimeout)
405 {
406 RelValue = ADC_SAR_IP_STATUS_TIMEOUT;
407 }
408
409 /* Return the value of ADC SAR status */
410 return RelValue;
411 }
412 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
413
414 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
415 /*FUNCTION*********************************************************************
416 *
417 * Function Name : Adc_Sar_GetResolution
418 * Description : Returns Adc Sar resolution for conversion data
419 *
420 *END*************************************************************************/
Adc_Sar_GetResolution(const uint32 Instance)421 static inline uint8 Adc_Sar_GetResolution(const uint32 Instance)
422 {
423 uint8 Resolution;
424 static const uint8 ResolutionArray[] = {14U, 12U, 10U, 8U}; /* maps each register bit value to resolution bit number */
425 const ADC_Type * const AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
426 uint32 Calbistreg = AdcBasePtr->CALBISTREG;
427 /* ResolutionArray can be used only for 2 bits resolutions. On S32K3 platforms only 2 bits are used so "& 3U" operation is needed */
428 uint8 ResolutionBits = (uint8)(((Calbistreg & ADC_CALBISTREG_RESN_MASK) >> ADC_CALBISTREG_RESN_SHIFT) & 3U);
429
430 Resolution = ResolutionArray[ResolutionBits];
431
432 return Resolution;
433 }
434 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
435
436 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
437 /*FUNCTION*********************************************************************
438 *
439 * Function Name : Adc_Sar_ConfigSelftestThreshold
440 * Description : Configure self-test threshold value
441 *
442 *END*************************************************************************/
Adc_Sar_ConfigSelftestThreshold(const uint32 Instance,const Adc_Sar_Ip_SelfTestThresholdType * SelfTestThresholdConfig)443 static inline void Adc_Sar_ConfigSelftestThreshold(const uint32 Instance,
444 const Adc_Sar_Ip_SelfTestThresholdType * SelfTestThresholdConfig)
445 {
446 ADC_Type * AdcBasePtr = NULL_PTR;
447 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
448 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
449 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
450 #ifdef ADC_STAW0R_AWDE
451 volatile uint32 * STAW0RAddr = NULL_PTR;
452 #endif /* ADC_STAW0R_AWDE */
453 #ifdef ADC_STAW1R_AWDE
454 volatile uint32 * STAW1RAddr = NULL_PTR;
455 #endif /* ADC_STAW1R_AWDE */
456 #ifdef ADC_STAW1AR_AWDE
457 volatile uint32 * STAW1ARAddr = NULL_PTR;
458 volatile uint32 * STAW1BRAddr = NULL_PTR;
459 #endif /* ADC_STAW1AR_AWDE */
460 #ifdef ADC_STAW2R_AWDE
461 volatile uint32 * STAW2RAddr = NULL_PTR;
462 #endif /* ADC_STAW2R_AWDE */
463 #ifdef ADC_STAW4R_AWDE
464 volatile uint32 * STAW4RAddr = NULL_PTR;
465 volatile uint32 * STAW5RAddr = NULL_PTR;
466 #endif /* ADC_STAW4R_AWDE */
467
468 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
469 if (Instance >= ADC_INSTANCE_COUNT)
470 {
471 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
472 #ifdef ADC_STAW0R_AWDE
473 STAW0RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW0R);
474 #endif /* ADC_STAW0R_AWDE */
475 #ifdef ADC_STAW1R_AWDE
476 STAW1RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW1R);
477 #endif /* ADC_STAW1R_AWDE */
478 #ifdef ADC_STAW1AR_AWDE
479 STAW1ARAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW1AR);
480 STAW1BRAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW1BR);
481 #endif /* ADC_STAW1AR_AWDE */
482 #ifdef ADC_STAW2R_AWDE
483 STAW2RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW2R);
484 #endif /* ADC_STAW2R_AWDE */
485 #ifdef ADC_STAW4R_AWDE
486 STAW4RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW4R);
487 STAW5RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW5R);
488 #endif /* ADC_STAW4R_AWDE */
489 }
490 else
491 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
492 {
493 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
494 #ifdef ADC_STAW0R_AWDE
495 STAW0RAddr = (volatile uint32 *)&(AdcBasePtr->STAW0R);
496 #endif /* ADC_STAW0R_AWDE */
497 #ifdef ADC_STAW1R_AWDE
498 STAW1RAddr = (volatile uint32 *)&(AdcBasePtr->STAW1R);
499 #endif /* ADC_STAW1R_AWDE */
500 #ifdef ADC_STAW1AR_AWDE
501 STAW1ARAddr = (volatile uint32 *)&(AdcBasePtr->STAW1AR);
502 STAW1BRAddr = (volatile uint32 *)&(AdcBasePtr->STAW1BR);
503 #endif /* ADC_STAW1AR_AWDE */
504 #ifdef ADC_STAW2R_AWDE
505 STAW2RAddr = (volatile uint32 *)&(AdcBasePtr->STAW2R);
506 #endif /* ADC_STAW2R_AWDE */
507 #ifdef ADC_STAW4R_AWDE
508 STAW4RAddr = (volatile uint32 *)&(AdcBasePtr->STAW4R);
509 STAW5RAddr = (volatile uint32 *)&(AdcBasePtr->STAW5R);
510 #endif /* ADC_STAW4R_AWDE */
511 }
512
513 #ifdef ADC_STAW0R_AWDE
514 /* Configure the self-test watchdog threshold for S0 algorithm */
515 *STAW0RAddr &= ~(ADC_STAW0R_THRH_MASK | ADC_STAW0R_THRL_MASK);
516 *STAW0RAddr |= ADC_STAW0R_THRH(SelfTestThresholdConfig->AdcSTAW0RHighVal) | ADC_STAW0R_THRL(SelfTestThresholdConfig->AdcSTAW0RLowVal);
517 #endif /* ADC_STAW0R_AWDE */
518
519 #ifdef ADC_STAW1R_AWDE
520 /* Configure the self-test watchdog threshold for S1 algorithm */
521 *STAW1RAddr &= ~(ADC_STAW1R_THRL_MASK);
522 *STAW1RAddr |= ADC_STAW1R_THRL(SelfTestThresholdConfig->AdcSTAW1RLowVal);
523 #endif /* ADC_STAW1R_AWDE */
524 #ifdef ADC_STAW1AR_AWDE
525 /* Configure the self-test watchdog threshold for S1 algorithm */
526 *STAW1ARAddr &= ~(ADC_STAW1AR_THRH_MASK | ADC_STAW1AR_THRL_MASK);
527 *STAW1ARAddr |= ADC_STAW1AR_THRH(SelfTestThresholdConfig->AdcSTAW1ARHighVal) | ADC_STAW1AR_THRL(SelfTestThresholdConfig->AdcSTAW1ARLowVal);
528 *STAW1BRAddr &= ~(ADC_STAW1BR_THRH_MASK | ADC_STAW1BR_THRL_MASK);
529 *STAW1BRAddr |= ADC_STAW1BR_THRH(SelfTestThresholdConfig->AdcSTAW1BRHighVal) | ADC_STAW1BR_THRL(SelfTestThresholdConfig->AdcSTAW1BRLowVal);
530 #endif /* ADC_STAW1AR_AWDE */
531
532 #ifdef ADC_STAW2R_AWDE
533 /* Configure the self-test watchdog threshold for S2 algorithm */
534 *STAW2RAddr &= ~(ADC_STAW2R_THRL_MASK);
535 *STAW2RAddr |= ADC_STAW2R_THRL(SelfTestThresholdConfig->AdcSTAW2RLowVal);
536 #endif /* ADC_STAW2R_AWDE */
537
538 #ifdef ADC_STAW4R_AWDE
539 /* Configure the self-test watchdog threshold for C algorithm */
540 *STAW4RAddr &= ~(ADC_STAW4R_THRH_MASK | ADC_STAW4R_THRL_MASK);
541 *STAW4RAddr |= ADC_STAW4R_THRH(SelfTestThresholdConfig->AdcSTAW4RHighVal) | ADC_STAW4R_THRL(SelfTestThresholdConfig->AdcSTAW4RLowVal);
542 *STAW5RAddr &= ~(ADC_STAW5R_THRH_MASK | ADC_STAW5R_THRL_MASK);
543 *STAW5RAddr |= ADC_STAW5R_THRH(SelfTestThresholdConfig->AdcSTAW5RHighVal) | ADC_STAW5R_THRL(SelfTestThresholdConfig->AdcSTAW5RLowVal);
544 #endif /* ADC_STAW4R_AWDE */
545 }
546
547 /*FUNCTION*********************************************************************
548 *
549 * Function Name : Adc_Sar_EnableSelftestThreshold
550 * Description : Enable self-test threshold
551 *
552 *END*************************************************************************/
Adc_Sar_EnableSelftestThreshold(const uint32 Instance)553 static inline void Adc_Sar_EnableSelftestThreshold(const uint32 Instance)
554 {
555 ADC_Type * AdcBasePtr = NULL_PTR;
556 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
557 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
558 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
559 #ifdef ADC_STAW0R_AWDE
560 volatile uint32 * STAW0RAddr = NULL_PTR;
561 #endif /* ADC_STAW0R_AWDE */
562 #ifdef ADC_STAW1R_AWDE
563 volatile uint32 * STAW1RAddr = NULL_PTR;
564 #endif /* ADC_STAW1R_AWDE */
565 #ifdef ADC_STAW1AR_AWDE
566 volatile uint32 * STAW1ARAddr = NULL_PTR;
567 #endif /* ADC_STAW1AR_AWDE */
568 #ifdef ADC_STAW2R_AWDE
569 volatile uint32 * STAW2RAddr = NULL_PTR;
570 #endif /* ADC_STAW2R_AWDE */
571 #ifdef ADC_STAW4R_AWDE
572 volatile uint32 * STAW4RAddr = NULL_PTR;
573 #endif /* ADC_STAW4R_AWDE */
574
575 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
576 if (Instance >= ADC_INSTANCE_COUNT)
577 {
578 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
579 #ifdef ADC_STAW0R_AWDE
580 STAW0RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW0R);
581 #endif /* ADC_STAW0R_AWDE */
582 #ifdef ADC_STAW1R_AWDE
583 STAW1RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW1R);
584 #endif /* ADC_STAW1R_AWDE */
585 #ifdef ADC_STAW1AR_AWDE
586 STAW1ARAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW1AR);
587 #endif /* ADC_STAW1AR_AWDE */
588 #ifdef ADC_STAW2R_AWDE
589 STAW2RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW2R);
590 #endif /* ADC_STAW2R_AWDE */
591 #ifdef ADC_STAW4R_AWDE
592 STAW4RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW4R);
593 #endif /* ADC_STAW4R_AWDE */
594 }
595 else
596 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
597 {
598 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
599 #ifdef ADC_STAW0R_AWDE
600 STAW0RAddr = (volatile uint32 *)&(AdcBasePtr->STAW0R);
601 #endif /* ADC_STAW0R_AWDE */
602 #ifdef ADC_STAW1R_AWDE
603 STAW1RAddr = (volatile uint32 *)&(AdcBasePtr->STAW1R);
604 #endif /* ADC_STAW1R_AWDE */
605 #ifdef ADC_STAW1AR_AWDE
606 STAW1ARAddr = (volatile uint32 *)&(AdcBasePtr->STAW1AR);
607 #endif /* ADC_STAW1AR_AWDE */
608 #ifdef ADC_STAW2R_AWDE
609 STAW2RAddr = (volatile uint32 *)&(AdcBasePtr->STAW2R);
610 #endif /* ADC_STAW2R_AWDE */
611 #ifdef ADC_STAW4R_AWDE
612 STAW4RAddr = (volatile uint32 *)&(AdcBasePtr->STAW4R);
613 #endif /* ADC_STAW4R_AWDE */
614 }
615
616 #ifdef ADC_STAW0R_AWDE
617 /* Enable the self-test watchdog threshold for S0 algorithm */
618 *STAW0RAddr |= ADC_STAW0R_AWDE(0x1UL);
619 #endif /* ADC_STAW0R_AWDE */
620
621 #ifdef ADC_STAW1R_AWDE
622 /* Enable the self-test watchdog threshold for S1 algorithm */
623 *STAW1RAddr |= ADC_STAW1R_AWDE(0x1UL);
624 #endif /* ADC_STAW1R_AWDE */
625 #ifdef ADC_STAW1AR_AWDE
626 /* Enable the self-test watchdog threshold for S1 algorithm */
627 *STAW1ARAddr |= ADC_STAW1AR_AWDE(0x1UL);
628 #endif /* ADC_STAW1AR_AWDE */
629
630 #ifdef ADC_STAW2R_AWDE
631 /* Enable the self-test watchdog threshold for S2 algorithm */
632 *STAW2RAddr |= ADC_STAW2R_AWDE(0x1UL);
633 #endif /* ADC_STAW2R_AWDE */
634
635 #ifdef ADC_STAW4R_AWDE
636 /* Enable the self-test watchdog threshold for C algorithm */
637 *STAW4RAddr |= ADC_STAW4R_AWDE(0x1UL);
638 #endif /* ADC_STAW4R_AWDE */
639 }
640
641 /*FUNCTION*********************************************************************
642 *
643 * Function Name : Adc_Sar_DisableSelftestThreshold
644 * Description : Disable self-test threshold
645 *
646 *END*************************************************************************/
Adc_Sar_DisableSelftestThreshold(const uint32 Instance)647 static inline void Adc_Sar_DisableSelftestThreshold(const uint32 Instance)
648 {
649 ADC_Type * AdcBasePtr = NULL_PTR;
650 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
651 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
652 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
653 #ifdef ADC_STAW0R_AWDE
654 volatile uint32 * STAW0RAddr = NULL_PTR;
655 #endif /* ADC_STAW0R_AWDE */
656 #ifdef ADC_STAW1R_AWDE
657 volatile uint32 * STAW1RAddr = NULL_PTR;
658 #endif /* ADC_STAW1R_AWDE */
659 #ifdef ADC_STAW1AR_AWDE
660 volatile uint32 * STAW1ARAddr = NULL_PTR;
661 #endif /* ADC_STAW1AR_AWDE */
662 #ifdef ADC_STAW2R_AWDE
663 volatile uint32 * STAW2RAddr = NULL_PTR;
664 #endif /* ADC_STAW2R_AWDE */
665 #ifdef ADC_STAW4R_AWDE
666 volatile uint32 * STAW4RAddr = NULL_PTR;
667 #endif /* ADC_STAW4R_AWDE */
668
669 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
670 if (Instance >= ADC_INSTANCE_COUNT)
671 {
672 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
673 #ifdef ADC_STAW0R_AWDE
674 STAW0RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW0R);
675 #endif /* ADC_STAW0R_AWDE */
676 #ifdef ADC_STAW1R_AWDE
677 STAW1RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW1R);
678 #endif /* ADC_STAW1R_AWDE */
679 #ifdef ADC_STAW1AR_AWDE
680 STAW1ARAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW1AR);
681 #endif /* ADC_STAW1AR_AWDE */
682 #ifdef ADC_STAW2R_AWDE
683 STAW2RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW2R);
684 #endif /* ADC_STAW2R_AWDE */
685 #ifdef ADC_STAW4R_AWDE
686 STAW4RAddr = (volatile uint32 *)&(AdcAEBasePtr->STAW4R);
687 #endif /* ADC_STAW4R_AWDE */
688 }
689 else
690 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
691 {
692 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
693 #ifdef ADC_STAW0R_AWDE
694 STAW0RAddr = (volatile uint32 *)&(AdcBasePtr->STAW0R);
695 #endif /* ADC_STAW0R_AWDE */
696 #ifdef ADC_STAW1R_AWDE
697 STAW1RAddr = (volatile uint32 *)&(AdcBasePtr->STAW1R);
698 #endif /* ADC_STAW1R_AWDE */
699 #ifdef ADC_STAW1AR_AWDE
700 STAW1ARAddr = (volatile uint32 *)&(AdcBasePtr->STAW1AR);
701 #endif /* ADC_STAW1AR_AWDE */
702 #ifdef ADC_STAW2R_AWDE
703 STAW2RAddr = (volatile uint32 *)&(AdcBasePtr->STAW2R);
704 #endif /* ADC_STAW2R_AWDE */
705 #ifdef ADC_STAW4R_AWDE
706 STAW4RAddr = (volatile uint32 *)&(AdcBasePtr->STAW4R);
707 #endif /* ADC_STAW4R_AWDE */
708 }
709
710 #ifdef ADC_STAW0R_AWDE
711 /* Disable the self-test watchdog threshold for S0 algorithm */
712 *STAW0RAddr &= ~(ADC_STAW0R_AWDE_MASK);
713 #endif /* ADC_STAW0R_AWDE */
714 #ifdef ADC_STAW1R_AWDE
715 /* Disable the self-test watchdog threshold for S1 algorithm */
716 *STAW1RAddr &= ~(ADC_STAW1R_AWDE_MASK);
717 #endif /* ADC_STAW1R_AWDE */
718 #ifdef ADC_STAW1AR_AWDE
719 /* Enable the self-test watchdog threshold for S1 algorithm */
720 *STAW1ARAddr &= ~(ADC_STAW1AR_AWDE_MASK);
721 #endif /* ADC_STAW1AR_AWDE */
722 #ifdef ADC_STAW2R_AWDE
723 /* Disable the self-test watchdog threshold for S2 algorithm */
724 *STAW2RAddr &= ~(ADC_STAW2R_AWDE_MASK);
725 #endif /* ADC_STAW2R_AWDE */
726 #ifdef ADC_STAW4R_AWDE
727 /* Disable the self-test watchdog threshold for C algorithm */
728 *STAW4RAddr &= ~(ADC_STAW4R_AWDE_MASK);
729 #endif /* ADC_STAW4R_AWDE */
730 }
731 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
732
733 /*FUNCTION*********************************************************************
734 *
735 * Function Name : Adc_Sar_GetMaskedResult
736 * Description : Returns result masked accordingly with alignment
737 *
738 *END*************************************************************************/
Adc_Sar_GetMaskedResult(const uint32 Instance,const uint32 Cdr)739 static inline uint16 Adc_Sar_GetMaskedResult(const uint32 Instance,
740 const uint32 Cdr)
741 {
742 uint32 CdrMask;
743 uint16 Result;
744 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
745 uint8 Resolution;
746 uint32 ResolutionMask;
747 uint8 ResolutionShift;
748 #else
749 uint8 Resolution = ADC_SAR_IP_MAX_RESOLUTION;
750 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
751
752 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
753 if (FALSE == Adc_Sar_Ip_axAdcSarState[Instance].BypassResolution)
754 {
755 Resolution = Adc_Sar_GetResolution(Instance);
756 }
757 else
758 {
759 Resolution = ADC_SAR_IP_RESULT_RESOLUTION;
760 }
761 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
762
763 /* If the result is left aligned, adjust register mask accordingly */
764 if (Adc_Sar_Ip_axAdcSarState[Instance].DataAlign == ADC_SAR_IP_DATA_ALIGNED_LEFT)
765 {
766 /* Assumption: the width of the register is less than 16 */
767 CdrMask = (uint32)ADC_CDR_CDATA_MASK << (16u - Resolution);
768 Result = ((uint16)(Cdr & CdrMask)) >> (16u - Resolution + ADC_CDR_CDATA_SHIFT);
769 }
770 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
771 else
772 {
773 ResolutionMask = (uint32)ADC_CDR_CDATA_MASK << (ADC_SAR_IP_RESULT_RESOLUTION - Resolution);
774 ResolutionShift = ADC_SAR_IP_RESULT_RESOLUTION - Resolution + ADC_CDR_CDATA_SHIFT;
775 CdrMask = ((uint32)ADC_CDR_CDATA_MASK >> 1u) & ResolutionMask;
776 Result = ((uint16)(Cdr & CdrMask)) >> ResolutionShift;
777 }
778 #else
779 else
780 {
781 CdrMask = (uint32)ADC_CDR_CDATA_MASK;
782 Result = ((uint16)(Cdr & CdrMask)) >> ADC_CDR_CDATA_SHIFT;
783 }
784 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
785 return Result;
786 }
787
788
789 /*FUNCTION*********************************************************************
790 *
791 * Function Name : Adc_Sar_GetMsrFlags
792 * Description : Returns the flag status from MSR register
793 *
794 *END*************************************************************************/
Adc_Sar_GetMsrFlags(const uint32 Instance)795 static inline uint32 Adc_Sar_GetMsrFlags(const uint32 Instance)
796 {
797 uint32 Msr = 0U;
798 uint32 Flags = 0U;
799 const ADC_Type * AdcBasePtr = NULL_PTR;
800 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
801 const SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
802 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
803
804 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
805 if (Instance >= ADC_INSTANCE_COUNT)
806 {
807 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
808 Msr = AdcAEBasePtr->MSR;
809 }
810 else
811 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
812 {
813 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
814 Msr = AdcBasePtr->MSR;
815 }
816
817 #if FEATURE_ADC_HAS_CALIBRATION
818 Flags |= ((Msr & ADC_MSR_CALIBRTD_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_CALIBRATED : 0U;
819 #endif /* FEATURE_ADC_HAS_CALIBRATION */
820 Flags |= ((Msr & ADC_MSR_NSTART_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_NORMAL_STARTED : 0U;
821 Flags |= ((Msr & ADC_MSR_JABORT_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_INJECTED_ABORTED : 0U;
822 Flags |= ((Msr & ADC_MSR_JSTART_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_INJECTED_STARTED : 0U;
823 #if ADC_SAR_IP_HAS_CTU
824 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
825 if (ADC_SAR_IP_INST_HAS_CTU(Instance))
826 {
827 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
828 Flags |= ((Msr & ADC_MSR_CTUSTART_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_CTU_STARTED : 0U;
829 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
830 }
831 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
832 #endif /* ADC_SAR_IP_HAS_CTU */
833 Flags |= ((Msr & ADC_MSR_ACKO_MASK) != 0U) ? ADC_SAR_IP_STATUS_FLAG_AUTOCLOCKOFF : 0U;
834
835 return Flags;
836 }
837
838 /*FUNCTION*********************************************************************
839 *
840 * Function Name : Adc_Sar_GetIsrFlags
841 * Description : Returns the flag status from ISR register
842 *
843 *END*************************************************************************/
Adc_Sar_GetIsrFlags(const uint32 Instance)844 static inline uint32 Adc_Sar_GetIsrFlags(const uint32 Instance)
845 {
846 uint32 Flags = 0U;
847 uint32 Isr = 0U;
848 const ADC_Type * AdcBasePtr = NULL_PTR;
849 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
850 const SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
851 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
852
853 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
854 if (Instance >= ADC_INSTANCE_COUNT)
855 {
856 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
857 Isr = AdcAEBasePtr->ISR;
858 }
859 else
860 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
861 {
862 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
863 Isr = AdcBasePtr->ISR;
864 }
865 Flags |= ((Isr & ADC_ISR_EOC_MASK) != 0U) ? ADC_SAR_IP_NOTIF_FLAG_NORMAL_EOC : 0U;
866 Flags |= ((Isr & ADC_ISR_ECH_MASK) != 0U) ? ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN : 0U;
867 Flags |= ((Isr & ADC_ISR_JEOC_MASK) != 0U) ? ADC_SAR_IP_NOTIF_FLAG_INJECTED_EOC : 0U;
868 Flags |= ((Isr & ADC_ISR_JECH_MASK) != 0U) ? ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN : 0U;
869 #if ADC_SAR_IP_HAS_CTU
870 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
871 if (ADC_SAR_IP_INST_HAS_CTU(Instance))
872 {
873 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
874 Flags |= ((Isr & ADC_ISR_EOCTU_MASK) != 0U) ? ADC_SAR_IP_NOTIF_FLAG_CTU_EOC : 0U;
875 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
876 }
877 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
878 #endif /* ADC_SAR_IP_HAS_CTU */
879
880 return Flags;
881 }
882
883 #if ADC_SAR_IP_HAS_ADCLKSEL
884 /*FUNCTION*********************************************************************
885 *
886 * Function Name : Adc_Sar_GetADCLKSELValue
887 * Description : This function returns the value that ADCLKSEL field should
888 * have based on the input parameter.
889 *
890 *END*************************************************************************/
Adc_Sar_GetADCLKSELValue(Adc_Sar_Ip_ClockSelType ClockSel)891 static inline uint32 Adc_Sar_GetADCLKSELValue(Adc_Sar_Ip_ClockSelType ClockSel)
892 {
893 #if ADC_SAR_IP_HAS_CLKSEL_EXTENDED
894 return ADC_MCR_ADCLKSEL(ClockSel);
895 #else
896 uint32 Temp = 0u;
897 switch (ClockSel)
898 {
899 case ADC_SAR_IP_CLK_FULL_BUS:
900 /* Full bus clock when MCR[ADCLKSEL] = 1 */
901 Temp = ADC_MCR_ADCLKSEL(1U);
902 break;
903 case ADC_SAR_IP_CLK_HALF_BUS:
904 /* Half bus clock when MCR[ADCLKSEL] = 0 */
905 break;
906 default:
907 /* no-op */
908 break;
909 }
910 return Temp;
911 #endif /* ADC_SAR_IP_HAS_CLKSEL_EXTENDED */
912 }
913 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
914
915 /*FUNCTION*********************************************************************
916 *
917 * Function Name : Adc_Sar_CollectMcrMasks
918 * Description : The function collects the mask for MCR register from provided
919 * structure. The funcion is used to reduce the complexity of Adc_Sar_Ip_Init()
920 *
921 *END*************************************************************************/
Adc_Sar_CollectMcrMasks(const uint32 Instance,const Adc_Sar_Ip_ConfigType * const Config,uint32 InitialMcr)922 static inline uint32 Adc_Sar_CollectMcrMasks(const uint32 Instance,
923 const Adc_Sar_Ip_ConfigType * const Config,
924 uint32 InitialMcr)
925 {
926 uint32 Mcr = InitialMcr;
927
928 Mcr &= ~(ADC_MCR_MODE_MASK);
929 Mcr |= ADC_MCR_MODE(Config->ConvMode);
930 #if ADC_SAR_IP_HAS_ADCLKSEL
931 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK);
932 Mcr |= Adc_Sar_GetADCLKSELValue(Config->ClkSelect);
933 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
934 Mcr &= ~(ADC_MCR_ACKO_MASK);
935 Mcr |= Adc_Sar_GetValueFromBool(Config->AutoClockOff, ADC_MCR_ACKO_MASK, 0U);
936 Mcr &= ~(ADC_MCR_OWREN_MASK);
937 Mcr |= Adc_Sar_GetValueFromBool(Config->OverwriteEnable, ADC_MCR_OWREN_MASK, 0U);
938 Mcr &= ~(ADC_MCR_WLSIDE_MASK);
939 Mcr |= ADC_MCR_WLSIDE(Config->DataAlign);
940
941 #if ADC_SAR_IP_HAS_CTU
942 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
943 if (ADC_SAR_IP_INST_HAS_CTU(Instance))
944 {
945 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
946 Mcr &= ~(ADC_MCR_CTUEN_MASK | ADC_MCR_CTU_MODE_MASK); /* Clear CTU_MODE bit of MCR*/
947
948 switch (Config->CtuMode)
949 {
950 case ADC_SAR_IP_CTU_MODE_CONTROL:
951 Mcr |= ADC_MCR_CTUEN(1U); /* Enable CTU */
952 break;
953 #if ADC_SAR_IP_HAS_CTU_TRIGGER_MODE
954 case ADC_SAR_IP_CTU_MODE_TRIGGER:
955 Mcr |= ADC_MCR_CTU_MODE(1U); /* Set CTU to Trigger Mode CTU_MODE = 1 */
956 Mcr |= ADC_MCR_CTUEN(1U); /* Enable CTU */
957 break;
958 #endif /* ADC_SAR_IP_HAS_CTU_TRIGGER_MODE */
959 case ADC_SAR_IP_CTU_MODE_DISABLED:
960 /* CTU is disabled (CTUEN = 0 and CTU_MODE = 0) */
961 /* Pass through */
962 default:
963 ; /* no-op */
964 break;
965 }
966 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
967 }
968 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
969 #endif /* ADC_SAR_IP_HAS_CTU */
970 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
971 #if FEATURE_ADC_HAS_INJ_EXT_TRIGGER
972 switch (Config->InjectedEdge)
973 {
974 case ADC_SAR_IP_EXT_TRIG_EDGE_FALLING:
975 /* Already on falling edge JEDGE = 0 */
976 Mcr &= ~(ADC_MCR_JTRGEN_MASK);
977 Mcr |= ADC_MCR_JTRGEN_MASK; /* enable Injected trigger */
978 break;
979 case ADC_SAR_IP_EXT_TRIG_EDGE_RISING:
980 /* Enable Injected trigger and set to rising edge JEDGE = 1 */
981 Mcr &= ~(ADC_MCR_JEDGE_MASK | ADC_MCR_JTRGEN_MASK);
982 Mcr |= (ADC_MCR_JEDGE_MASK | ADC_MCR_JTRGEN_MASK);
983 break;
984 case ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED:
985 /* Already set to injected trigger disabled (JTRGEN = 0 and JEDGE = 0) */
986 default:
987 ; /* no-op */
988 break;
989 }
990 #endif /* FEATURE_ADC_HAS_INJ_EXT_TRIGGER */
991 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
992
993 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
994 #if FEATURE_ADC_HAS_EXT_TRIGGER
995 /* Get normal trigger masks */
996 Mcr &= ~(ADC_MCR_EDGE_MASK);
997 Mcr |= (Config->ExtTrigger == ADC_SAR_IP_EXT_TRIG_EDGE_RISING) ? (ADC_MCR_EDGE(1U)) : 0U;
998 if (Config->ExtTrigger != ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED)
999 {
1000 Mcr &= ~(ADC_MCR_TRGEN_MASK);
1001 Mcr |= Adc_Sar_GetValueFromBool(Config->NormalExtTrgEn, ADC_MCR_TRGEN_MASK, 0U);
1002 #if FEATURE_ADC_HAS_AUX_EXT_TRIGGER
1003 Mcr &= ~(ADC_MCR_XSTRTEN_MASK);
1004 Mcr |= Adc_Sar_GetValueFromBool(Config->NormalAuxExtTrgEn, ADC_MCR_XSTRTEN_MASK, 0U);
1005 #endif /* FEATURE_ADC_HAS_AUX_EXT_TRIGGER */
1006 }
1007 #endif /* FEATURE_ADC_HAS_EXT_TRIGGER */
1008 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
1009
1010 #if FEATURE_ADC_HAS_AVERAGING
1011 Mcr &= ~(ADC_MCR_AVGEN_MASK);
1012 Mcr |= Adc_Sar_GetValueFromBool(Config->AvgEn, ADC_MCR_AVGEN_MASK, 0U);
1013 Mcr &= ~(ADC_MCR_AVGS_MASK);
1014 Mcr |= ADC_MCR_AVGS(Config->AvgSel);
1015 #else
1016 #if FEATURE_ADC_HAS_CALIBRATION
1017 /* On platforms that use AVGEN only for calibration, reset to default value */
1018 Mcr |= ADC_MCR_AVGEN_MASK;
1019 #endif /* FEATURE_ADC_HAS_CALIBRATION */
1020 #endif /* FEATURE_ADC_HAS_AVERAGING */
1021
1022 #if FEATURE_ADC_HAS_CALIBRATION
1023 #if ADC_SAR_IP_CALIBRATION_USES_MCR
1024 /* Reset NRSMPL to default value */
1025 Mcr &= ~(ADC_MCR_NRSMPL_MASK);
1026 Mcr |= ADC_MCR_NRSMPL_MASK;
1027 #endif /* ADC_SAR_IP_CALIBRATION_USES_MCR */
1028 #endif /* FEATURE_ADC_HAS_CALIBRATION */
1029
1030 return Mcr;
1031 }
1032
1033
1034 /*FUNCTION*********************************************************************
1035 *
1036 * Function Name : Adc_Sar_ConfigChannels
1037 * Description : Configure a list of channels by enabling channel notifications
1038 * and setting presampling.
1039 *END*************************************************************************/
Adc_Sar_ConfigChannels(const uint32 Instance,const Adc_Sar_Ip_ChanConfigType * ChannelConfigsPtr,uint8 NumChannels)1040 static inline void Adc_Sar_ConfigChannels(const uint32 Instance,
1041 const Adc_Sar_Ip_ChanConfigType * ChannelConfigsPtr,
1042 uint8 NumChannels)
1043 {
1044 uint8 Index;
1045 uint32 VectAdr;
1046 uint32 VectBit;
1047 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1048 uint32 CimrMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1049 #else
1050 const uint32 CimrMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1051 #endif
1052 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1053 uint32 CwenrMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1054 #else
1055 const uint32 CwenrMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1056 #endif
1057 uint32 DmarMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1058 #if FEATURE_ADC_HAS_PRESAMPLING
1059 uint32 PsrMask[ADC_SAR_IP_NUM_GROUP_CHAN] = ADC_SAR_IP_NUM_GROUP_CHAN_INIT_VAL;
1060 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
1061 const Adc_Sar_Ip_ChanConfigType * ChnConfig;
1062
1063 ADC_Type * AdcBasePtr = NULL_PTR;
1064 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1065 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1066 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1067
1068 for (Index = 0U; Index < NumChannels; Index++)
1069 {
1070 ChnConfig = &(ChannelConfigsPtr[Index]);
1071 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1072 /* Each CWSELR register contains 8 watchdog selections according to 8 channels
1073 Each watchdog selection possibly needs maximum 4 bits for setting
1074 This is to calculate the CWSELR register index and position of channel on that register */
1075 VectAdr = (uint32)ChnConfig->ChanIndex / 8U;
1076 VectBit = (uint32)ChnConfig->ChanIndex % 8U;
1077 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
1078 if (ADC_SAR_IP_INST_HAS_CWSELRn(Instance, VectAdr))
1079 {
1080 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
1081 Adc_Sar_WriteChannelMapping(Instance, VectAdr, VectBit, ChnConfig->WdgThreshRegIndex);
1082 /* Store threshold register index for configured channel */
1083 Adc_Sar_Ip_axAdcSarState[Instance].ChanWdgThresholdIndex[ChnConfig->ChanIndex] = ChnConfig->WdgThreshRegIndex;
1084 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
1085 }
1086 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
1087 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1088
1089 VectAdr = ADC_SAR_IP_CHAN_2_VECT((uint32)ChnConfig->ChanIndex);
1090 VectBit = ADC_SAR_IP_CHAN_2_BIT((uint32)ChnConfig->ChanIndex);
1091 /* Collect bit-mask for WDG, EOC, DMA and Presample */
1092 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1093 CimrMask[VectAdr] |= Adc_Sar_GetValueFromBool(ChnConfig->EndOfConvNotification, (1UL << VectBit), 0UL);
1094 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1095 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1096 CwenrMask[VectAdr] |= Adc_Sar_GetValueFromBool(ChnConfig->WdgNotificationEn, (1UL << VectBit), 0UL);
1097 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1098 DmarMask[VectAdr] |= Adc_Sar_GetValueFromBool(ChnConfig->EndOfConvDmaEnable, (1UL << VectBit), 0UL);
1099 #if FEATURE_ADC_HAS_PRESAMPLING
1100 PsrMask[VectAdr] |= Adc_Sar_GetValueFromBool(ChnConfig->PresamplingEnable, (1UL << VectBit), 0UL);
1101 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
1102 }
1103
1104 /* Enable WDG, EOC, DMA and Presample */
1105 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
1106 {
1107 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1108 if (Instance >= ADC_INSTANCE_COUNT)
1109 {
1110 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1111 CIMR(AdcAEBasePtr, Index) = CimrMask[Index];
1112 CWENR(AdcAEBasePtr, Index) = CwenrMask[Index];
1113 DMAR(AdcAEBasePtr, Index) = DmarMask[Index];
1114 #if FEATURE_ADC_HAS_PRESAMPLING
1115 PSR(AdcAEBasePtr, Index) = PsrMask[Index];
1116 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
1117 }
1118 else
1119 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1120 {
1121 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1122 CIMR(AdcBasePtr, Index) = CimrMask[Index];
1123 CWENR(AdcBasePtr, Index) = CwenrMask[Index];
1124 DMAR(AdcBasePtr, Index) = DmarMask[Index];
1125 #if FEATURE_ADC_HAS_PRESAMPLING
1126 PSR(AdcBasePtr, Index) = PsrMask[Index];
1127 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
1128 }
1129 }
1130 }
1131
1132 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
1133 /*FUNCTION*********************************************************************
1134 *
1135 * Function Name : Adc_Sar_CheckSelfTestProgress
1136 * Description : Configures watchdog threshold with provided array of configuration
1137 *
1138 *END*************************************************************************/
Adc_Sar_CheckSelfTestProgress(const uint32 Instance)1139 static inline Adc_Sar_Ip_StatusType Adc_Sar_CheckSelfTestProgress(const uint32 Instance)
1140 {
1141 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
1142 uint32 Reg = 0U;
1143 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
1144 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
1145 uint32 ElapsedTicks;
1146 volatile const uint32 * MSRAddr = NULL_PTR;
1147 volatile const uint32 * STSR1Addr = NULL_PTR;
1148 uint8 Index;
1149
1150 const ADC_Type * AdcBasePtr = NULL_PTR;
1151 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1152 const SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1153 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1154
1155 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1156 if (Instance >= ADC_INSTANCE_COUNT)
1157 {
1158 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1159 MSRAddr = (volatile const uint32 *)&(AdcAEBasePtr->MSR);
1160 STSR1Addr = &(AdcAEBasePtr->STSR1);
1161 }
1162 else
1163 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1164 {
1165 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1166 MSRAddr = (volatile const uint32 *)&(AdcBasePtr->MSR);
1167 STSR1Addr = &(AdcBasePtr->STSR1);
1168 }
1169
1170 /* Each for loop checks the conversion of all steps in self-test S algorithm
1171 * ForLoop(0): while (AlgS-start-1) ->S0 -> S1 -> S2 -> while (Alg-end-1) -> C0 to C11 ->
1172 * ForLoop(1): while (AlgS-start-2) ->S0 -> S1 -> S2 -> while (Alg-end-2)
1173 */
1174 for (Index = 0U; Index < 2U; Index++)
1175 {
1176 /* Wait until Alg S has started*/
1177 ElapsedTicks = 0U;
1178 while ((((*MSRAddr) & ADC_MSR_SELF_TEST_S_MASK) != ADC_MSR_SELF_TEST_S_MASK) && (ElapsedTicks < TimeoutTicks))
1179 {
1180 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
1181 }
1182 if (ElapsedTicks >= TimeoutTicks)
1183 {
1184 Status = ADC_SAR_IP_STATUS_TIMEOUT;
1185 }
1186 if (Status == ADC_SAR_IP_STATUS_SUCCESS)
1187 {
1188 /* Wait until Alg S has finished*/
1189 ElapsedTicks = 0U;
1190 while ((((*MSRAddr) & ADC_MSR_SELF_TEST_S_MASK) == ADC_MSR_SELF_TEST_S_MASK) && (ElapsedTicks < TimeoutTicks))
1191 {
1192 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
1193 }
1194 if (ElapsedTicks >= TimeoutTicks)
1195 {
1196 Status = ADC_SAR_IP_STATUS_TIMEOUT;
1197 }
1198 }
1199 if (Status == ADC_SAR_IP_STATUS_TIMEOUT)
1200 {
1201 /* Break the loop if timeout occured in order to increase performance */
1202 break;
1203 }
1204 }
1205
1206 if (Status != ADC_SAR_IP_STATUS_TIMEOUT)
1207 {
1208 Reg |= ADC_STSR1_ERR_S0_MASK;
1209 #if (defined(ADC_STSR1_ERR_S1_MASK) || defined(ADC_STSR1_ERR_S2_MASK) || defined(ADC_STSR1_ERR_C_MASK))
1210 Reg |= ADC_STSR1_ERR_S1_MASK | ADC_STSR1_ERR_S2_MASK | ADC_STSR1_ERR_C_MASK;
1211 #endif
1212 if (((*STSR1Addr) & Reg) != 0UL)
1213 {
1214 Status = ADC_SAR_IP_STATUS_ERROR;
1215 }
1216 }
1217
1218 return Status;
1219 }
1220 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
1221 /*FUNCTION*********************************************************************
1222 *
1223 * Function Name : Adc_Sar_GetConvResults
1224 * Description : Reads the conversion results to output arrays
1225 * Params:
1226 * - Instance : the ADC Instance to read
1227 * - ChainType : the conversion chain (Normal, Injected or CTU)
1228 * - ResultsRaw : an uint16 array to write only conversion data
1229 * - ResultsStruct : an Adc_Sar_Ip_ChanResultType array to write detailed information
1230 about each conversion result
1231 * - length : the maximum size of ResultsRaw and ResultsStruct
1232 *
1233 * ResultsRaw or ResultsStruct can be NULL, but not both, as the function will
1234 * have nowhere to write the results.
1235 *
1236 *END*************************************************************************/
Adc_Sar_GetConvResults(const uint32 Instance,const Adc_Sar_Ip_ConvChainType ChainType,uint16 * const ResultsRaw,Adc_Sar_Ip_ChanResultType * const ResultsStruct,const uint32 Length)1237 static uint32 Adc_Sar_GetConvResults(const uint32 Instance,
1238 const Adc_Sar_Ip_ConvChainType ChainType,
1239 uint16 * const ResultsRaw,
1240 Adc_Sar_Ip_ChanResultType * const ResultsStruct,
1241 const uint32 Length)
1242 {
1243 uint32 Index = 0u;
1244 boolean LengthExceeded = FALSE;
1245 ADC_Type * AdcBasePtr = NULL_PTR;
1246 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1247 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1248 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1249 uint32 VectAdr;
1250 uint32 VectBit;
1251 uint8 ChnIdx;
1252 uint32 Cdr;
1253 volatile uint32 * CEOCFRAddr = NULL_PTR;
1254 const uint16 AdcChanCount[ADC_SAR_IP_INSTANCE_COUNT][ADC_SAR_IP_NUM_GROUP_CHAN] = FEATURE_ADC_MAX_CHN_COUNT;
1255
1256 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1257 if (Instance >= ADC_INSTANCE_COUNT)
1258 {
1259 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1260 }
1261 else
1262 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1263 {
1264 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1265 }
1266 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
1267 /* ResultsRaw and ResultsStruct cannot be both NULL */
1268 DevAssert((ResultsRaw != NULL_PTR) || (ResultsStruct != NULL_PTR));
1269 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
1270
1271 /* Go through each channel group */
1272 for (VectAdr = 0u; VectAdr < Adc_Sar_Ip_au8AdcGroupCount[Instance]; VectAdr++)
1273 {
1274 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1275 if (Instance >= ADC_INSTANCE_COUNT)
1276 {
1277 CEOCFRAddr = &(CEOCFR(AdcAEBasePtr, VectAdr));
1278 }
1279 else
1280 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1281 {
1282 CEOCFRAddr = &(CEOCFR(AdcBasePtr, VectAdr));
1283 }
1284 /* go through each bit in the group, check if there is a completed conversion */
1285 for (VectBit = 0u; VectBit < AdcChanCount[Instance][VectAdr]; VectBit++)
1286 {
1287 ChnIdx = (uint8)((VectAdr * 32u) + VectBit);
1288 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
1289 if ((0u == ChnIdx) && ((ADC_SAR_IP_CONV_CHAIN_INJECTED == ChainType) || (ADC_SAR_IP_CONV_CHAIN_CTU == ChainType)))
1290 {
1291 continue;
1292 }
1293 #endif /* FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND */
1294 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
1295 if (!(ADC_SAR_IP_INST_HAS_CDRn(Instance, ChnIdx)))
1296 {
1297 continue; /* skip if the CDR register is not available */
1298 }
1299 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
1300 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1301 if (Instance >= ADC_INSTANCE_COUNT)
1302 {
1303 Cdr = CDR_AE(AdcAEBasePtr, ChnIdx);
1304 }
1305 else
1306 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1307 {
1308 Cdr = CDR(AdcBasePtr, ChnIdx);
1309 }
1310
1311 if ((ADC_CDR_RESULT((uint32)ChainType) | ADC_CDR_VALID_MASK) == (Cdr & (ADC_CDR_RESULT_MASK | ADC_CDR_VALID_MASK)))
1312 {
1313 /* if the result type matches the one request by ChainType
1314 and the data is valid, write to the output array(s)
1315 */
1316 if (ResultsRaw != NULL_PTR)
1317 {
1318 ResultsRaw[Index] = Adc_Sar_GetMaskedResult(Instance, Cdr);
1319 }
1320 if (ResultsStruct != NULL_PTR)
1321 {
1322 ResultsStruct[Index].ConvData = Adc_Sar_GetMaskedResult(Instance, Cdr);
1323 ResultsStruct[Index].AdcChnIdx = ChnIdx;
1324 ResultsStruct[Index].ValidFlag = ((Cdr & ADC_CDR_VALID_MASK) != 0U) ? TRUE : FALSE;
1325 ResultsStruct[Index].OverWrittenFlag = ((Cdr & ADC_CDR_OVERW_MASK) != 0U) ? TRUE : FALSE;
1326 }
1327 /* Increment the current Index and reset the CEOCFR flag */
1328 *CEOCFRAddr = ((uint32)1UL << VectBit); /* w1c bit */
1329 Index++;
1330 if (Index >= Length)
1331 {
1332 /* We have filled the output buffer, exit the loop.
1333 * Data may still exist in the result registers, which won't be reached.
1334 */
1335 LengthExceeded = TRUE;
1336 break;
1337 }
1338 }
1339 }
1340 if (LengthExceeded)
1341 {
1342 break;
1343 }
1344 }
1345 return Index;
1346 }
1347
1348 /*FUNCTION*********************************************************************
1349 *
1350 * Function Name : Adc_Sar_ResetWdog
1351 * Description : Reset and disable the Analog Watchdog feature
1352 *
1353 *END*************************************************************************/
Adc_Sar_ResetWdog(const uint32 Instance)1354 static void Adc_Sar_ResetWdog(const uint32 Instance)
1355 {
1356 uint8 Index;
1357 uint8 MaxThresholdRegs = 0U;
1358
1359 ADC_Type * AdcBasePtr = NULL_PTR;
1360 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1361 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1362 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1363
1364 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1365 if (Instance >= ADC_INSTANCE_COUNT)
1366 {
1367 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1368 MaxThresholdRegs = ADC_SAR_AE_IP_THRHLR_COUNT;
1369 }
1370 else
1371 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1372 {
1373 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1374 MaxThresholdRegs = ADC_SAR_IP_THRHLR_COUNT;
1375 }
1376
1377 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
1378 {
1379 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1380 if (Instance >= ADC_INSTANCE_COUNT)
1381 {
1382 CWENR(AdcAEBasePtr, Index) = 0u;
1383 AWORR(AdcAEBasePtr, Index) = 0xFFFFFFFFu; /* w1c bits */
1384 }
1385 else
1386 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1387 {
1388 CWENR(AdcBasePtr, Index) = 0u;
1389 AWORR(AdcBasePtr, Index) = 0xFFFFFFFFu; /* w1c bits */
1390 }
1391
1392 }
1393
1394 for (Index = 0u; Index < MaxThresholdRegs; Index++)
1395 {
1396 Adc_Sar_WriteThresholds(Instance, Index, 0xFFFFu, 0u);
1397 }
1398
1399 for (Index = 0u; Index < ADC_SAR_IP_CWSELR_COUNT; Index++)
1400 {
1401 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
1402 if (!(ADC_SAR_IP_INST_HAS_CWSELRn(Instance, Index)))
1403 {
1404 continue; /* skip register if it's not available */
1405 }
1406 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
1407 Adc_Sar_ResetWdogCWSELR(Instance, Index);
1408 }
1409 }
1410
1411 #if FEATURE_ADC_HAS_CLOCK_DIVIDER
1412 /*FUNCTION*********************************************************************
1413 *
1414 * Function Name : Adc_Sar_EnableClkDiv
1415 * Description : Configure clock divider
1416 *
1417 *END*************************************************************************/
Adc_Sar_EnableClkDiv(const uint32 Instance,const boolean ClkDivEnable)1418 static inline void Adc_Sar_EnableClkDiv(const uint32 Instance,
1419 const boolean ClkDivEnable)
1420 {
1421 ADC_Type * const AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1422
1423 /* Enable clock divider */
1424 if (ClkDivEnable)
1425 {
1426 AdcBasePtr->CLKDIV_CTRL |= ADC_CLKDIV_CTRL_CLKDIV_ENABLE(1U);
1427 }
1428 else
1429 {
1430 AdcBasePtr->CLKDIV_CTRL &= ~(ADC_CLKDIV_CTRL_CLKDIV_ENABLE_MASK);
1431 }
1432 }
1433 #endif /* FEATURE_ADC_HAS_CLOCK_DIVIDER */
1434
1435 #if ( \
1436 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || (STD_ON == ADC_SAR_IP_JECH_ENABLED) || \
1437 ((ADC_SAR_IP_HAS_CTU == 1U) && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) && (STD_ON == ADC_SAR_IP_EOC_ENABLED)) \
1438 )
1439 /*FUNCTION*********************************************************************
1440 *
1441 * Function Name : Adc_Sar_CheckAndCallNotification
1442 * Description : Checks if the given callback is not NULL then calls it
1443 *
1444 *END*************************************************************************/
Adc_Sar_CheckAndCallNotification(void (* Callback)(void))1445 static inline void Adc_Sar_CheckAndCallNotification(void (*Callback)(void))
1446 {
1447 if (Callback != NULL_PTR)
1448 {
1449 Callback();
1450 }
1451 }
1452 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) .. */
1453
1454 #if (ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) && (STD_ON == ADC_SAR_IP_EOC_ENABLED))
Adc_Sar_CheckAndCallEoctuNotification(const uint32 Instance)1455 static inline void Adc_Sar_CheckAndCallEoctuNotification(const uint32 Instance)
1456 {
1457 volatile const uint32 * CIMRBaseAddr;
1458 volatile uint32 * CEOCFBaseRAddr;
1459 volatile uint32 * ISRAddr;
1460 uint32 Imr; /* Interrupt mask */
1461 uint32 Cimr; /* Channel Interrupt Mask */
1462 uint32 Ceocfr; /* Channel Pending Flag*/
1463 uint32 ChannelValidMask;
1464 boolean ValidInterrupt = FALSE;
1465 uint32 GroupIdx;
1466 ADC_Type * AdcBasePtr;
1467 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1468 SAR_ADC_AE_Type * AdcAEBasePtr;
1469
1470 if (Instance >= ADC_INSTANCE_COUNT)
1471 {
1472 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1473 CEOCFBaseRAddr = &(CEOCFR(AdcAEBasePtr, 0U));
1474 CIMRBaseAddr = &(CIMR(AdcAEBasePtr, 0U));
1475 ISRAddr = (volatile uint32 *)&(AdcAEBasePtr->ISR);
1476 Imr = AdcAEBasePtr->IMR;
1477 }
1478 else
1479 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1480 {
1481 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1482 CEOCFBaseRAddr = &(CEOCFR(AdcBasePtr, 0U));
1483 CIMRBaseAddr = &(CIMR(AdcBasePtr, 0U));
1484 ISRAddr = (volatile uint32 *)&(AdcBasePtr->ISR);
1485 Imr = AdcBasePtr->IMR;
1486 }
1487
1488 if ( ((*ISRAddr & ADC_ISR_EOCTU_MASK) != 0U) && ((Imr & ADC_IMR_MSKEOCTU_MASK) != 0U) )
1489 {
1490 for (GroupIdx = 0U; GroupIdx < Adc_Sar_Ip_au8AdcGroupCount[Instance]; GroupIdx++)
1491 {
1492 ChannelValidMask = Adc_Sar_Ip_au32AdcChanBitmap[Instance][GroupIdx];
1493 /* Read channels interrupt mask and status in this group */
1494 Cimr = CIMRBaseAddr[GroupIdx] & ChannelValidMask;
1495 Ceocfr = CEOCFBaseRAddr[GroupIdx] & ChannelValidMask;
1496 /* CPR_RTD_00644: Check if the interrupt is spurious or not (both enabled and flag bits are set) */
1497 if ((Ceocfr & Cimr) != 0U)
1498 {
1499 /* Clears flag by w1c */
1500 CEOCFBaseRAddr[GroupIdx] = Ceocfr;
1501 ValidInterrupt = TRUE;
1502 /* Continue to check and clear pending flags for the rest of channel groups.
1503 Because the EOC events of channels might be consecutively issued very fast.
1504 For instance:
1505 - While ISR handler is processing EOC event of a channel
1506 - other channels might complete their conversions and raise the interrupt requests.
1507 Therefore, we should clear all the individual channel flags (CEOCFR) along with the CTU flag ISR[EOCTU].
1508 */
1509 }
1510 }
1511
1512 if (ValidInterrupt)
1513 {
1514 /* CPR_RTD_00644 */
1515 *ISRAddr = ADC_ISR_EOCTU_MASK;
1516 Adc_Sar_CheckAndCallNotification(Adc_Sar_Ip_axAdcSarState[Instance].EndOfCtuConversionNotification);
1517 }
1518 }
1519 }
1520 #endif /* (ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) && (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
1521
1522 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1523 /*FUNCTION*********************************************************************
1524 *
1525 * Function Name : Adc_Sar_CheckAndCallEocNotification
1526 * Description : Checks if the given channel interrupt was triggered, clears
1527 * the interrupt, check if it is not spurious, checks that the
1528 * callback is not null.
1529 *
1530 *END*************************************************************************/
Adc_Sar_CheckAndCallEocNotification(uint32 Instance,uint16 ChanIdx,uint16 VectAdr,uint32 EocFlag,boolean * CeocfrFlag)1531 static inline void Adc_Sar_CheckAndCallEocNotification(uint32 Instance,
1532 uint16 ChanIdx,
1533 uint16 VectAdr,
1534 uint32 EocFlag,
1535 boolean * CeocfrFlag)
1536 {
1537 ADC_Type * AdcBasePtr = NULL_PTR;
1538 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1539 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1540 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1541 const uint32 Mask = (uint32)1UL << ADC_SAR_IP_CHAN_2_BIT(ChanIdx);
1542 uint32 Ceocfr = 0U;
1543 uint32 Cimr = 0U;
1544 volatile uint32 * CEOCFRAddr = NULL_PTR;
1545
1546 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1547 if (Instance >= ADC_INSTANCE_COUNT)
1548 {
1549 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1550 CEOCFRAddr = &(CEOCFR(AdcAEBasePtr, VectAdr));
1551 Cimr = (CIMR(AdcAEBasePtr, VectAdr) & Mask);
1552 }
1553 else
1554 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1555 {
1556 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1557 CEOCFRAddr = &(CEOCFR(AdcBasePtr, VectAdr));
1558 Cimr = (CIMR(AdcBasePtr, VectAdr) & Mask);
1559 }
1560
1561 Ceocfr = ((*CEOCFRAddr) & Mask);
1562 /* Check if the interrupt was not spurious */
1563 if ((Ceocfr != 0U) && (Cimr != 0U) && (EocFlag != 0U))
1564 {
1565 /* Clears flag by w1c */
1566 *CEOCFRAddr = Mask;
1567 *CeocfrFlag = TRUE;
1568
1569 /* Check if the callback is not null */
1570 if (Adc_Sar_Ip_axAdcSarState[Instance].EndOfConvNotification != NULL_PTR)
1571 {
1572 Adc_Sar_Ip_axAdcSarState[Instance].EndOfConvNotification(ChanIdx);
1573 }
1574 }
1575 }
1576 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1577
1578 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1579 /*FUNCTION*********************************************************************
1580 *
1581 * Function Name : Adc_Sar_CheckAndCallWorrNotification
1582 * Description : Checks if the given channel interrupt was triggered, clears
1583 * the interrupt, check if it is not spurious, checks that the
1584 * callback is not null and return WTISR flag
1585 * in order to be cleared outside of this function when loop of all channels is completed.
1586 *
1587 *END*************************************************************************/
Adc_Sar_CheckAndCallWorrNotification(uint32 Instance,uint16 ChanIdx,uint16 VectAdr)1588 static inline uint32 Adc_Sar_CheckAndCallWorrNotification(uint32 Instance,
1589 uint16 ChanIdx,
1590 uint16 VectAdr)
1591 {
1592 ADC_Type * AdcBasePtr = NULL_PTR;
1593 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1594 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1595 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1596 const uint32 Mask = (uint32)1UL << ADC_SAR_IP_CHAN_2_BIT(ChanIdx);
1597 uint32 Aworr = 0U;
1598 uint32 Cwenr = 0U;
1599 uint32 Wtisr = 0U;
1600 uint32 Wtimr = 0U;
1601 uint32 WdgFlags = 0U;
1602 /* Use 16-bit width instead of 32-bit to avoid CWE INTEGER_OVERFLOW when performing multiplication in macros ADC_SAR_IP_WDG_REG_MASK below */
1603 uint16 ThresholdIndex;
1604 volatile uint32 * AWORRAddr;
1605
1606 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1607 if (Instance >= ADC_INSTANCE_COUNT)
1608 {
1609 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1610 AWORRAddr = &(AWORR(AdcAEBasePtr, VectAdr));
1611 Cwenr = (CWENR(AdcAEBasePtr, VectAdr) & Mask);
1612 Wtisr = AdcAEBasePtr->WTISR;
1613 Wtimr = AdcAEBasePtr->WTIMR;
1614 }
1615 else
1616 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1617 {
1618 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1619 AWORRAddr = &(AWORR(AdcBasePtr, VectAdr));
1620 Cwenr = (CWENR(AdcBasePtr, VectAdr) & Mask);
1621 Wtisr = AdcBasePtr->WTISR;
1622 Wtimr = AdcBasePtr->WTIMR;
1623 }
1624 Aworr = ((*AWORRAddr) & Mask);
1625
1626 /* Check if wdg channel enabled associated to the wdg out of range flag */
1627 if ((Aworr != 0U) && (Cwenr != 0U))
1628 {
1629 /* Get the mapping threshold register index corresponding to the configured channel */
1630 ThresholdIndex = (uint16)(Adc_Sar_Ip_axAdcSarState[Instance].ChanWdgThresholdIndex[ChanIdx]);
1631
1632 /* Check if the high/low flags were not set spuriously. */
1633 if ((Wtimr & (ADC_SAR_IP_WDG_REG_MASK_LOW(ThresholdIndex))) != 0u)
1634 {
1635 WdgFlags |= ((Wtisr & ADC_SAR_IP_WDG_REG_MASK_LOW(ThresholdIndex)) != 0u) ? ADC_SAR_IP_WDG_LOW_FLAG : 0u;
1636 }
1637 if ((Wtimr & (ADC_SAR_IP_WDG_REG_MASK_HIGH(ThresholdIndex))) != 0u)
1638 {
1639 WdgFlags |= ((Wtisr & ADC_SAR_IP_WDG_REG_MASK_HIGH(ThresholdIndex)) != 0u) ? ADC_SAR_IP_WDG_HIGH_FLAG : 0u;
1640 }
1641 if (WdgFlags != 0u)
1642 {
1643 /* Only clear relevant flags if interrupt is not spurious (i.e: satisfy combination of AWORR-CWENR and WTISR-WTIMR) */
1644 *AWORRAddr = Mask;
1645 /* Multiple ADC channels can use same THRHLRx so return the associated WTISR flag value of that threshold
1646 which will be used for clearing all WTISR flags outside of this function, when completing the loop for ADC channels */
1647 WdgFlags = (uint32)(WdgFlags << (ThresholdIndex << 1U));
1648 /* Check if the callback is not null */
1649 if (Adc_Sar_Ip_axAdcSarState[Instance].WdgOutOfRangeNotification != NULL_PTR)
1650 {
1651 Adc_Sar_Ip_axAdcSarState[Instance].WdgOutOfRangeNotification(ChanIdx, WdgFlags);
1652 }
1653 }
1654 }
1655
1656 return WdgFlags;
1657 }
1658 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1659
1660 #if ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED))
1661 /*LOCAL FUNCTION*********************************************************************
1662 *
1663 * Function Name : Adc_CheckAndCallAllChannelNotification
1664 * Description : Check for all watchdog interrupts and for all individual channel interrupts
1665 * if it was detected. And then call the appropriate notification
1666 *
1667 *END*********************************************************************************/
Adc_CheckAndCallAllChannelNotification(const uint32 Instance)1668 static inline void Adc_CheckAndCallAllChannelNotification(const uint32 Instance)
1669 {
1670 ADC_Type * AdcBasePtr = NULL_PTR;
1671 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1672 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1673 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1674 uint16 VectAdr;
1675 uint16 PhyChan;
1676 uint16 ChanCnt;
1677 const uint16 AdcChanCount[ADC_SAR_IP_INSTANCE_COUNT][ADC_SAR_IP_NUM_GROUP_CHAN] = FEATURE_ADC_MAX_CHN_COUNT;
1678 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1679 uint32 WtisrMask = 0U;
1680 volatile uint32 * WTISRAddr = NULL_PTR;
1681 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1682 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1683 volatile const uint32 * IMRAddr = NULL_PTR;
1684 volatile uint32 * ISRAddr = NULL_PTR;
1685 uint32 EocFlag = 0U;
1686 boolean CeocfrFlag = FALSE;
1687 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1688
1689 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1690 if (Instance >= ADC_INSTANCE_COUNT)
1691 {
1692 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1693 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1694 IMRAddr = (volatile uint32 *)&(AdcAEBasePtr->IMR);
1695 ISRAddr = (volatile uint32 *)&(AdcAEBasePtr->ISR);
1696 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1697 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1698 WTISRAddr = (volatile uint32 *)&(AdcAEBasePtr->WTISR);
1699 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1700 }
1701 else
1702 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1703 {
1704 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1705 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1706 IMRAddr = (volatile uint32 *)&(AdcBasePtr->IMR);
1707 ISRAddr = (volatile uint32 *)&(AdcBasePtr->ISR);
1708 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1709 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1710 WTISRAddr = (volatile uint32 *)&(AdcBasePtr->WTISR);
1711 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1712 }
1713 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1714 /* EocFlag = 0 if all EOC flags are spurious interrupts */
1715 /* Avoid Compiler Warning about accessing two volatile variables simultaneously */
1716 EocFlag = (*IMRAddr);
1717 EocFlag &= (*ISRAddr);
1718 EocFlag &= (ADC_ISR_EOC_MASK | ADC_ISR_JEOC_MASK);
1719
1720 /* Clear EOC Flag */
1721 if (EocFlag != 0)
1722 {
1723 *ISRAddr = EocFlag;
1724 }
1725 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1726
1727 for (VectAdr = 0U; VectAdr < Adc_Sar_Ip_au8AdcGroupCount[Instance]; VectAdr++)
1728 {
1729 for (ChanCnt = 0U; ChanCnt < AdcChanCount[Instance][VectAdr]; ChanCnt++)
1730 {
1731 PhyChan = (ChanCnt + (uint16)(ADC_SAR_IP_HW_REG_SIZE * VectAdr));
1732
1733 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
1734 /* Check end of conversion interrupt */
1735 Adc_Sar_CheckAndCallEocNotification(Instance, PhyChan, VectAdr, EocFlag, &CeocfrFlag);
1736 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
1737
1738 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1739 /* Check watchdog out of range interrupt */
1740 WtisrMask |= Adc_Sar_CheckAndCallWorrNotification(Instance, PhyChan, VectAdr);
1741 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1742 }
1743 }
1744
1745 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
1746 if (WtisrMask != 0U)
1747 {
1748 *WTISRAddr = WtisrMask;
1749 }
1750 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
1751 }
1752 #endif /* ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
1753
1754 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
1755 #if (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER)
1756 /*FUNCTION**********************************************************************
1757 *
1758 * Function Name : Adc_Sar_ConfigExternalTrigger
1759 * Description : This function configures the external trigger.
1760 *
1761 * END**************************************************************************/
Adc_Sar_ConfigExternalTrigger(const uint32 Instance,const Adc_Sar_Ip_ExtTriggerEdgeType TriggerEdge,const uint32 TrgEdgeSetMask,const uint32 TrgEdgeClrMask,const uint32 TrigSrcMask)1762 static inline void Adc_Sar_ConfigExternalTrigger(const uint32 Instance,
1763 const Adc_Sar_Ip_ExtTriggerEdgeType TriggerEdge,
1764 const uint32 TrgEdgeSetMask,
1765 const uint32 TrgEdgeClrMask,
1766 const uint32 TrigSrcMask)
1767 {
1768 ADC_Type * AdcBasePtr = NULL_PTR;
1769 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1770 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1771 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1772 volatile uint32 * MCRAddr = NULL_PTR;
1773
1774 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
1775 /* calibration must not be interrupted */
1776 if(FALSE == Adc_Sar_Ip_axAdcSarState[Instance].CalibrationOnGoing)
1777 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
1778 {
1779 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1780 if (Instance >= ADC_INSTANCE_COUNT)
1781 {
1782 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1783 MCRAddr = (volatile uint32 *)&(AdcAEBasePtr->MCR);
1784 }
1785 else
1786 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1787 {
1788 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1789 MCRAddr = (volatile uint32 *)&(AdcBasePtr->MCR);
1790 }
1791 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_21();
1792
1793 switch (TriggerEdge)
1794 {
1795 case ADC_SAR_IP_EXT_TRIG_EDGE_FALLING:
1796 *MCRAddr &= ~TrgEdgeSetMask; /* set to falling edge 0 */
1797 *MCRAddr |= TrigSrcMask; /* enable external trigger */
1798 break;
1799 case ADC_SAR_IP_EXT_TRIG_EDGE_RISING:
1800 /* enable external trigger and set to rising edge EDGE = 1 */
1801 *MCRAddr |= (TrgEdgeSetMask | TrigSrcMask);
1802 break;
1803 case ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED:
1804 /* disable external trigger and reset edge field */
1805 *MCRAddr &= ~(TrgEdgeClrMask | TrigSrcMask);
1806 break;
1807 default:
1808 ; /* no-op */
1809 break;
1810 }
1811 }
1812 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_21();
1813 }
1814 #endif /* (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER) */
1815 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
1816
1817 #if ADC_SAR_IP_HAS_TEMPSENSE_CHN
1818 #if (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON)
1819 /*FUNCTION**********************************************************************
1820 *
1821 * Function Name : Adc_Sar_TempsenseConvFp2Int
1822 * Description : The function converts the number in signed fixed point format
1823 * (1,11,4) to the integer number multipled with ADC_SAR_IP_TEMPSENSE_MULTIPLIER to avoid
1824 * rounding the decimal part.
1825 *
1826 *END**************************************************************************/
Adc_Sar_TempsenseConvFp2Int(const uint32 FloatingPoint)1827 static inline uint32 Adc_Sar_TempsenseConvFp2Int(const uint32 FloatingPoint)
1828 {
1829 uint32 RetVal;
1830
1831 /* The integer and decimal part multiple with ADC_SAR_IP_TEMPSENSE_MULTIPLIER to avoid rounding the decimal part */
1832 RetVal = ((FloatingPoint & ADC_SAR_IP_TEMPSENSE_INTEGER_MASK) >> ADC_SAR_IP_TEMPSENSE_INTEGER_SHIFT) * ADC_SAR_IP_TEMPSENSE_MULTIPLIER;
1833 RetVal += ((FloatingPoint & ADC_SAR_IP_TEMPSENSE_DECIMAL_MASK) * ADC_SAR_IP_TEMPSENSE_MULTIPLIER) / (ADC_SAR_IP_TEMPSENSE_DECIMAL_MASK + 1U);
1834
1835 return RetVal;
1836 }
1837
1838 /*FUNCTION**********************************************************************
1839 *
1840 * Function Name : Adc_Sar_TempsenseConvInt2Fp
1841 * Description : The function converts the number in integer number to signed fixed
1842 * point format (1,11,4). The integer number parameter is multipled with ADC_SAR_IP_TEMPSENSE_MULTIPLIER
1843 *
1844 *END**************************************************************************/
Adc_Sar_TempsenseConvInt2Fp(const sint32 SignedInteger)1845 static inline uint16 Adc_Sar_TempsenseConvInt2Fp(const sint32 SignedInteger)
1846 {
1847 uint16 RetVal;
1848 uint32 Temp;
1849
1850 if (SignedInteger < 0)
1851 {
1852 RetVal = ADC_SAR_IP_TEMPSENSE_SIGN_MASK;
1853 Temp = (uint32)(- SignedInteger);
1854 }
1855 else
1856 {
1857 RetVal = 0U;
1858 Temp = (uint32)SignedInteger;
1859 }
1860
1861 /* Calculates the integer part */
1862 RetVal |= (uint16)(((Temp / ADC_SAR_IP_TEMPSENSE_MULTIPLIER) << ADC_SAR_IP_TEMPSENSE_INTEGER_SHIFT) & ADC_SAR_IP_TEMPSENSE_INTEGER_MASK);
1863 /* Calculates the decimal part */
1864 RetVal |= (uint16)(((Temp % ADC_SAR_IP_TEMPSENSE_MULTIPLIER) * (ADC_SAR_IP_TEMPSENSE_DECIMAL_MASK + 1U)) / ADC_SAR_IP_TEMPSENSE_MULTIPLIER);
1865
1866 return RetVal;
1867 }
1868 #endif /* (ADC_SAR_IP_TEMPSENSE_ENABLED == STD_ON) */
1869 #endif /* ADC_SAR_IP_HAS_TEMPSENSE_CHN */
1870
1871 /*FUNCTION*********************************************************************
1872 *
1873 * Function Name : Adc_Sar_Ip_IRQHandler
1874 * Description : Handles Adc Sar interrupts
1875 *
1876 * @implements Adc_Sar_Ip_IRQHandler_Activity
1877 *END*************************************************************************/
Adc_Sar_Ip_IRQHandler(const uint32 Instance)1878 void Adc_Sar_Ip_IRQHandler(const uint32 Instance)
1879 {
1880 ADC_Type * AdcBasePtr = NULL_PTR;
1881 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1882 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1883 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1884 volatile uint32 * ISRAddr = NULL_PTR;
1885 volatile uint32 * WTISRAddr = NULL_PTR;
1886 uint32 Isr = 0u;
1887 uint32 Wtisr = 0u;
1888 #if ((ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || \
1889 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || \
1890 (STD_ON == ADC_SAR_IP_JECH_ENABLED))
1891 uint32 Imr = 0u;
1892 #endif /* (ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || ... */
1893
1894 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
1895 DevAssert(Instance < ADC_SAR_IP_INSTANCE_COUNT);
1896 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
1897
1898 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1899 if (Instance >= ADC_INSTANCE_COUNT)
1900 {
1901 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1902 ISRAddr = (volatile uint32 *)&(AdcAEBasePtr->ISR);
1903 WTISRAddr = (volatile uint32 *)&(AdcAEBasePtr->WTISR);
1904 #if ((ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || \
1905 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || \
1906 (STD_ON == ADC_SAR_IP_JECH_ENABLED))
1907 Imr = AdcAEBasePtr->IMR;
1908 #endif /* (ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || ... */
1909 }
1910 else
1911 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1912 {
1913 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1914 ISRAddr = (volatile uint32 *)&(AdcBasePtr->ISR);
1915 WTISRAddr = (volatile uint32 *)&(AdcBasePtr->WTISR);
1916 #if ((ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || \
1917 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || \
1918 (STD_ON == ADC_SAR_IP_JECH_ENABLED))
1919 Imr = AdcBasePtr->IMR;
1920 #endif /* (ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) || ... */
1921 }
1922
1923 /* CPR_RTD_00011 */
1924 if (Adc_Sar_Ip_axAdcSarState[Instance].InitStatus)
1925 {
1926 /* Check which interrupt was triggered and not spurious, clear it and call the associated callback */
1927 #if (ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) && (STD_ON == ADC_SAR_IP_EOC_ENABLED))
1928 Adc_Sar_CheckAndCallEoctuNotification(Instance);
1929 #endif /* (ADC_SAR_IP_HAS_CTU && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) && (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
1930 #if (STD_ON == ADC_SAR_IP_ECH_ENABLED)
1931 if ((((*ISRAddr) & ADC_ISR_ECH_MASK) != 0U) && ((Imr & ADC_IMR_MSKECH_MASK) != 0U))
1932 {
1933 /* CPR_RTD_00644 */
1934 *ISRAddr = ADC_ISR_ECH_MASK;
1935 Adc_Sar_CheckAndCallNotification(Adc_Sar_Ip_axAdcSarState[Instance].EndOfNormalChainNotification);
1936 }
1937 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) */
1938 #if (STD_ON == ADC_SAR_IP_JECH_ENABLED)
1939 if ((((*ISRAddr) & ADC_ISR_JECH_MASK) != 0U) && ((Imr & ADC_IMR_MSKJECH_MASK)!= 0U))
1940 {
1941 /* CPR_RTD_00644 */
1942 *ISRAddr = ADC_ISR_JECH_MASK;
1943 Adc_Sar_CheckAndCallNotification(Adc_Sar_Ip_axAdcSarState[Instance].EndOfInjectedChainNotification);
1944 }
1945 #endif /* (STD_ON == ADC_SAR_IP_JECH_ENABLED) */
1946
1947 #if ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED))
1948 Adc_CheckAndCallAllChannelNotification(Instance);
1949 #endif /* ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
1950 }
1951 else
1952 {
1953 /* CPR_RTD_00011 */
1954 Isr = *ISRAddr;
1955 *ISRAddr = Isr;
1956
1957 Wtisr = *WTISRAddr;
1958 *WTISRAddr = Wtisr;
1959 }
1960 }
1961
1962 /*FUNCTION**********************************************************************
1963 *
1964 * Function Name : Adc_Sar_SetNormalChain
1965 * Description : This function configures the ADC Normal Chain.
1966 *
1967 *END**************************************************************************/
Adc_Sar_SetNormalChain(const uint32 Instance,const uint32 * const Mask)1968 static inline void Adc_Sar_SetNormalChain(const uint32 Instance,
1969 const uint32 * const Mask)
1970 {
1971 uint8 Index;
1972
1973 ADC_Type * AdcBasePtr = NULL_PTR;
1974 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1975 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
1976 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1977
1978 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
1979 if (Instance >= ADC_INSTANCE_COUNT)
1980 {
1981 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
1982 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
1983 {
1984 NCMR(AdcAEBasePtr, Index) = Mask[Index];
1985 }
1986 }
1987 else
1988 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
1989 {
1990 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
1991 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
1992 {
1993 NCMR(AdcBasePtr, Index) = Mask[Index];
1994 }
1995 }
1996 }
1997
1998 /*FUNCTION**********************************************************************
1999 *
2000 * Function Name : Adc_Sar_SetInjectedChain
2001 * Description : This function configures the ADC Injected Chain.
2002 *
2003 *END**************************************************************************/
Adc_Sar_SetInjectedChain(const uint32 Instance,const uint32 * const Mask)2004 static inline void Adc_Sar_SetInjectedChain(const uint32 Instance,
2005 const uint32 * const Mask)
2006 {
2007 uint8 Index;
2008
2009 ADC_Type * AdcBasePtr = NULL_PTR;
2010 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2011 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2012 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2013
2014 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2015 if (Instance >= ADC_INSTANCE_COUNT)
2016 {
2017 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
2018 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
2019 {
2020 JCMR(AdcAEBasePtr, Index) = Mask[Index];
2021 }
2022 }
2023 else
2024 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2025 {
2026 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
2027 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[Instance]; Index++)
2028 {
2029 JCMR(AdcBasePtr, Index) = Mask[Index];
2030 }
2031 }
2032 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
2033 JCMR(AdcBasePtr, 0) |= ADC_JCMR0_CH0_MASK;
2034 #endif /* FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND */
2035 }
2036
2037 /*FUNCTION**********************************************************************
2038 *
2039 * Function Name : Adc_Sar_GetValueFromBool
2040 * Description : The function is used to reduce complexity for parent function
2041 *
2042 *END**************************************************************************/
Adc_Sar_GetValueFromBool(const boolean bVal,const uint32 TrueVal,const uint32 FalseVal)2043 static inline uint32 Adc_Sar_GetValueFromBool(const boolean bVal,
2044 const uint32 TrueVal,
2045 const uint32 FalseVal)
2046 {
2047 return ((TRUE == bVal) ? TrueVal : FalseVal);
2048 }
2049 #if FEATURE_ADC_HAS_CALIBRATION
2050 /*FUNCTION**********************************************************************
2051 *
2052 * Function Name : Adc_Sar_CalibrationClkSelect
2053 * Description : This function configures ADC clock for calibration.
2054 *
2055 *END**************************************************************************/
2056
Adc_Sar_CalibrationClkSelect(const uint32 u32Instance,volatile uint32 * MCRAddr,uint32 * McrSavedValue)2057 static inline Adc_Sar_Ip_StatusType Adc_Sar_CalibrationClkSelect(const uint32 u32Instance, volatile uint32 * MCRAddr, uint32 * McrSavedValue)
2058 {
2059 uint32 Mcr;
2060 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
2061
2062 /* Set CLKSEL to CalibrationClkSelect value */
2063 Status = Adc_Sar_Ip_Powerdown(u32Instance);
2064 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2065 {
2066 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12();
2067 *McrSavedValue = *MCRAddr;
2068 Mcr = *MCRAddr;
2069 #if ADC_SAR_IP_HAS_ADCLKSEL
2070 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK);
2071 Mcr |= Adc_Sar_GetADCLKSELValue(Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationClkSelect);
2072 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
2073
2074 /* Disable AutoClockOff */
2075 Mcr &= ~(ADC_MCR_ACKO_MASK);
2076 *MCRAddr = Mcr;
2077 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12();
2078
2079 Status = Adc_Sar_Ip_Powerup(u32Instance);
2080
2081 }
2082 return Status;
2083 }
2084
2085 /*FUNCTION**********************************************************************
2086 *
2087 * Function Name : Adc_Sar_CalibrationClkRestore
2088 * Description : This function restore ADC clock after calibration.
2089 *
2090 *END**************************************************************************/
Adc_Sar_CalibrationClkRestore(const uint32 u32Instance,volatile uint32 * MCRAddr,uint32 McrSavedValue)2091 static inline Adc_Sar_Ip_StatusType Adc_Sar_CalibrationClkRestore(const uint32 u32Instance, volatile uint32 * MCRAddr, uint32 McrSavedValue)
2092 {
2093 uint32 Mcr;
2094 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
2095
2096 #if ADC_SAR_IP_HAS_ADCLKSEL
2097 /* Restore state of ADCLKSEL */
2098 uint32 AdcClkSel = McrSavedValue & ADC_MCR_ADCLKSEL_MASK;
2099 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
2100
2101 /* Restore state of ADCKO */
2102 uint32 AdcAutoClkOff = McrSavedValue & ADC_MSR_ACKO_MASK;
2103
2104 /* Restore the state of ADCLKSEL */
2105 Status = Adc_Sar_Ip_Powerdown(u32Instance);
2106
2107 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12();
2108 Mcr = *MCRAddr;
2109 #if ADC_SAR_IP_HAS_ADCLKSEL
2110 Mcr &= ~(ADC_MCR_ADCLKSEL_MASK);
2111 Mcr |= AdcClkSel;
2112 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
2113 Mcr |= AdcAutoClkOff;
2114 *MCRAddr = Mcr;
2115 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12();
2116
2117 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2118 {
2119 Status = Adc_Sar_Ip_Powerup(u32Instance);
2120 }
2121
2122 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
2123 Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing = FALSE;
2124 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
2125 return Status;
2126 }
2127 #endif /* FEATURE_ADC_HAS_CALIBRATION */
2128 /*==================================================================================================
2129 * GLOBAL FUNCTIONS
2130 ==================================================================================================*/
2131 /*FUNCTION**********************************************************************
2132 *
2133 * Function Name : Adc_Sar_Ip_Init
2134 * Description : This function initializes the ADC_SAR module by configuring all
2135 * available features.
2136 *
2137 * @implements Adc_Sar_Ip_Init_Activity
2138 * END**************************************************************************/
Adc_Sar_Ip_Init(const uint32 u32Instance,const Adc_Sar_Ip_ConfigType * const pConfig)2139 Adc_Sar_Ip_StatusType Adc_Sar_Ip_Init(const uint32 u32Instance,
2140 const Adc_Sar_Ip_ConfigType * const pConfig)
2141 {
2142 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
2143 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
2144 uint8 Index = 0u;
2145 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
2146 volatile uint32 * MCRAddr = NULL_PTR;
2147 volatile uint32 * PDEDRAddr = NULL_PTR;
2148 volatile uint32 * DMAEAddr = NULL_PTR;
2149 #if FEATURE_ADC_SAR_DECODE_DELAY
2150 volatile uint32 * DSDRAddr = NULL_PTR;
2151 #endif /* FEATURE_ADC_SAR_DECODE_DELAY */
2152 #if FEATURE_ADC_HAS_PRESAMPLING
2153 volatile uint32 * PSCRAddr = NULL_PTR;
2154 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2155
2156 ADC_Type * AdcBasePtr = NULL_PTR;
2157 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2158 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2159 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2160
2161 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2162 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2163 DevAssert(pConfig != NULL_PTR);
2164 #if ADC_SAR_IP_HAS_CTU
2165 #if (ADC_SAR_IP_HAS_CTU_TRIGGER_MODE == 0u)
2166 /* test that the feature is enabled only on platforms that have it */
2167 DevAssert(pConfig->CtuMode != ADC_SAR_IP_CTU_MODE_TRIGGER);
2168 #endif /* ADC_SAR_IP_HAS_CTU */
2169 #endif /* (ADC_SAR_IP_HAS_CTU_TRIGGER_MODE == 0u) */
2170 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2171
2172 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2173 if (u32Instance >= ADC_INSTANCE_COUNT)
2174 {
2175 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2176 MCRAddr = (volatile uint32 *)&(AdcAEBasePtr->MCR);
2177 PDEDRAddr = (volatile uint32 *)&(AdcAEBasePtr->PDEDR);
2178 DMAEAddr = (volatile uint32 *)&(AdcAEBasePtr->DMAE);
2179 #if FEATURE_ADC_SAR_DECODE_DELAY
2180 DSDRAddr = (volatile uint32 *)&(AdcAEBasePtr->DSDR);
2181 #endif /* FEATURE_ADC_SAR_DECODE_DELAY */
2182 #if FEATURE_ADC_HAS_PRESAMPLING
2183 PSCRAddr = (volatile uint32 *)&(AdcAEBasePtr->PSCR);
2184 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2185 }
2186 else
2187 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2188 {
2189 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2190 MCRAddr = (volatile uint32 *)&(AdcBasePtr->MCR);
2191 PDEDRAddr = (volatile uint32 *)&(AdcBasePtr->PDEDR);
2192 DMAEAddr = (volatile uint32 *)&(AdcBasePtr->DMAE);
2193 #if FEATURE_ADC_SAR_DECODE_DELAY
2194 DSDRAddr = (volatile uint32 *)&(AdcBasePtr->DSDR);
2195 #endif /* FEATURE_ADC_SAR_DECODE_DELAY */
2196 #if FEATURE_ADC_HAS_PRESAMPLING
2197 PSCRAddr = (volatile uint32 *)&(AdcBasePtr->PSCR);
2198 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2199 }
2200
2201 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
2202 /* Set the UAA bit in REG_PROT to make the instance accessible in user mode */
2203 OsIf_Trusted_Call1param(Adc_Sar_Ip_SetUserAccessAllowed, u32Instance);
2204 #endif
2205
2206 /* Stop any conversions, if any */
2207 (void)Adc_Sar_Ip_AbortChain(u32Instance, TRUE, FALSE);
2208
2209 /* Clear CTUEN to allow Powerdown operation to succeed. */
2210 #if defined(ADC_MCR_CTUEN_MASK)
2211 *MCRAddr &= ~ADC_MCR_CTUEN_MASK;
2212 #endif /* ADC_MCR_CTUEN_MASK */
2213
2214 /* Clear pending interrupt flags - CPR_RTD_01182 */
2215 Adc_Sar_Ip_ClearStatusFlags(u32Instance, ADC_SAR_IP_NOTIF_FLAG_ALL);
2216
2217 Status = Adc_Sar_Ip_Powerdown(u32Instance);
2218 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2219 {
2220 /* Collects the mask and writes MCR mask */
2221 *MCRAddr = Adc_Sar_CollectMcrMasks(u32Instance, pConfig, *MCRAddr);
2222
2223 Adc_Sar_Ip_axAdcSarState[u32Instance].DataAlign = pConfig->DataAlign;
2224
2225 Status = Adc_Sar_Ip_Powerup(u32Instance);
2226 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2227 {
2228 if (ADC_SAR_IP_CTU_MODE_TRIGGER == pConfig->CtuMode)
2229 {
2230 /* Workaround to enable CTU_MODE because it cannot be written in power-down mode in SAF85 */
2231 *MCRAddr |= ADC_MCR_CTU_MODE(1U);
2232 }
2233 #if FEATURE_ADC_HAS_HIGH_SPEED_ENABLE
2234 /* Enables high speed conversion or calibration */
2235 Adc_Sar_EnableHighSpeed(AdcBasePtr, pConfig->HighSpeedConvEn);
2236 #endif /* FEATURE_ADC_HAS_HIGH_SPEED_ENABLE */
2237
2238 #if FEATURE_ADC_HAS_CONVERSION_TIMING
2239 /* Set the sample times for each channnel group */
2240 Adc_Sar_Ip_SetSampleTimes(u32Instance, pConfig->SampleTimeArr);
2241 #endif /* FEATURE_ADC_HAS_CONVERSION_TIMING */
2242
2243 *PDEDRAddr = ADC_PDEDR_PDED(pConfig->PowerDownDelay);
2244
2245 #if FEATURE_ADC_HAS_CLOCK_DIVIDER
2246 /* Configure clock divider */
2247 Adc_Sar_EnableClkDiv(u32Instance, pConfig->ClkDivEnable);
2248 #endif /* FEATURE_ADC_HAS_CLOCK_DIVIDER */
2249
2250 #ifdef ADC_DSDR_DSD
2251 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
2252 if (ADC_SAR_IP_INST_HAS_DSDR(u32Instance))
2253 {
2254 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
2255 #if FEATURE_ADC_SAR_DECODE_DELAY
2256 *DSDRAddr = ADC_DSDR_DSD(pConfig->DecodeDelay);
2257 #endif /* FEATURE_ADC_SAR_DECODE_DELAY */
2258 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
2259 }
2260 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
2261 #endif /* ADC_DSDR_DSD */
2262
2263 /* Configure chain conversions */
2264 Adc_Sar_SetNormalChain(u32Instance, pConfig->ChanMaskNormal);
2265 Adc_Sar_SetInjectedChain(u32Instance, pConfig->ChanMaskInjected);
2266
2267 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
2268 /* Configure resolution */
2269 Adc_Sar_Ip_SetResolution(u32Instance, pConfig->AdcResolution);
2270 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
2271
2272 /* Configure WDG */
2273 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
2274 if ((pConfig->WdgThresholds != NULL_PTR) && (pConfig->NumWdgThresholds > 0u))
2275 {
2276 for (Index = 0U; Index < pConfig->NumWdgThresholds; Index++)
2277 {
2278 Adc_Sar_Ip_SetWdgThreshold(u32Instance, pConfig->WdgThresholds[Index].WdgIndex, &pConfig->WdgThresholds[Index]);
2279 }
2280 }
2281 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
2282
2283 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
2284 if (pConfig->SelfTestThresholdConfig != NULL_PTR)
2285 {
2286 /* Configure self-test threshold value */
2287 Adc_Sar_ConfigSelftestThreshold(u32Instance, pConfig->SelfTestThresholdConfig);
2288 }
2289 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
2290
2291 /* Configure DMA for channels */
2292 *DMAEAddr &= ~(ADC_DMAE_DMAEN_MASK | ADC_DMAE_DCLR_MASK);
2293 if (pConfig->DmaEnable)
2294 {
2295 *DMAEAddr |= (ADC_DMAE_DMAEN(1U) | ADC_DMAE_DCLR((uint32)pConfig->DmaClearSource));
2296 }
2297
2298 /* Configure per channel notifications and presampling */
2299 if ((pConfig->ChannelConfigsPtr != NULL_PTR) && (pConfig->NumChannels > 0u))
2300 {
2301 Adc_Sar_ConfigChannels(u32Instance, pConfig->ChannelConfigsPtr, pConfig->NumChannels);
2302 }
2303
2304 #if FEATURE_ADC_HAS_PRESAMPLING
2305 /* Configure presampling sources */
2306 *PSCRAddr &= ~(ADC_PSCR_PRECONV_MASK);
2307 *PSCRAddr |= ADC_PSCR_PRECONV(pConfig->BypassSampling ? 1u : 0u);
2308
2309 Adc_Sar_Ip_SetPresamplingSource(u32Instance, ADC_SAR_IP_CHAN_GROUP_0, pConfig->PresamplingSourceArr[0u]);
2310 Adc_Sar_Ip_SetPresamplingSource(u32Instance, ADC_SAR_IP_CHAN_GROUP_1, pConfig->PresamplingSourceArr[1u]);
2311 #if ADC_SAR_IP_NUM_GROUP_CHAN > 2u
2312 Adc_Sar_Ip_SetPresamplingSource(u32Instance, ADC_SAR_IP_CHAN_GROUP_2, pConfig->PresamplingSourceArr[2u]);
2313 #endif /* ADC_SAR_IP_NUM_GROUP_CHAN > 2u */
2314 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2315
2316
2317 /* Add notification callbacks to the state structure */
2318 #if (STD_ON == ADC_SAR_IP_ECH_ENABLED)
2319 Adc_Sar_Ip_axAdcSarState[u32Instance].EndOfNormalChainNotification = pConfig->EndOfNormalChainNotification;
2320 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) */
2321 #if (STD_ON == ADC_SAR_IP_JECH_ENABLED)
2322 Adc_Sar_Ip_axAdcSarState[u32Instance].EndOfInjectedChainNotification = pConfig->EndOfInjectedChainNotification;
2323 #endif /* (STD_ON == ADC_SAR_IP_JECH_ENABLED) */
2324 #if ADC_SAR_IP_HAS_CTU
2325 #if (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)
2326 Adc_Sar_Ip_axAdcSarState[u32Instance].EndOfCtuConversionNotification = pConfig->EndOfCtuConversionNotification;
2327 #endif /* (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) */
2328 #endif /* ADC_SAR_IP_HAS_CTU */
2329 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
2330 Adc_Sar_Ip_axAdcSarState[u32Instance].EndOfConvNotification = pConfig->EndOfConvNotification;
2331 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
2332 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
2333 Adc_Sar_Ip_axAdcSarState[u32Instance].WdgOutOfRangeNotification = pConfig->WdgOutOfRangeNotification;
2334 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
2335 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
2336 Adc_Sar_Ip_axAdcSarState[u32Instance].BypassResolution = pConfig->BypassResolution;
2337 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
2338 Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationClkSelect = pConfig->CalibrationClkSelect;
2339
2340 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2341 if (u32Instance >= ADC_INSTANCE_COUNT)
2342 {
2343 /* Configure user gain and offset */
2344 AdcAEBasePtr->ADC_AE_USER_OFFSET_GAIN_REG = ADC_AE_USER_OFFSET(pConfig->UsrOffset) | ADC_AE_USER_GAIN(pConfig->UsrGain);
2345 }
2346 else
2347 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2348 {
2349 /* Configure user gain and offset */
2350 AdcBasePtr->ADC_USER_OFFSET_GAIN_REG = ADC_USER_OFFSET(pConfig->UsrOffset) | ADC_USER_GAIN(pConfig->UsrGain);
2351 }
2352
2353 /* Mark that the driver was initialized */
2354 Adc_Sar_Ip_axAdcSarState[u32Instance].InitStatus = TRUE;
2355 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
2356 Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing = FALSE;
2357 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
2358 }
2359 }
2360
2361 return Status;
2362 }
2363
2364 /*FUNCTION**********************************************************************
2365 *
2366 * Function Name : Adc_Sar_Ip_Deinit
2367 * Description : This function writes all the internal ADC registers with
2368 * their Reference Manual reset values.
2369 *
2370 * @implements Adc_Sar_Ip_DeInit_Activity
2371 * END**************************************************************************/
Adc_Sar_Ip_Deinit(const uint32 u32Instance)2372 Adc_Sar_Ip_StatusType Adc_Sar_Ip_Deinit(const uint32 u32Instance)
2373 {
2374 ADC_Type * AdcBasePtr = NULL_PTR;
2375 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2376 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2377 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2378 uint32 Index;
2379 Adc_Sar_Ip_ConfigType DefaultConfig;
2380 Adc_Sar_Ip_StatusType Status;
2381
2382 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2383 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2384 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2385
2386 DefaultConfig.ConvMode = ADC_SAR_IP_CONV_MODE_ONESHOT;
2387 DefaultConfig.ClkSelect = ADC_SAR_IP_CLK_FULL_BUS;
2388 DefaultConfig.CalibrationClkSelect = ADC_SAR_IP_CLK_HALF_BUS;
2389 #if FEATURE_ADC_HAS_HIGH_SPEED_ENABLE
2390 DefaultConfig.HighSpeedConvEn = FALSE;
2391 #endif /* FEATURE_ADC_HAS_HIGH_SPEED_ENABLE */
2392 #if ADC_SAR_IP_HAS_CTU
2393 DefaultConfig.CtuMode = ADC_SAR_IP_CTU_MODE_DISABLED;
2394 #endif /* ADC_SAR_IP_HAS_CTU */
2395 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
2396 #if FEATURE_ADC_HAS_INJ_EXT_TRIGGER
2397 DefaultConfig.InjectedEdge = ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED;
2398 #endif /* FEATURE_ADC_HAS_INJ_EXT_TRIGGER */
2399 #if FEATURE_ADC_HAS_EXT_TRIGGER
2400 DefaultConfig.ExtTrigger = ADC_SAR_IP_EXT_TRIG_EDGE_DISABLED;
2401 DefaultConfig.NormalExtTrgEn = FALSE;
2402 #if FEATURE_ADC_HAS_AUX_EXT_TRIGGER
2403 DefaultConfig.NormalAuxExtTrgEn = FALSE;
2404 #endif /* FEATURE_ADC_HAS_AUX_EXT_TRIGGER */
2405 #endif /* FEATURE_ADC_HAS_EXT_TRIGGER */
2406 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
2407 #if (FEATURE_ADC_HAS_CONVERSION_TIMING || FEATURE_ADC_HAS_PRESAMPLING)
2408 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
2409 {
2410 #if FEATURE_ADC_HAS_CONVERSION_TIMING
2411 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2412 if (u32Instance >= ADC_INSTANCE_COUNT)
2413 {
2414 DefaultConfig.SampleTimeArr[Index] = ADC_SAR_AE_IP_DEF_SAMPLE_TIME;
2415 }
2416 else
2417 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2418 {
2419 DefaultConfig.SampleTimeArr[Index] = ADC_SAR_IP_DEF_SAMPLE_TIME;
2420 }
2421 #endif /* FEATURE_ADC_HAS_CONVERSION_TIMING */
2422 #if FEATURE_ADC_HAS_PRESAMPLING
2423 #if (ADC_PSCR_PREVAL0_WIDTH > 1u)
2424 DefaultConfig.PresamplingSourceArr[Index] = ADC_SAR_IP_PRESAMPLE_DVDD;
2425 #else
2426 DefaultConfig.PresamplingSourceArr[Index] = ADC_SAR_IP_PRESAMPLE_VREFL;
2427 #endif /* (ADC_PSCR_PREVAL0_WIDTH > 1u) */
2428 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2429 }
2430 #endif /* (FEATURE_ADC_HAS_CONVERSION_TIMING || FEATURE_ADC_HAS_PRESAMPLING) */
2431 #if FEATURE_ADC_HAS_PRESAMPLING
2432 DefaultConfig.BypassSampling = FALSE;
2433 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2434 DefaultConfig.AutoClockOff = FALSE;
2435 DefaultConfig.OverwriteEnable = FALSE;
2436 DefaultConfig.DataAlign = ADC_SAR_IP_DATA_ALIGNED_RIGHT;
2437 #if FEATURE_ADC_SAR_DECODE_DELAY
2438 DefaultConfig.DecodeDelay = 0u;
2439 #endif /* FEATURE_ADC_SAR_DECODE_DELAY */
2440 DefaultConfig.PowerDownDelay = 0u;
2441 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
2442 DefaultConfig.SelfTestThresholdConfig = NULL_PTR;
2443 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
2444 #if FEATURE_ADC_HAS_CLOCK_DIVIDER
2445 DefaultConfig.ClkDivEnable = FALSE;
2446 #endif /* FEATURE_ADC_HAS_CLOCK_DIVIDER */
2447 #if FEATURE_ADC_HAS_AVERAGING
2448 DefaultConfig.AvgEn = FALSE;
2449 DefaultConfig.AvgSel = ADC_SAR_IP_AVG_4_CONV;
2450 #endif /* FEATURE_ADC_HAS_AVERAGING */
2451 DefaultConfig.UsrOffset = 0u;
2452 DefaultConfig.UsrGain = 0u;
2453 DefaultConfig.DmaEnable = FALSE;
2454 DefaultConfig.DmaClearSource = ADC_SAR_IP_DMA_REQ_CLEAR_ON_ACK;
2455 DefaultConfig.NumChannels = 0u;
2456 DefaultConfig.ChannelConfigsPtr = NULL_PTR;
2457 #if (STD_ON == ADC_SAR_IP_ECH_ENABLED)
2458 DefaultConfig.EndOfNormalChainNotification = NULL_PTR;
2459 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) */
2460 #if (STD_ON == ADC_SAR_IP_JECH_ENABLED)
2461 DefaultConfig.EndOfInjectedChainNotification = NULL_PTR;
2462 #endif /* (STD_ON == ADC_SAR_IP_JECH_ENABLED) */
2463 #if ADC_SAR_IP_HAS_CTU
2464 #if (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)
2465 DefaultConfig.EndOfCtuConversionNotification = NULL_PTR;
2466 #endif /* (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) */
2467 #endif /* ADC_SAR_IP_HAS_CTU */
2468
2469 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
2470 DefaultConfig.EndOfConvNotification = NULL_PTR;
2471 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
2472 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
2473 DefaultConfig.NumWdgThresholds = 0u;
2474 DefaultConfig.WdgThresholds = NULL_PTR;
2475 DefaultConfig.WdgOutOfRangeNotification = NULL_PTR;
2476 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
2477 Status = Adc_Sar_Ip_Init(u32Instance, &DefaultConfig);
2478 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
2479 {
2480 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2481 if ((u32Instance >= ADC_INSTANCE_COUNT))
2482 {
2483 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2484 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
2485 {
2486 CIMR(AdcAEBasePtr, Index) = 0u;
2487 CEOCFR(AdcAEBasePtr, Index) = 0xFFFFFFFFu; /* w1c bits */
2488 DMAR(AdcAEBasePtr, Index) = 0u;
2489 #if FEATURE_ADC_HAS_PRESAMPLING
2490 PSR(AdcAEBasePtr, Index) = 0u;
2491 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2492 }
2493
2494 /* Deinit watchdog interrupts */
2495 Adc_Sar_ResetWdog(u32Instance);
2496 AdcAEBasePtr->WTIMR = 0u;
2497 }
2498 else
2499 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2500 {
2501 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2502 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
2503 {
2504 CIMR(AdcBasePtr, Index) = 0u;
2505 CEOCFR(AdcBasePtr, Index) = 0xFFFFFFFFu; /* w1c bits */
2506 DMAR(AdcBasePtr, Index) = 0u;
2507 #if FEATURE_ADC_HAS_PRESAMPLING
2508 PSR(AdcBasePtr, Index) = 0u;
2509 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
2510 }
2511
2512 /* Deinit watchdog interrupts */
2513 Adc_Sar_ResetWdog(u32Instance);
2514 AdcBasePtr->WTIMR = 0u;
2515 }
2516 /* Deinit channel configuration */
2517
2518 Adc_Sar_Ip_ClearStatusFlags(u32Instance, ADC_SAR_IP_NOTIF_FLAG_ALL);
2519 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
2520 /* Set default resolution */
2521 Adc_Sar_Ip_SetResolution(u32Instance, ADC_SAR_IP_RESOLUTION_12);
2522 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
2523
2524 /* Mark that the driver was deinitialized */
2525 Adc_Sar_Ip_axAdcSarState[u32Instance].InitStatus = FALSE;
2526
2527 Status = Adc_Sar_Ip_Powerdown(u32Instance);
2528
2529 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
2530 /* Clear the UAA bit in REG_PROT to reset the elevation requirement */
2531 OsIf_Trusted_Call1param(Adc_Sar_Ip_ClrUserAccessAllowed, u32Instance);
2532 #endif
2533 }
2534
2535 return Status;
2536 }
2537
2538 /*FUNCTION**********************************************************************
2539 *
2540 * Function Name : Adc_Sar_Ip_ChainConfig
2541 * Description : This function configures the ADC Normal and Injected Chains
2542 * with the options provided in the structure.
2543 *
2544 * @implements Adc_Sar_Ip_ChainConfig_Activity
2545 * END**************************************************************************/
Adc_Sar_Ip_ChainConfig(const uint32 u32Instance,const Adc_Sar_Ip_ChansIdxMaskType * const pChansIdxMask,const Adc_Sar_Ip_ConvChainType pChainType)2546 void Adc_Sar_Ip_ChainConfig(const uint32 u32Instance,
2547 const Adc_Sar_Ip_ChansIdxMaskType * const pChansIdxMask,
2548 const Adc_Sar_Ip_ConvChainType pChainType)
2549 {
2550 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2551 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2552 DevAssert(pChansIdxMask != NULL_PTR);
2553 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
2554 uint8 i;
2555
2556 /* Enabling unavailable channels is forbidden */
2557 for (i = 0U; i < ADC_SAR_IP_NUM_GROUP_CHAN; i++)
2558 {
2559 DevAssert((pChansIdxMask->ChanMaskArr[i] & (~Adc_Sar_Ip_au32AdcChanBitmap[u32Instance][i])) == 0u);
2560 }
2561 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
2562 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2563
2564 switch (pChainType)
2565 {
2566 case ADC_SAR_IP_CONV_CHAIN_NORMAL:
2567 Adc_Sar_SetNormalChain(u32Instance, pChansIdxMask->ChanMaskArr);
2568 break;
2569 case ADC_SAR_IP_CONV_CHAIN_INJECTED:
2570 Adc_Sar_SetInjectedChain(u32Instance, pChansIdxMask->ChanMaskArr);
2571 break;
2572 default:
2573 ; /* no-op */
2574 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2575 DevAssert(FALSE);
2576 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2577 break;
2578 }
2579 }
2580
2581 /*FUNCTION**********************************************************************
2582 *
2583 * Function Name : Adc_Sar_Ip_EnableChannel
2584 * Description : This function enables a channel in a conversion chain (
2585 * ADC_SAR_IP_CONV_CHAIN_NORMAL or ADC_SAR_IP_CONV_CHAIN_INJECTED).
2586 *
2587 * @implements Adc_Sar_Ip_EnableChannel_Activity
2588 * END**************************************************************************/
Adc_Sar_Ip_EnableChannel(const uint32 u32Instance,const Adc_Sar_Ip_ConvChainType pChainType,const uint32 u32ChnIdx)2589 void Adc_Sar_Ip_EnableChannel(const uint32 u32Instance,
2590 const Adc_Sar_Ip_ConvChainType pChainType,
2591 const uint32 u32ChnIdx)
2592 {
2593 uint32 VectAdr;
2594 uint32 VectBit;
2595 ADC_Type * AdcBasePtr = NULL_PTR;
2596 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2597 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2598 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2599 volatile uint32 * NCMRAddr = NULL_PTR;
2600 volatile uint32 * JCMRAddr = NULL_PTR;
2601
2602 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2603 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2604 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
2605 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
2606 DevAssert(!((0U == u32ChnIdx) && ((ADC_SAR_IP_CONV_CHAIN_INJECTED == pChainType) || (ADC_SAR_IP_CONV_CHAIN_CTU == pChainType))));
2607 #endif
2608 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
2609 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
2610 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
2611 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2612
2613 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
2614 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
2615
2616 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2617 if (u32Instance >= ADC_INSTANCE_COUNT)
2618 {
2619 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2620 NCMRAddr = &(NCMR(AdcAEBasePtr, VectAdr));
2621 JCMRAddr = &(JCMR(AdcAEBasePtr, VectAdr));
2622 }
2623 else
2624 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2625 {
2626 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2627 NCMRAddr = &(NCMR(AdcBasePtr, VectAdr));
2628 JCMRAddr = &(JCMR(AdcBasePtr, VectAdr));
2629 }
2630
2631 switch (pChainType)
2632 {
2633 case ADC_SAR_IP_CONV_CHAIN_NORMAL:
2634 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_23();
2635 *NCMRAddr |= (1UL << VectBit);
2636 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_23();
2637 break;
2638 case ADC_SAR_IP_CONV_CHAIN_INJECTED:
2639 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_26();
2640 *JCMRAddr |= (1UL << VectBit);
2641 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_26();
2642 break;
2643 default:
2644 ; /* no-op */
2645 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2646 DevAssert(FALSE);
2647 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2648 break;
2649 }
2650 }
2651
2652 /*FUNCTION**********************************************************************
2653 *
2654 * Function Name : Adc_Sar_Ip_DisableChannel
2655 * Description : This function disables a channel from a conversion chain (ADC_SAR_IP_CONV_CHAIN_NORMAL
2656 * or ADC_SAR_IP_CONV_CHAIN_INJECTED).
2657 *
2658 * @implements Adc_Sar_Ip_DisableChannel_Activity
2659 * END**************************************************************************/
Adc_Sar_Ip_DisableChannel(const uint32 u32Instance,const Adc_Sar_Ip_ConvChainType pChainType,const uint32 u32ChnIdx)2660 void Adc_Sar_Ip_DisableChannel(const uint32 u32Instance,
2661 const Adc_Sar_Ip_ConvChainType pChainType,
2662 const uint32 u32ChnIdx)
2663 {
2664 uint32 VectAdr;
2665 uint32 VectBit;
2666 ADC_Type * AdcBasePtr = NULL_PTR;
2667 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2668 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2669 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2670 volatile uint32 * NCMRAddr = NULL_PTR;
2671 volatile uint32 * JCMRAddr = NULL_PTR;
2672
2673 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2674 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2675 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
2676 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
2677 DevAssert((0U == u32ChnIdx) && (ADC_SAR_IP_CONV_CHAIN_INJECTED == pChainType));
2678 #endif
2679 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
2680 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
2681 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
2682 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2683
2684 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
2685 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
2686
2687 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2688 if (u32Instance >= ADC_INSTANCE_COUNT)
2689 {
2690 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2691 NCMRAddr = &(NCMR(AdcAEBasePtr, VectAdr));
2692 JCMRAddr = &(JCMR(AdcAEBasePtr, VectAdr));
2693 }
2694 else
2695 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2696 {
2697 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2698 NCMRAddr = &(NCMR(AdcBasePtr, VectAdr));
2699 JCMRAddr = &(JCMR(AdcBasePtr, VectAdr));
2700 }
2701
2702 switch (pChainType)
2703 {
2704 case ADC_SAR_IP_CONV_CHAIN_NORMAL:
2705 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_24();
2706 *NCMRAddr &= ~(1UL << VectBit);
2707 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_24();
2708 break;
2709 case ADC_SAR_IP_CONV_CHAIN_INJECTED:
2710 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_27();
2711 *JCMRAddr &= ~(1UL << VectBit);
2712 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_27();
2713 break;
2714 default:
2715 ; /* no-op */
2716 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2717 DevAssert(FALSE);
2718 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2719 break;
2720 }
2721 }
2722
2723 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
2724 /*FUNCTION**********************************************************************
2725 *
2726 * Function Name : Adc_Sar_Ip_SetResolution
2727 * Description : This function sets the conversion resolution (number of bits per conversion data)
2728 *
2729 * @implements Adc_Sar_Ip_SetResolution_Activity
2730 * END**************************************************************************/
Adc_Sar_Ip_SetResolution(const uint32 u32Instance,const Adc_Sar_Ip_Resolution eResolution)2731 void Adc_Sar_Ip_SetResolution(const uint32 u32Instance,
2732 const Adc_Sar_Ip_Resolution eResolution)
2733 {
2734 uint32 Calbistreg;
2735 ADC_Type * AdcBasePtr = NULL_PTR;
2736 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2737 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2738 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2739 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2740 uint32 Msr;
2741 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2742 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2743 volatile uint32 * CALBISTREGAddr = NULL_PTR;
2744 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
2745 /* calibration must not be interrupted */
2746 if(FALSE == Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing)
2747 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
2748 {
2749 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2750 if (u32Instance >= ADC_INSTANCE_COUNT)
2751 {
2752 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2753 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2754 Msr = AdcAEBasePtr->MSR;
2755 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2756 CALBISTREGAddr = (volatile uint32 *)&(AdcAEBasePtr->CALBISTREG);
2757 }
2758 else
2759 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2760 {
2761 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2762 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2763 Msr = AdcBasePtr->MSR;
2764 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2765 CALBISTREGAddr = (volatile uint32 *)&(AdcBasePtr->CALBISTREG);
2766 }
2767
2768 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2769 /* The selected ADC should be in IDLE state */
2770 DevAssert((Msr & ADC_MSR_ADCSTATUS_MASK) == ADC_MSR_ADCSTATUS(ADC_SAR_IP_MSR_ADCSTATUS_IDLE));
2771 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2772 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_37();
2773 Calbistreg = *CALBISTREGAddr;
2774 /* Clear the bits and set resolution value */
2775 Calbistreg &= ~(ADC_CALBISTREG_RESN_MASK);
2776 Calbistreg |= ADC_CALBISTREG_RESN(eResolution);
2777 *CALBISTREGAddr = Calbistreg;
2778 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_37();
2779 }
2780 }
2781 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
2782
2783 /*FUNCTION**********************************************************************
2784 *
2785 * Function Name : Adc_Sar_Ip_StartConversion
2786 * Description : This function starts a conversion chain (ADC_SAR_IP_CONV_CHAIN_NORMAL
2787 * or ADC_SAR_IP_CONV_CHAIN_INJECTED).
2788 *
2789 * @implements Adc_Sar_Ip_StartConversion_Activity
2790 * END**************************************************************************/
Adc_Sar_Ip_StartConversion(const uint32 u32Instance,const Adc_Sar_Ip_ConvChainType pChainType)2791 void Adc_Sar_Ip_StartConversion(const uint32 u32Instance,
2792 const Adc_Sar_Ip_ConvChainType pChainType)
2793 {
2794 ADC_Type * AdcBasePtr = NULL_PTR;
2795 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2796 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2797 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2798 volatile uint32 * MCRAddr = NULL_PTR;
2799
2800 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2801 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2802 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2803 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
2804 /* calibration must not be interrupted */
2805 if(FALSE == Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing)
2806 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
2807 {
2808 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2809 if (u32Instance >= ADC_INSTANCE_COUNT)
2810 {
2811 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2812 MCRAddr = (volatile uint32 *)&(AdcAEBasePtr->MCR);
2813 }
2814 else
2815 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2816 {
2817 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2818 MCRAddr = (volatile uint32 *)&(AdcBasePtr->MCR);
2819 }
2820
2821 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_10();
2822 switch (pChainType)
2823 {
2824 case ADC_SAR_IP_CONV_CHAIN_NORMAL:
2825 *MCRAddr |= ADC_MCR_NSTART(1U);
2826 break;
2827 case ADC_SAR_IP_CONV_CHAIN_INJECTED:
2828 *MCRAddr |= ADC_MCR_JSTART(1U);
2829 break;
2830 default:
2831 ; /* no-op */
2832 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2833 DevAssert(FALSE);
2834 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2835 break;
2836 }
2837 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_10();
2838 }
2839 }
2840
2841 /*FUNCTION**********************************************************************
2842 *
2843 * Function Name : Adc_Sar_Ip_GetStatusFlags
2844 * Description : This function returns the status flags of the ADC.
2845 *
2846 * @implements Adc_Sar_Ip_GetStatusFlags_Activity
2847 * END**************************************************************************/
Adc_Sar_Ip_GetStatusFlags(const uint32 u32Instance)2848 uint32 Adc_Sar_Ip_GetStatusFlags(const uint32 u32Instance)
2849 {
2850 uint32 Flags = 0U;
2851
2852 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2853 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2854 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2855
2856 /* Returns the flag status from MSR register */
2857 Flags |= Adc_Sar_GetMsrFlags(u32Instance);
2858 /* Returns the flag status from ISR register */
2859 Flags |= Adc_Sar_GetIsrFlags(u32Instance);
2860
2861 return Flags;
2862 }
2863
2864 /*FUNCTION**********************************************************************
2865 *
2866 * Function Name : Adc_Sar_Ip_ClearStatusFlags
2867 * Description : This function clears the status flags that are set to '1' in
2868 * the mask.
2869 *
2870 * @implements Adc_Sar_Ip_ClearStatusFlags_Activity
2871 * END**************************************************************************/
Adc_Sar_Ip_ClearStatusFlags(const uint32 u32Instance,const uint32 u32Mask)2872 void Adc_Sar_Ip_ClearStatusFlags(const uint32 u32Instance,
2873 const uint32 u32Mask)
2874 {
2875 uint32 IsrFlags = 0U;
2876 volatile uint32 * ISRAddr = NULL_PTR;
2877
2878 ADC_Type * AdcBasePtr = NULL_PTR;
2879 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2880 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2881 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2882
2883 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2884 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2885 DevAssert((u32Mask & (~ADC_SAR_IP_NOTIF_FLAG_ALL)) == 0UL);
2886 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2887
2888 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2889 if (u32Instance >= ADC_INSTANCE_COUNT)
2890 {
2891 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2892 ISRAddr = (volatile uint32 *)&(AdcAEBasePtr->ISR);
2893 }
2894 else
2895 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2896 {
2897 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
2898 ISRAddr = (volatile uint32 *)&(AdcBasePtr->ISR);
2899 }
2900
2901 IsrFlags |= ((u32Mask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_EOC) != 0U) ? ADC_ISR_EOC(1U) : 0U;
2902 IsrFlags |= ((u32Mask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN) != 0U) ? ADC_ISR_ECH(1U) : 0U;
2903 IsrFlags |= ((u32Mask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_EOC) != 0U) ? ADC_ISR_JEOC(1U) : 0U;
2904 IsrFlags |= ((u32Mask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN) != 0U) ? ADC_ISR_JECH(1U) : 0U;
2905 #if ADC_SAR_IP_HAS_CTU
2906 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
2907 if (ADC_SAR_IP_INST_HAS_CTU(u32Instance))
2908 {
2909 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
2910 IsrFlags |= ((u32Mask & ADC_SAR_IP_NOTIF_FLAG_CTU_EOC) != 0U) ? ADC_ISR_EOCTU(1U) : 0U;
2911 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
2912 }
2913 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
2914 #endif /* ADC_SAR_IP_HAS_CTU */
2915
2916 /* Write-1-to-clear bits in ISR register */
2917 *ISRAddr = IsrFlags;
2918 #ifdef FEATURE_CPU_HAS_WRITE_BUFFER
2919 (void) *ISRAddr;
2920 #endif /* FEATURE_CPU_HAS_WRITE_BUFFER */
2921 }
2922
2923 #if (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED)
2924 /*FUNCTION**********************************************************************
2925 *
2926 * Function Name : Adc_Sar_Ip_SelfTest
2927 * Description : This function executes a self test on the ADC instance.
2928 *
2929 * @implements Adc_Sar_Ip_SelfTest_Activity
2930 * END**************************************************************************/
Adc_Sar_Ip_SelfTest(const uint32 u32Instance)2931 Adc_Sar_Ip_StatusType Adc_Sar_Ip_SelfTest(const uint32 u32Instance)
2932 {
2933 ADC_Type * AdcBasePtr = NULL_PTR;
2934 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2935 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
2936 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2937 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
2938 #if ADC_SAR_IP_HAS_SELFTEST_STCR1
2939 uint32 Reg;
2940 #endif /* ADC_SAR_IP_HAS_SELFTEST_STCR1 */
2941 uint32 MsrStatus;
2942 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
2943 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
2944 uint32 ElapsedTicks = 0U;
2945 #if (ADC_SAR_IP_SELFTEST_FULL_CLK && ADC_SAR_IP_HAS_ADCLKSEL)
2946 uint32 AdcClkSel = 0u;
2947 #endif /* (ADC_SAR_IP_SELFTEST_FULL_CLK && ADC_SAR_IP_HAS_ADCLKSEL) */
2948 volatile uint32 * MCRAddr = NULL_PTR;
2949 volatile const uint32 * MSRAddr = NULL_PTR;
2950 #if !ADC_SAR_IP_HAS_SELFTEST_USE_CH32
2951 volatile uint32 * NCMR0Addr = NULL_PTR;
2952 #else
2953 volatile uint32 * NCMR1Addr = NULL_PTR;
2954 #endif /* ADC_SAR_IP_HAS_SELFTEST_USE_CH32 */
2955 #if ADC_SAR_IP_HAS_SELFTEST_STCR1
2956 volatile uint32 * STCR1Addr = NULL_PTR;
2957 #endif /* ADC_SAR_IP_HAS_SELFTEST_STCR1 */
2958 volatile uint32 * STCR2Addr = NULL_PTR;
2959 #if ADC_SAR_IP_HAS_SELFTEST_STCR3
2960 volatile uint32 * STCR3Addr = NULL_PTR;
2961 #endif /* ADC_SAR_IP_HAS_SELFTEST_STCR3 */
2962 #ifdef ADC_GPADC_ANA_TEST0_VDAC
2963 uint32 BackupVdacAnaTest0;
2964 #endif
2965 #ifdef ADC_GPADC_ANA_CONF_VIN_SE_REF
2966 uint32 BackupVinSeRefAnaConf;
2967 #endif
2968
2969 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
2970 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
2971 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
2972 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
2973 /* calibration must not be interrupted */
2974 if(FALSE == Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing)
2975 {
2976 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
2977 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
2978 if (u32Instance >= ADC_INSTANCE_COUNT)
2979 {
2980 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
2981 MCRAddr = (volatile uint32 *)&(AdcAEBasePtr->MCR);
2982 MSRAddr = (volatile uint32 *)&(AdcAEBasePtr->MSR);
2983 #if !ADC_SAR_IP_HAS_SELFTEST_USE_CH32
2984 NCMR0Addr = &(NCMR(AdcAEBasePtr, 0u));
2985 #else
2986 NCMR1Addr = &(NCMR(AdcAEBasePtr, 1u));
2987 #endif /* ADC_SAR_IP_HAS_SELFTEST_USE_CH32 */
2988 #if ADC_SAR_IP_HAS_SELFTEST_STCR1
2989 STCR1Addr = (volatile uint32 *)&(AdcAEBasePtr->STCR1);
2990 #endif /* ADC_SAR_IP_HAS_SELFTEST_STCR1 */
2991 STCR2Addr = (volatile uint32 *)&(AdcAEBasePtr->STCR2);
2992 #if ADC_SAR_IP_HAS_SELFTEST_STCR3
2993 STCR3Addr = (volatile uint32 *)&(AdcAEBasePtr->STCR3);
2994 #endif /* ADC_SAR_IP_HAS_SELFTEST_STCR3 */
2995 }
2996 else
2997 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
2998 {
2999 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3000 MCRAddr = (volatile uint32 *)&(AdcBasePtr->MCR);
3001 MSRAddr = (volatile uint32 *)&(AdcBasePtr->MSR);
3002 #if !ADC_SAR_IP_HAS_SELFTEST_USE_CH32
3003 NCMR0Addr = &(NCMR(AdcBasePtr, 0u));
3004 #else
3005 NCMR1Addr = &(NCMR(AdcBasePtr, 1u));
3006 #endif /* ADC_SAR_IP_HAS_SELFTEST_USE_CH32 */
3007 #if ADC_SAR_IP_HAS_SELFTEST_STCR1
3008 STCR1Addr = (volatile uint32 *)&(AdcBasePtr->STCR1);
3009 #endif /* ADC_SAR_IP_HAS_SELFTEST_STCR1 */
3010 STCR2Addr = (volatile uint32 *)&(AdcBasePtr->STCR2);
3011 #if ADC_SAR_IP_HAS_SELFTEST_STCR3
3012 STCR3Addr = (volatile uint32 *)&(AdcBasePtr->STCR3);
3013 #endif /* ADC_SAR_IP_HAS_SELFTEST_STCR3 */
3014 }
3015
3016 #if ADC_SAR_IP_SELFTEST_FULL_CLK
3017 /* Enter into power-down Mode */
3018 Status = Adc_Sar_Ip_Powerdown(u32Instance);
3019 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3020 {
3021 #if ADC_SAR_IP_HAS_ADCLKSEL
3022 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11();
3023 /* Save the current state of ADCLKSEL in order to restore it */
3024 AdcClkSel = ((*MCRAddr) & ADC_MCR_ADCLKSEL_MASK);
3025 /* ADC self-test should be run with MCR[ADCLKSE] bit set to 1 */
3026 *MCRAddr &= ~(ADC_MCR_ADCLKSEL_MASK);
3027 *MCRAddr |= ADC_MCR_ADCLKSEL(1U);
3028 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11();
3029 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3030
3031 /* Exit into power-down Mode */
3032 Status = Adc_Sar_Ip_Powerup(u32Instance);
3033 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3034 {
3035 #endif /* ADC_SAR_IP_SELFTEST_FULL_CLK */
3036 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_25();
3037 #if !ADC_SAR_IP_HAS_SELFTEST_USE_CH32
3038 /* 1. Program NCMR0 to select channels to be converted for normal conversion.*/
3039 *NCMR0Addr |= ADC_NCMR_CH0(0x1UL);
3040 #else
3041 /* Workaround for SAF8544 since self-test result register is written twice with the last channel of chain and self-test channel 32
3042 Enabling channel 32 at last of chain to have register field having only result of selftest channel 32 */
3043 *NCMR1Addr |= ADC_NCMR1_CH32(0x1UL);
3044 #endif /* ADC_SAR_IP_HAS_SELFTEST_USE_CH32 */
3045 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_25();
3046
3047 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11();
3048 /* Self-test will only run with CPU mode so clear CTU enable */
3049 #if defined(ADC_MCR_CTUEN_MASK)
3050 *MCRAddr &= ~(ADC_MCR_CTUEN_MASK);
3051 #endif /* ADC_MCR_CTUEN_MASK */
3052
3053 /* 2. Program MCR[MODE] = 1 to select Scan mode. ADC_ONE_SHOT_MODE_U32 ADCDIG_CONTINUOUS_MODE_U32*/
3054 *MCRAddr |= ADC_MCR_MODE(0x1UL);
3055 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11();
3056 #if ADC_SAR_IP_HAS_SELFTEST_STCR1
3057 /* 3. Program sampling duration values in STCR1[INPSAMPx].*/
3058 Reg = 0u;
3059 Reg |= ADC_STCR1_INPSAMP_S(0x10UL) | ADC_STCR1_INPSAMP_C(0x10UL);
3060 *STCR1Addr = Reg;
3061 #endif /* ADC_SAR_IP_HAS_SELFTEST_STCR1 */
3062
3063 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35();
3064 #if ADC_SAR_IP_HAS_SELFTEST_STCR3
3065 /* 4. Select the self-testing algorithm in STCR3[ALG]. */
3066 *STCR3Addr |= ADC_STCR3_ALG(0x3UL);
3067 #endif /* ADC_SAR_IP_HAS_SELFTEST_STCR3 */
3068 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35();
3069
3070 Adc_Sar_EnableSelftestThreshold(u32Instance);
3071 #ifdef ADC_GPADC_ANA_TEST0_VDAC
3072 /* Save the current state of GPADC_ANA_TEST0[ADAC] in order to restore it */
3073 BackupVdacAnaTest0 = AdcBasePtr->GPADC_ANA_TEST0;
3074 AdcBasePtr->GPADC_ANA_TEST0 &= ~(ADC_GPADC_ANA_TEST0_VDAC_MASK);
3075 AdcBasePtr->GPADC_ANA_TEST0 |= ADC_GPADC_ANA_TEST0_VDAC(8U);
3076 #endif /* ADC_GPADC_ANA_TEST0_VDAC */
3077 #ifdef ADC_GPADC_ANA_CONF_VIN_SE_REF
3078 /* Save the current state of GPADC_ANA_CONF[VIN_SE_REF] in order to restore it */
3079 BackupVinSeRefAnaConf = AdcBasePtr->GPADC_ANA_CONF;
3080 #endif
3081 #ifdef ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF
3082 if (ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_1V6 == ((REG_ACCESS_BY_ADDR(ADC_GPADC_CALCFG0_ADDR) & ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_MASK) >> ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_SHIFT))
3083 {
3084 #ifdef ADC_GPADC_ANA_CONF_VIN_SE_REF
3085 /* GPADC_ANA_CONF[VIN_SE_REF] = 1 (enable self-test channel div2 mode) to be aligned with CALCFG0[SET_VREF_OUT_BUF] = 4 (1.6v) (only shown in DDTS) */
3086 AdcBasePtr->GPADC_ANA_CONF |= ADC_GPADC_ANA_CONF_VIN_SE_REF(1U);
3087 #endif /* ADC_GPADC_ANA_CONF_VIN_SE_REF */
3088 }
3089 else if (ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_0V8 == ((REG_ACCESS_BY_ADDR(ADC_GPADC_CALCFG0_ADDR) & ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_MASK) >> ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_SHIFT))
3090 {
3091 #ifdef ADC_GPADC_ANA_CONF_VIN_SE_REF
3092 /* GPADC_ANA_CONF[VIN_SE_REF] = 0 (disable self-test channel div2 mode) to be aligned with CALCFG0[SET_VREF_OUT_BUF] = 2 (0.8v) (only shown in DDTS) */
3093 AdcBasePtr->GPADC_ANA_CONF |= ADC_GPADC_ANA_CONF_VIN_SE_REF(0U);
3094 #endif /* ADC_GPADC_ANA_CONF_VIN_SE_REF */
3095 }
3096 else
3097 {
3098 /* Overwrite to 4 (1.6v vref) */
3099 REG_ACCESS_BY_ADDR(ADC_GPADC_CALCFG0_ADDR) &= ~(ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_MASK);
3100 REG_ACCESS_BY_ADDR(ADC_GPADC_CALCFG0_ADDR) |= ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF(ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF_1V6);
3101 #ifdef ADC_GPADC_ANA_CONF_VIN_SE_REF
3102 /* GPADC_ANA_CONF[VIN_SE_REF] = 1 (enable self-test channel div2 mode) to be aligned with CALCFG0[SET_VREF_OUT_BUF] = 4 (1.6v) (only shown in DDTS) */
3103 AdcBasePtr->GPADC_ANA_CONF |= ADC_GPADC_ANA_CONF_VIN_SE_REF(1U);
3104 #endif /* ADC_GPADC_ANA_CONF_VIN_SE_REF */
3105 /* Wait after changing SET_VREF_OUT_BUF to avoid unstable result */
3106 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_BANDGAP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
3107 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
3108 ElapsedTicks = 0u;
3109 while (ElapsedTicks < TimeoutTicks)
3110 {
3111 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3112 }
3113 }
3114 #endif /* ADC_GPADC_CALCFG0_SET_VREF_OUT_BUF */
3115
3116 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35();
3117 /* 5. Enable the self-testing channel by setting STCR2[EN]. */
3118 *STCR2Addr |= ADC_STCR2_EN(0x1UL);
3119 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35();
3120
3121 /* 6. Start the normal conversion by setting MCR[NSTART]. */
3122 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11();
3123 *MCRAddr |= ADC_MCR_NSTART(0x1UL);
3124 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11();
3125
3126 /* Check that all algorithms have executed at least once. */
3127 Status = Adc_Sar_CheckSelfTestProgress(u32Instance);
3128
3129 /* Stop the conversion */
3130 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11();
3131 *MCRAddr &= ~(ADC_MCR_NSTART(0x1UL));
3132 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11();
3133
3134 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3135 {
3136 /* Read ADC status */
3137 MsrStatus = ((*MSRAddr) & ADC_MSR_ADCSTATUS_MASK) >> ADC_MSR_ADCSTATUS_SHIFT;
3138 /* Wait for ADC changes to the expected Idle mode, The bitfield MSR[ADCSTATUS] should be checked to Idle state when MCR[NSTART] is written to 0 */
3139 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
3140 ElapsedTicks = 0U;
3141 while ((MsrStatus != ADC_MSR_ADCSTATUS(ADC_SAR_IP_MSR_ADCSTATUS_IDLE)) && (ElapsedTicks < TimeoutTicks))
3142 {
3143 MsrStatus = ((*MSRAddr) & ADC_MSR_ADCSTATUS_MASK) >> ADC_MSR_ADCSTATUS_SHIFT;
3144 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3145 }
3146 }
3147
3148 Adc_Sar_DisableSelftestThreshold(u32Instance);
3149
3150 #ifdef ADC_GPADC_ANA_TEST0_VDAC
3151 /* Restore the state of GPADC_ANA_TEST0[VDAC] */
3152 AdcBasePtr->GPADC_ANA_TEST0 = BackupVdacAnaTest0;
3153 #endif /* ADC_GPADC_ANA_TEST0_VDAC */
3154 #ifdef ADC_GPADC_ANA_CONF_VIN_SE_REF
3155 /* Restore the state of GPADC_ANA_CONF[VIN_SE_REF] */
3156 AdcBasePtr->GPADC_ANA_CONF = BackupVinSeRefAnaConf;
3157 #endif /* ADC_GPADC_ANA_CONF_VIN_SE_REF */
3158
3159 /* Disable Self-test */
3160 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35();
3161 *STCR2Addr &= ~(ADC_STCR2_EN(0x1UL));
3162 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35();
3163
3164 #if ADC_SAR_IP_SELFTEST_FULL_CLK
3165 }
3166 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3167 {
3168 /* Enter into power-down Mode */
3169 Status = Adc_Sar_Ip_Powerdown(u32Instance);
3170 #if ADC_SAR_IP_HAS_ADCLKSEL
3171 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11();
3172 /* Restore the state of ADCLKSEL */
3173 *MCRAddr &= ~(ADC_MCR_ADCLKSEL_MASK);
3174 *MCRAddr |= AdcClkSel;
3175 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11();
3176 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
3177
3178 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3179 {
3180 /* Exit into power-down Mode */
3181 Status = Adc_Sar_Ip_Powerup(u32Instance);
3182 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3183 #endif /* ADC_SAR_IP_SELFTEST_FULL_CLK */
3184 {
3185 Status = Adc_Sar_CheckTimeoutStatus(ElapsedTicks, TimeoutTicks);
3186 }
3187 #if ADC_SAR_IP_SELFTEST_FULL_CLK
3188 }
3189 }
3190 }
3191 #endif /* ADC_SAR_IP_SELFTEST_FULL_CLK */
3192 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
3193 }
3194 else
3195 {
3196 Status = ADC_SAR_IP_STATUS_CAL_ONGOING;
3197 }
3198 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
3199 return Status;
3200 }
3201 #endif /* (STD_ON == ADC_SAR_IP_SELFTEST_ENABLED) */
3202
3203 /*FUNCTION**********************************************************************
3204 *
3205 * Function Name : Adc_Sar_Ip_GetConvDataToArray
3206 * Description : This function reads the conversion result values for a conversion chain
3207 * (ADC_SAR_IP_CONV_CHAIN_NORMAL, ADC_SAR_IP_CONV_CHAIN_INJECTED or ADC_SAR_IP_CONV_CHAIN_CTU).
3208 *
3209 * @implements Adc_Sar_Ip_GetConvDataToArray_Activity
3210 * END**************************************************************************/
Adc_Sar_Ip_GetConvDataToArray(const uint32 u32Instance,const Adc_Sar_Ip_ConvChainType pChainType,const uint32 u32Length,uint16 * const pResults)3211 uint32 Adc_Sar_Ip_GetConvDataToArray(const uint32 u32Instance,
3212 const Adc_Sar_Ip_ConvChainType pChainType,
3213 const uint32 u32Length,
3214 uint16 * const pResults)
3215 {
3216 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3217 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3218 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3219 return Adc_Sar_GetConvResults(u32Instance, pChainType, pResults, NULL_PTR, u32Length);
3220 }
3221
3222 /*FUNCTION**********************************************************************
3223 *
3224 * Function Name : Adc_Sar_Ip_GetConvResultsToArray
3225 * Description : This function gets the conversion results for the selected
3226 * Conversion Chain. It follows the same algorithm as Adc_Sar_Ip_GetConvDataToArray,
3227 * but will copy some extra information to the output.
3228 *
3229 * @implements Adc_Sar_Ip_GetConvResultsToArray_Activity
3230 * END**************************************************************************/
Adc_Sar_Ip_GetConvResultsToArray(const uint32 u32Instance,const Adc_Sar_Ip_ConvChainType pChainType,const uint32 u32Length,Adc_Sar_Ip_ChanResultType * const pResults)3231 uint32 Adc_Sar_Ip_GetConvResultsToArray(const uint32 u32Instance,
3232 const Adc_Sar_Ip_ConvChainType pChainType,
3233 const uint32 u32Length,
3234 Adc_Sar_Ip_ChanResultType* const pResults)
3235 {
3236 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3237 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3238 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3239 return Adc_Sar_GetConvResults(u32Instance, pChainType, NULL_PTR, pResults, u32Length);
3240 }
3241
3242 /*FUNCTION**********************************************************************
3243 *
3244 * Function Name : Adc_Sar_Ip_GetConvData
3245 * Description : This function returns the result of the conversion for
3246 * a single channel
3247 *
3248 * @implements Adc_Sar_Ip_GetConvData_Activity
3249 * END**************************************************************************/
Adc_Sar_Ip_GetConvData(const uint32 u32Instance,const uint32 u32ChnIdx)3250 uint16 Adc_Sar_Ip_GetConvData(const uint32 u32Instance,
3251 const uint32 u32ChnIdx)
3252 {
3253 uint16 Result = 0U;
3254 uint32 VectAdr;
3255 uint32 VectBit;
3256 uint32 Cdr;
3257 ADC_Type * AdcBasePtr = NULL_PTR;
3258 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3259 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3260 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3261
3262 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3263 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3264 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
3265 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
3266 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
3267 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
3268 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3269
3270 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
3271 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
3272 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3273 if (u32Instance >= ADC_INSTANCE_COUNT)
3274 {
3275 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3276 Cdr = CDR_AE(AdcAEBasePtr, u32ChnIdx);
3277 /* check if the conversion data is valid */
3278 if (((Cdr & ADC_CDR_VALID_MASK) != 0U))
3279 {
3280 /* the data is correct, store the result in and clear the flag */
3281 Result = Adc_Sar_GetMaskedResult(u32Instance, Cdr);
3282 CEOCFR(AdcAEBasePtr, VectAdr) = ((uint32)1UL << VectBit); /* w1c bit */
3283 }
3284 }
3285 else
3286 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3287 {
3288 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3289 Cdr = CDR(AdcBasePtr, u32ChnIdx);
3290 /* check if the conversion data is valid */
3291 if (((Cdr & ADC_CDR_VALID_MASK) != 0U))
3292 {
3293 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
3294 if (!(((ADC_CDR_RESULT((uint32)ADC_SAR_IP_CONV_CHAIN_INJECTED) == (Cdr & (ADC_CDR_RESULT_MASK))) \
3295 || (ADC_CDR_RESULT((uint32)ADC_SAR_IP_CONV_CHAIN_CTU) == (Cdr & (ADC_CDR_RESULT_MASK)))) \
3296 && (0u == u32ChnIdx) \
3297 ) \
3298 )
3299 #endif
3300 {
3301 /* the data is correct, store the result in and clear the flag */
3302 Result = Adc_Sar_GetMaskedResult(u32Instance, Cdr);
3303 CEOCFR(AdcBasePtr, VectAdr) = ((uint32)1UL << VectBit); /* w1c bit */
3304 }
3305 }
3306 }
3307
3308 return Result;
3309 }
3310
3311 /*FUNCTION**********************************************************************
3312 *
3313 * Function Name : Adc_Sar_Ip_GetConvResult
3314 * Description : This function returns the result and the status of
3315 * the conversion for a single channel
3316 *
3317 * @implements Adc_Sar_Ip_GetConvResult_Activity
3318 * END**************************************************************************/
Adc_Sar_Ip_GetConvResult(const uint32 u32Instance,const uint32 u32ChnIdx,const Adc_Sar_Ip_ConvChainType pChainType,Adc_Sar_Ip_ChanResultType * const pResult)3319 void Adc_Sar_Ip_GetConvResult(const uint32 u32Instance,
3320 const uint32 u32ChnIdx,
3321 const Adc_Sar_Ip_ConvChainType pChainType,
3322 Adc_Sar_Ip_ChanResultType * const pResult)
3323 {
3324 uint32 VectAdr;
3325 uint32 VectBit;
3326 uint32 Cdr;
3327 volatile uint32 * CEOCFRAddr = NULL_PTR;
3328 ADC_Type * AdcBasePtr = NULL_PTR;
3329 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3330 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3331 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3332
3333 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3334 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3335 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
3336 DevAssert(pResult != NULL_PTR);
3337 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
3338 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
3339 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
3340 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3341
3342 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
3343 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
3344
3345 pResult->ConvData = 0u;
3346 pResult->AdcChnIdx = (uint8)u32ChnIdx;
3347 pResult->ValidFlag = FALSE;
3348 pResult->OverWrittenFlag = FALSE;
3349
3350 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3351 if (u32Instance >= ADC_INSTANCE_COUNT)
3352 {
3353 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3354 Cdr = CDR_AE(AdcAEBasePtr, u32ChnIdx);
3355 CEOCFRAddr = &(CEOCFR(AdcAEBasePtr, VectAdr));
3356 }
3357 else
3358 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3359 {
3360 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3361 Cdr = CDR(AdcBasePtr, u32ChnIdx);
3362 CEOCFRAddr = &(CEOCFR(AdcBasePtr, VectAdr));
3363 }
3364
3365 /* check if the result type matches the one request by pChainType */
3366 if (ADC_CDR_RESULT((uint32)pChainType) == (Cdr & ADC_CDR_RESULT_MASK))
3367 {
3368 #if FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND
3369 if (!((0U == u32ChnIdx) && ((ADC_SAR_IP_CONV_CHAIN_INJECTED == pChainType) || (ADC_SAR_IP_CONV_CHAIN_CTU == pChainType))))
3370 #endif /* FEATURE_ADC_SAF8544_CHANNEL_WORKAROUND */
3371 {
3372 pResult->ValidFlag = ((Cdr & ADC_CDR_VALID_MASK) != 0U) ? TRUE : FALSE;
3373 pResult->OverWrittenFlag = (1U == ((Cdr & ADC_CDR_OVERW_MASK) >> ADC_CDR_OVERW_SHIFT));
3374 pResult->ConvData = Adc_Sar_GetMaskedResult(u32Instance, Cdr);
3375 }
3376 }
3377
3378 *CEOCFRAddr = ((uint32)1UL << VectBit); /* w1c bit */
3379 }
3380
3381 #if FEATURE_ADC_HAS_CALIBRATION
3382 /*FUNCTION**********************************************************************
3383 *
3384 * Function Name : Adc_Sar_Ip_DoCalibration
3385 * Description : This functions executes a calibration sequence. It is recommended
3386 * to run this sequence before using the ADC converter. The maximum clock frequency
3387 * for the calibration is 40 MHz, this function sets the ADCLKSEL bit resulting in
3388 * a maximum input clock frequency of 80 MHz.
3389 *
3390 * @implements Adc_Sar_Ip_DoCalibration_Activity
3391 * END**************************************************************************/
Adc_Sar_Ip_DoCalibration(const uint32 u32Instance)3392 Adc_Sar_Ip_StatusType Adc_Sar_Ip_DoCalibration(const uint32 u32Instance)
3393 {
3394 ADC_Type * AdcBasePtr = NULL_PTR;
3395 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3396 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3397 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3398 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
3399 Adc_Sar_Ip_StatusType CalStatus = ADC_SAR_IP_STATUS_SUCCESS;
3400 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
3401 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
3402 uint32 ElapsedTicks = 0u;
3403
3404 static uint32 McrSavedValue = 0u;
3405 #if ADC_SAR_IP_CALIBRATION_USES_MCR
3406 uint32 Mcr;
3407 #endif /* ADC_SAR_IP_CALIBRATION_USES_MCR */
3408 volatile uint32 * MCRAddr = NULL_PTR;
3409 #if (!ADC_SAR_IP_CALIBRATION_USES_MCR || FEATURE_ADC_HAS_APPLICATION_EXTENSION)
3410 uint32 Calbistreg;
3411 volatile uint32 * CALBISTREGAddr = NULL_PTR;
3412 #if defined(ADC_CAL2_ENX_MASK)
3413 volatile uint32 * CAL2Addr = NULL_PTR;
3414 #endif /* defined(ADC_CAL2_ENX_MASK) */
3415 #endif /* (!ADC_SAR_IP_CALIBRATION_USES_MCR || FEATURE_ADC_HAS_APPLICATION_EXTENSION) */
3416
3417 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3418 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3419 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3420
3421 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3422 if (u32Instance >= ADC_INSTANCE_COUNT)
3423 {
3424 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3425 MCRAddr = (volatile uint32 *)&(AdcAEBasePtr->MCR);
3426 CALBISTREGAddr = (volatile uint32 *)&(AdcAEBasePtr->CALBISTREG);
3427 #if defined(ADC_CAL2_ENX_MASK)
3428 CAL2Addr = (volatile uint32 *)&(AdcAEBasePtr->CAL2);
3429 #endif /* defined(ADC_CAL2_ENX_MASK) */
3430 }
3431 else
3432 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3433 {
3434 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3435 MCRAddr = (volatile uint32 *)&(AdcBasePtr->MCR);
3436 #if !ADC_SAR_IP_CALIBRATION_USES_MCR
3437 CALBISTREGAddr = (volatile uint32 *)&(AdcBasePtr->CALBISTREG);
3438 #if defined(ADC_CAL2_ENX_MASK)
3439 CAL2Addr = (volatile uint32 *)&(AdcBasePtr->CAL2);
3440 #endif /* defined(ADC_CAL2_ENX_MASK) */
3441 #endif /* !ADC_SAR_IP_CALIBRATION_USES_MCR */
3442 }
3443
3444 #if (!ADC_SAR_IP_CALIBRATION_USES_MCR || FEATURE_ADC_HAS_APPLICATION_EXTENSION)
3445 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3446 if (u32Instance >= ADC_INSTANCE_COUNT)
3447 {
3448 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3449 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
3450 if (Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing == FALSE)
3451 {
3452 Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing = TRUE;
3453 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
3454 Status = Adc_Sar_CalibrationClkSelect(u32Instance, MCRAddr, &McrSavedValue);
3455
3456 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3457 {
3458 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_36();
3459 Calbistreg = *CALBISTREGAddr;
3460 /* clear the bits and set to calibration values */
3461 Calbistreg &= ~(ADC_SAR_IP_CALBISTREG_TSAMP_MASK | ADC_SAR_IP_CALBISTREG_NR_SMPL_MASK | ADC_SAR_IP_CALBISTREG_AVG_EN_MASK | ADC_SAR_IP_CALBISTREG_TEST_EN_MASK);
3462 Calbistreg |= ADC_SAR_IP_CALBISTREG_NR_SMPL(0x03u) | ADC_SAR_IP_CALBISTREG_AVG_EN(1U);
3463 *CALBISTREGAddr = Calbistreg;
3464 /* clear the calibration failed before a new calibration */
3465 *CALBISTREGAddr |= ADC_SAR_IP_CALBISTREG_TEST_FAIL_MASK;
3466 /* Disable the error correction for the smaller capacitances in the CDAC of the ADC */
3467 #if defined(ADC_CAL2_ENX_MASK)
3468 *CAL2Addr &= ~(ADC_CAL2_ENX_MASK);
3469 #endif /* defined(ADC_CAL2_ENX_MASK) */
3470 /* Start calibration */
3471 *CALBISTREGAddr |= ADC_SAR_IP_CALBISTREG_TEST_EN(1U);
3472 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_36();
3473
3474 }
3475 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
3476 Status = ADC_SAR_IP_STATUS_CAL_ONGOING;
3477 }
3478 else
3479 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
3480 {
3481
3482 /* Wait for calibration to finish */
3483 while (((*CALBISTREGAddr & ADC_SAR_IP_CALBISTREG_C_T_BUSY_MASK) != 0U) && (ElapsedTicks < TimeoutTicks))
3484 {
3485 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3486 }
3487 if (ElapsedTicks >= TimeoutTicks)
3488 {
3489 CalStatus = ADC_SAR_IP_STATUS_TIMEOUT;
3490 }
3491 else if ((*CALBISTREGAddr & ADC_SAR_IP_CALBISTREG_TEST_FAIL_MASK) != 0U)
3492 {
3493 /* If the calibration failed, return error */
3494 CalStatus = ADC_SAR_IP_STATUS_ERROR;
3495 }
3496 else
3497 {
3498 ; /* Empty else branch to avoid MISRA */
3499 }
3500 Status = Adc_Sar_CalibrationClkRestore(u32Instance, MCRAddr, McrSavedValue);
3501
3502 }
3503 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3504 }
3505 else
3506 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3507 #endif /* (!ADC_SAR_IP_CALIBRATION_USES_MCR || FEATURE_ADC_HAS_APPLICATION_EXTENSION) */
3508 {
3509 #if ADC_SAR_IP_CALIBRATION_USES_MCR
3510 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
3511 if(Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing == FALSE)
3512 {
3513 Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing = TRUE;
3514 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
3515 Status = Adc_Sar_CalibrationClkSelect(u32Instance, MCRAddr, &McrSavedValue);
3516
3517 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3518 {
3519 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12();
3520 /* Clear the bits and set to calibration values */
3521 Mcr = AdcBasePtr->MCR;
3522 Mcr &= ~(ADC_MCR_TSAMP_MASK | ADC_MCR_NRSMPL_MASK | ADC_MCR_AVGEN_MASK);
3523 Mcr |= ADC_MCR_NRSMPL(0x03u) | ADC_MCR_AVGEN(1U);
3524 AdcBasePtr->MCR = Mcr;
3525
3526 /* Start calibration */
3527 AdcBasePtr->MCR |= ADC_MCR_CALSTART(1U);
3528 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12();
3529 }
3530 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
3531 Status = ADC_SAR_IP_STATUS_CAL_ONGOING;
3532 }
3533 else
3534 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)*/
3535 {
3536 /* Wait for calibration to finish */
3537 while (((AdcBasePtr->MSR & ADC_MSR_CALBUSY_MASK) != 0U) && (ElapsedTicks < TimeoutTicks))
3538 {
3539 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3540 }
3541
3542 if (ElapsedTicks >= TimeoutTicks)
3543 {
3544 CalStatus = ADC_SAR_IP_STATUS_TIMEOUT;
3545 }
3546 else if ((AdcBasePtr->MSR & ADC_MSR_CALFAIL_MASK) != 0U)
3547 {
3548 /* If the calibration failed, return error */
3549 CalStatus = ADC_SAR_IP_STATUS_ERROR;
3550 }
3551 else
3552 {
3553 ; /* Empty else branch to avoid MISRA */
3554 }
3555 Status = Adc_Sar_CalibrationClkRestore(u32Instance, MCRAddr, McrSavedValue);
3556 }
3557 #endif /* ADC_SAR_IP_CALIBRATION_USES_MCR */
3558 }
3559 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
3560 {
3561 Status = CalStatus;
3562 }
3563 return Status;
3564 }
3565 #endif /* FEATURE_ADC_HAS_CALIBRATION */
3566
3567 /*FUNCTION**********************************************************************
3568 *
3569 * Function Name : Adc_Sar_Ip_Powerup
3570 * Description : This function enables the ADC module (by clearing the Powerdown
3571 * bit).
3572 *
3573 * @implements Adc_Sar_Ip_Powerup_Activity
3574 * END**************************************************************************/
Adc_Sar_Ip_Powerup(const uint32 u32Instance)3575 Adc_Sar_Ip_StatusType Adc_Sar_Ip_Powerup(const uint32 u32Instance)
3576 {
3577 Adc_Sar_Ip_StatusType ReturnStatus = ADC_SAR_IP_STATUS_SUCCESS;
3578
3579 const ADC_Type * AdcBasePtr = NULL_PTR;
3580 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3581 const SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3582 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3583 #if ADC_SAR_IP_HAS_BANDGAP_STATUS
3584 uint32 BandGapStatus = 0u;
3585 #else
3586 uint32 ExpectedStatus = ADC_MSR_ADCSTATUS(ADC_SAR_IP_MSR_ADCSTATUS_IDLE); /* expected status is IDLE */
3587 uint32 MsrStatus;
3588 volatile const uint32 * MSRAddr = NULL_PTR;
3589 #endif /* ADC_SAR_IP_HAS_BANDGAP_STATUS */
3590 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
3591 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
3592 uint32 ElapsedTicks = 0u;
3593
3594 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3595 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3596 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3597
3598 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3599 if (u32Instance >= ADC_INSTANCE_COUNT)
3600 {
3601 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3602 #if !ADC_SAR_IP_HAS_BANDGAP_STATUS
3603 MSRAddr = (volatile const uint32 *)&(AdcAEBasePtr->MSR);
3604 #endif /* !ADC_SAR_IP_HAS_BANDGAP_STATUS */
3605 }
3606 else
3607 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3608 {
3609 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3610 #if !ADC_SAR_IP_HAS_BANDGAP_STATUS
3611 MSRAddr = (volatile const uint32 *)&(AdcBasePtr->MSR);
3612 #endif /* !ADC_SAR_IP_HAS_BANDGAP_STATUS */
3613 }
3614
3615 #if ADC_SAR_IP_HAS_BANDGAP_STATUS
3616 BandGapStatus = AdcBasePtr->GPADC_READOUT & ADC_GPADC_READOUT_BG_OK_MASK;
3617 #else
3618 MsrStatus = (*MSRAddr) & ADC_MSR_ADCSTATUS_MASK;
3619 #endif /* ADC_SAR_IP_HAS_BANDGAP_STATUS */
3620
3621 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_13();
3622 Adc_Sar_Powerup(u32Instance);
3623 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_13();
3624
3625 /* Wait for the device to power up */
3626 #if ADC_SAR_IP_HAS_BANDGAP_STATUS
3627 while ((0U == BandGapStatus) && (ElapsedTicks < TimeoutTicks))
3628 {
3629 BandGapStatus = AdcBasePtr->GPADC_READOUT & ADC_GPADC_READOUT_BG_OK_MASK;
3630 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3631 }
3632 #else
3633 while ((MsrStatus != ExpectedStatus) && (ElapsedTicks < TimeoutTicks))
3634 {
3635 MsrStatus = (*MSRAddr) & ADC_MSR_ADCSTATUS_MASK;
3636 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3637 }
3638 #endif /* ADC_SAR_IP_HAS_BANDGAP_STATUS */
3639
3640 if (ElapsedTicks >= TimeoutTicks)
3641 {
3642 ReturnStatus = ADC_SAR_IP_STATUS_TIMEOUT;
3643 }
3644 #if ADC_SAR_IP_HAS_BANDGAP_STATUS
3645 else
3646 {
3647 /* Wait for 20us after BandGap is OK */
3648 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_BANDGAP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
3649 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
3650 ElapsedTicks = 0u;
3651 while (ElapsedTicks < TimeoutTicks)
3652 {
3653 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3654 }
3655 }
3656 #endif /* ADC_SAR_IP_HAS_BANDGAP_STATUS */
3657
3658 #if (1U == FEATURE_ADC_HAS_CLOCK_DIVIDER)
3659 if (ADC_SAR_IP_STATUS_SUCCESS == ReturnStatus)
3660 {
3661 /* Ensure the clock div is enabled because it was automatically disabled when entering power-down mode */
3662 Adc_Sar_EnableClkDiv(u32Instance, TRUE);
3663 }
3664 #endif /* 1U == FEATURE_ADC_HAS_CLOCK_DIVIDER */
3665
3666 return ReturnStatus;
3667 }
3668
3669 /*FUNCTION**********************************************************************
3670 *
3671 * Function Name : Adc_Sar_Ip_Powerdown
3672 * Description : This function disables the ADC module (by setting the Powerdown
3673 * bit).
3674 *
3675 * @implements Adc_Sar_Ip_Powerdown_Activity
3676 * END**************************************************************************/
Adc_Sar_Ip_Powerdown(const uint32 u32Instance)3677 Adc_Sar_Ip_StatusType Adc_Sar_Ip_Powerdown(const uint32 u32Instance)
3678 {
3679 const ADC_Type * AdcBasePtr = NULL_PTR;
3680 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3681 const SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3682 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3683 Adc_Sar_Ip_StatusType ReturnStatus = ADC_SAR_IP_STATUS_SUCCESS;
3684
3685 #if ADC_SAR_IP_HAS_BANDGAP_STATUS
3686 uint32 BandGapStatus = 0u;
3687 #else
3688 uint32 ExpectedStatus = ADC_MSR_ADCSTATUS(ADC_SAR_IP_MSR_ADCSTATUS_POWER_DOWN); /* expected status is powered down */
3689 uint32 MsrStatus;
3690 volatile const uint32 * MSRAddr = NULL_PTR;
3691 #endif /* ADC_SAR_IP_HAS_BANDGAP_STATUS */
3692 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
3693 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
3694 uint32 ElapsedTicks = 0u;
3695
3696 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3697 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3698 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3699
3700 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3701 if (u32Instance >= ADC_INSTANCE_COUNT)
3702 {
3703 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3704 #if !ADC_SAR_IP_HAS_BANDGAP_STATUS
3705 MSRAddr = (volatile const uint32 *)&(AdcAEBasePtr->MSR);
3706 #endif /* !ADC_SAR_IP_HAS_BANDGAP_STATUS */
3707 }
3708 else
3709 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3710 {
3711 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3712 #if !ADC_SAR_IP_HAS_BANDGAP_STATUS
3713 MSRAddr = (volatile const uint32 *)&(AdcBasePtr->MSR);
3714 #endif /* !ADC_SAR_IP_HAS_BANDGAP_STATUS */
3715 }
3716
3717 #if ADC_SAR_IP_HAS_BANDGAP_STATUS
3718 BandGapStatus = AdcBasePtr->GPADC_READOUT & ADC_GPADC_READOUT_BG_OK_MASK;
3719 #else
3720 MsrStatus = (*MSRAddr) & ADC_MSR_ADCSTATUS_MASK;
3721 #endif /* ADC_SAR_IP_HAS_BANDGAP_STATUS */
3722
3723 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_14();
3724 Adc_Sar_Powerdown(u32Instance);
3725 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_14();
3726
3727 /* Wait for the device to power down */
3728 #if ADC_SAR_IP_HAS_BANDGAP_STATUS
3729 while ((1U == BandGapStatus) && (ElapsedTicks < TimeoutTicks))
3730 {
3731 BandGapStatus = AdcBasePtr->GPADC_READOUT & ADC_GPADC_READOUT_BG_OK_MASK;
3732 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3733 }
3734 #else
3735 while ((MsrStatus != ExpectedStatus) && (ElapsedTicks < TimeoutTicks))
3736 {
3737 MsrStatus = (*MSRAddr) & ADC_MSR_ADCSTATUS_MASK;
3738 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
3739 }
3740 #endif /* ADC_SAR_IP_HAS_BANDGAP_STATUS */
3741
3742 if (ElapsedTicks >= TimeoutTicks)
3743 {
3744 ReturnStatus = ADC_SAR_IP_STATUS_TIMEOUT;
3745 }
3746
3747 return ReturnStatus;
3748 }
3749
3750 #if ( \
3751 (STD_ON == ADC_SAR_IP_ECH_ENABLED) || (STD_ON == ADC_SAR_IP_JECH_ENABLED) || \
3752 (STD_ON == ADC_SAR_IP_EOC_ENABLED) || \
3753 ((ADC_SAR_IP_HAS_CTU == 1U) && (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)) \
3754 )
3755 /*FUNCTION**********************************************************************
3756 *
3757 * Function Name : Adc_Sar_Ip_EnableNotifications
3758 * Description : This function enables the ADC notifications set to '1' in the
3759 * mask parameter.
3760 *
3761 * @implements Adc_Sar_Ip_EnableNotifications_Activity
3762 * END**************************************************************************/
Adc_Sar_Ip_EnableNotifications(const uint32 u32Instance,const uint32 u32NotificationMask)3763 void Adc_Sar_Ip_EnableNotifications(const uint32 u32Instance,
3764 const uint32 u32NotificationMask)
3765 {
3766 ADC_Type * AdcBasePtr = NULL_PTR;
3767 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3768 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3769 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3770 uint32 ImrFlags = 0U;
3771
3772 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3773 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3774 DevAssert((u32NotificationMask & (~ADC_SAR_IP_NOTIF_FLAG_ALL)) == 0UL);
3775 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3776
3777 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3778 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_EOC) != 0U) ? ADC_IMR_MSKEOC(1U) : 0U;
3779 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_EOC) != 0U) ? ADC_IMR_MSKJEOC(1U) : 0U;
3780 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3781 #if (STD_ON == ADC_SAR_IP_ECH_ENABLED)
3782 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN) != 0U) ? ADC_IMR_MSKECH(1U) : 0U;
3783 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) */
3784 #if (STD_ON == ADC_SAR_IP_JECH_ENABLED)
3785 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN) != 0U) ? ADC_IMR_MSKJECH(1U) : 0U;
3786 #endif /* (STD_ON == ADC_SAR_IP_JECH_ENABLED) */
3787 #if ADC_SAR_IP_HAS_CTU
3788 #if (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)
3789 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
3790 if (ADC_SAR_IP_INST_HAS_CTU(u32Instance))
3791 {
3792 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
3793 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_CTU_EOC) != 0U) ? ADC_IMR_MSKEOCTU(1U) : 0U;
3794 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
3795 }
3796 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
3797 #endif /* (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) */
3798 #endif /* ADC_SAR_IP_HAS_CTU */
3799
3800 /* Clear pending interrupt flags - CPR_RTD_01182 */
3801 Adc_Sar_Ip_ClearStatusFlags(u32Instance, ADC_SAR_IP_NOTIF_FLAG_ALL);
3802
3803 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3804 if (u32Instance >= ADC_INSTANCE_COUNT)
3805 {
3806 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3807 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_33();
3808 AdcAEBasePtr->IMR |= ImrFlags;
3809 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_33();
3810 }
3811 else
3812 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3813 {
3814 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3815 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_33();
3816 AdcBasePtr->IMR |= ImrFlags;
3817 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_33();
3818 }
3819 }
3820
3821 /*FUNCTION**********************************************************************
3822 *
3823 * Function Name : Adc_Sar_Ip_DisableNotifications
3824 * Description : This function disables the ADC notifications set to '1' in the
3825 * mask parameter.
3826 *
3827 * @implements Adc_Sar_Ip_DisableNotifications_Activity
3828 * END**************************************************************************/
Adc_Sar_Ip_DisableNotifications(const uint32 u32Instance,const uint32 u32NotificationMask)3829 void Adc_Sar_Ip_DisableNotifications(const uint32 u32Instance,
3830 const uint32 u32NotificationMask)
3831 {
3832 ADC_Type * AdcBasePtr = NULL_PTR;
3833 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3834 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3835 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3836 uint32 ImrFlags = 0U;
3837
3838 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3839 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3840 DevAssert((u32NotificationMask & (~ADC_SAR_IP_NOTIF_FLAG_ALL)) == 0UL);
3841 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3842
3843 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3844 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_EOC) != 0U) ? ADC_IMR_MSKEOC(1U) : 0U;
3845 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_EOC) != 0U) ? ADC_IMR_MSKJEOC(1U) : 0U;
3846 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3847 #if (STD_ON == ADC_SAR_IP_ECH_ENABLED)
3848 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_NORMAL_ENDCHAIN) != 0U) ? ADC_IMR_MSKECH(1U) : 0U;
3849 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) */
3850 #if (STD_ON == ADC_SAR_IP_JECH_ENABLED)
3851 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_INJECTED_ENDCHAIN) != 0U) ? ADC_IMR_MSKJECH(1U) : 0U;
3852 #endif /* (STD_ON == ADC_SAR_IP_JECH_ENABLED) */
3853 #if ADC_SAR_IP_HAS_CTU
3854 #if (STD_ON == ADC_SAR_IP_EOCTU_ENABLED)
3855 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
3856 if (ADC_SAR_IP_INST_HAS_CTU(u32Instance))
3857 {
3858 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
3859 ImrFlags |= ((u32NotificationMask & ADC_SAR_IP_NOTIF_FLAG_CTU_EOC) != 0U) ? ADC_IMR_MSKEOCTU(1U) : 0U;
3860 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
3861 }
3862 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
3863 #endif /* (STD_ON == ADC_SAR_IP_EOCTU_ENABLED) */
3864 #endif /* ADC_SAR_IP_HAS_CTU */
3865 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3866 if (u32Instance >= ADC_INSTANCE_COUNT)
3867 {
3868 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3869 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_34();
3870 AdcAEBasePtr->IMR &= ~(ImrFlags);
3871 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_34();
3872 }
3873 else
3874 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3875 {
3876 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3877 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_34();
3878 AdcBasePtr->IMR &= ~(ImrFlags);
3879 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_34();
3880 }
3881 }
3882 #endif /* (STD_ON == ADC_SAR_IP_ECH_ENABLED) .. */
3883
3884 #if ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED))
3885 /*FUNCTION**********************************************************************
3886 *
3887 * Function Name : Adc_Sar_Ip_EnableChannelNotifications
3888 * Description : This function enables End-of-Conversion and watchdog
3889 * interrupts generation for a single channel.
3890 *
3891 * @implements Adc_Sar_Ip_EnableChannelNotifications_Activity
3892 * END**************************************************************************/
Adc_Sar_Ip_EnableChannelNotifications(const uint32 u32Instance,const uint32 u32ChnIdx,const uint32 u32Mask)3893 void Adc_Sar_Ip_EnableChannelNotifications(const uint32 u32Instance,
3894 const uint32 u32ChnIdx,
3895 const uint32 u32Mask)
3896 {
3897 ADC_Type * AdcBasePtr = NULL_PTR;
3898 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3899 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3900 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3901 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3902 volatile uint32 * CIMRAddr = NULL_PTR;
3903 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3904 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3905 volatile uint32 * CWENRAddr = NULL_PTR;
3906 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3907 uint32 VectAdr;
3908 uint32 VectBit;
3909
3910 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3911 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3912 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
3913 DevAssert((u32Mask & ~(ADC_SAR_IP_CHAN_NOTIF_FLAG_ALL)) == 0UL);
3914 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
3915 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
3916 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
3917 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3918
3919 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
3920 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
3921
3922 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3923 if (u32Instance >= ADC_INSTANCE_COUNT)
3924 {
3925 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
3926 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3927 CIMRAddr = &(CIMR(AdcAEBasePtr, VectAdr));
3928 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3929 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3930 CWENRAddr = &(CWENR(AdcAEBasePtr, VectAdr));
3931 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3932 }
3933 else
3934 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3935 {
3936 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
3937 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3938 CIMRAddr = &(CIMR(AdcBasePtr, VectAdr));
3939 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3940 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3941 CWENRAddr = &(CWENR(AdcBasePtr, VectAdr));
3942 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3943 }
3944
3945 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3946 if ((u32Mask & ADC_SAR_IP_CHAN_NOTIF_EOC) != 0u)
3947 {
3948 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_30();
3949 *CIMRAddr |= 1UL << VectBit;
3950 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_30();
3951 }
3952 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3953
3954 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3955 if ((u32Mask & ADC_SAR_IP_CHAN_NOTIF_WDG) != 0u)
3956 {
3957 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_28();
3958 *CWENRAddr |= 1UL << VectBit;
3959 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_28();
3960 }
3961 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3962 }
3963
3964 /*FUNCTION**********************************************************************
3965 *
3966 * Function Name : Adc_Sar_Ip_DisableChannelNotifications
3967 * Description : This function disables End-of-Conversion and watchdog
3968 * interrupts generation for a single channel.
3969 *
3970 * @implements Adc_Sar_Ip_DisableChannelNotifications_Activity
3971 * END**************************************************************************/
Adc_Sar_Ip_DisableChannelNotifications(const uint32 u32Instance,const uint32 u32ChnIdx,const uint32 u32Mask)3972 void Adc_Sar_Ip_DisableChannelNotifications(const uint32 u32Instance,
3973 const uint32 u32ChnIdx,
3974 const uint32 u32Mask)
3975 {
3976 ADC_Type * AdcBasePtr = NULL_PTR;
3977 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
3978 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
3979 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
3980 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
3981 volatile uint32 * CIMRAddr = NULL_PTR;
3982 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
3983 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
3984 volatile uint32 * CWENRAddr = NULL_PTR;
3985 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
3986 uint32 VectAdr;
3987 uint32 VectBit;
3988
3989 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
3990 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
3991 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
3992 DevAssert((u32Mask & ~(ADC_SAR_IP_CHAN_NOTIF_FLAG_ALL)) == 0UL);
3993 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
3994 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
3995 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
3996 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
3997
3998 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
3999 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
4000
4001 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4002 if (u32Instance >= ADC_INSTANCE_COUNT)
4003 {
4004 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4005 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
4006 CIMRAddr = &(CIMR(AdcAEBasePtr, VectAdr));
4007 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
4008 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
4009 CWENRAddr = &(CWENR(AdcAEBasePtr, VectAdr));
4010 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
4011 }
4012 else
4013 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4014 {
4015 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4016 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
4017 CIMRAddr = &(CIMR(AdcBasePtr, VectAdr));
4018 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
4019 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
4020 CWENRAddr = &(CWENR(AdcBasePtr, VectAdr));
4021 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
4022 }
4023
4024 #if (STD_ON == ADC_SAR_IP_EOC_ENABLED)
4025 if ((u32Mask & ADC_SAR_IP_CHAN_NOTIF_EOC) != 0u)
4026 {
4027 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_31();
4028 *CIMRAddr &= ~(1UL << VectBit);
4029 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_31();
4030 }
4031 #endif /* (STD_ON == ADC_SAR_IP_EOC_ENABLED) */
4032
4033 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
4034 if ((u32Mask & ADC_SAR_IP_CHAN_NOTIF_WDG) != 0u)
4035 {
4036 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_29();
4037 *CWENRAddr &= ~(1UL << VectBit);
4038 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_29();
4039 }
4040 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
4041 }
4042 #endif /* ((STD_ON == ADC_SAR_IP_WDG_ENABLED) || (STD_ON == ADC_SAR_IP_EOC_ENABLED)) */
4043
4044 /*FUNCTION**********************************************************************
4045 *
4046 * Function Name : Adc_Sar_Ip_SetClockMode
4047 * Description : This function initializes the ADC clock configuration.
4048 *
4049 * @implements Adc_Sar_Ip_SetClockMode_Activity
4050 * END**************************************************************************/
Adc_Sar_Ip_SetClockMode(const uint32 u32Instance,const Adc_Sar_Ip_ClockConfigType * const pConfig)4051 Adc_Sar_Ip_StatusType Adc_Sar_Ip_SetClockMode(const uint32 u32Instance,
4052 const Adc_Sar_Ip_ClockConfigType * const pConfig)
4053 {
4054 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
4055 #if ADC_SAR_IP_HAS_ADCLKSEL
4056 uint32 Mcr = 0u;
4057 volatile uint32 * MCRAddr = NULL_PTR;
4058 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
4059 volatile uint32 * PDEDRAddr = NULL_PTR;
4060 ADC_Type * AdcBasePtr = NULL_PTR;
4061 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4062 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4063 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4064
4065 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4066 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4067 DevAssert(pConfig != NULL_PTR);
4068 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4069 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
4070 /* calibration must not be interrupted */
4071 if(FALSE == Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing)
4072 {
4073 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
4074 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4075 if (u32Instance >= ADC_INSTANCE_COUNT)
4076 {
4077 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4078 #if ADC_SAR_IP_HAS_ADCLKSEL
4079 MCRAddr =(volatile uint32 *) &(AdcAEBasePtr->MCR);
4080 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
4081 PDEDRAddr = (volatile uint32 *)&(AdcAEBasePtr->PDEDR);
4082 }
4083 else
4084 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4085 {
4086 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4087 #if ADC_SAR_IP_HAS_ADCLKSEL
4088 MCRAddr = (volatile uint32 *)&(AdcBasePtr->MCR);
4089 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
4090 PDEDRAddr = (volatile uint32 *)&(AdcBasePtr->PDEDR);
4091 }
4092
4093 #if ADC_SAR_IP_HAS_ADCLKSEL
4094 /* Read MCR value and clear values that will be replaced */
4095 Mcr |= Adc_Sar_GetADCLKSELValue(pConfig->ClkSelect);
4096 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
4097 Status = Adc_Sar_Ip_Powerdown(u32Instance);
4098 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
4099 {
4100 #if ADC_SAR_IP_HAS_ADCLKSEL
4101 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_15();
4102 *MCRAddr = ((*MCRAddr) & ~(ADC_MCR_ADCLKSEL_MASK)) | Mcr;
4103 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_15();
4104 #endif /* ADC_SAR_IP_HAS_ADCLKSEL */
4105
4106 Status = Adc_Sar_Ip_Powerup(u32Instance);
4107 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
4108 {
4109 #if FEATURE_ADC_HAS_HIGH_SPEED_ENABLE
4110 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_51();
4111 /* Enables high speed conversion or calibration */
4112 Adc_Sar_EnableHighSpeed(AdcBasePtr, pConfig->HighSpeedConvEn);
4113 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_51();
4114 #endif /* FEATURE_ADC_HAS_HIGH_SPEED_ENABLE */
4115
4116 #if FEATURE_ADC_HAS_AVERAGING
4117 Adc_Sar_Ip_SetAveraging(u32Instance, pConfig->AvgEn, pConfig->AvgSel);
4118 #endif /* FEATURE_ADC_HAS_AVERAGING */
4119
4120 /* Set powerdown delay */
4121 *PDEDRAddr = ADC_PDEDR_PDED(pConfig->PowerDownDelay);
4122
4123 #if FEATURE_ADC_HAS_CONVERSION_TIMING
4124 /* Set sample times */
4125 Adc_Sar_Ip_SetSampleTimes(u32Instance, pConfig->SampleTimeArr);
4126 #endif /* FEATURE_ADC_HAS_CONVERSION_TIMING */
4127 }
4128 }
4129 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
4130 }
4131 else
4132 {
4133 Status = ADC_SAR_IP_STATUS_CAL_ONGOING;
4134 }
4135 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
4136 return Status;
4137 }
4138
4139 #if FEATURE_ADC_HAS_CONVERSION_TIMING
4140 /*FUNCTION**********************************************************************
4141 *
4142 * Function Name : Adc_Sar_Ip_SetSampleTimes
4143 * Description : This function sets the sample times for each channnel group.
4144 *
4145 * @implements Adc_Sar_Ip_SetSampleTimes_Activity
4146 * END**************************************************************************/
Adc_Sar_Ip_SetSampleTimes(const uint32 u32Instance,const uint8 * const aSampleTimes)4147 void Adc_Sar_Ip_SetSampleTimes(const uint32 u32Instance,
4148 const uint8 * const aSampleTimes)
4149 {
4150 ADC_Type * AdcBasePtr = NULL_PTR;
4151 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4152 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4153 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4154 uint8 Index;
4155
4156 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4157 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4158 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4159
4160 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4161 if (u32Instance >= ADC_INSTANCE_COUNT)
4162 {
4163 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4164 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
4165 {
4166 /* Set sample times */
4167 CTR(AdcAEBasePtr, Index) = ADC_CTR_INPSAMP(aSampleTimes[Index]);
4168 }
4169 }
4170 else
4171 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4172 {
4173 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4174 for (Index = 0u; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
4175 {
4176 /* Set sample times */
4177 CTR(AdcBasePtr, Index) = ADC_CTR_INPSAMP(aSampleTimes[Index]);
4178 }
4179 }
4180 }
4181 #endif /* FEATURE_ADC_HAS_CONVERSION_TIMING */
4182
4183
4184 /*FUNCTION**********************************************************************
4185 *
4186 * Function Name : Adc_Sar_Ip_AbortConversion
4187 * Description : This function aborts an ongoing conversion.
4188 *
4189 * @implements Adc_Sar_Ip_AbortConversion_Activity
4190 * END**************************************************************************/
Adc_Sar_Ip_AbortConversion(const uint32 u32Instance)4191 void Adc_Sar_Ip_AbortConversion(const uint32 u32Instance)
4192 {
4193 ADC_Type * AdcBasePtr = NULL_PTR;
4194 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4195 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4196 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4197
4198 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4199 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4200 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4201 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
4202 /* calibration must not be interrupted */
4203 if(FALSE == Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing)
4204 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
4205 {
4206 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4207 if (u32Instance >= ADC_INSTANCE_COUNT)
4208 {
4209 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4210 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_17();
4211 AdcAEBasePtr->MCR |= ADC_MCR_ABORT(1U);
4212 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_17();
4213 }
4214 else
4215 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4216 {
4217 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4218 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_17();
4219 AdcBasePtr->MCR |= ADC_MCR_ABORT(1U);
4220 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_17();
4221 }
4222
4223 }
4224 }
4225
4226 /*FUNCTION**********************************************************************
4227 *
4228 * Function Name : Adc_Sar_Ip_AbortChain
4229 * Description : This function aborts an ongoing chain of conversions.
4230 *
4231 * @implements Adc_Sar_Ip_AbortChain_Activity
4232 * END**************************************************************************/
Adc_Sar_Ip_AbortChain(const uint32 u32Instance,const boolean bBlocking,const boolean bAllowRestart)4233 Adc_Sar_Ip_StatusType Adc_Sar_Ip_AbortChain(const uint32 u32Instance,
4234 const boolean bBlocking,
4235 const boolean bAllowRestart)
4236 {
4237 ADC_Type * AdcBasePtr = NULL_PTR;
4238 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4239 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4240 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4241 volatile uint32 * MCRAddr = NULL_PTR;
4242 volatile const uint32 * MSRAddr = NULL_PTR;
4243 uint32 MsrStatus;
4244 uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_SAR_IP_TIMEOUT_VAL, ADC_SAR_IP_TIMEOUT_TYPE);
4245 uint32 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
4246 uint32 ElapsedTicks = 0u;
4247 Adc_Sar_Ip_StatusType ReturnStatus = ADC_SAR_IP_STATUS_SUCCESS;
4248
4249 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4250 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4251 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4252 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
4253 /* calibration must not be interrupted */
4254 if(FALSE == Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing)
4255 {
4256 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
4257 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4258 if (u32Instance >= ADC_INSTANCE_COUNT)
4259 {
4260 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4261 MCRAddr = (volatile uint32 *)&(AdcAEBasePtr->MCR);
4262 MSRAddr = (volatile uint32 *)&(AdcAEBasePtr->MSR);
4263 }
4264 else
4265 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4266 {
4267 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4268 MCRAddr = (volatile uint32 *)&(AdcBasePtr->MCR);
4269 MSRAddr = (volatile uint32 *)&(AdcBasePtr->MSR);
4270 }
4271
4272 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_18();
4273 /* The behavior of the ADC depends on MCR[MODE] (One-Shot/Scan Operation modes).
4274 If Scan Operation mode is disabled, MSR[NSTART] is automatically reset together with MCR[ABORTCHAIN].
4275 Otherwise, in Scan Operation mode, a new chain is started. Therefore MCR[NSTART] should be cleared
4276 before abort the current chain of conversions. */
4277 if (!bAllowRestart)
4278 {
4279 *MCRAddr &= ~(ADC_MCR_NSTART(1U));
4280 #if ADC_SAR_IP_ABORTCHAIN_WORKAROUND
4281 /* Workaround to fix abort chain cannot clear MSR[NSTART] bit in scan mode */
4282 while (ElapsedTicks < TimeoutTicks)
4283 {
4284 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
4285 }
4286 #endif /* ADC_SAR_IP_ABORTCHAIN_WORKAROUND */
4287 }
4288 *MCRAddr |= ADC_MCR_ABORTCHAIN(1U);
4289 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_18();
4290
4291 if (bBlocking)
4292 {
4293 #if ADC_SAR_IP_ABORTCHAIN_WORKAROUND
4294 CurrentTicks = OsIf_GetCounter(ADC_SAR_IP_TIMEOUT_TYPE);
4295 ElapsedTicks = 0u;
4296 #endif /* ADC_SAR_IP_ABORTCHAIN_WORKAROUND */
4297 /* Wait for the ongoing conversion to stop */
4298 MsrStatus = *MSRAddr & ADC_MSR_NSTART_MASK;
4299 while ((MsrStatus == ADC_MSR_NSTART_MASK) && (ElapsedTicks < TimeoutTicks))
4300 {
4301 MsrStatus = *MSRAddr & ADC_MSR_NSTART_MASK;
4302 ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_SAR_IP_TIMEOUT_TYPE);
4303 }
4304 if (ElapsedTicks >= TimeoutTicks)
4305 {
4306 ReturnStatus = ADC_SAR_IP_STATUS_TIMEOUT;
4307 }
4308 #if !ADC_SAR_IP_W1C_ABORT
4309 else
4310 {
4311 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_18();
4312 /* Clear the ABORT_CHAIN bit if set, otherwise the next chain will be ABORTED without any End of Chain Interrupt */
4313 if (((*MCRAddr) & ADC_MCR_ABORTCHAIN_MASK) != 0u)
4314 {
4315 *MCRAddr &= ~(ADC_MCR_ABORTCHAIN(1U));
4316 }
4317 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_18();
4318 }
4319 #endif /* ADC_SAR_IP_W1C_ABORT */
4320 }
4321 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
4322 }
4323 else
4324 {
4325 ReturnStatus = ADC_SAR_IP_STATUS_CAL_ONGOING;
4326 }
4327 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
4328 return ReturnStatus;
4329 }
4330
4331 #if FEATURE_ADC_HAS_PRESAMPLING
4332 /*FUNCTION**********************************************************************
4333 *
4334 * Function Name : Adc_Sar_Ip_SetPresamplingSource
4335 * Description : This function configures the Presampling Source for a channel group (0-31, 32-63, 64 -95)
4336 *
4337 * @implements Adc_Sar_Ip_SetPresamplingSource_Activity
4338 * END**************************************************************************/
Adc_Sar_Ip_SetPresamplingSource(const uint32 u32Instance,const Adc_Sar_Ip_ChanGroupType pChanGroup,const Adc_Sar_Ip_PresamplingSourceType pPresampleSource)4339 void Adc_Sar_Ip_SetPresamplingSource(const uint32 u32Instance,
4340 const Adc_Sar_Ip_ChanGroupType pChanGroup,
4341 const Adc_Sar_Ip_PresamplingSourceType pPresampleSource)
4342 {
4343 uint32 Pscr;
4344 ADC_Type * AdcBasePtr = NULL_PTR;
4345 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4346 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4347 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4348 volatile uint32 * PSCRAddr = NULL_PTR;
4349
4350 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4351 if (u32Instance >= ADC_INSTANCE_COUNT)
4352 {
4353 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4354 PSCRAddr = (volatile uint32 *)&(AdcAEBasePtr->PSCR);
4355 }
4356 else
4357 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4358 {
4359 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4360 PSCRAddr = (volatile uint32 *)&(AdcBasePtr->PSCR);
4361 }
4362
4363 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4364 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4365 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4366
4367 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
4368 if (ADC_SAR_IP_INST_HAS_PSCR(u32Instance))
4369 {
4370 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
4371
4372 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_38();
4373
4374 Pscr = *PSCRAddr;
4375
4376 switch (pChanGroup)
4377 {
4378 #ifdef ADC_PSCR_PREVAL0
4379 case ADC_SAR_IP_CHAN_GROUP_0:
4380 Pscr &= ~(ADC_PSCR_PREVAL0_MASK);
4381 Pscr |= ADC_PSCR_PREVAL0((uint32)pPresampleSource);
4382 break;
4383 #endif /* ADC_PSCR_PREVAL0 */
4384 #ifdef ADC_PSCR_PREVAL1
4385 case ADC_SAR_IP_CHAN_GROUP_1:
4386 Pscr &= ~(ADC_PSCR_PREVAL1_MASK);
4387 Pscr |= ADC_PSCR_PREVAL1((uint32)pPresampleSource);
4388 break;
4389 #endif /* ADC_PSCR_PREVAL1 */
4390 #ifdef ADC_PSCR_PREVAL2
4391 case ADC_SAR_IP_CHAN_GROUP_2:
4392 Pscr &= ~(ADC_PSCR_PREVAL2_MASK);
4393 Pscr |= ADC_PSCR_PREVAL2((uint32)pPresampleSource);
4394 break;
4395 #endif /* ADC_PSCR_PREVAL2 */
4396 default:
4397 ; /* no-op */
4398 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4399 /* Not supported */
4400 DevAssert(FALSE);
4401 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4402 break;
4403 }
4404
4405 *PSCRAddr = Pscr;
4406
4407 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_38();
4408 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
4409 }
4410 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
4411 }
4412
4413 /*FUNCTION**********************************************************************
4414 *
4415 * Function Name : Adc_Sar_Ip_EnableChannelPresampling
4416 * Description : This function enables the Presampling on one channel of the ADC.
4417 *
4418 * @implements Adc_Sar_Ip_EnableChannelPresampling_Activity
4419 * END**************************************************************************/
Adc_Sar_Ip_EnableChannelPresampling(const uint32 u32Instance,const uint32 u32ChnIdx)4420 void Adc_Sar_Ip_EnableChannelPresampling(const uint32 u32Instance,
4421 const uint32 u32ChnIdx)
4422 {
4423 uint32 VectAdr;
4424 uint32 VectBit;
4425 ADC_Type * AdcBasePtr = NULL_PTR;
4426 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4427 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4428 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4429
4430 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4431 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4432 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
4433 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
4434 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
4435 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
4436 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4437
4438 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
4439 if (ADC_SAR_IP_INST_HAS_PSCR(u32Instance))
4440 {
4441 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
4442 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
4443 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
4444 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4445 if (u32Instance >= ADC_INSTANCE_COUNT)
4446 {
4447 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4448 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_41();
4449 PSR(AdcAEBasePtr, VectAdr) |= 1UL << VectBit;
4450 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_41();
4451 }
4452 else
4453 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4454 {
4455 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4456 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_41();
4457 PSR(AdcBasePtr, VectAdr) |= 1UL << VectBit;
4458 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_41();
4459 }
4460 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
4461 }
4462 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
4463 }
4464
4465 /*FUNCTION**********************************************************************
4466 *
4467 * Function Name : Adc_Sar_Ip_DisableChannelPresampling
4468 * Description : This function disables the Presampling on one channel of the ADC.
4469 *
4470 * @implements Adc_Sar_Ip_DisableChannelPresampling_Activity
4471 * END**************************************************************************/
Adc_Sar_Ip_DisableChannelPresampling(const uint32 u32Instance,const uint32 u32ChnIdx)4472 void Adc_Sar_Ip_DisableChannelPresampling(const uint32 u32Instance,
4473 const uint32 u32ChnIdx)
4474 {
4475 uint32 VectAdr;
4476 uint32 VectBit;
4477 ADC_Type * AdcBasePtr = NULL_PTR;
4478 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4479 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4480 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4481
4482 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4483 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4484 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
4485 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
4486 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
4487 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
4488 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4489
4490 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
4491 if (ADC_SAR_IP_INST_HAS_PSCR(u32Instance))
4492 {
4493 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
4494 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
4495 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
4496 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4497 if (u32Instance >= ADC_INSTANCE_COUNT)
4498 {
4499 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4500 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_42();
4501 PSR(AdcAEBasePtr, VectAdr) &= ~(1UL << VectBit);
4502 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_42();
4503 }
4504 else
4505 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4506 {
4507 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4508 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_42();
4509 PSR(AdcBasePtr, VectAdr) &= ~(1UL << VectBit);
4510 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_42();
4511 }
4512 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
4513 }
4514 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
4515 }
4516
4517 /*FUNCTION**********************************************************************
4518 *
4519 * Function Name : Adc_Sar_Ip_EnablePresampleConversion
4520 * Description : This function enables bypass of the Sampling Phase, resulting in a conversion
4521 * of the presampled data. This is available only for channels that have presampling
4522 * enabled.
4523 *
4524 * @implements Adc_Sar_Ip_EnablePresampleConversion_Activity
4525 * END**************************************************************************/
Adc_Sar_Ip_EnablePresampleConversion(const uint32 u32Instance)4526 void Adc_Sar_Ip_EnablePresampleConversion(const uint32 u32Instance)
4527 {
4528 ADC_Type * AdcBasePtr = NULL_PTR;
4529 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4530 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4531 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4532
4533 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4534 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4535 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4536
4537 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
4538 if (ADC_SAR_IP_INST_HAS_PSCR(u32Instance))
4539 {
4540 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
4541
4542 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4543 if (u32Instance >= ADC_INSTANCE_COUNT)
4544 {
4545 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4546 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_39();
4547 AdcAEBasePtr->PSCR |= ADC_PSCR_PRECONV(1U);
4548 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_39();
4549 }
4550 else
4551 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4552 {
4553 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4554 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_39();
4555 AdcBasePtr->PSCR |= ADC_PSCR_PRECONV(1U);
4556 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_39();
4557 }
4558 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
4559 }
4560 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
4561 }
4562
4563 /*FUNCTION**********************************************************************
4564 *
4565 * Function Name : Adc_Sar_Ip_DisablePresampleConversion
4566 * Description : This function disables Sampling Phase bypass.
4567 *
4568 * @implements Adc_Sar_Ip_DisablePresampleConversion_Activity
4569 * END**************************************************************************/
Adc_Sar_Ip_DisablePresampleConversion(const uint32 u32Instance)4570 void Adc_Sar_Ip_DisablePresampleConversion(const uint32 u32Instance)
4571 {
4572 ADC_Type * AdcBasePtr = NULL_PTR;
4573 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4574 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4575 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4576
4577 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4578 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4579 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4580 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
4581 if (ADC_SAR_IP_INST_HAS_PSCR(u32Instance))
4582 {
4583 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
4584
4585 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4586 if (u32Instance >= ADC_INSTANCE_COUNT)
4587 {
4588 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4589 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_40();
4590 AdcAEBasePtr->PSCR &= ~(ADC_PSCR_PRECONV(1U));
4591 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_40();
4592 }
4593 else
4594 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4595 {
4596 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4597 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_40();
4598 AdcBasePtr->PSCR &= ~(ADC_PSCR_PRECONV(1U));
4599 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_40();
4600 }
4601
4602 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
4603 }
4604 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE */
4605 }
4606 #endif /* FEATURE_ADC_HAS_PRESAMPLING */
4607
4608 /*FUNCTION**********************************************************************
4609 *
4610 * Function Name : Adc_Sar_Ip_EnableDma
4611 * Description : This function enables requests to DMA from ADC
4612 *
4613 * @implements Adc_Sar_Ip_EnableDma_Activity
4614 * END**************************************************************************/
Adc_Sar_Ip_EnableDma(const uint32 u32Instance)4615 void Adc_Sar_Ip_EnableDma(const uint32 u32Instance)
4616 {
4617 ADC_Type * AdcBasePtr = NULL_PTR;
4618 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4619 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4620 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4621
4622 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4623 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4624 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4625
4626 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4627 if (u32Instance >= ADC_INSTANCE_COUNT)
4628 {
4629 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4630 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_43();
4631 AdcAEBasePtr->DMAE |= ADC_DMAE_DMAEN(1U);
4632 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_43();
4633 }
4634 else
4635 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4636 {
4637 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4638 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_43();
4639 AdcBasePtr->DMAE |= ADC_DMAE_DMAEN(1U);
4640 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_43();
4641 }
4642 }
4643
4644 /*FUNCTION**********************************************************************
4645 *
4646 * Function Name : Adc_Sar_Ip_DisableDma
4647 * Description : This function disables requests to DMA from ADC
4648 *
4649 * @implements Adc_Sar_Ip_DisableDma_Activity
4650 * END**************************************************************************/
Adc_Sar_Ip_DisableDma(const uint32 u32Instance)4651 void Adc_Sar_Ip_DisableDma(const uint32 u32Instance)
4652 {
4653 ADC_Type * AdcBasePtr = NULL_PTR;
4654 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4655 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4656 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4657
4658 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4659 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4660 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4661
4662 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4663 if (u32Instance >= ADC_INSTANCE_COUNT)
4664 {
4665 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4666 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_44();
4667 AdcAEBasePtr->DMAE &= ~(ADC_DMAE_DMAEN(1U));
4668 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_44();
4669 }
4670 else
4671 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4672 {
4673 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4674 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_44();
4675 AdcBasePtr->DMAE &= ~(ADC_DMAE_DMAEN(1U));
4676 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_44();
4677 }
4678 }
4679
4680 /*FUNCTION**********************************************************************
4681 *
4682 * Function Name : Adc_Sar_Ip_EnableChannelDma
4683 * Description : This function enables DMA requests triggered by End of Conversion event from
4684 * a selected channel.
4685 *
4686 * @implements Adc_Sar_Ip_EnableChannelDma_Activity
4687 * END**************************************************************************/
Adc_Sar_Ip_EnableChannelDma(const uint32 u32Instance,const uint32 u32ChnIdx)4688 void Adc_Sar_Ip_EnableChannelDma(const uint32 u32Instance,
4689 const uint32 u32ChnIdx)
4690 {
4691 ADC_Type * AdcBasePtr = NULL_PTR;
4692 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4693 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4694 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4695 uint32 VectAdr;
4696 uint32 VectBit;
4697
4698 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4699 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4700 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
4701 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
4702 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
4703 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
4704 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4705
4706 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
4707 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
4708
4709 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4710 if (u32Instance >= ADC_INSTANCE_COUNT)
4711 {
4712 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4713 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_46();
4714 DMAR(AdcAEBasePtr, VectAdr) |= 1UL << VectBit;
4715 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_46();
4716 }
4717 else
4718 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4719 {
4720 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4721 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_46();
4722 DMAR(AdcBasePtr, VectAdr) |= 1UL << VectBit;
4723 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_46();
4724 }
4725 }
4726
4727 /*FUNCTION**********************************************************************
4728 *
4729 * Function Name : Adc_Sar_Ip_DisableChannelDma
4730 * Description : This function disables DMA requests triggered by End of Conversion event from
4731 * a selected channel.
4732 *
4733 * @implements Adc_Sar_Ip_DisableChannelDma_Activity
4734 * END**************************************************************************/
Adc_Sar_Ip_DisableChannelDma(const uint32 u32Instance,const uint32 u32ChnIdx)4735 void Adc_Sar_Ip_DisableChannelDma(const uint32 u32Instance,
4736 const uint32 u32ChnIdx)
4737 {
4738 ADC_Type * AdcBasePtr = NULL_PTR;
4739 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4740 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4741 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4742 uint32 VectAdr;
4743 uint32 VectBit;
4744
4745 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4746 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4747 DevAssert(u32ChnIdx < ADC_SAR_IP_CDR_COUNT);
4748 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
4749 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChnIdx));
4750 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
4751 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4752
4753 VectAdr = ADC_SAR_IP_CHAN_2_VECT(u32ChnIdx);
4754 VectBit = ADC_SAR_IP_CHAN_2_BIT(u32ChnIdx);
4755
4756 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4757 if (u32Instance >= ADC_INSTANCE_COUNT)
4758 {
4759 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4760 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_47();
4761 DMAR(AdcAEBasePtr, VectAdr) &= ~(1UL << VectBit);
4762 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_47();
4763 }
4764 else
4765 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4766 {
4767 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4768 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_47();
4769 DMAR(AdcBasePtr, VectAdr) &= ~(1UL << VectBit);
4770 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_47();
4771 }
4772 }
4773
4774 /*FUNCTION**********************************************************************
4775 *
4776 * Function Name : Adc_Sar_Ip_DisableChannelDmaAll
4777 * Description : This function disables DMA requests triggered by End of Conversion event from
4778 * all channels.
4779 *
4780 * @implements Adc_Sar_Ip_DisableChannelDmaAll_Activity
4781 * END**************************************************************************/
Adc_Sar_Ip_DisableChannelDmaAll(const uint32 u32Instance)4782 void Adc_Sar_Ip_DisableChannelDmaAll(const uint32 u32Instance)
4783 {
4784 ADC_Type * AdcBasePtr = NULL_PTR;
4785 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4786 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4787 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4788 uint8 Index;
4789
4790 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4791 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4792 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4793
4794 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4795 if (u32Instance >= ADC_INSTANCE_COUNT)
4796 {
4797 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4798 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
4799 {
4800 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_48();
4801 DMAR(AdcAEBasePtr, Index) &= ~(Adc_Sar_Ip_au32AdcChanBitmap[u32Instance][Index]);
4802 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_48();
4803 }
4804 }
4805 else
4806 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4807 {
4808 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4809 for (Index = 0U; Index < Adc_Sar_Ip_au8AdcGroupCount[u32Instance]; Index++)
4810 {
4811 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_48();
4812 DMAR(AdcBasePtr, Index) &= ~(Adc_Sar_Ip_au32AdcChanBitmap[u32Instance][Index]);
4813 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_48();
4814 }
4815 }
4816 }
4817
4818 /*FUNCTION**********************************************************************
4819 *
4820 * Function Name : Adc_Sar_Ip_SetDmaClearSource
4821 * Description : This function selects the DMA Request Flag Clear Source.
4822 *
4823 * @implements Adc_Sar_Ip_SetDmaClearSource_Activity
4824 * END**************************************************************************/
Adc_Sar_Ip_SetDmaClearSource(const uint32 u32Instance,const Adc_Sar_Ip_ClearSourceType pDmaClear)4825 void Adc_Sar_Ip_SetDmaClearSource(const uint32 u32Instance,
4826 const Adc_Sar_Ip_ClearSourceType pDmaClear)
4827 {
4828 ADC_Type * AdcBasePtr = NULL_PTR;
4829 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4830 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4831 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4832
4833 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4834 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4835 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4836
4837 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4838 if (u32Instance >= ADC_INSTANCE_COUNT)
4839 {
4840 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4841 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_45();
4842 AdcAEBasePtr->DMAE &= ~(ADC_DMAE_DCLR_MASK);
4843 AdcAEBasePtr->DMAE |= ADC_DMAE_DCLR((uint32)pDmaClear);
4844 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_45();
4845 }
4846 else
4847 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4848 {
4849 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4850 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_45();
4851 AdcBasePtr->DMAE &= ~(ADC_DMAE_DCLR_MASK);
4852 AdcBasePtr->DMAE |= ADC_DMAE_DCLR((uint32)pDmaClear);
4853 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_45();
4854 }
4855 }
4856
4857 #if (STD_ON == ADC_SAR_IP_WDG_ENABLED)
4858 /*FUNCTION**********************************************************************
4859 *
4860 * Function Name : Adc_Sar_Ip_SetWdgThreshold
4861 * Description : This function sets the watchdog thresholds for a certain register.
4862 *
4863 * @implements Adc_Sar_Ip_SetWdgThreshold_Activity
4864 * END**************************************************************************/
Adc_Sar_Ip_SetWdgThreshold(const uint32 u32Instance,const uint8 u8RegisterIdx,const Adc_Sar_Ip_WdgThresholdType * const pThresholdValues)4865 void Adc_Sar_Ip_SetWdgThreshold(const uint32 u32Instance,
4866 const uint8 u8RegisterIdx,
4867 const Adc_Sar_Ip_WdgThresholdType * const pThresholdValues)
4868 {
4869 ADC_Type * AdcBasePtr = NULL_PTR;
4870 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4871 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4872 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4873 volatile uint32 * WTIMRAddr = NULL_PTR;
4874 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
4875 uint8 Shift;
4876 uint16 HighThreshold;
4877 uint16 LowThreshold;
4878 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
4879 uint32 Wtimr;
4880
4881 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4882 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4883 DevAssert(pThresholdValues != NULL_PTR);
4884 DevAssert(u8RegisterIdx < ADC_SAR_IP_THRHLR_COUNT);
4885 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4886
4887 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4888 if (u32Instance >= ADC_INSTANCE_COUNT)
4889 {
4890 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4891 WTIMRAddr = (volatile uint32 *)&(AdcAEBasePtr->WTIMR);
4892 }
4893 else
4894 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4895 {
4896 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4897 WTIMRAddr = (volatile uint32 *)&(AdcBasePtr->WTIMR);
4898 }
4899
4900 #if (ADC_SAR_IP_SET_RESOLUTION == STD_ON)
4901 if (FALSE == Adc_Sar_Ip_axAdcSarState[u32Instance].BypassResolution)
4902 {
4903 /* Calculate the shift of the threshold value to get the number of bits
4904 * needed by the hardware unit. */
4905 Shift = ADC_SAR_IP_RESULT_RESOLUTION - Adc_Sar_GetResolution(u32Instance);
4906 /* Shift the threshold to obtain the value to be written in the threshold register. */
4907 HighThreshold = (pThresholdValues->HighThreshold) << Shift;
4908 LowThreshold = (pThresholdValues->LowThreshold) << Shift;
4909
4910 /* If the bits of the high threshold value that are ignored due to
4911 * resolution remain 0, this will trigger interrupts when the conversion
4912 * value is equal to the high threshold value because the ignored bits
4913 * of the conversion result will be more than 0, so the high threshold
4914 * value will need to have the ignored bits set to 1. */
4915 HighThreshold |= (((uint16)1U << Shift) - 1U);
4916
4917 Adc_Sar_WriteThresholds(u32Instance, u8RegisterIdx, HighThreshold, LowThreshold);
4918 }
4919 else
4920 #endif /* (ADC_SAR_IP_SET_RESOLUTION == STD_ON) */
4921 {
4922 Adc_Sar_WriteThresholds(u32Instance, u8RegisterIdx, pThresholdValues->HighThreshold, pThresholdValues->LowThreshold);
4923 }
4924
4925 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_32();
4926
4927 Wtimr = *WTIMRAddr;
4928
4929 if (pThresholdValues->HighThresholdIntEn)
4930 {
4931 Wtimr |= (ADC_SAR_IP_WDG_REG_MASK_HIGH(u8RegisterIdx));
4932 }
4933 else
4934 {
4935 Wtimr &= (~ADC_SAR_IP_WDG_REG_MASK_HIGH(u8RegisterIdx));
4936 }
4937 if (pThresholdValues->LowThresholdIntEn)
4938 {
4939 Wtimr |= (ADC_SAR_IP_WDG_REG_MASK_LOW(u8RegisterIdx));
4940 }
4941 else
4942 {
4943 Wtimr &= (~ADC_SAR_IP_WDG_REG_MASK_LOW(u8RegisterIdx));
4944 }
4945
4946 *WTIMRAddr = Wtimr;
4947
4948 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_32();
4949 }
4950 #endif /* (STD_ON == ADC_SAR_IP_WDG_ENABLED) */
4951
4952 /*FUNCTION**********************************************************************
4953 *
4954 * Function Name : Adc_Sar_Ip_SetConversionMode
4955 * Description : This function configures the used conversion mode.
4956 * Note: The ADC instance must be in IDLE state in order to change this.
4957 *
4958 * @implements Adc_Sar_Ip_SetConversionMode_Activity
4959 * END**************************************************************************/
Adc_Sar_Ip_SetConversionMode(const uint32 u32Instance,const Adc_Sar_Ip_ConvModeType eConvMode)4960 void Adc_Sar_Ip_SetConversionMode(const uint32 u32Instance,
4961 const Adc_Sar_Ip_ConvModeType eConvMode)
4962 {
4963 ADC_Type * AdcBasePtr = NULL_PTR;
4964 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4965 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
4966 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4967 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4968 volatile const uint32 * MSRAddr = NULL_PTR;
4969 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4970 volatile uint32 * MCRAddr = NULL_PTR;
4971
4972 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4973 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
4974 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4975 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
4976 /* calibration must not be interrupted */
4977 if(FALSE == Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing)
4978 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
4979 {
4980 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
4981 if (u32Instance >= ADC_INSTANCE_COUNT)
4982 {
4983 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
4984 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4985 MSRAddr = (volatile uint32 *)&(AdcAEBasePtr->MSR);
4986 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4987 MCRAddr = (volatile uint32 *)&(AdcAEBasePtr->MCR);
4988 }
4989 else
4990 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
4991 {
4992 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
4993 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
4994 MSRAddr = (volatile uint32 *)&(AdcBasePtr->MSR);
4995 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
4996 MCRAddr = (volatile uint32 *)&(AdcBasePtr->MCR);
4997 }
4998
4999 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5000 /* The selected ADC should be in IDLE state */
5001 DevAssert(((*MSRAddr) & ADC_MSR_ADCSTATUS_MASK) == ADC_MSR_ADCSTATUS(ADC_SAR_IP_MSR_ADCSTATUS_IDLE));
5002 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5003
5004 /* Edit MODE */
5005 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_19();
5006 switch (eConvMode)
5007 {
5008 case ADC_SAR_IP_CONV_MODE_ONESHOT:
5009 *MCRAddr &= ~(ADC_MCR_MODE(1u)); /* MODE = 0 */
5010 break;
5011 case ADC_SAR_IP_CONV_MODE_SCAN:
5012 *MCRAddr |= ADC_MCR_MODE(1u); /* MODE = 1 */
5013 break;
5014 default:
5015 ; /* no-op */
5016 break;
5017 }
5018 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_19();
5019 }
5020 }
5021
5022 #if ADC_SAR_IP_HAS_CTU
5023 /*FUNCTION**********************************************************************
5024 *
5025 * Function Name : Adc_Sar_Ip_SetCtuMode
5026 * Description : This function configures the CTU mode and enable.
5027 *
5028 * @implements Adc_Sar_Ip_SetCtuMode_Activity
5029 * END**************************************************************************/
Adc_Sar_Ip_SetCtuMode(const uint32 u32Instance,const Adc_Sar_Ip_CtuModeType eCtuMode)5030 Adc_Sar_Ip_StatusType Adc_Sar_Ip_SetCtuMode(const uint32 u32Instance,
5031 const Adc_Sar_Ip_CtuModeType eCtuMode)
5032 {
5033 ADC_Type * AdcBasePtr = NULL_PTR;
5034 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5035 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
5036 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5037 Adc_Sar_Ip_StatusType Status = ADC_SAR_IP_STATUS_SUCCESS;
5038 volatile uint32 * MCRAddr = NULL_PTR;
5039
5040 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5041 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
5042 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
5043 DevAssert(!((FALSE == ADC_SAR_IP_INST_HAS_CTU_TRIGGER_MODE(u32Instance)) && (ADC_SAR_IP_CTU_MODE_TRIGGER == eCtuMode)));
5044 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
5045 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5046 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
5047 /* calibration must not be interrupted */
5048 if(FALSE == Adc_Sar_Ip_axAdcSarState[u32Instance].CalibrationOnGoing)
5049 {
5050 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
5051 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5052 if (u32Instance >= ADC_INSTANCE_COUNT)
5053 {
5054 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT];
5055 MCRAddr = (volatile uint32 *)&(AdcAEBasePtr->MCR);
5056 }
5057 else
5058 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5059 {
5060 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[u32Instance];
5061 MCRAddr = (volatile uint32 *)&(AdcBasePtr->MCR);
5062 }
5063
5064 /* Clear CTUEN to allow Powerdown operation to succeed. */
5065 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_20();
5066 *MCRAddr &= ~ADC_MCR_CTUEN_MASK;
5067 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_20();
5068
5069 /* Power down */
5070 Status = Adc_Sar_Ip_Powerdown(u32Instance);
5071 if (ADC_SAR_IP_STATUS_SUCCESS == Status)
5072 {
5073 /* Configure CTU */
5074 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
5075 if (ADC_SAR_IP_INST_HAS_CTU(u32Instance))
5076 {
5077 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
5078 SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_20();
5079 switch (eCtuMode)
5080 {
5081 case ADC_SAR_IP_CTU_MODE_CONTROL:
5082 *MCRAddr &= ~(ADC_MCR_CTU_MODE(1U)); /* CTU_MODE = 0 */
5083 *MCRAddr |= ADC_MCR_CTUEN(1U); /* CTUEN = 1 */
5084 break;
5085 #if ADC_SAR_IP_HAS_CTU_TRIGGER_MODE
5086 case ADC_SAR_IP_CTU_MODE_TRIGGER:
5087 /* Set CTU_MODE = 1 and CTUEN = 1 */
5088 *MCRAddr |= (ADC_MCR_CTU_MODE(1U) | ADC_MCR_CTUEN(1U));
5089 break;
5090 #endif /* ADC_SAR_IP_HAS_CTU_TRIGGER_MODE */
5091 /* Set CTU_MODE = 0 and CTUEN = 0 */
5092 case ADC_SAR_IP_CTU_MODE_DISABLED:
5093 *MCRAddr &= ~(ADC_MCR_CTU_MODE(1U) | ADC_MCR_CTUEN(1U));
5094 break;
5095 default:
5096 ; /* no-op */
5097 break;
5098 }
5099 SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_20();
5100 #if ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE
5101 }
5102 #endif /*ADC_SAR_IP_BAD_ACCESS_PROT_FEATURE*/
5103
5104 /* Power up */
5105 Status = Adc_Sar_Ip_Powerup(u32Instance);
5106 }
5107 #if (ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON)
5108 }
5109 else
5110 {
5111 Status = ADC_SAR_IP_STATUS_CAL_ONGOING;
5112 }
5113 #endif /*(ADC_SAR_IP_ASYNC_CALIBARTION_ENABLED == STD_ON) */
5114 return Status;
5115 }
5116 #endif /* ADC_SAR_IP_HAS_CTU */
5117
5118 #if (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE)
5119 #if (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER)
5120 /*FUNCTION**********************************************************************
5121 *
5122 * Function Name : Adc_Sar_Ip_SetExternalTrigger
5123 * Description : This function configures the external trigger.
5124 *
5125 * @implements Adc_Sar_Ip_SetExternalTrigger_Activity
5126 * END**************************************************************************/
Adc_Sar_Ip_SetExternalTrigger(const uint32 u32Instance,const Adc_Sar_Ip_ExtTriggerEdgeType eTriggerEdge,const Adc_Sar_Ip_ExtTriggerSourceType eTrggerSrc)5127 void Adc_Sar_Ip_SetExternalTrigger(const uint32 u32Instance,
5128 const Adc_Sar_Ip_ExtTriggerEdgeType eTriggerEdge,
5129 const Adc_Sar_Ip_ExtTriggerSourceType eTrggerSrc)
5130 {
5131 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5132 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
5133 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5134
5135 /* Switch between injected and normal external trigger */
5136 switch (eTrggerSrc)
5137 {
5138 #if FEATURE_ADC_HAS_EXT_TRIGGER
5139 case ADC_SAR_IP_NORMAL_EXT_TRIG:
5140 Adc_Sar_ConfigExternalTrigger(u32Instance, eTriggerEdge, ADC_MCR_EDGE_MASK, 0U, ADC_MCR_TRGEN_MASK);
5141 break;
5142 #if FEATURE_ADC_HAS_AUX_EXT_TRIGGER
5143 case ADC_SAR_IP_AUX_NORMAL_EXT_TRIG:
5144 Adc_Sar_ConfigExternalTrigger(u32Instance, eTriggerEdge, ADC_MCR_EDGE_MASK, 0U, ADC_MCR_XSTRTEN_MASK);
5145 break;
5146 case ADC_SAR_IP_ALL_NORMAL_EXT_TRIG:
5147 Adc_Sar_ConfigExternalTrigger(u32Instance, eTriggerEdge, ADC_MCR_EDGE_MASK, ADC_MCR_EDGE_MASK, (ADC_MCR_TRGEN_MASK | ADC_MCR_XSTRTEN_MASK));
5148 break;
5149 #endif /* FEATURE_ADC_HAS_AUX_EXT_TRIGGER */
5150 #endif /* FEATURE_ADC_HAS_EXT_TRIGGER */
5151 #if FEATURE_ADC_HAS_INJ_EXT_TRIGGER
5152 case ADC_SAR_IP_INJECTED_EXT_TRIG:
5153 Adc_Sar_ConfigExternalTrigger(u32Instance, eTriggerEdge, ADC_MCR_JEDGE_MASK, ADC_MCR_JEDGE_MASK, ADC_MCR_JTRGEN_MASK);
5154 break;
5155 #endif /* FEATURE_ADC_HAS_INJ_EXT_TRIGGER */
5156 default:
5157 ; /* no-op */
5158 break;
5159 }
5160 }
5161 #endif /* (FEATURE_ADC_HAS_INJ_EXT_TRIGGER || FEATURE_ADC_HAS_EXT_TRIGGER) */
5162 #endif /* (ADC_SAR_IP_EXTERNAL_TRIGGER_ENABLE) */
5163
5164 /*FUNCTION**********************************************************************
5165 *
5166 * Function Name : Adc_Sar_Ip_SetUserGainAndOffset
5167 * Description : This function configures user gain and offset.
5168 *
5169 * @implements Adc_Sar_Ip_SetUserGainAndOffset_Activity
5170 * END**************************************************************************/
Adc_Sar_Ip_SetUserGainAndOffset(const uint32 Instance,const uint16 Gain,const uint8 Offset)5171 void Adc_Sar_Ip_SetUserGainAndOffset(const uint32 Instance,
5172 const uint16 Gain,
5173 const uint8 Offset)
5174 {
5175 uint32 RegVal;
5176 ADC_Type * AdcBasePtr = NULL_PTR;
5177 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5178 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
5179 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5180 /* Write in RegVal the value needed for the register. */
5181
5182 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5183 DevAssert(Instance < ADC_SAR_IP_INSTANCE_COUNT);
5184 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5185
5186 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5187
5188 if (Instance >= ADC_INSTANCE_COUNT)
5189 {
5190 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
5191
5192 RegVal = ADC_AE_USER_OFFSET(Offset);
5193 RegVal |= ADC_AE_USER_GAIN(Gain);
5194 AdcAEBasePtr->ADC_AE_USER_OFFSET_GAIN_REG = RegVal;
5195 }
5196 else
5197 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5198 {
5199 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
5200
5201 RegVal = ADC_USER_OFFSET(Offset);
5202 RegVal |= ADC_USER_GAIN(Gain);
5203 AdcBasePtr->ADC_USER_OFFSET_GAIN_REG = RegVal;
5204 }
5205 }
5206
5207
5208 /*FUNCTION*********************************************************************
5209 *
5210 * Function Name : Adc_Sar_Ip_GetDataAddress
5211 * Description : Returns the address of the specified CDR register
5212 * @implements Adc_Sar_Ip_GetDataAddress_Activity
5213 *END*************************************************************************/
Adc_Sar_Ip_GetDataAddress(uint32 u32Instance,uint32 u32ChannelIndex)5214 uint32 Adc_Sar_Ip_GetDataAddress(uint32 u32Instance,
5215 uint32 u32ChannelIndex)
5216 {
5217 uint32 returnAddr = 0U;
5218
5219 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5220 DevAssert(u32Instance < ADC_SAR_IP_INSTANCE_COUNT);
5221 DevAssert(u32ChannelIndex < ADC_SAR_IP_CDR_COUNT);
5222 #if ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL
5223 DevAssert(ADC_SAR_IP_INST_HAS_CHANn(u32Instance, u32ChannelIndex));
5224 #endif /* ADC_SAR_IP_BAD_ACCESS_PROT_CHANNEL */
5225 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5226
5227 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5228 if (u32Instance >= ADC_INSTANCE_COUNT)
5229 {
5230 returnAddr = (uint32)&(CDR_AE(Adc_Sar_AE_Ip_apxAdcBase[u32Instance - ADC_INSTANCE_COUNT], u32ChannelIndex)) - ADC_SAR_IP_APPLICATION_EXTENSION_BASE_ADDRESS;
5231 }
5232 else
5233 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5234 {
5235 returnAddr = (Adc_Sar_Ip_uintPtrType)&(CDR(Adc_Sar_Ip_apxAdcBase[u32Instance], u32ChannelIndex));
5236 }
5237 return returnAddr;
5238 }
5239
5240 #if (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT)
5241 /*FUNCTION**********************************************************************
5242 *
5243 * Function Name : Adc_Sar_Ip_SetUserAccessAllowed
5244 * Description : Sets the UAA bit in REG_PROT to make the instance accessible in user mode.
5245 *
5246 *END**************************************************************************/
Adc_Sar_Ip_SetUserAccessAllowed(const uint32 Instance)5247 void Adc_Sar_Ip_SetUserAccessAllowed(const uint32 Instance)
5248 {
5249 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5250 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
5251 #else
5252 #ifdef SAR_ADC_PROT_MEM_U32
5253 ADC_Type * AdcBasePtr = NULL_PTR;
5254 #endif /* SAR_ADC_PROT_MEM_U32 */
5255 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5256
5257 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5258 DevAssert(Instance < ADC_SAR_IP_INSTANCE_COUNT);
5259 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5260
5261 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5262 if (Instance >= ADC_INSTANCE_COUNT)
5263 {
5264 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
5265 SET_USER_ACCESS_ALLOWED((uint32)AdcAEBasePtr, SAR_ADC_AE_PROT_MEM_U32);
5266 }
5267 #else
5268 #ifdef SAR_ADC_PROT_MEM_U32
5269 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
5270 SET_USER_ACCESS_ALLOWED((uint32)AdcBasePtr, SAR_ADC_PROT_MEM_U32);
5271 #else
5272 (void)Instance;
5273 #endif /* SAR_ADC_PROT_MEM_U32 */
5274 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5275 }
5276
5277 /*FUNCTION**********************************************************************
5278 *
5279 * Function Name : Adc_Sar_Ip_ClrUserAccessAllowed
5280 * Description : Clears the UAA bit in REG_PROT to make the instance inaccessible in user mode.
5281 *
5282 *END**************************************************************************/
Adc_Sar_Ip_ClrUserAccessAllowed(const uint32 Instance)5283 void Adc_Sar_Ip_ClrUserAccessAllowed(const uint32 Instance)
5284 {
5285 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5286 SAR_ADC_AE_Type * AdcAEBasePtr = NULL_PTR;
5287 #else
5288 #ifdef SAR_ADC_PROT_MEM_U32
5289 ADC_Type * AdcBasePtr = NULL_PTR;
5290 #endif /* SAR_ADC_PROT_MEM_U32 */
5291 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5292
5293 #if (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON)
5294 DevAssert(Instance < ADC_SAR_IP_INSTANCE_COUNT);
5295 #endif /* (ADC_SAR_IP_DEV_ERROR_DETECT == STD_ON) */
5296
5297 #if FEATURE_ADC_HAS_APPLICATION_EXTENSION
5298 if (Instance >= ADC_INSTANCE_COUNT)
5299 {
5300 AdcAEBasePtr = Adc_Sar_AE_Ip_apxAdcBase[Instance - ADC_INSTANCE_COUNT];
5301 CLR_USER_ACCESS_ALLOWED((uint32)AdcAEBasePtr, SAR_ADC_AE_PROT_MEM_U32);
5302 }
5303 #else
5304 #ifdef SAR_ADC_PROT_MEM_U32
5305 AdcBasePtr = Adc_Sar_Ip_apxAdcBase[Instance];
5306 CLR_USER_ACCESS_ALLOWED((uint32)AdcBasePtr, SAR_ADC_PROT_MEM_U32);
5307 #else
5308 (void)Instance;
5309 #endif /* SAR_ADC_PROT_MEM_U32 */
5310 #endif /* FEATURE_ADC_HAS_APPLICATION_EXTENSION */
5311 }
5312 #endif /* (STD_ON == ADC_SAR_IP_ENABLE_USER_MODE_SUPPORT) */
5313
5314 #define ADC_STOP_SEC_CODE
5315 #include "Adc_MemMap.h"
5316
5317 #ifdef __cplusplus
5318 }
5319 #endif
5320
5321 /** @} */
5322
