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Searched refs:kCLOCK_DivFcclk0Clk (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/boards/mimxrt700evk/project_template/
Dboard.h36 #define BOARD_DEBUG_UART_FCCLK_DIV kCLOCK_DivFcclk0Clk
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h1711 …kCLOCK_DivFcclk0Clk = CLKCTL0_TUPLE_MUXA(FCCLK0DIV_OFFSET, 0), /*!< FCCLK0 Clk Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h1711 …kCLOCK_DivFcclk0Clk = CLKCTL0_TUPLE_MUXA(FCCLK0DIV_OFFSET, 0), /*!< FCCLK0 Clk Divider. */ enumerator
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h1711 …kCLOCK_DivFcclk0Clk = CLKCTL0_TUPLE_MUXA(FCCLK0DIV_OFFSET, 0), /*!< FCCLK0 Clk Divider. */ enumerator