1 /* 2 * Copyright 2023 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _BOARD_H_ 9 #define _BOARD_H_ 10 11 #include "clock_config.h" 12 #include "fsl_common.h" 13 #include "fsl_reset.h" 14 #include "fsl_gpio.h" 15 #if defined(MIMXRT798S_cm33_core0_SERIES) || defined(MIMXRT798S_cm33_core1_SERIES) 16 #include "fsl_glikey.h" 17 #endif 18 #if defined(MIMXRT798S_cm33_core0_SERIES) 19 #include "fsl_xspi.h" 20 #include "fsl_power.h" 21 #endif 22 23 /******************************************************************************* 24 * Definitions 25 ******************************************************************************/ 26 /*! @brief The board name */ 27 #define BOARD_NAME "MIMXRT700-EVK" 28 29 /*! @brief The UART to use for debug messages. */ 30 #define BOARD_DEBUG_UART_TYPE kSerialPort_Uart 31 #if (defined(MIMXRT798S_cm33_core0_SERIES) || defined(MIMXRT798S_hifi4_SERIES)) 32 #define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART0 33 #define BOARD_DEBUG_UART_INSTANCE 0U 34 #define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetLPFlexCommClkFreq(0) 35 #define BOARD_DEBUG_UART_CLK_ATTACH kFCCLK0_to_FLEXCOMM0 36 #define BOARD_DEBUG_UART_FCCLK_DIV kCLOCK_DivFcclk0Clk 37 #define BOARD_DEBUG_UART_FCCLK_ATTACH kOSC_CLK_to_FCCLK0 38 #define BOARD_UART_IRQ_HANDLER LP_FLEXCOMM0_IRQHandler 39 #define BOARD_UART_IRQ LP_FLEXCOMM0_IRQn 40 #elif (defined(MIMXRT798S_cm33_core1_SERIES) || defined(MIMXRT798S_hifi1_SERIES) || defined(MIMXRT798S_ezhv_SERIES)) 41 #define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART19 42 #define BOARD_DEBUG_UART_INSTANCE 19U 43 #define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetLPFlexCommClkFreq(19) 44 #define BOARD_DEBUG_UART_CLK_ATTACH kSENSE_BASE_to_FLEXCOMM19 45 #define BOARD_DEBUG_UART_CLK_DIV kCLOCK_DivLPFlexComm19Clk 46 #define BOARD_UART_IRQ_HANDLER LP_FLEXCOMM19_IRQHandler 47 #define BOARD_UART_IRQ LP_FLEXCOMM19_IRQn 48 #else 49 #error "Unsupported core!" 50 #endif 51 52 #ifndef BOARD_DEBUG_UART_BAUDRATE 53 #define BOARD_DEBUG_UART_BAUDRATE 115200 54 #endif /* BOARD_DEBUG_UART_BAUDRATE */ 55 56 /* Board RGB LED color mapping */ 57 #define LOGIC_LED_ON 1U 58 #define LOGIC_LED_OFF 0U 59 #ifndef BOARD_LED_GREEN_GPIO 60 #define BOARD_LED_GREEN_GPIO GPIO0 61 #endif 62 #ifndef BOARD_LED_GREEN_GPIO_PIN 63 #define BOARD_LED_GREEN_GPIO_PIN 18U 64 #endif 65 #ifndef BOARD_LED_BLUE_GPIO 66 #define BOARD_LED_BLUE_GPIO GPIO0 67 #endif 68 #ifndef BOARD_LED_BLUE_GPIO_PIN 69 #define BOARD_LED_BLUE_GPIO_PIN 17U 70 #endif 71 72 #ifndef BOARD_LED_RED_GPIO 73 #define BOARD_LED_RED_GPIO GPIO8 74 #endif 75 #ifndef BOARD_LED_RED_GPIO_PIN 76 #define BOARD_LED_RED_GPIO_PIN 6U 77 #endif 78 79 /* SSD1963 (TFT_PROTO_5) panel. */ 80 /* RST pin. */ 81 #define BOARD_SSD1963_RST_GPIO GPIO2 82 #define BOARD_SSD1963_RST_PIN 15 83 /* CS pin. */ 84 #define BOARD_SSD1963_CS_GPIO GPIO2 85 #define BOARD_SSD1963_CS_PIN 0 86 /* D/C pin, also named RS pin. */ 87 #define BOARD_SSD1963_RS_GPIO GPIO2 88 #define BOARD_SSD1963_RS_PIN 1 89 /* Touch panel. */ 90 #define BOARD_SSD1963_TOUCH_I2C_BASEADDR LPI2C8 91 #define BOARD_SSD1963_TOUCH_I2C_CLOCK_FREQ CLOCK_GetLPFlexCommClkFreq(8U) 92 93 /* MIPI panel. */ 94 #define BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR LPI2C8 95 #define BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_FREQ CLOCK_GetLPFlexCommClkFreq(8U) 96 #define BOARD_MIPI_PANEL_TOUCH_RST_GPIO GPIO3 97 #define BOARD_MIPI_PANEL_TOUCH_RST_PIN 8 98 #define BOARD_MIPI_PANEL_TOUCH_INT_GPIO GPIO1 99 #define BOARD_MIPI_PANEL_TOUCH_INT_PIN 13 100 #define BOARD_MIPI_TOUCH_INT_GPIO_IRQ GPIO10_IRQn 101 #define BOARD_MIPI_TOUCH_INT_GPIO_IRQ_Handler GPIO10_IRQHandler 102 103 /* RST pin. */ 104 #define BOARD_MIPI_RST_GPIO GPIO3 105 #define BOARD_MIPI_RST_PIN 4 106 /* POWER pin .*/ 107 #define BOARD_MIPI_POWER_GPIO GPIO1 108 #define BOARD_MIPI_POWER_PIN 10 109 /* Backlight pin. */ 110 #define BOARD_MIPI_BL_GPIO GPIO1 111 #define BOARD_MIPI_BL_PIN 14 112 /* TE pin. */ 113 #define BOARD_MIPI_TE_GPIO GPIO3 114 #define BOARD_MIPI_TE_PIN 5 115 #define BOARD_MIPI_TE_GPIO_IRQn GPIO30_IRQn 116 #define BOARD_MIPI_TE_GPIO_IRQ_Handler GPIO30_IRQHandler 117 118 #define LED_RED_INIT(output) \ 119 GPIO_PinWrite(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PIN, output); \ 120 BOARD_LED_RED_GPIO->PDDR |= (1U << BOARD_LED_RED_GPIO_PIN) /*!< Enable target LED_RED */ 121 #define LED_RED_ON() GPIO_PortSet(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */ 122 #define LED_RED_OFF() GPIO_PortClear(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */ 123 #define LED_RED_TOGGLE() \ 124 GPIO_PortToggle(BOARD_LED_RED_GPIO, 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED1 */ 125 126 #define LED_GREEN_INIT(output) \ 127 GPIO_PinWrite(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PIN, output); \ 128 BOARD_LED_GREEN_GPIO->PDDR |= (1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Enable target LED_GREEN */ 129 #define LED_GREEN_ON() \ 130 GPIO_PortSet(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */ 131 #define LED_GREEN_OFF() \ 132 GPIO_PortClear(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */ 133 #define LED_GREEN_TOGGLE() \ 134 GPIO_PortToggle(BOARD_LED_GREEN_GPIO, 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */ 135 136 #define LED_BLUE_INIT(output) \ 137 GPIO_PinWrite(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PIN, output); \ 138 BOARD_LED_BLUE_GPIO->PDDR |= (1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Enable target LED_BLUE */ 139 #define LED_BLUE_ON() \ 140 GPIO_PortSet(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE \ 141 */ 142 #define LED_BLUE_OFF() \ 143 GPIO_PortClear(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE \ 144 */ 145 #define LED_BLUE_TOGGLE() \ 146 GPIO_PortToggle(BOARD_LED_BLUE_GPIO, 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */ 147 148 /* Board SW PIN */ 149 #ifndef BOARD_SW5_GPIO /* User button 1 */ 150 #define BOARD_SW5_GPIO GPIO0 151 #define BOARD_SW5_NAME "SW5" 152 #endif 153 #ifndef BOARD_SW5_GPIO_PIN 154 #define BOARD_SW5_GPIO_PIN 9U 155 #endif 156 #ifndef BOARD_SW6_GPIO /* User button 3 */ 157 #define BOARD_SW6_GPIO GPIO8 158 #endif 159 #ifndef BOARD_SW6_GPIO_PIN 160 #define BOARD_SW6_GPIO_PIN 5U 161 #endif 162 #ifndef BOARD_SW7_GPIO /* User button 2 */ 163 #define BOARD_SW7_GPIO GPIO1 164 #endif 165 #ifndef BOARD_SW7_GPIO_PIN 166 #define BOARD_SW7_GPIO_PIN 3U 167 #endif 168 169 /* USB PHY configuration */ 170 #define BOARD_USB_PHY_D_CAL (0x07U) 171 #define BOARD_USB_PHY_TXCAL45DP (0x06U) 172 #define BOARD_USB_PHY_TXCAL45DM (0x06U) 173 174 #define BOARD_ACCEL_I2C_BASEADDR LPI2C20 175 176 #define BOARD_CODEC_I2C_BASEADDR LPI2C2 177 #define BOARD_CODEC_I2C_CLOCK_FREQ CLOCK_GetLPI2cClkFreq(2) 178 #define BOARD_CODEC_I2C_INSTANCE 2 179 180 #define BOARD_PMIC_I2C_BASEADDR LPI2C15 181 #define BOARD_PMIC_I2C_CLOCK_FREQ CLOCK_GetLPI2cClkFreq(15) 182 183 /* Definitions for eRPC MU transport layer */ 184 #if (defined(MIMXRT798S_cm33_core0_SERIES)) 185 #define MU_BASE MU1_MUA 186 #define MU_IRQ MU1_A_IRQn 187 #define MU_IRQ_HANDLER MU1_A_IRQHandler 188 #elif (defined(MIMXRT798S_cm33_core1_SERIES)) 189 #define MU_BASE MU1_MUB 190 #define MU_IRQ MU1_B_IRQn 191 #define MU_IRQ_HANDLER MU1_B_IRQHandler 192 #endif 193 #define MU_IRQ_PRIORITY (2) 194 195 #ifndef BOARD_PSRAM_ENABLE_VARIABLE_LATENCY 196 #define BOARD_PSRAM_ENABLE_VARIABLE_LATENCY (1U) 197 #endif 198 199 /* ERPC LPSPI configuration */ 200 #define ERPC_BOARD_LPSPI_SLAVE_READY_USE_GPIO (1) 201 #define ERPC_BOARD_LPSPI_BASEADDR LPSPI14 202 #define ERPC_BOARD_LPSPI_BAUDRATE 500000U 203 #define ERPC_BOARD_LPSPI_CLK_FREQ (CLOCK_GetFreq(kCLOCK_LPSpi14Clk)) 204 #define ERPC_BOARD_LPSPI_INT_GPIO GPIO1 205 #define ERPC_BOARD_LPSPI_INT_PIN 11U 206 207 /* ERPC LPI2C configuration */ 208 #define ERPC_BOARD_LPI2C_BASEADDR LPI2C2_BASE 209 #define ERPC_BOARD_LPI2C_BAUDRATE 100000U 210 #define ERPC_BOARD_LPI2C_CLKSRC kCLOCK_Flexcomm2 211 #define ERPC_BOARD_LPI2C_CLK_FREQ CLOCK_GetLPFlexCommClkFreq(2u) 212 #define ERPC_BOARD_LPI2C_INT_GPIO GPIO3 213 #define ERPC_BOARD_LPI2C_INT_PIN 2U 214 215 #if (defined(MIMXRT798S_cm33_core0_SERIES)) 216 #define IS_XIP_XSPI0() \ 217 ((((uint32_t)BOARD_ConfigMPU >= 0x28000000U) && ((uint32_t)BOARD_ConfigMPU < 0x30000000U)) || \ 218 (((uint32_t)BOARD_ConfigMPU >= 0x38000000U) && ((uint32_t)BOARD_ConfigMPU < 0x40000000U))) 219 #define IS_XIP_XSPI1() \ 220 ((((uint32_t)BOARD_ConfigMPU >= 0x08000000U) && ((uint32_t)BOARD_ConfigMPU < 0x10000000U)) || \ 221 (((uint32_t)BOARD_ConfigMPU >= 0x18000000U) && ((uint32_t)BOARD_ConfigMPU < 0x20000000U))) 222 #endif 223 224 #if defined(__cplusplus) 225 extern "C" { 226 #endif /* __cplusplus */ 227 228 /******************************************************************************* 229 * API 230 ******************************************************************************/ 231 void BOARD_InitDebugConsole(void); 232 #if defined(MIMXRT798S_cm33_core0_SERIES) || defined(MIMXRT798S_cm33_core1_SERIES) 233 /*! 234 * @brief Initializes the AHB Secure Controller, allow SRAM and Media access for masters. 235 */ 236 void BOARD_InitAHBSC(void); 237 /*! 238 * @brief Enable write for the Glikey protected registers. 239 * 240 * @param base GLIKEY peripheral base pointer 241 * @param idx target index. 242 */ 243 void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx); 244 /*! 245 * @brief Reset the Glikey to init status. 246 * 247 * @param base GLIKEY peripheral base pointer 248 */ 249 void GlikeyClearConfig(GLIKEY_Type *base); 250 #endif 251 252 #if defined(MIMXRT798S_cm33_core0_SERIES) 253 void BOARD_ConfigMPU(void); 254 void BOARD_Init16bitsPsRam(XSPI_Type *base); 255 void BOARD_XspiClockSafeConfig(void); 256 AT_QUICKACCESS_SECTION_CODE(void BOARD_SetXspiClock(XSPI_Type *base, uint32_t src, uint32_t divider)); 257 AT_QUICKACCESS_SECTION_CODE(void BOARD_DeinitXspi(XSPI_Type *base, CACHE64_CTRL_Type *cache)); 258 AT_QUICKACCESS_SECTION_CODE(void BOARD_InitXspi(XSPI_Type *base, CACHE64_CTRL_Type *cache)); 259 #endif 260 261 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED 262 void BOARD_I2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz); 263 status_t BOARD_I2C_Send(LPI2C_Type *base, 264 uint8_t deviceAddress, 265 uint32_t subAddress, 266 uint8_t subaddressSize, 267 uint8_t *txBuff, 268 uint8_t txBuffSize); 269 status_t BOARD_I2C_Receive(LPI2C_Type *base, 270 uint8_t deviceAddress, 271 uint32_t subAddress, 272 uint8_t subaddressSize, 273 uint8_t *rxBuff, 274 uint8_t rxBuffSize); 275 276 void BOARD_PMIC_I2C_Init(void); 277 void BOARD_PMIC_I2C_Deinit(void); 278 status_t BOARD_PMIC_I2C_Send( 279 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize); 280 status_t BOARD_PMIC_I2C_Receive( 281 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); 282 283 284 #if defined(MIMXRT798S_cm33_core0_SERIES) 285 void BOARD_MIPIPanelTouch_I2C_Init(void); 286 status_t BOARD_MIPIPanelTouch_I2C_Send( 287 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize); 288 status_t BOARD_MIPIPanelTouch_I2C_Receive( 289 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); 290 #endif 291 #endif /* SDK_I2C_BASED_COMPONENT_USED */ 292 293 #if defined(__cplusplus) 294 } 295 #endif /* __cplusplus */ 296 297 #endif /* _BOARD_H_ */ 298
