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/hal_nxp-latest/mcux/mcux-sdk/boards/evkmcimx7ulp/
Dclock_config.c117 .divSlow = kSCG_SysClkDivBy2, /* Slow clock divider. */
134 .divSlow = kSCG_SysClkDivBy6, /* Slow clock divider. */
152 .divSlow = kSCG_SysClkDivBy8, /* Slow clock divider. */
168 .divSlow = kSCG_SysClkDivBy8, /* Slow clock divider. */
184 .divSlow = kSCG_SysClkDivBy2, /* Slow clock divider. */
/hal_nxp-latest/mcux/mcux-sdk/boards/evkmimx8ulp/
Dclock_config.c94 .divSlow = 3, /* Slow clock divider. */
146 .divSlow = 9, /* Slow clock divider. */
151 .divSlow = 9, /* Slow clock divider. */
156 .divSlow = 7, /* Slow clock divider. */
373 tmp_sys_clk_cfg.divSlow = *slow_clk_divider - 1; in BOARD_CalculateCoreClkDivider()
412 g_sysClkConfigFroSource.divSlow = slow_clk_divider - 1; in BOARD_SwitchToFROClk()
903 g_sysClkConfigRun.divSlow = slow_clk_divider - 1; in BOARD_SwitchDriveMode()
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke17z512/
Dclock_config.c73 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */ in CLOCK_CONFIG_FircSafeConfig()
161 .divSlow = kSCG_SysClkDivBy3, /* Slow Clock Divider: divided by 3 */
271 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
373 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l3a6/
Dclock_config.c78 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */ in CLOCK_CONFIG_FircSafeConfig()
140 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
240 .divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
348 .divSlow = kSCG_SysClkDivBy9, /* Slow Clock Divider: divided by 9 */
/hal_nxp-latest/mcux/mcux-sdk/boards/twrke18f/
Dclock_config.c76 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */ in CLOCK_CONFIG_FircSafeConfig()
159 .divSlow = kSCG_SysClkDivBy8, /* Slow Clock Divider: divided by 8 */
271 .divSlow = kSCG_SysClkDivBy5, /* Slow Clock Divider: divided by 5 */
391 .divSlow = kSCG_SysClkDivBy7, /* Slow Clock Divider: divided by 7 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l2a4s/
Dclock_config.c92 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */ in CLOCK_CONFIG_FircSafeConfig()
176 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
307 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
423 .divSlow = kSCG_SysClkDivBy8, /* Slow Clock Divider: divided by 8 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke16z/
Dclock_config.c76 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */ in CLOCK_CONFIG_FircSafeConfig()
161 .divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
269 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke15z/
Dclock_config.c77 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */ in CLOCK_CONFIG_FircSafeConfig()
160 .divSlow = kSCG_SysClkDivBy3, /* Slow Clock Divider: divided by 3 */
265 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke17z/
Dclock_config.c74 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */ in CLOCK_CONFIG_FircSafeConfig()
156 .divSlow = kSCG_SysClkDivBy3, /* Slow Clock Divider: divided by 3 */
257 .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
/hal_nxp-latest/mcux/mcux-sdk/boards/k32w148evk/
Dclock_config.c80 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow clock divider */ in CLOCK_CONFIG_FircSafeConfig()
160 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
/hal_nxp-latest/mcux/mcux-sdk/boards/kw45b41zevk/
Dclock_config.c80 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow clock divider */ in CLOCK_CONFIG_FircSafeConfig()
160 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
/hal_nxp-latest/mcux/mcux-sdk/boards/kw45b41zloc/
Dclock_config.c80 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow clock divider */ in CLOCK_CONFIG_FircSafeConfig()
160 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmmcxw71/
Dclock_config.c80 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow clock divider */ in CLOCK_CONFIG_FircSafeConfig()
160 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/drivers/
Dfsl_clock.h1178 …uint32_t divSlow : 6; /*!< Slow clock divider, selected division is the value of the field + 1 */ member
1738 assert(config->divSlow > config->divBus); in CLOCK_SetCm33SysClkConfig()
1739 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetCm33SysClkConfig()
1766 assert(config->divSlow > config->divBus); in CLOCK_SetFusionSysClkConfig()
1767 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetFusionSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/drivers/
Dfsl_clock.h1178 …uint32_t divSlow : 6; /*!< Slow clock divider, selected division is the value of the field + 1 */ member
1738 assert(config->divSlow > config->divBus); in CLOCK_SetCm33SysClkConfig()
1739 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetCm33SysClkConfig()
1766 assert(config->divSlow > config->divBus); in CLOCK_SetFusionSysClkConfig()
1767 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetFusionSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/drivers/
Dfsl_clock.h1178 …uint32_t divSlow : 6; /*!< Slow clock divider, selected division is the value of the field + 1 */ member
1738 assert(config->divSlow > config->divBus); in CLOCK_SetCm33SysClkConfig()
1739 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetCm33SysClkConfig()
1766 assert(config->divSlow > config->divBus); in CLOCK_SetFusionSysClkConfig()
1767 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetFusionSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/drivers/
Dfsl_clock.h1178 …uint32_t divSlow : 6; /*!< Slow clock divider, selected division is the value of the field + 1 */ member
1738 assert(config->divSlow > config->divBus); in CLOCK_SetCm33SysClkConfig()
1739 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetCm33SysClkConfig()
1766 assert(config->divSlow > config->divBus); in CLOCK_SetFusionSysClkConfig()
1767 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetFusionSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/drivers/
Dfsl_clock.h1178 …uint32_t divSlow : 6; /*!< Slow clock divider, selected division is the value of the field + 1 */ member
1738 assert(config->divSlow > config->divBus); in CLOCK_SetCm33SysClkConfig()
1739 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetCm33SysClkConfig()
1766 assert(config->divSlow > config->divBus); in CLOCK_SetFusionSysClkConfig()
1767 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U); in CLOCK_SetFusionSysClkConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/drivers/
Dfsl_clock.c293 freq /= (sysClkConfig.divSlow + 1U); in CLOCK_GetSysClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/drivers/
Dfsl_clock.c292 freq /= (sysClkConfig.divSlow + 1U); in CLOCK_GetSysClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/drivers/
Dfsl_clock.c292 freq /= (sysClkConfig.divSlow + 1U); in CLOCK_GetSysClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/drivers/
Dfsl_clock.h307 uint32_t divSlow : 4; /*!< Slow clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/drivers/
Dfsl_clock.h303 uint32_t divSlow : 4; /*!< Slow clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/drivers/
Dfsl_clock.h295 uint32_t divSlow : 4; /*!< Slow clock divider, see @ref scg_sys_clk_div_t. */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/drivers/
Dfsl_clock.h318 uint32_t divSlow : 4; /*!< Slow clock divider, see @ref scg_sys_clk_div_t. */ member

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